ATMEL ATtiny85 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

• Non-volatile Program and Data Memories

– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)

• Endurance: 10,000 Write/Erase Cycles

– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)

• Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes Internal SRAM (ATtiny25/45/85) – Programming Lock for Self-Programming Flash Program and EEPROM Data

Security

• Peripheral Features

– 8-bit Timer/Counter with Prescaler and Two PWM Channels – 8-bit High Speed Timer/Counter with Separate Prescaler

• 2 High Frequency PWM Outputs with Separate Output Compare Registers

• Programmable Dead Time Generator – Universal Serial Interface with Start Condition Detector – 10-bit ADC

• 4 Single Ended Channels

• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator

• Special Microcontroller Features

– debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator

• I/O and Packages

– Six Programmable I/O Lines – 8-pin SOIC – 20-pin QFN

• Operating Voltage

– 2.7 - 5.5V for ATtiny25/45/85

• Speed Grade

– ATtiny25/45/85: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

• Automotive Temperature Range

– -40°C to +125°C

• Low Power Consumption

– Active Mode:

• 1 MHz, 2.7V: 300µA – Power-down Mode:

• 0.2µA at 2.7V

8-Bit Microcontroller

8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash

ATtiny25 ATtiny45 ATtiny85

Automotive

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1. Pin Configurations

1 2 3 4

8 7 6 5

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/XTAL1/OC1B/ADC3) PB3

(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4

GND

VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)

SOIC



Figure 1-1. Pinout ATtiny25/45/85

2. Overview

The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

ATtiny25/45/85

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2.1 Block Diagram

PROGRAM COUNTER

INTERNAL

OSCILLA

TOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

SRAM

MCU CONTROL

GENERAL PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTER0



SERIAL

UNIVERSAL

INTERFACE



TIMER/

COUNTER1

INSTRUCTION

DECODER

DATA DIR.

REG.PORT B

DATA REGISTER

PORT B

PROGRAMMING

LOGIC

TIMING AND

CONTROL

MCU STATUS

STATUS

ALU

PORT B DRIVERS

PB0-PB5

VCC

GND

CONTROL

LINES

8-BIT DATABUS

ADC /  ANALOG COMPARATOR  

INTERRUPT

UNIT

DATA

EEPROM

CALIBRATED

OSCILLATORS

RESET

ATtiny25/45/85

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

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The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high

speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving m o d e s . Th e Idl e mode stops the C P U whil e al l o w i n g the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core.

The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

2.2 Automotive Quality Grade

The ATtiny25/45/85 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATtiny25/45/85 have been verified during regular product qualification as per AEC-Q100 grade 1.

As indicated in the ordering information paragraph, the products are available in three different temperature grades, but with equivalent quality and reliability objectives. Different temperature identifiers have been defined as listed in Table 2-1.

Table 2-1. Temperature Grade Identification for Automotive Products

Temperature

-40 ; +85 T

-40 ; +105 T1 Reduced Automotive Temperature Range

-40 ; +125 Z Full AutomotiveTemperature Range

Identifier Comments

Similar to Industrial Temperature Grade but with Automotive Quality

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2.3 Pin Descriptions

2.3.1 VCC

Supply voltage.

2.3.2 GND

Ground.

2.3.3 Port B (PB5..PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on

page 54.

2.3.4 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page

36. Shorter pulses are not guaranteed to generate a reset.

ATtiny25/45/85

3. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

4. AVR CPU Core

4.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

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4.2 Architectural Overview

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2



I/O Module1

I/O Module n



Figure 4-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

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ATtiny25/45/85

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions are 16-bits wide. There are also 32-bit instructions.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.

4.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

4.4 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit 7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

I T H S V N Z C SREG

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• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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4.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

ATtiny25/45/85

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

4.5.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3.

Figure 4-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

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4.6 Stack Pointer

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit 15 14 13 12 11 10 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

1 0 0 1 1 1 1 1

4.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

, directly generated from the selected clock source for the

CPU

ATtiny25/45/85

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ATtiny25/45/85

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

Figure 4-4. The Parallel Instruction Fetches and Instruction Executions

Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destination register.

Figure 4-5. Single Cycle ALU Operation

4.8 Reset and Interrupt Handling

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The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 45. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

ATtiny25/45/85

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4.8.1 Interrupt Response Time

0x0000

0x03FF/0x07FF

Program Memory

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

5. AVR ATtiny25/45/85 Memories

This section describes the different memories in the ATtiny25/45/85. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

ATtiny25/45/85

5.1 In-System Re-programmable Flash Program Memory

The ATtiny25/45/85 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 1024/2048/4096 x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny25/45/85 Program Counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program memory locations. “Memory Programming” on page 129 contains a detailed description on Flash data serial downloading using the SPI pins.

Constant tables can be allocated within the entire Program memory address space (see the LPM – Load Program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 10.

Figure 5-1. Program Memory Map

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5.2 SRAM Data Memory

32 Registers

64 I/O Registers

Internal SRAM

(128/256/512 x 8)

0x0000 - 0x001F 0x0020 - 0x005F

0x0DF/0x015F/0x025F

0x0060

Data Memory

Figure 5-2 shows how the ATtiny25/45/85 SRAM Memory is organized.

The lower 224/352/607 Data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O memory, and the last 128/256/512 locations address the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 9.

Figure 5-2. Data Memory Map

5.2.1 Data Memory Access Times

ATtiny25/45/85

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

cycles as described in Figure 5-3.

CPU

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Figure 5-3. On-chip Data SRAM Access Cycles

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction



Next Instruction

5.3 EEPROM Data Memory

The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see page 133.

ATtiny25/45/85

5.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access times for the EEPROM are given in Table 5-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 20 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 18 for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

5.3.2 EEPROM Address Register High – EEARH

Bit 7 6 5 4 3 2 1 0

- - - - - - - EEAR8 EEARH

Read/Write R R R R R R R R/W

Initial Value X X X X X X X X

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• Bit 7..1 – Res6..0: Reserved Bits

These bits are reserved for future use and will always read as 0 in ATtiny25/45/85.

• Bits 0 – EEAR8: EEPROM Address

The EEPROM Address Register – EEARH – specifies the high EEPROM address in the 128/256/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127/255/511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

5.3.3 EEPROM Address Register – EEARL

Bit 7 6 5 4 3 2 1 0

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value X X X X X X X X

• Bits 7..0 – EEAR7..0: EEPROM Address

The EEPROM Address Register – EEARL – specifies the low EEPROM address in the 128/256/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127/255/511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

5.3.4 EEPROM Data Register – EEDR

Bit 7 6 5 4 3 2 1 0

EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value X X X X X X X X

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

5.3.5 EEPROM Control Register – EECR

Bit 7 6 5 4 3 2 1 0

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use and will always read as 0 in ATtiny25/45/85. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reserved Bit

This bit is reserved in the ATtiny25/45/85 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

operations. The Programming times for the different modes are shown in Table 5-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 5-1. EEPROM Mode Bits

Programming

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation)

0 1 1.8 ms Erase Only

1 0 1.8 ms Write Only

1 1 – Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

Time Operation

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

5.3.6 Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEAR Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 20-1. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations.

7598G–AVR–03/08

5.3.7 Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after Power-up).

5.3.8 Erase

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 20-1). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations.

5.3.9 Write

To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 20-1). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations.

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “Oscillator Calibration Register – OSCCAL” on

page 26.

The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions

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Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r17) in address register

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

ATtiny25/45/85

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0>>EEPM0)

/* Set up address and data registers */

EEARL = ucAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

7598G–AVR–03/08

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r17) in address register

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEARL = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

5.3.10 Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

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5.4 I/O Memory

General I/O

Modules

CPU Core RAM

clk

I/O

AVR Clock

Control Unit

clk

CPU

Flash and EEPROM

clk

FLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Calibrated RC

Oscillator

External Clock

ADC

clk

ADC

Crystal

Oscillator

Low-Frequency

Crystal Oscillator

System Clock

Prescaler



PLL

Oscillator

clk

PCK

clk

PCK

ATtiny25/45/85

The I/O space definition of the ATtiny25/45/85 is shown in “Register Summary” on page 179.

All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 30. The clock systems are detailed below.

Figure 6-1. Clock Distribution

7598G–AVR–03/08

6.1.1 CPU Clock – clk

CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

6.1.2 I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

6.1.3 Flash Clock – clk

FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

6.1.4 ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

6.1.5 Internal PLL for Fast Peripheral Clock Generation - clk

The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a source input. The source of the PLL input clock is the output of the internal RC oscillator having a frequency of 8.0 MHz. Thus the output of the PLL, the fast peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for Timer/Counter1. See the Figure 6-2 on page 23.

The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this case is not locked any longer with the RC oscillator clock.

PCK

Therefore, it is recommended not to take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only when the PLLE bit in PLLCSR is set or the PLLCK fuse is programmed (‘0’). The bit PLOCK from PLLCSR is set when PLL is locked.

Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.

ATtiny25/45/85

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Figure 6-2. PCK Clocking System

8.0 MHz / 6.4 MHz

RC OSCILLATOR

OSCCAL

XTAL1

XTAL2

OSCILLATORS

DIVIDE

BY 4

SYSTEM

CLOCK

PLL

8x / 4x

PLLCK & CKSEL FUSES

PLLE

PCK

Lock 

Detector

PLOCK

64 / 25.6 MHz

System 

Clock

Prescaler

CLKPS3..0

ATtiny25/45/85

6.2 Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 6-1. Device Clocking Options Select

Device Clocking Option CKSEL3..0

External Clock 0000

PLL Clock 0001

Calibrated Internal RC Oscillator 8.0 MHz 0010

Watchdog Oscillator 128 kHz 0100

External Low-frequency Crystal 0110

External Crystal/Ceramic Resonator 1000-1111

Reserved 0101, 0111, 0011

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the startup, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-

(1)

7598G–AVR–03/08

Table 6-2. Number of Watchdog Oscillator Cycles

XTAL2

XTAL1

GND

6.3 Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at 8 MHz with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer.

6.4 Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-3. Either a quartz crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 6-3. For ceramic resonators, the capacitor values given by the manufacturer should be used.

Typ Time-out Number of Cycles

4 ms 512

64 ms 8K (8,192)

Figure 6-3. Crystal Oscillator Connections

The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-3.

Table 6-3. Crystal Oscillator Operating Modes

CKSEL3..1 Frequency Range (MHz)

(1)

100

101 0.9 - 3.0 12 - 22

110 3.0 - 8.0 12 - 22

111 8.0 - 12 - 22

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

6-4.

ATtiny25/45/85

Recommended Range for Capacitors C1 and

C2 for Use with Crystals (pF)

0.4 - 0.9 –

7598G–AVR–03/08

ATtiny25/45/85

Table 6-4. Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

CKSEL0 SUT1..0

0 00 258 CK

0 01 258 CK

0 10 1K CK

0 11 1K CK

1 00 1K CK

Power-save

(1)

(2)

1 01 16K CK 14CK

1 10 16K CK 14CK + 4 ms

1 11 16K CK 14CK + 64 ms

Additional Delay

from Reset

(VCC = 5.0V) Recommended Usage

14CK + 4 ms

14CK + 64 ms

14CK

14CK + 4 ms

14CK + 64 ms

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Crystal Oscillator, BOD enabled

Crystal Oscillator, fast rising power

Crystal Oscillator, slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

6.5 Low-frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL fuses to ‘0110’. The crystal should be connected as shown in Figure 6-3. Refer to the 32 kHz Crystal Oscillator Application Note for details on oscillator operation and how to choose appropriate values for C1 and C2.

When this oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 6-5.

Table 6-5. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

Start-up Time from

Power Down and Power

SUT1..0

00 1K CK

01 1K CK

10 32K CK 64 ms Stable frequency at start-up

11 Reserved

Notes: 1. These options should only be used if frequency stability at start-up is not important for the

application.

Save

Additional Delay from

Power On Reset

(VCC = 5.0V) Recommended usage

(1)

4 ms

64 ms Slowly rising power

Fast rising power or BOD enabled

7598G–AVR–03/08

6.6 Calibrated Internal RC Oscillator

The calibrated internal RC Oscillator provides an 8.0 MHz clock. The frequency is the nominal value at 3V and 25°C. If the frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 during start-up. “System Clock Prescaler” on page 29. for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6-6. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration gives a frequency within ± 1% of the nominal frequency. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section

“Calibration Byte” on page 132.

Table 6-6. Internal Calibrated RC Oscillator Operating Modes

CKSEL3..0 Nominal Frequency

(1)

0010

Note: 1. The device is shipped with this option selected.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-7.

Table 6-7. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

8.0 MHz

Start-up Time

SUT1..0

00 6 CK 14CK + 4 ms BOD enabled

01 6 CK 14CK + 4 ms Fast rising power

(1)

11 Reserved

Note: 1. The device is shipped with this option selected.

from Power-down

6 CK 14CK + 64 ms Slowly rising power

6.6.1 Oscillator Calibration Register – OSCCAL

Bit 7 6 5 4 3 2 1 0

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value Device Specific Calibration Value

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. This is done automatically during Chip Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal Oscillator. Writing 0xFF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 8.8 MHz frequency. Otherwise, the EEPROM or Flash write may fail.

Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

EXTERNAL

CLOCK

SIGNAL

CLKI

GND

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1 MHz.

Avoid changing the calibration value in large steps when calibrating the calibrated internal RC Oscillator to ensure stable operation of the MCU. A variation in frequency of more than 2% from one cycle to the next can lead to unpredicatble behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency

Table 6-8. Internal RC Oscillator Frequency Range

6.7 External Clock

Min Frequency in Percentage of

OSCCAL Value

0x00 50% 100%

0x3F 75% 150%

0x7F 100% 200%

Nominal Frequency

Max Frequency in Percentage of

Nominal Frequency

To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-

4. To run the device on an external clock, the CKSEL Fuses must be programmed to “00”.

Figure 6-4. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-9.

7598G–AVR–03/08

Table 6-9. Start-up Times for the External Clock Selection

Start-up Time from Power-

SUT1..0

00 6 CK 14CK BOD enabled

01 6 CK 14CK + 4 ms Fast rising power

10 6 CK 14CK + 64 ms Slowly rising power

11 Reserved

down and Power-save

Additional Delay from

Reset Recommended Usage

Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

29 for details.

6.7.1 High Frequency PLL Clock - PLL

There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like shown in Table 6-10. When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-11. See also “PCK Clocking System” on page 23.

Table 6-10. PLLCK Operating Modes

CKSEL3..0 Nominal Frequency

0001 16 MHz

Table 6-11. Start-up Times for the PLLCK

CLK

SUT1..0

00 1K CK 14CK + 8ms BOD enabled

01 16K CK 14CK + 8ms Fast rising power

10 1K CK 14CK + 68 ms Slowly rising power

11 16K CK 14CK + 68 ms Slowly rising power

6.8 128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequ ency is nominal at 3V and 25 °C. This clock may be select as the sy stem clo ck by programming the CKSEL Fuses to “11”.

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-12.

Table 6-12. Start-up Times for the 128 kHz Internal Oscillator

SUT1..0

00 6 CK 14CK BOD enabled

01 6 CK 14CK + 4 ms Fast rising power

10 6 CK 14CK + 64 ms Slowly rising power

Start-up Time from Power

Down and Power Save

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (VCC = 5.0V) Recommended usage

Additional Delay from

Reset Recommended Usage

11 Reserved

6.9 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not be output during reset and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.

ATtiny25/45/85

7598G–AVR–03/08

6.10 System Clock Prescaler

The ATtiny25/45/85 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk are divided by a factor as shown in Table 6-13.

6.10.1 Clock Prescale Register – CLKPR

Bit 7 6 5 4 3 2 1 0

CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

ATtiny25/45/85

I/O

, clk

ADC

, clk

, and clk

CPU

FLASH

• Bits 6..4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-13.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of eight at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selcted clock source has a higher frequency than the maximum frequency of the

7598G–AVR–03/08

device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 6-13. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0 0 0 0 1

0 0 0 1 2

0 0 1 0 4

0 0 1 1 8

0 1 0 0 16

0 1 0 1 32

0 1 1 0 64

0 1 1 1 128

1 0 0 0 256

1 0 0 1 Reserved

1 0 1 0 Reserved

1 0 1 1 Reserved

1 1 0 0 Reserved

1 1 0 1 Reserved

1 1 1 0 Reserved

1 1 1 1 Reserved

6.10.2 Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

7. Power Management and Sleep Modes

The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications.

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

ATtiny25/45/85

7598G–AVR–03/08

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruction. See Table 7-1 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

Figure 6-1 on page 21 presents the different clock systems in the ATtiny25/45/85, and their dis-

tribution. The figure is helpful in selecting an appropriate sleep mode.

7.0.1 MCU Control Register – MCUCR

The MCU Control Register contains control bits for power management.

Bit 7 6 5 4 3 2 1 0

BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – BODS: BOD Sleep BOD disable functionality is available in some devices, only. See “Limitations” on page 33.

ATtiny25/45/85

In order to disable BOD during sleep (see Table 7-2 on page 33) the BODS bit must be written to logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First,both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.

In devices where Sleeping BOD has not been implemented this bit is unused and will always read zero.

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.

• Bits 4, 3 – SM1..0: Sleep Mode Select Bits 2..0

These bits select between the three available sleep modes as shown in Table 7-1.

Table 7-1. Sleep Mode Select

SM1 SM0 Sleep Mode

0 0 Idle

0 1 ADC Noise Reduction

7598G–AVR–03/08

1 0 Power-down

1 1 Stand-by mode

• Bit 2 – BODSE: BOD Sleep Enable

BOD disable functionality is available in some devices, only. See “Limitations” on page 33.

The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is controlled by a timed sequence.

This bit is unused in devices where software BOD disable has not been implemented and will read as zero in those devices.

7.1 Idle Mode

When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

7.2 ADC Noise Reduction Mode

When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clk while allowing the other clocks to run.

I/O

CPU

, clk

and clk

, and clk

CPU

FLASH

, while

FLASH

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.

7.3 Power-down Mode

When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only.

ATtiny25/45/85

7598G–AVR–03/08

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 58 for details..

Table 7-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes

Active Clock Domains Oscillators Wake-up Sources

ATtiny25/45/85

CPU

Sleep Mode

Idle X X X X X X X X X X

ADC Noise Reduction

Power-down X

clk

FLASH

clk

Note: 1. For INT0, only level interrupt.

clk

ADC

clk

X X X

PCK

clk

Main Clock

Source Enabled

INT0 and

Pin Change

SPM/

EEPROM

Ready

USI Start Condition

ADC

Other I/O

(1)

X X X X

X X

7.4 Limitations

BOD disable functionality has been implemented in the following devices, only:

•

ATtiny25, revision D, and newer

•

ATtiny45, revision D, and newer

•

ATtiny85, revision C, and newer

7.5 Power Reduction Register

The Power Reduction Register, PRR, provides a method to stop the clock to individualperipherals to reduce power consumption. The current state of the peripheral is frozenand the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Watchdog

Interrupt

7598G–AVR–03/08

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped.

Bit 7 6 5 4 3 2 1 0

– - - - PRTIM1 PRTIM0 PRUSI PRADC PRR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7, 6, 5, 4- Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 3- PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.

• Bit 2- PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.

• Bit 1 - PRUSI: Power Reduction USI

Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

7.6 Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

7.6.1 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 107 for details on ADC operation.

7.6.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep m odes. Oth erwise, the Internal Vo ltage Reference will be enable d, independent of sleep mode. Refer to “Analog Comparator” on page 104 for details on how to configure the Analog Comparator.

7.6.3 Brown-out Detector

If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 38 for details on how to configure the Brown-out Detector.

7.6.4 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 40 for details on the start-up time.

ATtiny25/45/85

7598G–AVR–03/08

7.6.5 Watchdog Timer

7.6.6 Port Pins

ATtiny25/45/85

If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 41 for details on how to configure the Watchdog Timer.

When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 51 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to VCC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to

“Digital Input Disable Register 0 – DIDR0” on page 107 for details.

) and the ADC clock (clk

I/O

) are stopped, the input buffers of the device

ADC

8. System Control and Reset

8.0.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic. Table 8-1 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 23.

8.0.2 Reset Sources

The ATtiny25/45/85 has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer

than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out

Reset threshold (V

POT

) and the Brown-out Detector is enabled.

BOT

7598G–AVR–03/08

Figure 8-1. Reset Logic

MCU Status

Brown-out

Reset Circuit

BODLEVEL [1..0]

Delay Counters

CKSEL[1:0]

TIMEOUT

WDRF

BORF

EXTRF

PORF

DATA BUS

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

8.0.3 Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 8-1. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level.

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

RESET

TIME-OUT

INTERNAL

RESET

TOUT

RST

PORMAX

CCRR

PORMIN

RESET

TIM E- O UT

INTERN AL

RESET

TOUT

RST

POT

Figure 8-2. MCU Start-up, RESET Tied to V

Figure 8-3. MCU Start-up, RESET Extended Externally

8.0.4 External Reset

7598G–AVR–03/08

Table 8-1. Power On Reset Specifications

Symbol Parameter Min Typ Max Units

Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.7 V

POT

PORMAX

PORMIN

CCRR

RST

Power-on Reset Threshold Voltage (falling)

VCC Max. start voltage to ensure internal Poweron Reset signal

VCC Min. start voltage to ensure internal Poweron Reset signal

VCC Rise Rate to ensure Power-on Reset 0.01 V/ms

RESET Pin Threshold Voltage 0.1 V

Note: 1. Before rising the supply has to be between V

(1)

PORMIN

0.8 1.3 1.6 V

-0.1 V

0.9V

and V

PORMAX

to ensure Reset.

0.4 V

An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see Table 8-1) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V after the Time-out period – t

TOUT –

– on its positive edge, the delay counter starts the MCU

RST

has expired.

Figure 8-4. External Reset During Operation

8.0.5 Brown-out Detection

ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V V

BOT

Table 8-2. BODLEVEL Fuse Coding

+ V

HYST

/2 and V

BOT-

= V

BOT

- V

HYST

/2.

(1)

BOT+

BODLEVEL [2..0] Fuses Min V

BOT

Typ V

BOT

Max V

BOT

Units

111 BOD Disabled

110 1.7 1.8 2.0

101 2.5 2.7 2.9

100 4.0 4.3 4.6

(2)

during the production test. This guar-

BOT

Note: 1. V

011 2.3

010 2.2

001 1.9

000 2.0

may be below nominal minimum operating voltage for some devices. For devices where

BOT

this is the case, the device is tested down to VCC = V antees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed.

2. Centered value, not tested.

Table 8-3. Brown-out Characteristics

Symbol Parameter Min Typ Max Units

BOD

RAM

HYST

RAM Retention Voltage

Brown-out Detector Hysteresis 50 mV

Min Pulse Width on Brown-out Reset 2 µs

(1)

50 mV

Notes: 1. This is the limit to which VDD can be lowered without losing RAM data

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

RESET

TIME-OUT

INTERNAL

RESET

BOT-

BOT+

TOUT

8.0.6 Watchdog Reset

When the BOD is enabled, and VCC decreases to a value below the trigger level (V

in Figure

BOT-

8-5), the Brown-out Reset is immediately activated. When VCC increases above the trigger level

in Figure 8-5), the delay counter starts the MCU after the Time-out period t

BOT+

TOUT

has

expired.

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than t

given in Table 8-1.

BOD

Figure 8-5. Brown-out Reset During Operation

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT

. Refer to

page 41 for details on operation of the Watchdog Timer.

Figure 8-6. Watchdog Reset During Operation

8.0.7 MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU Reset.

Bit 7 6 5 4 3 2 1 0

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

• Bits 7..4 – Res: Reserved Bits

– – – – WDRF BORF EXTRF PORF MCUSR

7598G–AVR–03/08

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

8.1 Internal Voltage Reference

ATtiny25/45/85 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.

8.1.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 8-4. To save power, the reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse bits).

2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

Table 8-4. Internal Voltage Reference Characteristics

Symbol Parameter Condition Min Typ Max Units

Bandgap reference voltage

Bandgap reference start-up time

Bandgap reference current consumption

VCC = 1.1V / 2.7V,

TA = 25°C

VCC = 2.7V,

TA = 25°C

VCC = 2.7V,

TA = 25°C

1.0 1.1 1.2 V

40 70 µs

15 µA

ATtiny25/45/85

7598G–AVR–03/08

8.2 Watchdog Timer

OSC/2K

OSC/4K

OSC/8K

OSC/16K

OSC/32K

OSC/64K

OSC/128K

OSC/256K

OSC/512K

OSC/1024K

MCU RESET

WATCHDOG

PRESCALER

128 kHz

OSCILLATOR

WATCHDOG

RESET

WDP0 WDP1 WDP2 WDP3

WDE

The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table

8-7 on page 43. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The

Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 8-7 on page 43.

The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-5. Refer to

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 44 for

details.

Table 8-5. WDT Configuration as a Function of the Fuse Settings of WDTON

ATtiny25/45/85

Safety

WDTON

Level

Unprogrammed 1 Disabled Timed sequence No limitations

Programmed 2 Enabled Always enabled Timed sequence

Figure 8-7. Watchdog Timer

8.2.1 Watchdog Timer Control Register – WDTCR

Bit 7 6 5 4 3 2 1 0

WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X 0 0 0

WDT Initial State

How to Disable the WDT

How to Change Timeout

7598G–AVR–03/08

• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable

When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs.

If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt.

Table 8-6. Watchdog Timer Configuration

WDE WDIE Watchdog Timer State Action on Time-out

0 0 Stopped None

0 1 Running Interrupt

1 0 Running Reset

1 1 Running Interrupt

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. “Timed Sequences for Changing the Configuration of the Watchdog

Timer” on page 44.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. “Timed Sequences for Changing the Configuration of the Watchdog Timer” on

page 44.

In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCU Status Register –

MCUSR” on page 39 for description of WDRF. This means that WDE is always set when WDRF

is set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.

Note: If the watchdog timer is not going to be used in the application, it is important to go through a

watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. To avoid this situation, the application software should always clear the WDRF flag and the WDE control bit in the initialization routine.

• Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in

Table 8-7.

Table 8-7. Watchdog Timer Prescale Select

Number of WDT Oscillator

WDP3 WDP2 WDP1 WDP0

0 0 0 0 2K cycles 16 ms

0 0 0 1 4K cycles 32 ms

0 0 1 0 8K cycles 64 ms

0 0 1 1 16K cycles 0.125 s

0 1 0 0 32K cycles 0.25 s

0 1 0 1 64K cycles 0.5 s

0 1 1 0 128K cycles 1.0 s

0 1 1 1 256K cycles 2.0 s

1 0 0 0 512K cycles 4.0 s

1 0 0 1 1024K cycles 8.0 s

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Cycles

Reserved

Typical Time-out at

VCC = 5.0V

(1)

Note: 1. If selected, one of the valid settings below 0b1010 will be used.

7598G–AVR–03/08

The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

WDT_off:

WDR

; Clear WDRF in MCUSR

ldi r16, (0<<WDRF)

out MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional Watchdog

Reset

in r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example

(1)

void WDT_off(void)

{

_WDR();

/* Clear WDRF in MCUSR */

MCUSR = 0x00

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

Note: 1. The example code assumes that the part specific header file is included.

8.3 Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level.

8.3.1 Safety Level 1

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared.

ATtiny25/45/85

7598G–AVR–03/08

8.3.2 Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence.

2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

9. Interrupts

This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”

on page 11.

9.1 Interrupt Vectors in ATtiny25/45/85

Table 9-1. Reset and Interrupt Vectors

ATtiny25/45/85

Vector

No.

1 0x0000 RESET

2 0x0001 INT0 External Interrupt Request 0

3 0x0002 PCINT0 Pin Change Interrupt Request 0

4 0x0003 TIM1_COMPA Timer/Counter1 Compare Match A

5 0x0004 TIM1_OVF Timer/Counter1 Overflow

6 0x0005 TIM0_OVF Timer/Counter0 Overflow

7 0x0006 EE_RDY EEPROM Ready

8 0x0007 ANA_COMP Analog Comparator

9 0x0008 ADC ADC Conversion Complete

10 0x0009 TIM1_COMPB Timer/Counter1 Compare Match B

11 0x000A TIM0_COMPA Timer/Counter0 Compare Match A

12 0x000B TIM0_COMPB Timer/Counter0 Compare Match B

13 0x000C WDT Watchdog Time-out

14 0x000D USI_START USI START

15 0x000E USI_OVF USI Overflow

Program Address Source Interrupt Definition

External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset

If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny25/45/85 is:

7598G–AVR–03/08

Address Labels Code Comments

0x0000 rjmp RESET ; Reset Handler

0x0001 rjmp EXT_INT0 ; IRQ0 Handler

0x0002 rjmp PCINT0 ; PCINT0 Handler

10. I/O Ports

0x0003 rjmp TIM1_COMPA ; Timer1 CompareA Handler

0x0004 rjmp TIM1_OVF ; Timer1 Overflow Handler

0x0005 rjmp TIM0_OVF ; Timer0 Overflow Handler

0x0006 rjmp EE_RDY ; EEPROM Ready Handler

0x0007 rjmp ANA_COMP ; Analog Comparator Handler

0x0008 rjmp ADC ; ADC Conversion Handler

0x0009 rjmp TIM1_COMPB ; Timer1 CompareB Handler

0x000A rjmp TIM0_COMPA ;

0x000B rjmp TIM0_COMPB ;

0x000C rjmp WDT ;

0x000D rjmp USI_START ;

0x000E rjmp USI_OVF ;

0x000F RESET: ldi r16, low(RAMEND); Main program start

0x0010 ldi r17, high(RAMEND); Tiny85 has also SPH

0x0011 out SPL, r16 ; Set Stack Pointer to top of RAM

0x0012 out SPH, r17 ; Tiny85 has also SPH

0x0013 sei ; Enable interrupts

0x0014 <instr> xxx

... ... ... ...

10.1 Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 10-1. Refer to “Electrical Char-

acteristics” on page 147 for a complete list of parameters.

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

Logic

See Figure

"General Digital I/O" for

Details

Pxn

Figure 10-1. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 57.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

47. Most port pins are multiplexed with alternate functions for the peripheral features on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 52. Refer to the individual module sections for a full description of the alter-

nate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.

10.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn.

7598G–AVR–03/08

Figure 10-2. General Digital I/O

clk

RPx

RRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

DLQ

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BUS

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

WPx

WRx

WPx: WRITE PINx REGISTER

(1)

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

10.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description for I/O-Ports” on page 57, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

10.2.2 Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

SLEEP, and PUD are common to all ports.

I/O

ATtiny25/45/85

7598G–AVR–03/08

10.2.3 Switching Between Input and Output

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value.

Table 10-1. Port Pin Configurations

DDxn PORTxn

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled low.

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

ATtiny25/45/85

PUD

(in MCUCR) I/O Pull-up Comment

10.2.4 Reading the Pin Value

1 1 X Output No Output High (Source)

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t

pd,max

and t

respectively.

pd,min

Figure 10-3. Synchronization when Reading an Externally Applied Pin value

7598G–AVR–03/08

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period.

Figure 10-4. Synchronization when Reading a Software Assigned Pin Value

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

ATtiny25/45/85

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ATtiny25/45/85

Assembly Code Example

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB4)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

(1)

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

10.2.5 Digital Input Enable and Sleep Modes

As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 52.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

7598G–AVR–03/08

10.2.6 Unconnected Pins

clk

RPx

RRx

WRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

DLQ

SET

CLR

DIxn

AIOxn

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VAL UE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VAL UE

DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

RESET

CLR

PINxn

PORTxn

DDxn

DATA BUS

DIEOVxn

SLEEP

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL

Pxn

I/O

PTOExn

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

WPx: WRITE PINx

WPx

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.

10.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5 shows how the port pin control signals from the simplified Figure 10-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

(1)

Figure 10-5. Alternate Port Functions

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

I/O

Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally

in the modules having the alternate function.

Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.

If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.

If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.

If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.

PUOE

PUOV

DDOE

DDOV

PVOE

Pull-up Override Enable

Pull-up Override Value

Data Direction Override Enable

Data Direction Override Value

Port Value Override Enable

PVOV

PTOE

DIEOE

DIEOV

DI Digital Input

AIO

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

10.3.1 MCU Control Register – MCUCR

Bit 7 6 5 4 3 2 1 0

BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR

Port Value Override Value

Port Toggle Override Enable

Digital Input Enable Override Enable

Digital Input Enable Override Value

Analog Input/Output

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode).

If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt-trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.

This is the Analog Input/Output to/from alternate functions. The signal is connected directly to the pad, and can be used bidirectionally.

7598G–AVR–03/08

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 6 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 48 for more details about this feature.

10.3.2 Alternate Functions of Port B

The Port B pins with alternate function are shown in Table 10-3.

Table 10-3. Port B Pins Alternate Functions

Port Pin Alternate Function

PB5 RESET / dW / ADC0 / PCINT5

PB4 XTAL2 / CLKO / ADC2 / OC1B / PCINT4

PB3 XTAL1 / ADC3 / OC1B / PCINT3

PB2 SCK / ADC1 / T0 / USCK / SCL / INT0 / PCINT2

PB1 MISO / AIN1 / OC0B / OC1A / DO / PCINT1

PB0 MOSI / AIN0 / OC0A / OC1A / DI / SDA / AREF / PCINT0

Notes: 1. Reset Pin, debugWIRE I/O, ADC Input Channel or Pin Change Interrupt.

2. XOSC Output, Divided System Clock Output, ADC Input Channel, Timer/Counter1 Output Compare and PWM Output B, or Pin Change Interrupt.

3. XOSC Input / External Clock Input, ADC Input Channel, Timer/Counter1 Inverted Output Compare and PWM Output B, or Pin Change Interrupt.

4. Serial Clock Input, ADC Input Channel, Timer/Counter Clock Input, USI Clock (three-wire mode), USI Clock (two-wire mode), External Interrupt, or Pin Change Interrupt.

5. Serial Data Input, Analog Comparator Negative Input, Timer/Counter0 Output Compare and PWM Output B, Timer/Counter1 Output Compare and PWM Output A, USI Data Output (threewire mode), or Pin Change Interrupt.

6. Serial Data Output, Analog Comparator Positive Input, Timer/Counter0 Output Compare and PWM Output A, Timer/Counter1 Inverted Output Compare and PWM Output A, USI Data Input (three-wire mode), USI Data (two-wire mode), Voltage Ref., or Pin Change Interrupt.

(1)

(2)

(3)

(4)

(5)

(6)

• Port B, Bit 5 - RESET/dW/ADC0/PCINT5

RESET: External Reset input is active low and enabled by unprogramming (“1”) the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin.

dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator.

ADC0: Analog to Digital Converter, Channel 0

PCINT5: Pin Change Interrupt source 5.

• Port B, Bit 4- XTAL2/CLKO/ADC2/OC1B/PCINT4

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator or External clock as a Chip clock sources, PB4 serves as an ordinary I/O pin.

CLKO: The devided system clock can be output on the pin PB4. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB4 and DDB4 settings. It will also be output during reset.

ADC2: Analog to Digital Converter, Channel 2

OC1B: Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB4 set). The OC1B pin is also the output pin for the PWM mode timer function.

PCINT4: Pin Change Interrupt source 4.

• Port B, Bit 3 - XTAL1/ADC3/OC1B/PCINT3

XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal calibrateble RC oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

ADC3: Analog to Digital Converter, Channel 3

OC1B: Inverted Output Compare Match output: The PB3 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB3 set). The OC1B pin is also the inverted output pin for the PWM mode timer function.

PCINT3: Pin Change Interrupt source 3.

• Port B, Bit 2 - SCK/ADC1/T0/USCK/SCL/INT0/PCINT2

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDPB2. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.

7598G–AVR–03/08

ADC1: Analog to Digital Converter, Channel 1

T0: Timer/Counter0 counter source.

USCK: Three-wire mode Universal Serial Interface Clock.

SCL: Two-wire mode Serial Clock for USI Two-wire mode.

INT0: External Interrupt source 0.

PCINT2: Pin Change Interrupt source 2.

• Port B, Bit 1 - MISO/AIN1/OC0B/OC1A/DO/PCINT1

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB1. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB1 bit.

AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.

OC0B: Output Compare Match output. The PB1 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.

OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin is also the output pin for the PWM mode timer function.

DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output overrides PORTB1 value and it is driven to the port when data direction bit DDB1 is set (one). PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one).

PCINT1: Pin Change Interrupt source 1.

• Port B, Bit 0 - MOSI/AIN0/OC0A/OC1A/DI/SDA/AREF/PCINT0

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB0 bit.

AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.

OC0A: Output Compare Match output. The PB0 pin can serve as an external output for the Timer/Counter0 Compare Match A when configured as an output (DDB0 set (one)). The OC0A pin is also the output pin for the PWM mode timer function.

OC1A: Inverted Output Compare Match output: The PB0 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB0 set). The OC1A pin is also the inverted output pin for the PWM mode timer function.

SDA: Two-wire mode Serial Interface Data.

AREF: External Analog Reference for ADC. Pullup and output driver are disabled on PB0 when the pin is used as an external reference or Internal Voltage Reference with external capacitor at the AREF pin.

DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function.

PCINT0: Pin Change Interrupt source 0.

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

Table 10-4 and Table 10-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 52.

Table 10-4. Overriding Signals for Alternate Functions in PB5..PB3

Signal Name

PUOE RSTDISBL

PUOV 1 0 0

DDOE RSTDISBL

DDOV debugWire Transmit 0 0

PVOE 0 OC1B Enable _OC1B Enable

PVOV 0 OC1B _OC1B

PTOE 0 0 0

DIEOE

DIEOV ADC0D ADC2D ADC3D

DI PCINT5 Input PCINT4 Input PCINT3 Input

AIO RESET Input, ADC0 Input ADC2 Input ADC3 Input

Note: 1. 1 when the Fuse is “0” (Programmed).

PB5/RESET/ ADC0/PCINT5

(1)

• DWEN

(1)

• DWEN

RSTDISBL PCIE + ADC0D)

(1)

+ (PCINT5 •

PB4/ADC2/XTAL2/ OC1B/PCINT4

(1)

0 0

PCINT4 • PCIE + ADC2D PCINT3 • PCIE + ADC3D

PB3/ADC3/XTAL1/ _OC1B/PCINT3

Table 10-5. Overriding Signals for Alternate Functions in PB3..PB0

PB0/MOSI/DI/SDA/AIN0/AR Signal Name

PUOE 0 0 0

PB2/SCK/ADC1/T0/ USCK/SCL/INT0/PCINT2

PB1/MISO/DO/AIN1/ OC1A/OC0B/PCINT1

EF/_OC1A/OC0A/

PCINT0

PUOV 0 0 0

DDOE USI_TWO_WIRE 0 USI_TWO_WIRE

DDOV

PVOE USI_TWO_WIRE • DDB2

PVOV 0 OC0B + OC1A + DO OC0A + _OC1A

PTOE USITC 0 0

DIEOE

DIEOV ADC1D AIN1D AIN0D

AIO ADC1 Input

(USI_SCL_HOLD + PORTB2) • DDB2

PCINT2 • PCIE + ADC1D + USISIE

T0/USCK/SCL/INT0/ PCINT2 Input

10.4 Register Description for I/O-Ports

7598G–AVR–03/08

0 (SDA + PORTBO) • DDB0

OC0B Enable + OC1A Enable + USI_THREE_WIRE

PCINT1 • PCIE + AIN1D

PCINT1 Input DI/SDA/PCINT0 Input

Analog Comparator Negative Input

OC0A Enable + _OC1A

Enable + (USI_TWO_WIRE

• DDB0)

PCINT0 • PCIE + AIN0D +

USISIE

Analog Comparator Positive

Input

10.4.1 Port B Data Register – PORTB

Bit 7 6 5 4 3 2 1 0

– – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

10.4.2 Port B Data Direction Register – DDRB

Bit 7 6 5 4 3 2 1 0

– –

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

10.4.3 Port B Input Pins Address – PINB

Bit 7 6 5 4 3 2 1 0

– –

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 N/A N/A N/A N/A N/A N/A

11. External Interrupts

The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change interrupts PCI will trigger if any enabled PCINT5..0 pin toggles. The PCMSK Register control which pins contribute to the pin change inter rupts. Pin change interrupts on PCINT5..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.

DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 21. Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 21.

11.0.1 MCU Control Register – MCUCR

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit 7 6 5 4 3 2 1 0

BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

ATtiny25/45/85

7598G–AVR–03/08

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 11-1. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

Table 11-1. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Any logical change on INT0 generates an interrupt request.

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

11.0.2 General Interrupt Mask Register – GIMSK

Bit 7 6 5 4 3 2 1 0

– INT0 PCIE – – – – – GIMSK

Read/Write R R/W R/W R R R R R

Initial Value 0 0 0 0 0 0 0 0

ATtiny25/45/85

• Bits 7, 4..0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.

• Bit 5 – PCIE: Pin Change Interrupt Enable When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt Vector. PCINT5..0 pins are enabled individually by the PCMSK0 Register.

11.0.3 General Interrupt Flag Register – GIFR

Bit 7 6 5 4 3 2 1 0

– INTF0 PCIF – – – – – GIFR

Read/Write R R/W R/W R R R R R

Initial Value 0 0 0 0 0 0 0 0

7598G–AVR–03/08

• Bits 7, 4..0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.

• Bit 5 – PCIF: Pin Change Interrupt Flag

When a logic change on any PCINT5..0 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

11.0.4 Pin Change Mask Register – PCMSK

Bit 7 6 5 4 3 2 1 0

– – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 1 1 1 1 1 1

• Bits 7, 6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bits 5..0 – PCINT5..0: Pin Change Enable Mask 5..0

Each PCINT5..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT5..0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT5..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

12. 8-bit Timer/Counter0 with PWM

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are:

•

Two Independent Output Compare Units

•

Double Buffered Output Compare Registers

•

Clear Timer on Compare Match (Auto Reload)

•

Glitch Free, Phase Correct Pulse Width Modulator (PWM)

•

Variable PWM Period

•

Frequency Generator

•

Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

12.1 Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 12-1. For the actual placement of I/O pins, refer to “Pinout ATtiny25/45/85” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on page 71.

ATtiny25/45/85

7598G–AVR–03/08

Figure 12-1. 8-bit Timer/Counter Block Diagram

Clock Select

Timer/Counter

DATA BUS

OCRnA

OCRnB

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Fixed

TOP

Val ue

Control Logic

= 0

TOP BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

TCCRnA TCCRnB

Edge

Detector

( From Prescaler )

clk

ATtiny25/45/85

12.1.1 Registers

12.1.2 Definitions

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).

The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). “Output Compare Unit” on page 63. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request.

Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit def i n es i n a prog r am, t h e pr ec ise f or m mu st b e us e d, i . e . , TCNT0 f o r ac c e ssing Timer/Counter0 counter value and so on.

7598G–AVR–03/08

The definitions in Table 34 are also used extensively throughout the document.

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation.

12.2 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 77.

12.3 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

12-2 shows a block diagram of the counter and its surroundings.

Figure 12-2. Counter Unit Block Diagram

Signal description (internal signals):

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter

ATtiny25/45/85

count Increment or decrement TCNT0 by 1.

direction Select between increment and decrement.

clear Clear TCNT0 (set all bits to zero).

clk

Timer/Counter clock, referred to as clkT0 in the following.

top Signalize that TCNT0 has reached maximum value.

bottom Signalize that TCNT0 has reached minimum value (zero).

7598G–AVR–03/08

Control Register B (TCCR0B). There are close connections between how the counter behaves

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnX1:0

bottom

(counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see “Modes of Opera-

tion” on page 65.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

12.4 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 65.).

Figure 12-3 shows a block diagram of the Output Compare unit.

ATtiny25/45/85

Figure 12-3. Output Compare Unit, Block Diagram

The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

7598G–AVR–03/08

The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly.

12.4.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled).

12.4.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled.

12.4.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting.

The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately.

12.5 Compare Match Output Unit

The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 12-4 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”.

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

PORT

DDR

D Q

OCn

OCnx

D Q

Waveform Generator

COMnx1

COMnx0

DATA BUS

FOCn

clk

I/O

Figure 12-4. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. “8-bit Timer/Counter Register Description” on page 71.

12.5.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 12-1 on page 72. For fast PWM mode, refer to Table 12-2 on

page 72, and for phase correct PWM refer to Table 12-3 on page 72.

A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.

12.6 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (“Compare Match Output Unit” on page 64.).

For detailed timing information refer to Figure 12-8, Figure 12-9, Figure 12-10 and Figure 12-11 in “Timer/Counter Timing Diagrams” on page 70.

7598G–AVR–03/08

12.6.1 Normal Mode

TCNTn

OCn (Toggle)

OCnx Interrupt Flag Set

1 4

Period

2 3

(COMnx1:0 = 1)

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

12.6.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 12-5. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.

Figure 12-5. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

OC nx

clk_I/O

2 N 1 OCRn x+( )⋅ ⋅

--------------------------------------------------=

TCNTn

OCRnx Update and TOVn Interrupt Flag Set

Period

2 3

OCn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

4 5 6 7

12.6.3 Fast PWM Mode

the pin is set to output. The waveform generated will have a maximum frequency of f f

/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

clk_I/O

OC0

equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00.

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In noninverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.

Figure 12-6. Fast PWM Mode, Timing Diagram

7598G–AVR–03/08

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.

OC nxPW M

clk_I/O

N 256⋅

------------------=

Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allowes the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 12-2 on page 72). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f

OC0

= f

/2 when OCR0A is set to zero. This

clk_I/O

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.

12.6.4 Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In noninverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 12-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.

ATtiny25/45/85

7598G–AVR–03/08

Figure 12-7. Phase Correct PWM Mode, Timing Diagram

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

1 2 3

TCNTn

Period

OCn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

OC nxPC P W M

clk_I/O

N 510⋅

------------------=

ATtiny25/45/85

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 12-3 on page 72). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

7598G–AVR–03/08

At the very start of period 2 in Figure 12-7 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guaratee symmetry around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value from MAX, like in Figure 12-7. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

clk

(clk

I/O

/1)

TOVn

clk

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

TCNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up.

12.7 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 12-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 12-8. Timer/Counter Timing Diagram, no Prescaling

Figure 12-9 shows the same timing data, but with the prescaler enabled.

Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O

/8)

Figure 12-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC

mode and PWM mode, where OCR0A is TOP.

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(clk

I/O

/8)

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f

clk_I/O

/8)

Figure 12-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast

PWM mode where OCR0A is TOP.

Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f

clk_I/O

/8)

12.8 8-bit Timer/Counter Register Description

12.8.1 Timer/Counter Control Register A – TCCR0A

Bit 7 6 5 4 3 2 1 0

COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7:6 – COM01A:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.

7598G–AVR–03/08

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. Table 12-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM).

Table 12-1. Compare Output Mode, non-PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0A disconnected.

0 1 Toggle OC0A on Compare Match

1 0 Clear OC0A on Compare Match

1 1 Set OC0A on Compare Match

Table 12-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

Table 12-2. Compare Output Mode, Fast PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0A disconnected.

0 1

1 0 Clear OC0A on Compare Match, set OC0A at TOP

1 1 Set OC0A on Compare Match, clear OC0A at TOP

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 67 for more details.

WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match.

(1)

Table 12-3 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 12-3. Compare Output Mode, Phase Correct PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1

1 0

WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match.

Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting.

(1)

1 1

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

• Bits 5:4 – COM0B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver.

ATtiny25/45/85

Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting.

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 68 for more details.

7598G–AVR–03/08

ATtiny25/45/85

When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. Table 12-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM).

Table 12-4. Compare Output Mode, non-PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0B disconnected.

0 1 Toggle OC0B on Compare Match

1 0 Clear OC0B on Compare Match

1 1 Set OC0B on Compare Match

Table 12-2 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM

mode.

Table 12-5. Compare Output Mode, Fast PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0B disconnected.

0 1 Reserved

1 0 Clear OC0B on Compare Match, set OC0B at TOP

1 1 Set OC0B on Compare Match, clear OC0B at TOP

Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 67 for more details.

(1)

Table 12-3 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 12-6. Compare Output Mode, Phase Correct PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0B disconnected.

0 1 Reserved

1 0

1 1

Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting.

Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting.

(1)

7598G–AVR–03/08

Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 68 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 12-7. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 65).

Table 12-7. Waveform Generation Mode Bit Description

Timer/Counter Mode of

Mode WGM2 WGM1 WGM0

0 0 0 0 Normal 0xFF Immediate MAX

Operation TOP

Update of

OCRx at

TOV Flag

(1)(2)

Set on

1 0 0 1

2 0 1 0 CTC OCRA Immediate MAX

3 0 1 1 Fast PWM 0xFF TOP MAX

4 1 0 0 Reserved – – –

5 1 0 1

6 1 1 0 Reserved – – –

7 1 1 1 Fast PWM OCRA TOP TOP

Notes: 1. MAX = 0xFF

2. BOTTOM = 0x00

12.8.2 Timer/Counter Control Register B – TCCR0B

Bit 7 6 5 4 3 2 1 0

FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B

Read/Write W W R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

PWM, Phase Correct

0xFF TOP BOTTOM

OCRA TOP BOTTOM

However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.

The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 3 – WGM02: Waveform Generation Mode

See the description in the “Timer/Counter Control Register A – TCCR0A” on page 71.

• Bits 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

Table 12-8. Clock Select Bit Description

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped)

0 0 1 clk

0 1 0 clk

0 1 1 clk

1 0 0 clk

1 0 1 clk

1 1 0 External clock source on T0 pin. Clock on falling edge.

1 1 1 External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.

12.8.3 Timer/Counter Register – TCNT0

Bit 7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.

/(No prescaling)

I/O

/8 (From prescaler)

I/O

/64 (From prescaler)

I/O

/256 (From prescaler)

I/O

/1024 (From prescaler)

I/O

TCNT0[7:0] TCNT0

12.8.4 Output Compare Register A – OCR0A

Bit 7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

7598G–AVR–03/08

OCR0A[7:0] OCR0A

The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin.

12.8.5 Output Compare Register B – OCR0B

Bit 7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin.

12.8.6 Timer/Counter Interrupt Mask Register – TIMSK

Bit 7 6 5 4 3 2 1 0

– OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK

Read/Write R R R R R/W R/W R/W R

Initial Value 0 0 0 0 0 0 0 0

• Bits 7..4, 0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, an d the I-bit in the S tatus Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.

OCR0B[7:0] OCR0B

• Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE 0A bit is written to one , and the I-bit in the St atus Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Matc h in Timer/Counter0 occurs, i.e., when the OCF 0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

Whe n t h e TOIE0 bit is writt en t o o ne, and the I-bit in the S tatus Regis t er is set, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.

12.8.7 Timer/Counter 0 Interrupt Flag Register – TIFR

Bit 7 6 5 4 3 2 1 0

– OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – TIFR

Read/Write R R/W R/W R/W R/W R/W R/W R

Initial Value 0 0 0 0 0 0 0 0

• Bits 7, 0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 4– OCF0A: Output Compare Flag 0 A

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

• Bit 3 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 12-7, “Waveform

Generation Mode Bit Description” on page 74.

13. Timer/Counter Prescaler

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f clock source. The prescaled clock has a frequency of either f f

/1024.

CLK_I/O

13.0.1 Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution.

13.0.2 External Clock Source

An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock ( high period of the internal system clock.

). Alternatively, one of four taps from the prescaler can be used as a

CLK_I/O

/8, f

CLK_I/O

clk

). The latch is transparent in the

I/O

CLK_I/O

/64, f

CLK_I/O

/256, or

7598G–AVR–03/08

The edge detector generates one clk

Tn_sync

(To Clock Select Logic)

Edge DetectorSynchronization

D QD Q

D Q

clk

I/O

PSR10

Clear

clk

I/O

Synchronization

pulse for each positive (CSn2:0 = 7) or negative (CSn2:0

= 6) edge it detects.

Figure 13-1. T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f

ExtClk

< f

/2) given a 50/50% duty cycle. Since the edge detector uses

clk_I/O

sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f

clk_I/O

/2.5.

An external clock source can not be prescaled.

Figure 13-2. Prescaler for Timer/Counter0

13.0.3 General Timer/Counter Control Register – GTCCR

Note: 1. The synchronization logic on the input pins (

Bit 7 6 5 4 3 2 1 0

TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR

T0)

is shown in Figure 13-1.

ATtiny25/45/85

7598G–AVR–03/08

Read/Write R/W R R R R R R R/W

TIMER/COUNTER1 COUNT ENABLE

PSR1

CS10 CS11 CS12

PCK

64/32 MHz

CS13

14-BIT

T/C PRESCALER

T1CK/2

T1CK

T1CK/4

T1CK/8

T1CK/16

T1CK/32

T1CK/64

T1CK/128

T1CK/256

T1CK/512

T1CK/1024

T1CK/2048

T1CK/4096

T1CK/8192

T1CK/16384



S A

PCKE

T1CK

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by hardware, and the Timer/Counter start counting.

• Bit 0 – PSR0: Prescaler Reset Timer/Counter0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.

14. Counter and Compare Units

Figure 14-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchro-

nous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base. The PCKE bit from the PLLCSR register enables the asynchronous mode when it is set (‘1’).

ATtiny25/45/85

14.1 Timer/Counter1

7598G–AVR–03/08

Figure 14-1. Timer/Counter1 Prescaler

In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop, and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop. The clock options are described in Table 14-2 on page 82 and the Timer/Counter1 Control Register, TCCR1. Setting the PSR1 bit in GTCCR register resets the prescaler. The PCKE bit in the PLLCSR register enables the asynchronous mode. The frequency of the fast peripheral clock is 64 MHz (or 32 MHz in Low Speed Mode).

The Timer/Counter1 general operation is described in the asynchronous mode and the operation in the synchronous mode is mentioned only if there are differences between these two modes. Figure 14-2 shows Timer/Counter 1 synchronization register block diagram and synchronization delays in between registers. Note that all clock gating details are not shown in the

figure. The Timer/Counter1 register values go through the internal synchronization registers,

8-BIT DATABUS

OCR1A



OCR1A_SI



TCNT_SO

OCR1B



OCR1B_SI

OCR1C



OCR1C_SI

TCCR1



TCCR1_SI

GTCCR



GTCCR_SI

TCNT1



TCNT1_SI

OCF1A



OCF1A_SI

OCF1B



OCF1B_SI

TOV1



TOV1_SI



TOV1_SO



OCF1B_SO



OCF1A_SO

TCNT1

S  A

PCKE

PCK

IO-registers Input synchronization

registers

Timer/Counter1 Output synchronization

registers

SYNC MODE  ASYNC MODE

1 CK Delay 1/2 CK Delay

1 - 2 PCK Delay 1 PCK Delay ~1 CK Delay No Delay

TCNT1

OCF1A

OCF1B

TOV1

1/2 CK Delay 1 CK Delay

which cause the input synchronization delay, before affecting the counter operation. The registers TCCR1, GTCCR, OCR1A, OCR1B, and OCR1C can be read back right after writing the register. The read back values are delayed for the Timer/Counter1 (TCNT1) register and flags (OCF1A, OCF1B, and TOV1), because of the input and output synchronization.

The Timer/Counter1 features a high resolution and a high accuracy usage with the lower prescaling opportunities. It can also support two accurate, high speed, 8-bit Pulse Width Modulators using cl o ck spe e d s up t o 64 M Hz ( or 32 MHz i n Low Sp ee d Mode) . In th i s mode, Timer/Counter1 and the output compare registers serve as dual stand-alone PWMs with nonoverlapping non-inverted and inverted outputs. Refer to page 87 for a detailed description on this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions.

Figure 14-2. Timer/Counter 1 Synchronization Register Block Diagram.

ATtiny25/45/85

Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on the fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock in the asynchronous mode.

Note that the system clock frequency must be lower than one third of the PCK frequency. The synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk that data or control values are lost.

7598G–AVR–03/08

ATtiny25/45/85

8-BIT DATABUS

TIMER INT. FLAG REGISTER (TIFR)

TIMER/COUNTER1

8-BIT COMPARATOR

T/C1 OUTPUT

COMPARE REGISTER

TIMER INT. MASK

TIMER/COUNTER1

(TCNT1)

T/C CLEAR

T/C1 CONTROL

LOGIC

TOV1

OCF1B

TOV1

TOIE0

TOIE1

OCIE1B

OCIE1A

OCF1A



PCK

T/C1 OVER-

FLOW IRQ

T/C1 COMPARE

MATCH B IRQ

OC1A

(PB1)

T/C1 COMPARE

MATCH A IRQ

T/C CONTROL

COM1B1

PWM1A

PWM1B

COM1B0

FOC1A

FOC1B

(OCR1A) (OCR1B) (OCR1C)

8-BIT COMPARATOR

T/C1 OUTPUT

COMPARE REGISTER

TOV0

COM1A1

COM1A0



8-BIT COMPARATOR

T/C1 OUTPUT

COMPARE REGISTER



GLOBAL T/C CONTROL

CS12

PSR1

CS11

CS10

CS13

CTC1

OC1A (PB0)

OC1B

(PB4)

OC1B (PB3)

DEAD TIME GENERATOR

The following Figure 14-3 shows the block diagram for Timer/Counter1.

Figure 14-3. Timer/Counter1 Block Diagram

Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask Register - TIMSK.

The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and OCR1C as the data source to be compared with the Timer/Counter1 contents. In normal mode the Output Compare functions are operational with all three output compare registers. OCR1A determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin (PB3) and it can generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in the PWM mode the overflow interrupt is generated when Timer/Counter1 counts either from $FF to $00 or from OCR1C to $00. The inverted PWM outputs OC1A and OC1B are not connected in normal mode.

In PWM mode, OCR1A and OCR1B provide the data values against which the Timer Counter value is compared. Upon compare match the PWM outputs (OC1A, OC1A, OC1B, OC1B) are generated. In PWM mode, the Timer Counter counts up to the value specified in the output compare register OCR1C and starts again from $00. This feature allows limiting the counter “full” value to a specified value, lower than $FF. Together with the many prescaler options, flexible PWM frequency selection is provided. Table 14-6 lists clock selection and OCR1C values to

7598G–AVR–03/08

obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution.

14.1.1 Timer/Counter1 Control Register - TCCR1

Bit 7 6 5 4 3 2 1 0

$30 ($50)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 TCCR1

• Bit 7- CTC1 : Clear Timer/Counter on Compare Match

When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match.

• Bit 6- PWM1A: Pulse Width Modulator A Enable

When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.

• Bits 5,4 - COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode.

Table 14-1. Comparator A Mode Select

COM1A1 COM1A0 Description

0 0 Timer/Counter Comparator A disconnected from output pin OC1A.

0 1 Toggle the OC1A output line.

1 0 Clear the OC1A output line.

1 1 Set the OC1A output line

In PWM mode, these bits have different functions. Refer to Table 14-4 on page 88 for a detailed description.

• Bits 3 .. 0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

Table 14-2. Timer/Counter1 Prescale Select

Asynchronous

CS13 CS12 CS11 CS10

0 0 0 0 T/C1 stopped T/C1 stopped

0 0 0 1 PCK CK

0 0 1 0 PCK/2 CK/2

0 0 1 1 PCK/4 CK/4

Clocking Mode

Synchronous Clocking Mode

0 1 0 0 PCK/8 CK/8

ATtiny25/45/85

7598G–AVR–03/08

Table 14-2. Timer/Counter1 Prescale Select (Continued)

ATtiny25/45/85

CS13 CS12 CS11 CS10

0 1 0 1 PCK/16 CK/16

0 1 1 0 PCK/32 CK/32

0 1 1 1 PCK/64 CK/64

1 0 0 0 PCK/128 CK/128

1 0 0 1 PCK/256 CK/256

1 0 1 0 PCK/512 CK/512

1 0 1 1 PCK/1024 CK/1024

1 1 0 0 PCK/2048 CK/2048

1 1 0 1 PCK/4096 CK/4096

1 1 1 0 PCK/8192 CK/8192

1 1 1 1 PCK/16384 CK/16384

The Stop condition provides a Timer Enable/Disable function.

14.1.2 General Timer/Counter1 Control Register - GTCCR

Bit 7 6 5 4 3 2 1 0

$2C ($4C) TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR

Read/Write R/W R/W R/W R/W W W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Asynchronous Clocking Mode

Synchronous Clocking Mode

• Bit 6- PWM1B: Pulse Width Modulator B Enable

When set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.

• Bits 5,4 - COM1B1, COM1B0: Comparator B Output Mode, Bits 1 and 0

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode.

Table 14-3. Comparator B Mode Select

COM1B1 COM1B0 Description

0 0 Timer/Counter Comparator B disconnected from output pin OC1B.

0 1 Toggle the OC1B output line.

1 0 Clear the OC1B output line.

1 1 Set the OC1B output line

In PWM mode, these bits have different functions. Refer to Table 14-4 on page 88 for a detailed description.

• Bit 3- FOC1B: Force Output Compare Match 1B

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Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is set.

• Bit 2- FOC1A: Force Output Compare Match 1A

Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is set.

• Bit 1- PSR1 : Prescaler Reset Timer/Counter1

When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero.

14.1.3 Timer/Counter1 - TCNT1

Bit 7 6 5 4 3 2 1 0

$2F ($4F) MSB LSB TCNT1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

This 8-bit register contains the value of Timer/Counter1.

Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asynchronous mode.

14.1.4 Timer/Counter1 Output Compare RegisterA - OCR1A

Bit 7 6 5 4 3 2 1 0

$2E ($4E) MSB LSB OCR1A

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

The output compare register A is an 8-bit read/write register.

The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare event.

ATtiny25/45/85

7598G–AVR–03/08

14.1.5 Timer/Counter1 Output Compare RegisterB - OCR1B

Bit 7 6 5 4 3 2 1 0

$2D ($4D) MSB LSB OCR1B

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

The output compare register B is an 8-bit read/write register.

The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1B after a synchronization delay following the compare event.

14.1.6 Timer/Counter1 Output Compare RegisterC - OCR1C

Bit 7 6 5 4 3 2 1 0

$2B ($4B) MSB LSB OCR1C

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 1 1 1 1 1 1 1 1

ATtiny25/45/85

The output compare register C is an 8-bit read/write register.

The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C value. A software write that sets TCNT1 and OCR1C to the same value does not generate a compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1.

This register has the same function in normal mode and PWM mode.

14.1.7 Timer/Counter Interrupt Mask Register - TIMSK

Bit 7 6 5 4 3 2 1 0

$39 ($59) - OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 - TIMSK

Read/Write R R/W R/W R/W R/W R/W R/W R

Initial value 0 0 0 0 0 0 0 0

• Bit 7 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

• Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable

When the OCI E1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.

7598G–AVR–03/08

• Bit 5 - OCIE1B: Timer/Counter1 Output Compare Interrupt Enable

When the OCI E1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector $009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.

• Bit 4– OCIE0A: Timer/Counter Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, an d the I-bit in the S tatus Register is set, the Timer/Counter Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0A bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.

• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

• Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

Whe n the TOIE1 bi t i s set (one) and t he I-bit in the Status Regi ster is set (on e), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.

• Bit 0 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

14.1.8 Timer/Counter Interrupt Flag Register - TIFR

Bit 7 6 5 4 3 2 1 0

$38 ($58) - OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 - TIFR

Read/Write R R/W R/W R R R/W R/W R

Initial value 0 0 0 0 0 0 0 0

• Bit 7 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

• Bit 6 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed.

• Bit 5 - OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B compare match interrupt is executed.

• Bit 2 - TOV1: Timer/Counter1 Overflow Flag

In normal mode (PWM1A=0 and PWM1B=0) the bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to the flag.

ATtiny25/45/85

7598G–AVR–03/08

In PWM mode (either PWM1A=1 or PWM1B=1) the bit TOV1 is set (one) when compare match occurs between Timer/Counter1 and data value in OCR1C - Output Compare Register 1C. Clearing the Timer/Counter1 with the bit CTC1 does not generate an overflow.

When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.

• Bit 0 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

14.1.9 PLL Control and Status Register - PLLCSR

Bit 7 6 5 4 3 2 1 0

$27 ($27) LSM - - - - PCKE PLLE PLOCK PLLCSR

Read/Write R/W R R R R R/W R/W R

Initial value 0 0 0 0 0 0 0/1 0

• Bit 7- LSM: Low Speed Mode

The high speed mode is enabled as default and the fast peripheral clock is 64 MHz, but the low speed mode can be set by writing the LSM bit to one. Then the fast peripheral clock is scaled down to 32 MHz. The low speed mode must be set, if the supply voltage is below 2.7 volts, because the Timer/Counter1 is not running fast enough on low voltage levels. It is highly recommended that Timer/Counter1 is stopped whenever the LSM bit is changed.

ATtiny25/45/85

• Bit 6.. 3- Res : Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and always read as zero.

• Bit 2- PCKE: PCK Enable

The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and system clock CK is used as Timer/Counter1 clock source. This bit can be set only if PLLE bit is set. It is safe to set this bit only when the PLL is locked i.e the PLOCK bit is 1. The bit PCKE can only be set, if the PLL has been enabled earlier.

• Bit 1- PLLE: PLL Enable

When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1.

• Bit 0- PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK for Timer/Counter1. After the PLL is enabled, it takes about 100 micro seconds for the PLL to lock.

14.1.10 Timer/Counter1 Initialization for Asynchronous Mode

To change Timer/Counter1 to the asynchronous mode, first enable PLL, wait 100 µs before polling the PLOCK bit until it is set, and then set the PCKE bit.

14.1.11 Timer/Counter1 in PWM Mode

When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the

7598G–AVR–03/08

PB1(OC1A) and PB3(OC1B) pins and inverted outputs on pins PB0(OC1A) and PB2(OC1B). As

PWM1x

x = A or B

non-overlap

non-overlap=0

default non-overlapping times for complementary output pairs are zero, but they can be inserted using a Dead Time Generator (see description on page 100).

Figure 14-4. The PWM Output Pair

When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 14-4.

Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register OCR1C, and starting from $00 up again. A compare match with OC1C will set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.

Table 14-4. Compare Mode Select in PWM Mode

COM11 COM10 Effect on Output Compare Pins

0 0

0 1

1 0

1 1

OC1x not connected. OC1x not connected.

OC1x cleared on compare match. Set whenTCNT1 = $01. OC1x set on compare match. Cleared when TCNT1 = $00.

OC1x cleared on compare match. Set when TCNT1 = $01. OC1x not connected.

OC1x Set on compare match. Cleared when TCNT1= $01. OC1x not connected.

Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data value is first transferred to a temporary location. The value is latched into OCR1A or OCR1B when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A or OCR1B. See Figure 14-5 for an example.

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

PWM Output OC1x

Unsynchronized OC1x Latch

Synchronized OC1x Latch



Counter Value

Compare Value

Counter Value

Compare Value

Compare Value changes

Glitch

Compare Value changes

PWM

TCK1

OCR1C + 1( )

------------------------------------=

Figure 14-5. Effects of Unsynchronized OCR Latching

During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B.

When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C register, the outpu t PB 1 (O C1 A ) or P B3 ( OC 1B ) is h e ld l ow o r hi gh a c co rdi ng t o th e s e t ti n gs o f COM1A1/COM1A0. This is shown in Table 14-5.

Table 14-5. PWM Outputs OCR1x = $00 or OCR1C, x = A or B

COM1x1 COM1x0 OCR1x Output OC1x Output OC1x

0 1 $00 L H

0 1 OCR1C H L

1 0 $00 L Not connected.

1 0 OCR1C H Not connected.

1 1 $00 H Not connected.

1 1 OCR1C L Not connected.

In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts.

The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See the following equation:

7598G–AVR–03/08

Resolution shows how many bit is required to express the value in the OCR1C register. It is calculated by following equation

Resolution

= log2(OCR1C + 1).

PWM

Table 14-6. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode

PWM Frequency Clock Selection CS13..CS10 OCR1C RESOLUTION

20 kHz PCK/16 0101 199 7.6

30 kHz PCK/16 0101 132 7.1

40 kHz PCK/8 0100 199 7.6

50 kHz PCK/8 0100 159 7.3

60 kHz PCK/8 0100 132 7.1

70 kHz PCK/4 0011 228 7.8

80 kHz PCK/4 0011 199 7.6

90 kHz PCK/4 0011 177 7.5

100 kHz PCK/4 0011 159 7.3

110 kHz PCK/4 0011 144 7.2

120 kHz PCK/4 0011 132 7.1

130 kHz PCK/2 0010 245 7.9

140 kHz PCK/2 0010 228 7.8

150 kHz PCK/2 0010 212 7.7

160 kHz PCK/2 0010 199 7.6

170 kHz PCK/2 0010 187 7.6

180 kHz PCK/2 0010 177 7.5

190 kHz PCK/2 0010 167 7.4

200 kHz PCK/2 0010 159 7.3

250 kHz PCK 0001 255 8.0

300 kHz PCK 0001 212 7.7

350 kHz PCK 0001 182 7.5

400 kHz PCK 0001 159 7.3

450 kHz PCK 0001 141 7.1

500 kHz PCK 0001 127 7.0

15. Dead Time Generator

The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B). The sharing of tasks is as follows: the timer/counter generates the PWM output and the Dead Time Generator generates the non-overlapping PWM output pair from the timer/counter PWM signal. Two Dead Time Generators are provided, one for each PWM output. The non-overlap time is adjust-

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

TIMER/COUNTER1

OC1A

OC1B

DEAD TIME GENERATOR

PWM GENERATOR

PCKE

T15M

PCK

DT1AH

DT1BH

DEAD TIME GENERATOR

PWM1BPWM1A



DT1AL

DT1BL

CLOCK CONTROL

OC1x

T/C1 CLOCK

PWM1x

4-BIT COUNTER

COMPARATOR

DT1xL



DT1xH

DT1x I/O REGISTER

DEAD TIME PRESCALER

DTPS11..10



able and the PWM output and it’s com plementary output are adjusted separately, and independently for both PWM outputs.

Figure 15-1. Timer/Counter1 & Dead Time Generators

The dead time generation is based on the 4-bit down counters that count the dead time, as shown in Figure 46. There is a dedicated prescaler in front of the Dead Time Generator that can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of dead times that can be generated. The prescaler is controlled by two control bits DTPS11..10 from the I/O register at address 0x23. The block has also a rising and falling edge detector that is used to start the dead time counting period. Depending on the edge, one of the transitions on the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The comparator is used to compare the counter with zero and stop the dead time insertion when zero has been reached. The counter is loaded with a 4-bit DT1xH or DT1xL value from DT1x I/O register, depending on the edge of the PWM generator output when the dead time insertion is started.

7598G–AVR–03/08

Figure 15-2. Dead Time Generator

The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can have different dead time periods. The dead time is adjusted as the number of prescaled dead time generator clock cycles.

Figure 15-3. The Complementary Output Pair

OC1x

x = A or B

non-overlap / rising edge

non-overlap / falling edge

OC1x

PWM1x

15.0.1 Timer/Counter1 Dead Time Prescaler register 1 - DTPS1

Bit 7 6 5 4 3 2 1 0

$23 ($43) DTPS11 DTPS10 DTPS1

Read/Write R R R R R R R/W R/W

Initial value 0 0 0 0 0 0 0 0

The dead time prescaler register, DTPS1 is a 2-bit read/write register.

Bits 1 - 0 - DTPS1: Timer/Counter1 Dead Time Prescaler register 1

The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. The Dead Time prescaler is controlled by two bits DTPS11..10 from the Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The division factors are given in table 46..

Table 15-1. Division factors of the Dead Time prescaler

DTPS11 DTPS10 Prescaler divides the T/C1 clock by

0 0 1x (no division)

0 1 2x

1 0 4x

1 1 8x

15.0.2 Timer/Counter1 Dead Time A - DT1A

Bit 7 6 5 4 3 2 1 0

$25 ($45) DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 DT1A

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

The dead time value register A is an 8-bit read/write register.

The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields, DT1AH3..0 and DT1AL3..0, one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A.

• Bits 7..4- DT1AH3..DT1AH0: Dead Time Value for OC1A Output

ATtiny25/45/85

7598G–AVR–03/08

The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15.

• Bits 3..0- DT1AL3..DT1AL0: Dead Time Value for OC1A Output

15.0.3 Timer/Counter1 Dead Time B - DT1B

Bit 7 6 5 4 3 2 1 0

$25 ($45) DT1BH3 DT1BH2 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 DT1B

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

The dead time value register Bis an 8-bit read/write register.

The dead time delay of is adjusted by the dead time value register, DT1B. The register consists of two fields, DT1BH3..0 and DT1BL3..0, one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A.

ATtiny25/45/85

• Bits 7..4- DT1BH3..DT1BH0: Dead Time Value for OC1B Output

The dead time value for the OC1B output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15.

• Bits 3..0- DT1BL3..DT1BL0: Dead Time Value for OC1B Output

16. Universal Serial Interface – USI

The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. The main features of the USI are:

•

Two-wire Synchronous Data Transfer (Master or Slave, f

•

Three-wire Synchronous Data Transfer (Master or Slave f

•

Data Received Interrupt

•

Wakeup from Idle Mode

•

In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

•

Two-wire Start Condition Detector with Interrupt Capability

SCLmax

SCKmax

= fCK/16)

= fCK/4)

16.1 Overview

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A simplified block diagram of the USI is shown on Figure 16-1. For the actual placement of I/O pins, refer to “Pinout ATtiny25/45/85” on page 2. CPU accessible I/O Registers, including I/O

bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed

DATA BUS

USIPF

USITC

USICLK

USICS0

USICS1

USIOIFUSIOIE

USIDC

USISIF

USIWM0

USIWM1

USISIE Bit7

Two-wire Clock

Control Unit

(Output only)

DI/SDA

(Input/Open Drain)

USCK/SCL

(Input/Open Drain)

4-bit Counter

USIDR

USISR

D Q LE

USICR

CLOCK

HOLD

TIM0 COMP

Bit0

[1]

USIDB

in the “USI Register Descriptions” on page 100.

Figure 16-1. Universal Serial Interface, Block Diagram

The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and outgoing data. The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The most significant bit is connected to one of two output pins depending of the wire mode configuration. A transparent latch is inserted between the Serial Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software.

The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows.

16.2 Functional Descriptions

16.2.1 Three-wire Mode

The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and USCK.

ATtiny25/45/85

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Figure 16-2. Three-wire Mode Operation, Simplified Diagram

SLAVE

MASTER

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

USCK

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

USCK

PORTxn

MSB

6 5 4 3 2 1 LSB

1 2 3 4 5 6 7 8

6 5 4 3 2 1 LSB

USCK

DCBA E

CYCLE

( Reference )

ATtiny25/45/85

Figure 16-2 shows two USI units operating in Three-wire mode, one as Master and one as

Slave. The two Shift Registers are interconnected in such way that after eight USCK clocks, the data in each register are interchanged. The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR.

Figure 16-3. Three-wire Mode, Timing Diagram

The Three-wire mode timing is shown in Figure 16-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., samples d ata at negative and ch anges the output at positive edges. Th e USI clock modes corresponds to the SPI data mode 0 and 1.

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Referring to the timing diagram (Figure 16-3.), a bus transfer involves the following steps:

1. The Slave device and Master device sets up its data output and, depending on the pro-

tocol used, enables its output driver (mark A and B). The output is set up by writing the

data to be transmitted to the Serial Data Register. Enabling of the output is done by setting the corresponding bit in the port Data Direction Register. Note that point A and B does not have any specific order, but both must be at least one half USCK cycle before point C where the data is sampled. This must be done to ensure that the data setup requirement is satisfied. The 4-bit counter is reset to zero.

2. The Master generates a clock pulse by software toggling the USCK line twice (C and

D). The bit value on the slave and master’s data input (DI) pin is sampled by the USI on the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter will count both edges.

3. Step 2. is repeated eight times for a complete register (byte) transfer.

4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that

the transfer is completed. The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it is set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance.

16.2.2 SPI Master Operation Example

The following code demonstrates how to use the USI module as a SPI Master:

SPITransfer:

sts USIDR,r16

ldi r16,(1<<USIOIF)

sts USISR,r16

ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)

SPITransfer_loop:

sts USICR,r16

lds r16, USISR

sbrs r16, USIOIF

rjmp SPITransfer_loop

lds r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register.

The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times.

The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4):

SPITransfer_Fast:

sts USIDR,r16

ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)

ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)

sts USICR,r16 ; MSB

sts USICR,r17

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sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16

sts USICR,r17

sts USICR,r16 ; LSB

sts USICR,r17

lds r16,USIDR

ret

ATtiny25/45/85

16.2.3 SPI Slave Operation Example

The following code demonstrates how to use the USI module as a SPI Slave:

init:

ldi r16,(1<<USIWM0)|(1<<USICS1)

sts USICR,r16

...

SlaveSPITransfer:

sts USIDR,r16

ldi r16,(1<<USIOIF)

sts USISR,r16

SlaveSPITransfer_loop:

lds r16, USISR

sbrs r16, USIOIF

rjmp SlaveSPITransfer_loop

lds r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO is configured as output and USCK pin is configured as input in the DDR Register. The value stored in register r16 prior to the function is called is transferred to the master device, and when the transfer is completed the data received from the Master is stored back into the r16 Register.

7598G–AVR–03/08

Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set.

16.2.4 Two-wire Mode

MASTER

SLAVE

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SDA

SCL

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Two-wire Clock

Control Unit

HOLD

SCL

PORTxn

SDA

SCL

VCC

The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.

Figure 16-4. Two-wire Mode Operation, Simplified Diagram

Figure 16-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave.

It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the Master and Slave operation at this level, is the serial clock generation which is always done by the Master, and only the Slave uses the clock control unit. Clock generation must be implemented in software, but the shift operation is done automatically by both devices. Note that only clocking on negative edge for shifting data is of practical use in this mode. The slave can insert wait states at start or end of transfer by forcing the SCL clock low. This means that the Master must always check if the SCL line was actually released after it has generated a positive edge.

Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORT Register.

The data direction is not given by the physical layer. A protocol, like the one used by the TWIbus, must be implemented to control the data flow.

ATtiny25/45/85

7598G–AVR–03/08

ATtiny25/45/85

ADDRESS

1 - 7 8 9

R/W ACK ACK

1 - 8 9

DATA ACK

1 - 8 9

DATA

SDA

SCL

A B D EC F

SDA

SCL

Write( USISIF)

CLOCK HOLD

USISIF

D Q

CLR

D Q

CLR

Figure 16-5. Two-wire Mode, Typical Timing Diagram

Referring to the timing diagram (Figure 16-5.), a bus transfer involves the following steps:

1. The a start condition is generated by the Master by forcing the SDA low line while the

SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the Data Direction Register bit must be set to one for the output to be enabled. The slave device’s start detector logic (Figure 16-6.) detects the start condition and sets the USISIF Flag. The flag can generate an interrupt if necessary.

2. In addition, the start detector will hold the SCL line low after the Master has forced an

negative edge on this line (B). This allows the Slave to wake up from sleep or complete its other tasks before setting up the Shift Register to receive the address. This is done by clearing the start condition flag and reset the counter.

3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave

samples the data and shift it into the Serial Register at the positive edge of the SCL clock.

4. After eight bits are transferred containing slave address and data direction (read or

write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not the one the Master has addressed, it releases the SCL line and waits for a new start condition.

5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle

before holding the SCL line low again (i.e., the Counter Register must be set to 14 before releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its output. If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).

6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is

given by the Master (F). Or a new start condition is given.

If the Slave is not able to receive more data it does not acknowledge the data byte it has last received. When the Master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted.

16.2.5 Start Condition Detector

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Figure 16-6. Start Condition Detector, Logic Diagram

The start condition detector is shown in Figure 16-6. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode.

The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by the CKSEL Fuses (see “Clock Systems and their Distribution” on page 21) must also be taken into the consideration. Refer to the USISIF bit description on page 101 for further details.

16.3 Alternative USI Usage

When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design.

16.3.1 Half-duplex Asynchronous Data Transfer

By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only.

16.3.2 4-bit Counter

The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked externally, both clock edges will generate an increment.

16.3.3 12-bit Timer/Counter

Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit counter.

16.3.4 Edge Triggered External Interrupt

By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit.

16.3.5 Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.

16.4 USI Register Descriptions

16.4.1 USI Data Register – USIDR

Bit 7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

When accessing the USI Data Register (USIDR) the Serial Register can be accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed. A (left) shift operation is performed depe nding of the USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note that even when no wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the Shift Register.

The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) during the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The output will be

MSB LSB USIDR

100

ATtiny25/45/85

7598G–AVR–03/08

ATMEL ATtiny85 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

2. Overview

2.1 Block Diagram

2.2 Automotive Quality Grade

2.3 Pin Descriptions

2.3.1 VCC

2.3.2 GND

2.3.3 Port B (PB5..PB0)

2.3.4 RESET

3. About Code Examples

4. AVR CPU Core

4.1 Introduction

4.2 Architectural Overview

4.4 Status Register

4.5 General Purpose Register File

4.5.1 The X-register, Y-register, and Z-register

4.6 Stack Pointer

4.7 Instruction Execution Timing

4.8 Reset and Interrupt Handling

4.8.1 Interrupt Response Time

5. AVR ATtiny25/45/85 Memories

5.1 In-System Re-programmable Flash Program Memory

5.2 SRAM Data Memory

5.2.1 Data Memory Access Times

5.3 EEPROM Data Memory

5.3.1 EEPROM Read/Write Access

5.3.6 Atomic Byte Programming

5.3.7 Split Byte Programming

5.3.8 Erase

5.3.9 Write

5.3.10 Preventing EEPROM Corruption

5.4 I/O Memory

6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

6.2 Clock Sources

6.3 Default Clock Source

6.4 Crystal Oscillator

6.5 Low-frequency Crystal Oscillator

6.6 Calibrated Internal RC Oscillator

6.7 External Clock

6.8 128 kHz Internal Oscillator

6.9 Clock Output Buffer

6.10 System Clock Prescaler

6.10.2 Switching Time

7. Power Management and Sleep Modes

7.1 Idle Mode

7.2 ADC Noise Reduction Mode

7.3 Power-down Mode

7.4 Limitations

7.5 Power Reduction Register

7.6 Minimizing Power Consumption

7.6.1 Analog to Digital Converter

7.6.2 Analog Comparator

7.6.3 Brown-out Detector

7.6.4 Internal Voltage Reference

7.6.5 Watchdog Timer

7.6.6 Port Pins

8. System Control and Reset

8.0.1 Resetting the AVR

8.0.2 Reset Sources

8.0.3 Power-on Reset

8.0.4 External Reset

8.0.5 Brown-out Detection

8.0.6 Watchdog Reset

8.1 Internal Voltage Reference

8.1.1 Voltage Reference Enable Signals and Start-up Time

8.2 Watchdog Timer

8.3 Timed Sequences for Changing the Configuration of the Watchdog Timer

8.3.1 Safety Level 1

8.3.2 Safety Level 2

9. Interrupts

9.1 Interrupt Vectors in ATtiny25/45/85

10. I/O Ports

10.1 Introduction

10.2 Ports as General Digital I/O