Atmel ATtiny84A Datasheet

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execu tion
– 32 x 8 General Purpose Working Registers
– Fully Static Operation

• High Endurance, Non-volatile Memory Segments

– 2K/4K/8K Bytes of In-System, Self-programmable Flash Program Memory

• Endurance: 10,000 Write/Erase Cycles

– 128/256/512 Bytes of In-System Programmable EEPROM

• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes of Internal SRAM
– Data Retention: 20 years at 85°C / 100 years at 25°C
– Programming Lock for Self-programming Flash & EEPROM Data Security

• Peripheral Features

– One 8-bit and One 16-bit Timer/Counter with Two PWM Channels, Each
– 10-bit ADC

• 8 Single-ended Channels

• 12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Universal Serial Interface

• Special Microcontroller Features

– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– Internal and External Interrupt Sources

• Pin Change Interrupt on 12 Pins
– Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit with Software Disable Function
– Internal Calibrated Oscillator
– On-chip Temperature Sensor

• I/O and Packages

– Available in 20-pin QFN/MLF/VQ FN, 14-p in SOIC, 14-p in PDIP and 15-ball UFBGA
– Twelve Programmable I/O Lines

• Operating Voltage:

– 1.8 – 5.5V

• Speed Grade:

– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 10 MHz @ 2.7 – 5.5V
– 0 – 20 MHz @ 4.5 – 5.5V

• Industrial Temperature Range: -40°C to +85°C

• Low Power Consumption

– Active Mode:

• 210 µA at 1.8V and 1 MHz
–Idle Mode:

• 33 µA at 1.8V and 1 MHz
– Power-down Mode:

• 0.1 µA at 1.8V and 25°C

®

8-bit Microcontroller

8-bit
Microcontroller
with 2K/4K/8K
Bytes In-System
Programmable
Flash

ATtiny24A
ATtiny44A
ATtiny84A

Summary

Rev. 8183FS–AVR–06/12

1. Pin Configurations

Figure 1-1. Pinout of ATtiny24A/44A/84A

PDIP/SOIC

VCC

(PCINT8/XTAL1/CLKI) PB0

(PCINT9/XTAL2) PB1

(PCINT11/RESET/dW) PB3

(PCINT10/INT0/OC0A/CKOUT) PB2

(PCINT7/ICP/OC0B/ADC7) PA7

(PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6

(ADC4/USCK/SCL/T1/PCINT4) PA4

(ADC3/T0/PCINT3) PA3
(ADC2/AIN1/PCINT2) PA2
(ADC1/AIN0/PCINT1) PA1

(ADC0/AREF/PCINT0) PA0

NOTE
Bottom pad should be
soldered to ground.
DNC: Do Not Connect

1
2
3
4
5
6
7

14
13
12
11
10

9
8

QFN/MLF/VQFN

PA 5

DNC

DNC

DNC

PA 6

2019181716

1
2
3
4
5

678910

DNC

DNC

GND

VCC

15
14
13
12
11

DNC

GND
PA0 (ADC0/AREF/PCINT0)
PA1 (ADC1/AIN0/PCINT1)
PA2 (ADC2/AIN1/PCINT2)
PA3 (ADC3/T0/PCINT3)
PA4 (ADC4/USCK/SCL/T1/PCINT4)
PA5 (ADC5/DO/MISO/OC1B/PCINT5)

Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6)
Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)

PA7 (PCINT7/ICP/OC0B/ADC7)
PB2 (PCINT10/INT0/OC0A/CKOUT)
PB3 (PCINT11/RESET/dW)
PB1 (PCINT9/XTAL2)
PB0 (PCINT8/XTAL1/CLKI)

Table 1-1. UFBGA - Pinout ATtiny24A/44A/84A (top view)

1234

A
B PA4 PA7 PB1 PB3
C PA3 PA2 PA1 PB0
D PA0 GND GND VCC

2

ATtiny24A/44A/84A

PA5 PA6 PB2

8183FS–AVR–06/12

1.1 Pin Descriptions

1.1.1 VCC

Supply voltage.

1.1.2 GND

Ground.

1.1.3 Port B (PB3:PB0)

Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability except PB3 which has the RESET
RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins tha t are externally pulled low
will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the cloc k is not runn in g.

Port B also serves the functions of various special features of the ATtiny24A/44A/84A as listed
in Section 10.2 “Alternate Port Functions” on page 58.

1.1.4 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. Th e min­imum pulse length is given in Table 20-4 on page 176. Shorter pulses are not guaranteed to
generate a reset.

ATtiny24A/44A/84A

capability. To use pin PB3 as an I/O pin, instead of

The reset pin can also be used as a (weak) I/O pin.

1.1.5 Port A (PA7:PA0)

Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter,
SPI and pin change interrupt as described in “Alternate Port Functions” on page 58.

8183FS–AVR–06/12

3

2. Overview

ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.

Figure 2-1. Block Diagram

VCC

GND

PROGRAM
COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

PROGRAMMING

LOGIC

STACK

POINTER

SRAM

GENERAL

PURPOSE

REGISTERS

X
Y
Z

ALU

STATUS

REGISTER

ISP INTERFACE

8-BIT DATABUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

REGISTER

MCU STATUS

REGISTER

TIMER/

COUNTER0

TIMER/

COUNTER1

INTERRUPT

UNIT

EEPROM

INTERNAL
CALIBRATED
OSCILLATOR

TIMING AND

CONTROL

OSCILLATORS

ADC

DATA REGISTER

PORT B

PORT B DRIVERS

PB[3:0]

DATA DIR.

REG.PORT B

PA[7:0]

DATA DIR.

REG.PORT A

DATA REGISTER

+

_

PORT A

ANALOG

COMPARATOR

PORT A DRIVERS

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

4

ATtiny24A/44A/84A

8183FS–AVR–06/12

ATtiny24A/44A/84A

The ATtiny24A/44A/84A provides the following features: 2K/4K/8K byte of In-System Program­mable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O
lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a
16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit
ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable
Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software select­able power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,
ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction
mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O mod­ules except the ADC. In Power-down mode registers keep their contents and all chip functions
are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator
oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined
with low power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The on­chip ISP Flash allows the Program memory to be re-programmed in-system through an SPI
serial interface, by a conventional non-volatile memory programmer or by an on-chip boo t code
running on the AVR core.

The ATtiny24A/44A/84A AVR is supported w ith a full suit e of progra m and s ystem de velopmen t
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation
kits.

8183FS–AVR–06/12

5

3. General Information

3.1 Resources

A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.

3.2 Code Examples

This documentation contains simple code examples tha t briefly sh ow how to use var ious par ts of
the device. These code examples assume that the part specific header file is included b efore
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Plea se con firm with th e C com piler d ocumen­tation for more details.

For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically, this
means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all
AVR devices include an extended I/O map.

3.3 Capacitive Touch Sensing

Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel
AVR microcontrollers. The QTouch Library includes support for QTouch
tion methods.

®

and QMatrix® acquisi-

3.4 Data Retention

3.5 Disclaimer

Touch sensing is easily added to any application by linking the QTouch Library and using the
Application Programming Interface (API) of the library to define the touch ch annels and senso rs.
The application then calls the API to retrieve channel information and determine the state of the
touch sensor.

The QTouch Library is free and can be downloaded from the Atmel website. For more informa­tion and details of implementation, refer to the QTouch Library User Guide – also available from
the Atmel website.

Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.

Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device has been characterized.

6

ATtiny24A/44A/84A

8183FS–AVR–06/12

ATtiny24A/44A/84A

4. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x3F (0x5F) SREG I T H S V N Z C Page 14

0x3E (0x5E) SPH – – – – – – SP9 SP8 Page 13
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Page 13
0x3C (0x5C) OCR0B
0x3B (0x5B) GIMSK – INT0 PCIE1
0x3A (0x5A) GIFR – INTF0 PCIF1

0x39 (0x59) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 Page 83

0x38 (0x58) TIFR0 – – – – – OCF0B OCF0A TOV0 Page 84

0x37 (0x57) SPMCSR – – RSIG CTPB RFLB PGWRT PGERS SPMEN Page 156

0x36 (0x56) OCR0A

0x35 (0x55) MCUCR BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Pages 36, 50, 66

0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF Page 44

0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Page 82

0x32 (0x52) TCNT0 Timer/Counter0 Page 83

0x31 (0x51) OSCCALCAL7CAL6CAL5CAL4CAL3CAL2CAL1CAL0 Page 31

0x30 (0x50) TCCR0A COM 0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Page 79
0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 Page 106
0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Page 108
0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte Page 110
0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte Page 110
0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte Page 110
0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte Page 110

0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte Page 110

0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte Page 110

0x27 (0x47) DWDR DWDR[7:0] Page 151

0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Page 31

0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte Page 111

0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte Page 111

0x23 (0x43) GTCCR TSM – – – – – – PSR10 Page 114

0x22 (0x42) TCCR1C FOC1A FOC1B – – – – – – Page 109

0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Page 44

0x20 (0x40) PCMSK1 – – – – PCINT11 PCINT10 PCINT9 PCINT8 Page 51
0x1F (0x3F) EEARH – – – – – – –EEAR8 Page 20
0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 Page 21
0x1D (0x3D) EEDR EEPROM Data Register Page 21
0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE Page 23
0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Page 66
0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Page 66

0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Page 67

0x18 (0x38) PORTB – – – – PORTB3 PORTB2 PORTB1 PORTB0 Page 67

0x17 (0x37) DDRB

0x16 (0x36) PINB – – – – PINB3 PINB2 PINB1 PINB0 Page 67

0x15 (0x35) GPIOR2 General Purpose I/O Register 2 Page 22

0x14 (0x34) GPIOR1 General Purpose I/O Register 1 Page 23

0x13 (0x33) GPIOR0 General Purpose I/O Register 0 Page 23

0x12 (0x32) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Page 52
0x11 (0x31)) Reserved

0x10 (0x30) USIBR USI Buffer Register Page 127
0x0F (0x2F) USIDR USI Data Register Page 126
0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Page 125
0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Page 123
0x0C (0x2C) TIMSK1
0x0B (0x2B) TIFR1
0x0A (0x2A) Reserved

0x09 (0x29) Reserved –

0x08 (0x28) ACSR ACD ACBG

0x07 (0x27) ADMUX REFS1 REFS0 MUX5 MUX4 MUX3 MUX2

0x06 (0x26) ADCSRA ADEN ADSC

0x05 (0x25) ADCH ADC Data Register High Byte Page 148

0x04 (0x24) ADCL ADC Data Register Low Byte Page 148

0x03 (0x23) ADCSRB BIN ACME –ADLAR– ADTS2 ADTS1 ADTS0 Pages 130, 148

0x02 (0x22) Reserved

0x01 (0x21) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Pages 131, 149

0x00 (0x20) PRR

– – – – DDB3 DDB2 DDB1 DDB0 Page 67

– –ICIE1– – OCIE1B OCIE1A TOIE1 Page 111
– –ICF1– – OCF1B OCF1A TOV1 Page 112

– – – – PRTIM1 PRTIM0 PRUSI PRADC Page 37

Timer/Counter0 – Output Compare Register B

Timer/Counter0 – Output Compare Register A

ACO ACI ACIE ACIC ACIS1 ACIS0 Page 129

ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Page 146

PCIE0
PCIF0

– – – – Page 50
– – – – Page 51

–

–

MUX1 MUX0 Page 144

–

Page 83

Page 83

8183FS–AVR–06/12

7