ATMEL ATtiny48, ATtiny88 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 123 Powe rful Instructions – Most Single Clock Cy cle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation

• High Endurance Non-volatile Memory Segments

– 4K/8K Bytes of In-System Self-Programmable Flash program memory(ATtiny48/88)
– 64/64 Bytes EEPROM (ATtiny48/88)
– 256/512 Bytes Internal SRAM (ATtiny48/88)
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C / 100 years at 25°C
– Optional Boot Code Section with Indepentent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Prescaler, and Compare and Capture Modes
– 8-channel 10-bit ADC in 32-lead TQFP and 32-pad QFN/MLF package
– 6-channel 10-bit ADC in 28-pin PDIP and 28-pad QFN/MLF package
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– Power-on Reset and Pr ogrammab l e Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, ADC Noise Reduction and Power-down

• I/O and Pac kages

– 28 Programmable I/O Lines in 32-lead TQFP and 32-pad QFN/MLF package
– 24 Programmable I/O Lines in 28-pin PDIP and 28-pad QFN/MLF package
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

• Operating Voltage:
– 5.5V

–1.8

• Temperature Range:

–-40°C to +85°C

• Speed Grade:

– 2 MHz @ 1.8 – 5.5V

–0
–0 – 6 MHz @ 2.7 – 5.5V

– 12 MHz @ 4.5 – 5.5V

–0

• Low Power Consumption

– Active Mode: 1 MHz, 1.8V: 240µA
– Power-down Mode: 0.1µA at 1.8V

®

8-Bit Microcontroller

2

C Compatible)

8-bit

Microcontroller
with 4/8K Bytes
In-System
Programmable
Flash

ATtiny48/88

Preliminary

Summary

Rev. 8008AS–AVR–06/08

ATtiny48/88

1. Pin Configurations

TQFP Top View

3)

2)

(

Figure 1-1. Pinout of ATtiny48/88

PDIP

(PCINT19/INT1) PD3

(PCINT20/T0) PD4

(PCINT26) PA2

VCC
GND

(PCINT27) PA3

(PCINT6/CLKI) PB6

(PCINT7) PB7

(PCINT19/INT1) PD3

(PCINT20/T0) PD4

(PCINT6/CLKI) PB6

(PCINT21/T1) PD5

VCC
GND

(PCINT7) PB7

PD2 (INT0/PCINT18)

PD1 (PCINT17)

PD0 (PCINT16)

PC6 (RESET/PCINT14)

32313029282726

1
2
3
4
5
6
7
8

9101112131415

(PCINT21/T1) PD5

(PCINT22/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT0/CLKO/ICP1) PB0

28 MLF Top View

PD2 (INT0/PCINT18)

PD1 (PCINT17)

PD0 (PCINT16)

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

28272625242322

1
2
3
4
5
6
7

891011121314

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

25

24

PC1 (ADC1/PCINT9)

23

PC0 (ADC0/PCINT8)

22

PA1 (ADC7/PCINT25)

21

GND

20

PC7 (PCINT15)

19

PA0 (ADC6/PCINT24)

18

AVCC

17

PB5 (SCK/PCINT5)

16

(PCINT3/MOSI) PB3

(PCINT4/MISO) PB4

(PCINT1/OC1A) PB1

(PCINT2/SS/OC1B) PB2

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

21

PC1 (ADC1/PCINT9)

20

PC0 (ADC0/PCINT8)

19

GND

18

PC7 (PCI NT15)

17

AVCC

16

PB5 (SCK/PCINT5)

15

(PCINT0/CLKO/ICP1) PB0

(PCINT19/INT1) PD3

(PCINT20/T0) PD4

(PCINT26) PA2

VCC
GND

(PCINT27) PA3

(PCINT6/CLKI) PB6

(PCINT7) PB7

(PCINT14/RESET) PC6

(PCINT16) PD0

(PCINT17) PD1
(PCINT18/INT0) PD2
(PCINT19/INT1) PD3

(PCINT20/T0) PD4

(PCINT6/CLKI) PB6

(PCINT21/T1) PD5
(PCINT22/AIN0) PD6
(PCINT23/AIN1) PD7

VCC
GND

(PCINT7) PB7

32 MLF Top View

PD2 (INT0/PCINT18)

PD1 (PCINT17)

PD0 (PCINT16)

32313029282726

1
2
3
4
5
6
7
8

9101112131415

1
2
3
4
5
6
7
8
9
10
11
12
13
14

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

25

24
23
22
21
20
19
18
17

16

PC5 (ADC5/SCL/PCINT1
PC4 (ADC4/SDA/PCINT1
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
PC7 (PCINT15)
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)

PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
PA1 (ADC7/PCINT25)
GND
PC7 (PCINT15)
PA0 (ADC6/PCINT24)
AVCC
PB5 (SCK/PCINT5)

NOTE: Bottom pad should be soldered to ground.

2

(PCINT1/OC1A) PB1

(PCINT22/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT3//MOSI) PB3

(PCINT2/SS/OC1B) PB2

PCINT0/CLKO/ICP1) PB0

(PCINT4/MISO) PB4

NOTE: Bottom pad should be soldered to ground.

(PCINT21/T1) PD5

(PCINT1/OC1A) PB1

(PCINT22/AIN0) PD6

(PCINT23/AIN1) PD7

PCINT0/CLKO/ICP1) PB0

(PCINT3/MOSI) PB3

(PCINT4/MISO) PB4

(PCINT2/SS/OC1B) PB2

8008AS–AVR–06/08

1.1 Pin Descriptions

1.1.1 VCC

Digital supply voltage.

1.1.2 GND

Ground.

1.1.3 Port A (PA3:0) (in 32-lead TQFP and 32-pad QFN/MLF packages, only)

Port A is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) in 32­lead TQFP and 32-pad QFN/MLF package. The PA3..0 output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port A pins that are exter­nally pulled low will source current if the pull-up resistors are activated. The Po rt A pins are tri­stated when a reset condition becomes active, even if the clock is not runn ing.

1.1.4 Port B (PB7:0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

ATtiny48/88

Depending on the clock selection fuse settings, PB6 can be used as input to the internal clock
operating circuit.

The various special features of Port B are elaborated in “Alternate Functions of Port B” on page

64 and “System Clock and Clock Options” on page 25.

1.1.5 Port C (PC7, PC5:0)

Port C is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PC7 and PC5..0 output buffers have symmetrical drive characteristics with both high sink and
source capability. As inputs, Port C pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes
active, even if the clock is not running.

1.1.6 PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char­acteristics of PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a r eset input . A low level on this pin f or
longer than the minimum pulse width will generate a reset, even if the clock is not running. The
minimum pulse length is given in Table 22-3 on page 201. Shorter pulses are not guaranteed to
generate a reset.

The various special features of Port C are elaborated in “Alternate Functions of Port C” on page

67.

1.1.7 Port D (PD7:0)

8008AS–AVR–06/08

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PD7..4 output buffers have symmetrical drive characteristics with both high sink and source
capabilities, while the PD3..0 output buffers hav e stronger sink capabilities. As inp uts, Port D

3

ATtiny48/88

pins that are externally pulled low will source current if the pull-up resistors are activated. The
Port D pins are tri-stated when a reset condition becom es active, even if the clock is not running.

The various special features of Port D are elaborated in “Alternate Functions of Port D” on page

70.

1.1.8 AV

CC

AVCC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should
be externally connec ted to V
mended this pin is connected to V

even if the ADC is not used. If the ADC is used, it is recom-

CC

through a low-pass filter, as described in “Analog Noise

CC

Canceling Techniques” on page 163.

The following pins receive their supply voltage from AV
ages) PA1:0. All other I/O pins take their supply voltage from V

: PC7, PC5:0 and (in 32-lead pack-

CC

.

CC

4

8008AS–AVR–06/08

2. Overview

2.1 Block Diagram

ATtiny48/88

The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATt iny48/88 achieves
throughputs approaching 1 MIPS pe r MHz allow ing the sy stem de signer to optimize power c on­sumption versus processing speed.

Figure 2-1. Block Diagram

GND

Watchdog

Timer

Watchdog

Oscillator

Oscillator

Circuits /

Clock

Generation

EEPROM

16bit T/C 18bit T/C 0 A/D Conv.

DATABUS

Powe r

Supervision

POR / BOD &

RESET

VCC

debugWIRE

CPU

Internal

Bandgap

Program

Logic

SRAMFlash

6

2

8008AS–AVR–06/08

Analog

Comp.

SPI TWI

PORT C (8)PORT B (8)PORT D (8)

PORT A (4)

RESET

CLKI

PA[0..3] (in TQFP and MLF)PC[0..7]PB[0..7]PD[0..7]

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

5

ATtiny48/88

The ATtiny48/88 provides the following features: 4/8K bytes of In-System Programmable Flash,
64/64 bytes EEPROM, 256/512 bytes SRAM, 24 general purpose I/O lines (28 I/Os in 32-lead
TQFP and 32-pad QFN/MLF packages), 32 general purpose working registers, two flexible
Timer/Counters with compare modes, internal and external interrupts, a byte-oriented 2-wire
serial interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in 32-lead TQFP and 32­pad QFN/MLF packages), a programmable Watchdog Timer with internal oscillator, and three
software selectable power saving modes. Idle mode stops the CPU while allowing
Timer/Counters, 2-wire serial interface, SPI port, and interrupt system to continue functioning.
Power-down mode saves the register contents but freezes the oscillator, disabling all other chip
functions until the next interrupt or hardware reset. ADC Noise Reduction mode stops the CPU
and all I/O modules except ADC, and helps to minimize switching noise during ADC
conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro­gram running on the AVR core. The Boot program can use any interface to download the
application program in the Flash memory. By combining an 8-bit RISC CPU with In-System Self­Programmable Flash on a monolithic chip, the Atmel ATtiny48/88 is a powerful microcontroller
that provides a highly flexible and cost effective solutio n to many embedded contro l applications.

The ATtiny48/88 AVR is supported by a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators and evaluation kits.

2.2 Comparison Between ATtiny48 and ATtiny88

The ATtiny48 and ATtiny88 differ only in memory sizes. Table 2-1 summarizes the different
memory sizes for the two devices.

Table 2-1. Memory Size Summary

Device Flash EEPROM RAM

ATtiny48 4K Bytes 64 Bytes 256 Bytes
ATtiny88 8K Bytes 64 Bytes 512 Bytes

6

8008AS–AVR–06/08

3. About

3.1 Resources

A comprehensive set of development tools, application notes and datasheets are available for
download at http://www.atmel.com/avr.

3.2 About Code Examples

This documentation contains simple code examples t hat brief ly show h ow to us e various parts of
the device. These code examples assume that the part specific header file is included b efore
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent . Please con firm wit h the C com piler d ocume n­tation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

3.3 Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.

ATtiny48/88

3.4 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es
will be available after the device is characterized.

8008AS–AVR–06/08

7