Features
ATtiny441/ATtiny841
8-bit AVR Microcontroller with 4/8K Bytes In-System
Programmable Flash
SUMMARY DATASHEET
High Performance, Low Power Atmel
Advanced RISC Architecture
120 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
Non-volatile Program and Data Memories
4/8K Bytes of In-System Programmable Flash Program Memory
Endurance: 10,000 Write/Erase Cycles
256/512 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
256/512 Bytes Internal SRAM
Data Retention: 20 Years at 85
Programming Lock for Self-Programming Flash & EEPROM Data Security
Peripheral Features
One 8-bit and Two 16-bit Timer/Counters with Two PWM Channels, Each
Programmable Ultra Low Power Watchdog Timer
10-bit Analog to Digital Converter
12 External and 5 Internal, Single-ended Input Channels
46 Differential ADC Channel Pairs with Programmable Gain (1x / 20x / 100x)
Two On-chip Analog Comparators
Two Full Duplex USARTs with Start Frame Detection
Master/Slave SPI Serial Interface
Slave I
Special Microcontroller Features
Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
Enhanced Power-on Reset Circuit
Programmable Brown-out Detection Circuit with Supply Voltage Sampling
External and Internal Interrupt Sources
Calibrated 8MHz Oscillator with Temperature Calibration Option
Calibrated 32kHz Ultra Low Power Oscillator
High-Current Drive Capability on 2 I/O Pins
I/O and Packages
14-pin SOIC, 20-pad MLF/QFN and 20-pad VQFN
12 Programmable I/O Lines
Speed Grade
0 – 2 MHz @ 1.7 – 1.8V
0 – 4 MHz @ 1.8 – 5.5V
0 – 10 MHz @ 2.7 – 5.5V
0 – 16 MHz @ 4.5 – 5.5V
Low Power Consumption
Active Mode: 0.2 mA at 1.8V and 1MHz
Idle Mode: 30 µA at 1.8V and 1MHz
Power-Down Mode (WDT Enabled): 1.3µA at 1.8V
Power-Down Mode (WDT Disabled): 150nA at 1.8V
2
C Serial Interface
Pin Change Interrupt on 12 Pins
®
AVR® 8-bit Microcontroller
o
C / 100 Years at 25oC
8495HS–AVR–05/2014
1. Pin Configurations
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
(PCINT8/ADC11/XTAL1/CLKI) PB0
(PCINT9/ADC10/XTAL2/INT0) PB1
(PCINT11/ADC9/RESET/dW) PB3
(PCINT10/ADC8/CLKO/TOCC7/ICP2/RXD0) PB2
(PCINT7/ADC7/TOCC6/ICP1/TXD0/SS) PA7
(PCINT6/ADC6/ACO1/TOCC5/XCK1/SDA/MOSI) PA6
GND
PA0 (PCINT0/ADC0/AREF/MISO)
PA1 (PCINT1/ADC1/AIN00/TOCC0/TXD0/MOSI)
PA2 (PCINT2/ADC2/AIN01/TOCC1/RXD0/SS)
PA3 (PCINT3/ADC3/AIN10/TOCC2/T0/XCK0/SCK)
PA4 (PCINT4/ADC4/AIN11/TOCC3/T1/RXD1/SCL/SCK)
PA5 (PCINT5/ADC5/ACO0/TOCC4/T2/TXD1/MISO)
Figure 1-1. Pinout in 14-pin SOIC.
Figure 1-2. Pinout in 20-pad VQFN/WQFN.
(PCINT4/ADC4/AIN11/TOCC3/T1/RXD1/SCL/SCK) PA4
(PCINT3/ADC3/AIN10/TOCC2/T0/XCK0/SCK) PA3
(PCINT2/ADC2/AIN01/TOCC1/RXD0/SS) PA2
(PCINT1/ADC1/AIN00/TOCC0/TXD0/MOSI) PA1
(PCINT0/ADC0/AREF/MISO) PA0
NOTE
Bottom pad should be
soldered to ground.
DNC: Do Not Connect
1.1 Pin Description
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
PA5 (PCINT5/ADC5/ACO0/TOCC4/T2/TXD1/MISO)
DNC
DNC
DNC
PA6 (PCINT6/ADC6/ACO1/TOCC5/XCK1/SDA/MOSI)
2019181716
1
2
3
4
5
678910
DNC
DNC
15
PA7 (PCINT7/ADC7/TOCC6/ICP1/TXD0/SS)
14
PB2 (PCINT10/ADC8/CLKO/TOCC7/ICP2/RXD0)
13
PB3 (PCINT11/ADC9/RESET/dW)
12
PB1 (PCINT9/ADC10/XTAL2/INT0)
11
PB0 (PCINT8/ADC11/XTAL1/CLKI)
VCC
DNC
GND
ATtiny441/841 [SUMMARY DATASHEET]
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2
1.1.3 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not
running and provided the reset pin has not been disabled. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.1.4 Port A (PA7:PA0)
This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have standard
sink and source capability, except ports PA7 and PA5, which have high sink capability.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, the analog comparator, and ADC.
1.1.5 Port B (PB3:PB0)
This is a 4-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have standard
sink and source capability.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, and ADC.
ATtiny441/841 [SUMMARY DATASHEET]
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2. Overview
DEBUG
INTERFACE
CALIBRATED ULP
OSCILLATOR
WATCHDOG
TIMER
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
V
CC
RESET
GND
8-BIT DATA BUS
PB[3:0]
CPU CORE
PROGRAM
MEMORY
(FLASH)
DATA
MEMORY
(SRAM)
POWER
SUPERVISION:
POR
BOD
RESET
ISP
INTERFACE
PORT A PORT B
VOLTAGE
REFERENCE
MULTIPLEXER
ANALOG
COMPARATOR
ADC
TEMPERATURE
SENSOR
8-BIT
TIMER/COUNTER
16-BIT
TIMER/COUNTER
TWO-WIRE
INTERFACE
USART
EEPROM
ON-CHIP
DEBUGGER
PA[7:0]
ANALOG
COMPARATOR
16-BIT
TIMER/COUNTER
USART
ATtiny441/841 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATtiny441/841 achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
ATtiny441/841 [SUMMARY DATASHEET]
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8495HS–AVR–05/2014
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
ATtiny441/841 provides the following features:
4K/8K bytes of in-system programmable Flash
256/512 bytes of SRAM data memory
256/512 bytes of EEPROM data memory
12 general purpose I/O lines
32 general purpose working registers
One 8-bit timer/counter with two PWM channels
Two 16-bit timer/counters with two PWM channels
Internal and external interrupts
One 10-bit ADC with 5 internal and 12 external channels
One ultra-low power, programmable watchdog timer with internal oscillator
Two programmable USARTs with start frame detection
Slave Two-Wire Interface (TWI)
Master/slave Serial Peripheral Interface (SPI)
Calibrated 8MHz oscillator
Calibrated 32kHz, ultra low power oscillator
Four software selectable power saving modes.
The device includes the following modes for saving power:
Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt
system to continue functioning
ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O
modules except the ADC
Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or
hardware reset
Standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up
combined with low power consumption
The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash program memory can
be re-programmed in-system through a serial interface, by a conventional non-volatile memory programmer or by an onchip boot code, running on the AVR core.
The ATtiny441/841 AVR is supported by a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators and evaluation kits.
ATtiny441/841 [SUMMARY DATASHEET]
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3. General Information
3.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for
download at http://www.atmel.com/avr.
3.2 Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code
examples assume that the part specific header file is included before compilation. Be aware that not all C compiler
vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with
the C compiler documentation for more details.
3.3 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years
at 85°C or 100 years at 25°C.
3.4 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers
manufactured on the same process technology.
ATtiny441/841 [SUMMARY DATASHEET]
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