ATMEL ATtiny28L User Manual
BDTIC www.bdtic.com/ATMEL
Features
• Utilizes the AVR
• AVR – High-performance and Low-power RISC Architecture
– 90 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 4 MIPS Throughput at 4 MHz
• Nonvolatile Program Memory
– 2K Bytes of Flash Program Memory
– Endurance: 1,000 Write/Erase Cycles
– Programming Lock for Flash Program Data Security
• Peripheral Features
– Interrupt and Wake-up on Low-level Input
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Built-in High-current LED Driver with Programmable Modulation
• Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circuit with Programmable Start-up Time
– Internal Calibrated RC Oscillator
• Power Consumption at 1 MHz, 2V, 25°C
– Active: 3.0 mA
– Idle Mode: 1.2 mA
– Power-down Mode: <1 µA
• I/O and Packages
– 11 Programmable I/O Lines, 8 Input Lines and a High-current LED Driver
– 28-lead PDIP, 32-lead TQFP, and 32-pad MLF
• Operating Voltages
: 1.8V - 5.5V for the ATtiny28V
–V
CC
–VCC: 2.7V - 5.5V for the ATtiny28L
• Speed Grades
– 0 - 1.2 MHz for the ATtiny28V
– 0 - 4 MHz For the ATtiny28L
®
RISC Architecture
8-bit
Microcontroller
with 2K Bytes of
Flash
ATtiny28L
ATtiny28V
Pin Configurations
PDIP
RESET
XTAL1
XTAL2
(AIN0) PB0
PD0
PD1
PD2
PD3
PD4
VCC
GND
PD5
PD6
PD7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PA0
PA1
PA3
PA2 (IR)
PB7
PB6
GND
NC
VCC
PB5
PB4 (INT1)
PB3 (INT0)
PB2 (T0)
PB1 (AIN1)
PD3
PD4
NC
VCC
GND
NC
XTAL1
XTAL2
TQFP/QFN/MLF
PD2
PD1
32313029282726
1
2
3
4
5
6
7
8
9101112131415
PD5
PD6
PD0
RESET
PD7
(AIN0) PB0
PA0
PA1
PA3
(T0) PB2
(INT0) PB3
(AIN1) PB1
PA2 (IR)
25
24
23
22
21
20
19
18
17
16
(INT1) PB4
PB7
PB6
NC
GND
NC
NC
VCC
PB5
Rev. 1062F–AVR–07/06
1
Description The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi-
tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves
throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize
power consumption versus processing speed. The AVR core combines a rich instruction
set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
Block Diagram Figure 1. The ATtiny28 Block Diagram
VCC
GND
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
DATA REGISTER
+
-
ANALOG
COMPARATOR
PORTB
STACK
POINTER
HARDWARE
STACK
GENERAL
PURPOSE
REGISTERS
STATUS
REGISTER
PORTB
8-BIT DATA BUS
Z
ALU
INTERNAL
OSCILLATOR
WATCHDOG
MCU CONTROL
REGISTER
TIMER/
COUNTER
INTERRUPT
DATA REGISTER
PORTD
TIMER
UNIT
PORTD
OSCILLATOR
TIMING AND
CONTROL
DATA DIR
REG. PORTD
XTAL2XTAL1
INTERNAL
CALIBRATED
OSCILLATOR
HARDWARE
MODULATOR
DATA REGISTER
PORTA
PORTA
PORTA CONTROL
REGISTER
RESET
The ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/O
lines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an
8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with
internal oscillator and 2 software-selectable power-saving modes. The Idle Mode stops
the CPU while allowing the timer/counter and interrupt system to continue functioning.
The Power-down mode saves the register contents but freezes the oscillator, disabling
all other chip functions until the next interrupt or hardware reset. The wake-up or inter-
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ATtiny28L/V
rupt on low-level input feature enables the ATtiny28 to be highly responsive to external
events, still featuring the lowest power consumption while in the power-down modes.
The device is manufactured using Atmel’s high-density, nonvolatile memory technology.
By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel
ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective
solution to many embedded control applications. The ATtiny28 AVR is supported with a
full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.
Pin Descriptions
VCC Supply voltage pin.
GND Ground pin.
Port A (PA3..PA0) Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED
driver. At V
bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tristated when a reset condition becomes active, even if the clock is not running.
= 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are
CC
Port B (PB7..PB0) Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B
pins that are externally pulled low will source current if the pull-ups are activated.
Port B also serves the functions of various special features of the ATtiny28 as listed on
page 27. If any of the special features are enabled, the pull-up(s) on the corresponding
pin(s) is automatically disabled. The port pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port D (PD7..PD0) Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for
each bit). The port pins are tri-stated when a reset condition becomes active, even if the
clock is not running.
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
Figure 2.
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3
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from
the register file, the operation is executed, and the result is stored back in the register
file – in one clock cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This
pointer is called the Z-pointer and can address the register file and the Flash program
memory.
Figure 3. The ATtiny28 AVR RISC Architecture
Data Bus 8-bit
1K x 16
Program
Flash
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Test
32 x 8
General
Purpose
Registrers
Z
ALU
Control
Registrers
Interrupts
Unit
8-bit
Timer/Counter
Watchdog
Timer
Analog
Comparator
20
I/O Lines
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 3
shows the ATtiny28 AVR RISC microcontroller architecture. The AVR uses a Harvard
architecture concept – with separate memories and buses for program and data memories. The program memory is accessed with a two-stage pipeline. While one instruction
is being executed, the next instruction is pre-fetched from the program memory. This
concept enables instructions to be executed every clock cycle. The program memory is
reprogrammable Flash memory.
With the relative jump and relative call instructions, the whole 1K address space is
directly accessed. All AVR instructions have a single 16-bit word format, meaning that
every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subroutines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions such as
Control Registers, Timer/Counters and other I/O functions. The memory spaces in the
AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
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rate interrupt vector in the interrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt
vector position. The lower the interrupt vector address, the higher the priority.
ALU – Arithmetic Logic
Unit
Subroutine and Interrupt Hardware Stack
General-purpose Register File
The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main
categories – arithmetic, logic and bit functions. Some microcontrollers in the AVR product family feature a hardware multiplier in the arithmetic part of the ALU.
The ATtiny28 uses a 3-level-deep hardware stack for subroutines and interrupts. The
hardware stack is 10 bits wide and stores the program counter (PC) return address
while subroutines and interrupts are executed.
RCALL instructions and interrupts push the PC return address onto stack level 0, and
the data in the other stack levels 1 - 2 are pushed one level deeper in the stack. When a
RET or RETI instruction is executed the returning PC is fetched from stack level 0, and
the data in the other stack levels 1 - 2 are popped one level in the stack.
If more than three subsequent subroutine calls or interrupts are executed, the first values written to the stack are overwritten.
Figure 4 shows the structure of the 32 general-purpose registers in the CPU.
Figure 4. AVR CPU General-purpose Working Registers
70
R0
R1
R2
General …
Purpose …
Working R28
Registers R29
R30 (Z-Register low byte)
R31(Z-Register high byte)
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All the register operating instructions in the instruction set have direct and single cycle
access to all registers. The only exception are the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the
LDI instruction for load immediate constant data. These instructions apply to the second
half of the registers in the register file – R16..R31. The general SBC, SUB, CP, AND,
OR and all other operations between two registers or on a single register apply to the
entire register file.
Registers 30 and 31 form a 16-bit pointer (the Z-pointer), which is used for indirect Flash
memory and register file access. When the register file is accessed, the contents of R31
are discarded by the CPU.
5
Status Register
Status Register – SREG The AVR status register (SREG) at I/O space location $3F is defined as:
Bit 76543210
$3F I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after
an interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
• Bit 5 – H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruction Set description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the
Instruction Set description for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
See the Instruction Set description for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation. See the
Instruction Set description for detailed information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruction Set description for detailed information.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by
software.
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ATtiny28L/V
System Clock and Clock Options
The device has the following clock source options, selectable by Flash Fuse bits as
shown in Table 1.
Table 1. Device Clocking Option Select
Clock Option CKSEL3..0
External Crystal/Ceramic Resonator 1111 - 1010
External Low-frequency Crystal 1001 - 1000
External RC Oscillator 0111 - 0101
Internal RC Oscillator 0100 - 0010
External Clock 0001 - 0000
Note: “1” means unprogrammed, “0” means programmed.
The various choices for each clocking option give different start-up times as shown in
Table 5 on page 16.
Internal RC Oscillator The internal RC oscillator option is an on-chip calibrated oscillator running at a nominal
frequency of 1.2 MHz. If selected, the device can operate with no external components.
The device is shipped with this option selected.
Calibrated Internal RC Oscillator
The calibrated internal oscillator provides a fixed 1.2 MHz (nominal) clock at 3V and
25°C. This clock may be used as the system clock. This oscillator can be calibrated by
writing the calibration byte to the OSCCAL register. When this oscillator is used as the
chip clock, the Watchdog oscillator will still be used for the Watchdog Timer and for the
reset time-out. For details on how to use the pre-programmed calibration value, see the
section “Calibration Byte” on page 46.
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which
can be configured for use as an on-chip oscillator, as shown in Figure 5. Either a quartz
crystal or a ceramic resonator may be used. When the INTCAP fuse is programmed,
internal load capacitors with typical values 50 pF are connected between XTAL1/XTAL2
and ground.
Figure 5. Oscillator Connections
MAX 1 HC BUFFER
HC
C2
C1
Note: 1. When using the MCU oscillator as a clock for an external device, an HC buffer should
be connected as indicated in the figure.
XTAL2
XTAL1
GND
External Clock To drive the device from an external clock source, XTAL2 should be left unconnected
while XTAL1 is driven as shown in Figure 6.
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7
Figure 6. External Clock Drive Configuration
NC
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
XTAL1
GND
External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 7 can
be used. For details on how to choose R and C, see Table 25 on page 56.
Figure 7. External RC Configuration
CC
V
R
C
NC
XTAL2
XTAL1
GND
8
ATtiny28L/V
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Register Description
Oscillator Calibration Register
– OSCCAL
ATtiny28L/V
Bit 76543210
$00 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bits 7..0 – CAL7..CAL0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the internal oscillator to remove process variation from the oscillator frequency. When OSCCAL is zero, the lowest available
frequency is chosen. Writing non-zero values to the register will increase the frequency
to the internal oscillator. Writing $FF to the register gives the highest available frequency. Table 2 shows the range for OSCCAL. Note that the oscillator is intended for
calibration to 1.2 MHz, thus tuning to other values is not guaranteed. At 3V and 25
the pre-programmed calibration byte gives a frequency within ± 1% of the nominal
frequency.
Table 2. Internal RC Oscillator Range
OSCCAL Value Min Frequency Max Frequency
0x00 0.6 MHz 1.2 MHz
0x7F 0.8 MHz 1.7 MHz
o
C,
0xFF 1.2 MHz 2.5 MHz
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9
Memories
I/O Memory The I/O space definition of the ATtiny28 is shown in Table 3.
Table 3. ATtiny28 I/O Space
Address Hex Name Function
$3F SREG Status Register
$1B PORTA Data Register, Port A
$1A PACR Port A Control Register
$19 PINA Input Pins, Port A
$16 PINB Input Pins, Port B
$12 PORTD Data Register, Port D
$11 DDRD Data Direction Register, Port D
$10 PIND Input Pins, Port D
$08 ACSR Analog Comparator Control and Status Register
$07 MCUCS MCU Control and Status Register
$06 ICR Interrupt Control Register
$05 IFR Interrupt Flag Register
$04 TCCR0 Timer/Counter0 Control Register
$03 TCNT0 Timer/Counter0 (8-bit)
$02 MODCR Modulation Control Register
$01 WDTCR Watchdog Timer Control Register
$00 OSCCAL Oscillator Calibration Register
Note: Reserved and unused locations are not shown in the table.
All ATtiny28 I/O and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions transferring data between the 32 general-purpose working registers and the I/O space. I/O registers within the address range $00 $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the Instruction Set section for more details.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
The I/O and peripherals control registers are explained in the following sections.
10
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ATtiny28L/V
Program and Data Addressing Modes
The ATtiny28 AVR RISC microcontroller supports powerful and efficient addressing
modes. This section describes the different addressing modes supported in the
ATtiny28. In the figures, OP means the operation code part of the instruction word. To
simplify, not all figures show the exact location of the addressing bits.
Register Direct, Single
Figure 8. Direct Single Register Addressing
Register Rd
The operand is contained in register d (Rd).
Register Indirect Figure 9. Indirect Register Addressing
REGISTERFILE
0
Register Direct, Two Registers Rd and Rr
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Z-Register
30
31
The register accessed is the one pointed to by the Z-register (R31, R30).
Figure 10. Direct Register Addressing, Two Registers
11
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d
(Rd).
I/O Direct Figure 11. I/O Direct Addressing
Operand address is contained in six bits of the instruction word. n is the destination or
source register address.
Relative Program Addressing, RJMP and RCALL
Constant Addressing Using the LPM Instruction
Figure 12. Relative Program Memory Addressing
15 0
PC
+1
15 012 11
OP
k
PROGRAM MEMORY
$000
$3FF
Program execution continues at address PC + k + 1. The relative address k is -2048 to
2047.
Figure 13. Code Memory Constant Addressing
PROGRAM MEMORY
15 1 0
Z-REGISTER
$000
12
$3FF
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ATtiny28L/V
Constant byte address is specified by the Z-register contents. The 15 MSBs select word
address (0 - 1K), and LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =
1).
Memory Access and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock, directly generated from the external clock
crystal for the chip. No internal clock division is used.
Figure 14 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks and functions per power unit.
Figure 14. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 15 shows the internal timing concept for the register file. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 15. Single Cycle ALU Operation
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
Flash Program Memory The ATtiny28 contains 2K bytes of on-chip Flash memory for program storage. Since all
instructions are single 16-bit words, the Flash is organized as 1K x 16 words. The Flash
memory has an endurance of at least 1,000 write/erase cycles.
The ATtiny28 program counter is 10 bits wide, thus addressing the 1K word Flash program memory. See “Programming the Flash” on page 47 for a detailed description of
Flash data downloading.
1062F–AVR–07/06
13
Sleep Modes To enter the sleep modes, the SE bit in MCUCS must be set (one) and a SLEEP instruc-
tion must be executed. The SM bit in the MCUCS register selects which sleep mode
(Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt
occurs while the MCU is in a sleep mode, the MCU awakes. The CPU is then halted for
four cycles. It executes the interrupt routine and resumes execution from the instruction
following SLEEP. The contents of the register file and I/O memory are unaltered. If a
reset occurs during sleep mode, the MCU wakes up and executes from the Reset
vector.
Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle
Mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered
interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset. If
wake-up from the Analog Comparator Interrupt is not required, the analog comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Status register (ACSR). This will reduce power consumption in Idle Mode. Note that the
ACD bit is set by default.
Power-down Mode When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-
down mode. In this mode, the external oscillator is stopped, while the external interrupts
and the Watchdog (if enabled) continue operating. Only an external reset, a Watchdog
reset (if enabled), or an external level interrupt can wake up the MCU.
Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. This makes the MCU
less sensitive to noise. The wake-up period is equal to the clock-counting part of the
reset period (see Table 5). The MCU will wake up from power-down if the input has the
required level for two Watchdog oscillator cycles. If the wake-up period is shorter than
two Watchdog oscillator cycles, the MCU will wake up if the input has the required level
for the duration of the wake-up period. If the wake-up condition disappears before the
wake-up period has expired, the MCU will wake up from power-down without executing
the corresponding interrupt. The period of the Watchdog oscillator is 2.7 µs (nominal) at
3.0V and 25°C. The frequency of the watchdog oscillator is voltage-dependent as
shown in the section “Typical Characteristics” on page 57.
14
When waking up from the Power-down mode, there is a delay from the wake-up condition until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped.
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System Control and Reset
Reset Sources The ATtiny28 provides three sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
• External Reset. The MCU is reset when a low level is present on the RESET
more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog is enabled.
During reset, all I/O registers are then set to their initial values and the program starts
execution from address $000. The instruction placed in address $000 must be an RJMP
(relative jump) instruction to the reset handling routine. If the program never enables an
interrupt source, the interrupt vectors are not used, and regular program code can be
placed at these locations. The circuit diagram in Figure 16 shows the reset logic. Table 4
defines the timing and electrical parameters of the reset circuitry.
Figure 16. Reset Logic
POT
).
ATtiny28L/V
pin for
DATA BUS
MCU Control and Status
Register (MCUCS)
PORF
WDRF
EXTRF
VCC
100 - 500K
RESET
Power-on
Reset Circuit
Reset Circuit
SRQ
Watchdog
Timer
CKSEL[3..0]
COUNTER RESET
On-chip
RC Oscillator
Delay Counters
Full
CK
Table 4. Reset Characteristics
Symbol Parameter Min Typ Max Unit
Power-on Reset Threshold Voltage (rising) 1.0 1.4 1.8 V
(1)
V
POT
V
RST
Note: 1. The Power-on Reset will not work unless the supply voltage has been below V
Power-on Reset Threshold Voltage (falling) 0.4 0.6 0.8 V
RESET Pin Threshold Voltage 0.6 V
(falling).
CC
INTERNAL RESET
V
POT
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15
Table 5. ATtiny28 Clock Options and Start-up Time
CKSEL3..0 Clock Source Start-up Time at 2.7V
1111 External Crystal/Ceramic Resonator
1110 External Crystal/Ceramic Resonator
1101 External Crystal/Ceramic Resonator
1100 External Crystal/Ceramic Resonator 16K CK
1011 External Crystal/Ceramic Resonator 4.2 ms + 16K CK
1010 External Crystal/Ceramic Resonator 67 ms + 16K CK
1001 External Low-frequency Crystal 67 ms + 1K CK
1000 External Low-frequency Crystal 67 ms + 32K CK
0111 External RC Oscillator 6 CK
0110 External RC Oscillator 4.2 ms + 6 CK
0101 External RC Oscillator 67 ms + 6 CK
0100 Internal RC Oscillator 6 CK
0011 Internal RC Oscillator 4.2 ms + 6 CK
0010 Internal RC Oscillator 67 ms + 6 CK
0001 External Clock 6 CK
0000 External Clock 4.2 ms + 6 CK
Note: 1. Due to limited number of clock cycles in the start-up period, it is recommended that
ceramic resonator be used.
(1)
(1)
(1)
1K CK
4.2 ms + 1K CK
67 ms + 1K CK
This table shows the start-up times from reset. From Power-down mode, only the clock
counting part of the start-up time is used. The Watchdog oscillator is used for timing the
real-time part of the start-up time. The number WDT oscillator cycles used for each
time-out is shown in Table 6.
Table 6. Number of Watchdog Oscillator Cycles
Time-out Number of Cycles
4.2 ms 1K
67 ms 16K
The frequency of the Watchdog oscillator is voltage-dependent, as shown in the section
“Typical Characteristics” on page 57.
The device is shipped with CKSEL = 0010.
Power-on Reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-
tion level is nominally 1.4V. The POR is activated whenever V
is below the detection
CC
level. The POR circuit can be used to trigger the start-up reset, as well as detect a failure in supply voltage.
The Power-on Reset (POR) circuit ensures that the device is reset from power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which determines the delay for which the device is kept in RESET after V
rise. The time-out
CC
period of the delay counter can be defined by the user through the CKSEL fuses. The
different selections for the delay period are presented in Table 5. The RESET signal is
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ATtiny28L/V
activated again, without any delay, when the VCC decreases below detection level. See
Figure 17.
If the built-in start-up delay is sufficient, RESET
an external pull-up resistor. By holding the RESET
can be connected to VCC directly or via
pin low for a period after VCC has
been applied, the Power-on Reset period can be extended. Refer to Figure 18 for a timing example of this.
Figure 17. MCU Start-up, RESET
V
VCC
RESET
TIME-OUT
INTERNAL
RESET
POT
V
RST
Figure 18. MCU Start-up, RESET
V
VCC
RESET
POT
Tied to VCC.
t
TOUT
Controlled Externally
V
RST
t
TIME-OUT
INTERNAL
RESET
TOUT
External Reset An external reset is generated by a low level on the RESET
than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not
guaranteed to generate a reset. When the applied voltage reaches the Reset Threshold
Voltage (V
period (t
) on its positive edge, the delay timer starts the MCU after the Time-out
RST
) has expired.
TOUT
pin. Reset pulses longer
1062F–AVR–07/06
17
Figure 19. External Reset during Operation
VCC
RESET
TIME-OUT
INTERNAL
RESET
V
RST
t
TOUT
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
). Refer to page 37 for details on operation of the Watchdog.
(t
TOUT
Figure 20. Watchdog Reset during Operation
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Register Description
ATtiny28L/V
MCU Control and Status
Register – MCUCS
The MCU Control and Status Register contains control and status bits for general MCU
functions.
Bit 76543210
$07 PLUPB – SE SM WDRF – EXTRF PORF MCUCS
Read/Write R/W R R/W R/W R/W R R/W R/W
Initial Value 0 0 0 0 See Bit
Desc.
0 See Bit Description
• Bit 7 – PLUPB: Pull-up Enable Port B
When the PLUPB bit is set (one), pull-up resistors are enabled on all Port B input pins.
When PLUPB is cleared, the pull-ups are disabled. If any of the special functions of Port
B is enabled, the corresponding pull-up(s) is disabled, independent of the value of
PLUPB.
• Bit 6 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and always reads as zero.
• Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to set the Sleep Enable SE bit just before the
execution of the SLEEP instruction.
• Bit 4 – SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle
Mode is selected as sleep mode. When SM is set (one), Power-down mode is selected
as sleep mode. For details, refer to “Sleep Modes” below.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog reset occurs. The bit is cleared by a Power-on Reset, or by
writing a logical “0” to the flag.
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and always reads as zero.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an external reset occurs. The bit is cleared by a Power-on Reset, or by
writing a logical “0” to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is cleared by writing a logical “0” to the
flag.
To make use of the reset flags to identify a reset condition, the user should read and
then clear the flag bits in MCUCS as early as possible in the program. If the register is
cleared before another reset occurs, the source of the reset can be found by examining
the reset flags.
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19
Interrupts
Reset and Interrupt The ATtiny28 provides five different interrupt sources. These interrupts and the reset
vector each have a separate program vector in the program memory space. All the interrupts are assigned to individual enable bits. In order to enable the interrupt, both the
individual enable bit and the I-bit in the status register (SREG) must be set to one.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 7. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
Table 7. Reset and Interrupt Vectors
Vector
No.
1 $000 RESET
2 $001 INT0 External Interrupt Request 0
3 $002 INT1 External Interrupt Request 1
4 $003 Input Pins Low-level Input on Port B
5$004
6 $005 ANA_COMP Analog Comparator
Program
Address Source Interrupt Definition
Hardware Pin, Power-on Reset and
Watchdog Reset
TIMER0,
OVF0
Timer/Counter0 Overflow
The most typical and general program setup for the Reset and Interrupt vector
addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset handler
$001 rjmp EXT_INT0 ; IRQ0 handler
$002 rjmp EXT_INT1 ; IRQ1 handler
$003 rjmp LOW_LEVEL ; Low level input handler
$004 rjmp TIM0_OVF ; Timer0 overflow handle
$005 rjmp ANA_COMP ; Analog Comparator handle
;
$006 MAIN: <instr> xxx ; Main program start
… … … …
Interrupt Handling The ATtiny28 has one 8-bit Interrupt Control Register (ICR).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the program counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
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If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled or the
flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is active.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by
software.
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After four clock cycles the program vector address for the actual interrupt
handling routine is executed. During this 4-clock-cycle period, the program counter (10
bits) is pushed onto the stack. The vector is normally a relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt occurs during execution of a
multi-cycle instruction, this instruction is completed before the interrupt is served. If an
interrupt occurs when the MCU is in sleep mode, the interrupt execution response time
is increased by four clock cycles.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the program counter (10 bits) is popped back from the stack, and the I-flag
in SREG is set. When AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
External Interrupt The external interrupt is triggered by the INT pins. Observe that, if enabled, the interrupt
will trigger even if the INT pin is configured as an output. This feature provides a way of
generating a software interrupt. The external interrupt can be triggered by a falling or rising edge, a pin change or a low level. This is set up as indicated in the specification for
the Interrupt Control Register (ICR). When the external interrupt is enabled and is configured as level-triggered, the interrupt will trigger as long as the pin is held low.
The external interrupt is set up as described in the specification for the Interrupt Control
Register (ICR).
Low-level Input Interrupt The low-level interrupt is triggered by setting any of the Port B pins low. However, if any
Port B pins are used for other special features, these pins will not trigger the interrupt.
For example, if the analog comparator is enabled, a low level on PB0 or PB1 will not
cause an interrupt. This is also the case for the special functions T0, INT0 and INT1. If
low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. When this interrupt is enabled, the
interrupt will trigger as long as any of the Port B pins are held low.
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21
Register Description
Interrupt Control Register –
ICR
Bit 76543210
$06 INT1 INT0 LLIE TOIE0 ISC11 ISC10 ISC01 ISC00 ICR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and I-bit in the Status Register (SREG) is set (one), the
external pin interrupt 1 is enabled. The interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) define whether the external interrupt is activated on rising or falling edge, on pin
change or low level of the INT1 pin. The corresponding interrupt of External Interrupt
Request 1 is executed from program memory address $002. See also “External
Interrupt”.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt 0 is enabled. The interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) define whether the external interrupt is activated on rising or falling edge, on pin
change or low level of the INT0 pin. The corresponding interrupt of External Interrupt
Request 0 is executed from program memory address $001. See also “External
Interrupt”.
• Bit 5 – LLIE: Low-level Input Interrupt Enable
When the LLIE is set (one) and the I-bit in the status register (SREG) is set (one), the
interrupt on low-level input is activated. Any of the Port B pins pulled low will then cause
an interrupt. However, if any Port B pins are used for other special features, these pins
will not trigger the interrupt. The corresponding interrupt of Low-level Input Interrupt
Request is executed from program memory address $003. See also “Low-level Input
Interrupt”.
• Bit 4 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
in the Interrupt Flag Register (IFR).
• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the
corresponding interrupt enable are set. The level and edges on the external INT1 pin
that activate the interrupt are defined in Table 8.
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Table 8. Interrupt 1 Sense Control
ISC11 ISC10 Description
0 0 The low level of INT1 generates an interrupt request.
0 1 Any change on INT1 generates an interrupt request.
1 0 The falling edge of INT1 generates an interrupt request.
1 1 The rising edge of INT1 generates an interrupt request.
Note: When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its Interrupt
Enable bit. Otherwise, an interrupt can occur when the bits are changed.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt enable are set. The level and edges on the external INT0 pin
that activate the interrupt are defined in Table 9.
Table 9. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
0 1 Any change on INT0 generates an interrupt request.
1 0 The falling edge of INT0 generates an interrupt request.
Interrupt Flag Register – IFR
1 1 The rising edge of INT0 generates an interrupt request.
Note: When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its Interrupt
Enable bit. Otherwise, an interrupt can occur when the bits are changed.
The value on the INT pins are sampled before detecting edges. If edge interrupt is
selected, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate
an interrupt request as long as the pin is held low.
Bit 76543210
$05 INTF1INTF0–TOV0––––IFR
Read/Write R/W R/W R R/W R R R R
Initial Value00000000
• Bit 7 – INTF1: External Interrupt Flag1
When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt
flag, INTF1 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT1 in GIMSK is set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical “1” to it. This flag is always cleared when INT1 is configured
as level interrupt.
1062F–AVR–07/06
• Bit 6 – INTF0: External Interrupt Flag0
When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt
flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt
23
enable bit, INT0 in GIMSK is set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured
as level interrupt.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and always reads as zero.
• Bit 4 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. TOV0 is
cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 in ICR and TOV0
are set (one), the Timer/Counter0 Overflow interrupt is executed.
• Bit 3..0 - Res: Reserved Bits
These bits are reserved bits in the ATtiny28 and always read as zero.
Note: 1. One should not try to use the SBI (Set Bit in I/O Register) instruction to clear individ-
ual flags in the Register. This will result in clearing all the flags in the register,
because the register is first read, then modified and finally written, thus writing ones
to all set flags. Using the CBI (Clear Bit in I/O Register) instruction on IFR will result in
clearing all bits apart from the specified bit.
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ATtiny28L/V
I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/O
ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same
applies for changing drive value (if configured as output) or enabling/disabling of pull-up
resistors (if configured as input).
Port A Port A is a 4-bit I/O port. PA3, PA1, and PA0 are bi-directional, while PA2 is output-only.
Before entering Power-down, see “Sleep Modes” on page 14, PORTA2 bit in PORTA
register should be set.
Three I/O memory address locations are allocated for Port A, one each for the Data
Register – PORTA, $1B, Port A Control Register – PACR, $1A and the Port A Input Pins
– PINA, $19. The Port A Input Pins address is read-only, while the Data Register and
the Control Register are read/write. Compared to other output ports, the Port A output is
delayed one extra clock cycle.
Port pins PA0, PA1 and PA3 have individually selectable pull-up resistors. When pins
PA0, PA1 or PA3 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. PA2 is output-only. The PA2 output
buffer can sink 25 mA and thus drive a high-current LED directly. This output can also
be modulated (see “Hardware Modulator” on page 39 for details).
Port A as General Digital I/O PA3, PA1 and PA0 are general I/O pins. The DDAn (n: 3,1,0) bits in PACR select the
direction of these pins. If DDAn is set (one), PAn is configured as an output pin. If DDAn
is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when the pin
is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up
resistor off, the PORTAn bit has to be cleared (zero) or the pin has to be configured as
an output pin. The effects of the DDAn and PORTAn bits on PA3, PA1 and PA0 are
shown in Table 10. The port pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Table 10. DDAn Effects on Port A Pins
DDAn PORTAn I/O Pull-up Comment
0 0 Input No Tri-state (high-Z)
0 1 Input Yes PAn will source current if ext. pulled low.
1 0 Output No Push-pull Zero Output
1 1 Output No Push-pull One Output
Note: n: 3,1,0, pin number
Alternate Function of PA2 PA2 is the built-in, high-current LED driver and it is always an output pin. The output sig-
nal can be modulated with a software programmable frequency. See “Hardware
Modulator” on page 39 for further details.
1062F–AVR–07/06
25
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