Features
• Frequency Range 5 GHz to 6 GHz
• P
25 dBm at 5.8 GHz
out
• Gain Typically 30 dB
• P
Typically 0 dBm
in
• V
2.7V to 3.8V
CC
• Power Consumption in Power-down Mode Typically < 1 µA
• Package: QFN16 3 mm × 3 mm
Benefits
• Biasing Control Extends Battery Time
• Simple Input and Output Matching
• Only One Single Supply Required
• No High-side Switching Transistor Required
1. Description
1.1 Process
This 5-GHz power amplifier (PA) is designed using Atmel’s Silicon-Germanium (SiGe)
process and provides high efficiency.
5.8 GHz WDCT
Power Amplifier
ATR7040
1.2 Circuitry
The PA, ATR7040, consists of a three-stage amplifier with a typical output power of
25 dBm. The output stage was implemented using an open-collector structure. Power
up, power down, and output level are controlled at bias control pin 6 (V
).
ctl
4868C–DECT–05/06
Figure 1-1. Block Diagram
RFIN
10
VCC1
7
13
VCTL
VCC2
6
ATR7040
Matching Matching
Bias control
14
GND
PADDLE
GND
RFOUT/VCC3
2
RFOUT/VCC3
3
15
VCC_CTL
2
ATR7040
4868C–DECT–05/06
2. Pin Configuration
Figure 2-1. Pinning QFN16
NC
RFOUT/VCC3
RFOUT/VCC3
NC
VCC_CTL
NC
16 15 14 13
1
ATR7040
2
3
GND on the
PADDLE
4
5 6 7 8
GND
VCTL
12
11
10
9
ATR7040
NC
NC
RFIN
NC
NC
Table 2-1. Pin Description
Pin Symbol Function
1 NC Not connected
2 RFOUT RF output and supply voltage for output amplifier stage
3 RFOUT RF output and supply voltage for output amplifier stage
4 NC Not connected
5 NC Not connected
6 VCC2 Supply voltage for second amplifier stage
7 VCC1 Supply voltage for first amplifier stage
8 NC Not connected
9 NC Not connected
10 RFIN RF input
11 NC Not connected
12 NC Not connected
13 VCTL Control voltage for power ramping
14 GND Ground
15 VCC_CTL Supply voltage for biasing control block
16 NC Not connected
PADDLE – Ground
Note: 1. Pin can be connected to paddle for increased GND area
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
VCC1
VCC2
NC
4868C–DECT–05/06
3
3. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Symbol Value Unit
Supply voltage V
Supply current I
Junction temperature T
Storage temperature T
Input RF power P
Control voltage V
CC
cc
j
Stg
in
ctl
5V
400 mA
150 °C
–40 to +125 °C
10 dBm
2.5 V
Note: The part may not survive all maximums applied simultaneously.
Electrostatic sensitive device.
Observe precautions for handling.
4. Thermal Resistance
Parameters Symbol Value Unit
Junction ambient package QFN16, 3 × 3,
slug soldered on PCB
R
thJA
40 K/W
5. Operating Range
Parameters Symbol Value Unit
Supply voltage V
Operating frequency range f
Ambient temperature range T
CC
in
amb
2.7 to 3.8 V
5100 to 5900 MHz
–25 to +75 °C
4
ATR7040
4868C–DECT–05/06
ATR7040
T
6. Electrical Characteristics
Operating conditions: VCC = 3.6V, V
= 25°C, unless otherwise specified.
T
amb
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
1.0 Frequency range
1.1 Supply voltage V
1.2 Input power P
1.3 Saturated power output P
1.4 Output power deviation P
1.5 Control voltage range
1.6 Control input current PA on 5 I
1.7 Input return loss With external matching 10 –7 –6 dB
1.8 Isolation V
1.9 Power added efficiency
1.10 Current consumption For 25 dBm output power I
1.11
Current consumption in
power-down mode
1.12 Duty cycle of operation At saturated output power 100 %
= 1.5V, input frequency = 5.8 GHz, input power 0 dBm, pulsed mode, duty cycle 10%, ton = 1 ms,
ctl
Depends on external
circuitry
PA operating mode V
Power-down mode V
≤ 0.2V ISO
ctl
At power saturation,
=0dBm
P
in
≤ 0.2V I
V
ctl
PA E 3 5 %
cc
in
25 dBm
sat
d
ctl
ctl
ctl
r
cc
cc
5100 5900 MHz
2.7 3.6 3.8 V
0dBm
–2 +2 dB
1.0 1.7 V
0.2 V
90 µA
33 35 dB
250 mA
1µA
7. Application Circuit
Figure 7-1. Application Circuit
RFIN
C1
TRL1
10
11
12
slug
9
VCC
765
8
13 14 15 16
VCCVCTL
4
3
TRL2
2
1
L1
C3C6RFOU
C2
4868C–DECT–05/06
5
8. Diagrams
Figure 8-1. Output Power, Efficiency and Supply Currents Versus Input Frequency
Pin = 0 dBm, Vcc = 3.6V, V
40
35
30
25
(dBm), PAE %
20
out
P
15
10
56 00 56 50 570 0 5750 58 00 58 50 59 00 59 50 6000
PAE (%)
I
ges
Frequency (MHz)
(mA)
ctl
P
out
= 1.4V
(dBm)
400
350
300
250
200
15 0
10 0
50
0
(mA)
ges
I
Figure 8-2. Output Power, Gain, Efficiency and Supply Currents Versus Input Power
Freq = 5800 MHz, Vcc = 3.6V, V
40
30
20
10
PAE (%)
0
-10
(dBm), Gain (dB), PAE (%)
out
-20
P
-30
-20 -15 -10 -5 0 5
P
out
Gain (dB)
(dBm)
= 1.4V
ctl
400
350
300
250
(mA)
200
ges
I
15 0
I
(mA)
ges
10 0
50
0
Pin (dBm)
Figure 8-3. Output Power, Efficiency and Supply Currents Versus Operating Voltage
Freq = 5800 MHz, Pin = 0 dBm, V
40
PAE (%)
35
30
(mA)
I
25
(dBm), PAE (%)
20
out
P
15
10
2.5 3.0 3.5 4.0
ges
P
(dBm)
out
Vcc (V)
= 1.5V
ctl
450
400
350
300
250
200
15 0
10 0
50
0
(mA)
ges
I
6
ATR7040
4868C–DECT–05/06
9. Ordering Information
Extended Type Number Package Remarks
ATR7040-PVPG QFN16, 3 × 3 Taped and reeled, MOQ 2000, Pb-free
ATR7040-PVQG QFN16, 3 × 3 Taped and reeled, MOQ 8000, Pb-free
10. Package Information
Package: QFN 16 - 3x3
Exposed pad 1.7x1.7
(acc. JEDEC OUTLINE No. MO-220)
Dimensions in mm
0.9±0.1
3
1.7
ATR7040
Not indicated tolerances ±0.05
16
1
4
Drawing-No.: 6.543-5115.01-4
Issue: 1; 07.03.05
Assembly Chip PAC
0.05
0.25
+0
-0.05
1613
12 1
0.4±0.1
94
0.5 nom.
1.5
2.68
technical drawings
according to DIN
specifications
0.15
58
4868C–DECT–05/06
7
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4868C–DECT–05/06
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