Atmel ATR7040 User Manual
Features
• Frequency Range 5 GHz to 6 GHz
• P
25 dBm at 5.8 GHz
out
• Gain Typically 30 dB
• P
Typically 0 dBm
in
• V
2.7V to 3.8V
CC
• Power Consumption in Power-down Mode Typically < 1 µA
• Package: QFN16 3 mm × 3 mm
Benefits
• Biasing Control Extends Battery Time
• Simple Input and Output Matching
• Only One Single Supply Required
• No High-side Switching Transistor Required
1. Description
1.1 Process
This 5-GHz power amplifier (PA) is designed using Atmel’s Silicon-Germanium (SiGe)
process and provides high efficiency.
5.8 GHz WDCT
Power Amplifier
ATR7040
1.2 Circuitry
The PA, ATR7040, consists of a three-stage amplifier with a typical output power of
25 dBm. The output stage was implemented using an open-collector structure. Power
up, power down, and output level are controlled at bias control pin 6 (V
).
ctl
4868C–DECT–05/06
Figure 1-1. Block Diagram
RFIN
10
VCC1
7
13
VCTL
VCC2
6
ATR7040
Matching Matching
Bias control
14
GND
PADDLE
GND
RFOUT/VCC3
2
RFOUT/VCC3
3
15
VCC_CTL
2
ATR7040
4868C–DECT–05/06
2. Pin Configuration
Figure 2-1. Pinning QFN16
NC
RFOUT/VCC3
RFOUT/VCC3
NC
VCC_CTL
NC
16 15 14 13
1
ATR7040
2
3
GND on the
PADDLE
4
5 6 7 8
GND
VCTL
12
11
10
9
ATR7040
NC
NC
RFIN
NC
NC
Table 2-1. Pin Description
Pin Symbol Function
1 NC Not connected
2 RFOUT RF output and supply voltage for output amplifier stage
3 RFOUT RF output and supply voltage for output amplifier stage
4 NC Not connected
5 NC Not connected
6 VCC2 Supply voltage for second amplifier stage
7 VCC1 Supply voltage for first amplifier stage
8 NC Not connected
9 NC Not connected
10 RFIN RF input
11 NC Not connected
12 NC Not connected
13 VCTL Control voltage for power ramping
14 GND Ground
15 VCC_CTL Supply voltage for biasing control block
16 NC Not connected
PADDLE – Ground
Note: 1. Pin can be connected to paddle for increased GND area
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
VCC1
VCC2
NC
4868C–DECT–05/06
3
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