Atmel ATmega8A Datasheet

Features

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 8K Bytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1K Byte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package

• Eight Channels 10-bit Accuracy

– 6-channel ADC in PDIP package

• Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF

• Operating Voltages

– 2.7 - 5.5V for ATmega8A

• Speed Grades

– 0 - 16 MHz for ATmega8A

• Power Consumption at 4 Mhz, 3V, 25°C

– Active: 3.6 mA
– Idle Mode: 1.0 mA
– Power-down Mode: 0.5 µA

®

8-bit Microcontroller

(1)

8-bit
with 8K Bytes
In-System
Programmable
Flash

ATmega8A

Summary

8159CS–AVR–07/09

1. Pin Configurations

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

(INT1) PD3

(XCK/T0) PD4

GND
VCC
GND

VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)

32313029282726

25

9101112131415

16

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP1) PB0

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

(MISO) PB4

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

TQFP Top View

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

(RESET) PC6

(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3

(XCK/T0) PD4

VCC

GND
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0

PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
GND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)

PDIP

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

32313029282726

25

9101112131415

16

MLF Top View

(INT1) PD3

(XCK/T0) PD4

GND
VCC
GND

VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP1) PB0

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

(MISO) PB4

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

NOTE:
The large center pad underneath the MLF
packages is made of metal and internally
connected to GND. It should be soldered
or glued to the PCB to ensure good
mechanical stability. If the center pad is
left unconneted, the package might
loosen from the PCB.

Figure 1-1. Pinout ATmega8A

ATmega8A

8159CS–AVR–07/09

2

INTERNAL

OSCILLATOR

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

OSCILLATOR

TIMERS/

COUNTERS

INTERRUPT

UNIT

STACK

POINTER

EEPROM

SRAM

STATUS

REGISTER

USART

PROGRAM
COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

PROGRAMMING

LOGIC

SPI

ADC

INTERFACE

COMP.

INTERFACE

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

GENERAL
PURPOSE

REGISTERS

X

Y

Z

ALU

+

-

PORTB DRIVERS/BUFFERS

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

XTAL1

XTAL2

CONTROL

LINES

VCC

GND

MUX &

ADC

AGND

AREF

PC0 - PC6 PB0 - PB7

PD0 - PD7

AVR CPU

TWI

RESET

ATmega8A

2. Overview

The ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR RISC architec­ture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves
throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power con­sumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

8159CS–AVR–07/09

3

ATmega8A

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

The ATmega8A provides the following features: 8K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general pur­pose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with
compare modes, internal and external interrupts, a serial programmable USART, a byte oriented
Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages)
with 10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial
port, and five software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the device is
sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchro­nous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,
the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows
very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The
Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a
conventional non-volatile memory programmer, or by an On-chip boot program running on the
AVR core. The boot program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash Section will continue to run while the
Application Flash Section is updated, providing true Read-While-Write operation. By combining
an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega8A is a powerful microcontroller that provides a highly-flexible and cost-effective solu­tion to many embedded control applications.

The ATmega8A AVR is supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators,
and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

8159CS–AVR–07/09

4

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil­lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1
input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in “Alternate Functions of Port B” on page

58 and “System Clock and Clock Options” on page 24.

2.2.4 Port C (PC5:PC0)

Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

2.2.5 PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char­acteristics of PC6 differ from those of the other pins of Port C.

ATmega8A

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 25-3 on page 247. Shorter pulses are not guaran­teed to generate a Reset.

The various special features of Port C are elaborated on page 61.

2.2.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8A as listed on page

63.

2.2.7 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 25-3 on page

247. Shorter pulses are not guaranteed to generate a reset.

2.2.8 AV

CC

AVCC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be
externally connected to V
nected to V

, even if the ADC is not used. If the ADC is used, it should be con-

CC

through a low-pass filter. Note that Port C (5:4) use digital supply voltage, VCC.

CC

2.2.9 AREF

8159CS–AVR–07/09

AREF is the analog reference pin for the A/D Converter.

5

2.2.10 ADC7:6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.

ATmega8A

8159CS–AVR–07/09

6

ATmega8A

5. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x3F (0x5F) SREG I T H S V N Z C 8

0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 11

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11

0x3C (0x5C) Reserved

0x3B (0x5B) GICR INT1 INT0 – – – – IVSEL IVCE 48, 68

0x3A (0x5A) GIFR INTF1 INTF0 – – – – – –69

0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 73, 104, 124

0x38 (0x58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 74, 104, 104

0x37 (0x57) SPMCR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 224

0x36 (0x56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 191

0x35 (0x55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 36, 67

0x34 (0x54) MCUCSR – – – – WDRF BORF EXTRF PORF 43

0x33 (0x53) TCCR0 – – – – – CS02 CS01 CS00 73

0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) 73

0x31 (0x51) OSCCAL Oscillator Calibration Register 31

0x30 (0x50) SFIOR

0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 99

0x2E (0x4E) TCCR1B ICNC1 ICES1

0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High byte 102

0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low byte 102

0x2B (0x4B) OCR1AH

0x2A (0x4A) OCR1AL

0x29 (0x49) OCR1BH

0x28 (0x48) OC R1BL

0x27 (0x47) ICR1H Timer/Counter1 – Input Capture Register High byte 103

0x26 (0x46) ICR1L Timer/Counter1 – Input Capture Register Low byte 103

0x25 (0x45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 121

0x24 (0x44) TCNT2 Timer/Counter2 (8 Bits) 123

0x23 (0x43) OCR2

0x22 (0x42) AS SR – – – – AS2 TCN2UB OCR2UB TCR2UB 123

0x21 (0x41) WDTCR – – – WDCE WDE WD P2 WDP1 WDP0 43

(1)

0x20

(0x40)

0x1F (0x3F) EEARH – – – – – – –EEAR8 19

0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 19

0x1D (0x3D) EEDR EEPROM Data Register 19

0x1C (0x3C) EECR – – – – EERIE EEMWE EEWE EERE 19

0x1B (0x3B) Reserved

0x1A (0x3A) Reserved

0x19 (0x39) Reserved

0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 65

0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 65

0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 65

0x15 (0x35) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 65

0x14 (0x34) DDRC

0x13 (0x33) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 65

0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 65

0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 65

0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 66

0x0F (0x2F) SPDR SPI Data Register 135

0x0E (0x2E) SPSR SPIF WCOL – – – – – SPI2X 134

0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 133

0x0C (0x2C) UDR USART I/O Data Register 156

0x0B (0x2B) UCSRA RXC TXC UDRE FE D OR PE U2X MPCM 157

0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 158

0x09 (0x29) UBRRL USART Baud Rate Register Low byte 160

0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 196

0x07 (0x27) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 208

0x06 (0x26) ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 209

0x05 (0x25) ADCH ADC Data Register High byte 210

0x04 (0x24) ADCL ADC Data Register Low byte 210

0x03 (0x23) TWDR Two-wire Serial Interface Data Register 193

0x02 (0x22) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 194

UBRRH URSEL – – – UBRR[11:8] 160

(1)

UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 159

– – – – ACME PUD PSR2 PSR10 57, 77, 125, 196

– WGM13 WGM12 CS12 CS11 CS10 101

Timer/Counter1 – Output Compare Register A High byte

Timer/Counter1 – Output Compare Register A Low byte

Timer/Counter1 – Output Compare Register B High byte

Timer/Counter1 – Output Compare Register B Low byte

Timer/Counter2 Output Compare Register

– DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 65

103

103

103

103

123

8159CS–AVR–07/09

7

ATmega8A

5. Register Summary (Continued)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x01 (0x21) TWSR TWS7

0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register 191

TWS6 TWS5 TWS4 TWS3

–

Note: 1. Refer to the USART description for details on how to access UBRRH and UCSRC.

2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.

TWPS1 TWPS0

193

8159CS–AVR–07/09

8

ATmega8A

6. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← ZNone3

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Clear ed if (H = 0) then PC ← PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2

Mnemonics Operands Description Operation Flags #Clocks

8159CS–AVR–07/09

9

ATmega8A

6. Instruction Set Summary (Continued)

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1 / 2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1 / 2

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word

LDI Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0:6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3:0)←Rd(7:4),Rd(7:4)←Rd(3:0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG( s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

Mnemonics Operands Description Operation Flags #Clocks

Rd+1:Rd ← Rr+1:Rr

None 1

8159CS–AVR–07/09

10

ATmega8A

6. Instruction Set Summary (Continued)

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

8159CS–AVR–07/09

11

ATmega8A

7. Ordering Information

Speed (MHz) Power Supply (V) Ordering Code Package

ATmega8A-AU

16 2.7 - 5.5

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc­tive). Also Halide free and fully Green.

ATmega8A-PU
ATmega8A-MU

(2)

(2)

(2)

32A
28P3
32M1-A

(1)

Operation Range

Industrial

°C to 85°C)

(-40

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

8159CS–AVR–07/09

12

8. Packaging Information

2325 Orchard Parkway
San Jose, CA 95131

TITLE

DRAWING NO.

R

REV.

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

B

32A

10/5/2001

PIN 1 IDENTIFIER

0˚~7˚

PIN 1

L

C

A1

A2 A

D1

D

e

E1 E

B

Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 8.75 9.00 9.25

D1 6.90 7.00 7.10 Note 2

E 8.75 9.00 9.25

E1 6.90 7.00 7.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

8.1 32A

ATmega8A

8159CS–AVR–07/09

13

8.2 28P3

2325 Orchard Parkway
San Jose, CA 95131

TITLE

DRAWING NO.

R

REV.

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

B

28P3

09/28/01

PIN

1

E1

A1

B

REF

E

B1

C

L

SEATING PLANE

A

0º ~ 15º

D

e

eB

B2

(4 PLACES)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

A – – 4.5724

A1 0.508 – –

D 34.544 – 34.798 Note 1

E 7.620 – 8.255

E1 7.112 – 7.493 Note 1

B 0.381 – 0.533

B1 1.143 – 1.397

B2 0.762 – 1.143

L 3.175 – 3.429

C 0.203 – 0.356

eB – – 10.160

e 2.540 TYP

Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

ATmega8A

8159CS–AVR–07/09

14

32M1-A

ATmega8A

D

D1

1

2

3

Pin 1 ID

E1

E

TOP VIEW

K

P

D2

P

Pin #1 Notch

(0.20 R)

1

2

3

E2

K

b

e

L

BOTTOM VIEW

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

A2

A

0

SIDE VIEW

A3

A1

0.08

SYMBOL

A 0.80 0.90 1.00

A1 – 0.02 0.05

A2 – 0.65 1.00

A3 0.20 REF

b 0.18 0.23 0.30

D

D1

D2 2.95 3.10 3.25

E

E1

E2 2.95 3.10 3.25

e 0.50 BSC

L 0.30 0.40 0.50

P – – 0.60

– – 12o

0

K 0.20 – –

COMMON DIMENSIONS

C

(Unit of Measure = mm)

MIN

4.90 5.00 5.10

4.70 4.75 4.80

4.90 5.00 5.10

4.70 4.75 4.80

NOM

MAX

NOTE

R

8159CS–AVR–07/09

2325 Orchard Parkway
San Jose, CA 95131

TITLE

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

DRAWING NO.

32M1-A

5/25/06

REV.

E

15

9. Errata

The revision letter in this section refers to the revision of the ATmega8A device.

9.1 ATmega8A, rev. L

• First Analog Comparator conversion may be delayed

• Interrupts may be lost when writing the timer registers in the asynchronous timer

• Signature may be Erased in Serial Programming Mode

• CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is

Used to Clock the Asynchronous Timer/Counter2

• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

ATmega8A

If the device is powered by a slow rising V
take longer than expected on some devices.

Problem Fix / Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.

The interrupt will be lost if a timer register that is synchronous timer clock is written when the
asynchronous Timer/Counter register (TCNTx) is 0x00.

Problem Fix / Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous
Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

, the first Analog Comparator conversion will

CC

3. Signature may be Erased in Serial Programming Mode

If the signature bytes are read before a chiperase command is completed, the signature may
be erased causing the device ID and calibration bytes to disappear. This is critical, espe­cially, if the part is running on internal RC oscillator.

Problem Fix / Workaround:

Ensure that the chiperase command has exceeded before applying the next command.

4. CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz
Oscillator is Used to Clock the Asynchronous Timer/Counter2

When the internal RC Oscillator is used as the main clock source, it is possible to run the
Timer/Counter2 asynchronously by connecting a 32 KHz Oscillator between XTAL1/TOSC1
and XTAL2/TOSC2. But when the internal RC Oscillator is selected as the main clock
source, the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and
XTAL2/TOSC2. As long as there are no capacitors connected to XTAL1/TOSC1 and
XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed.

Problem Fix / Workaround

Use external capacitors in the range of 20 - 36 pF on XTAL1/TOSC1 and XTAL2/TOSC2.
This will be fixed in ATmega8A Rev. G where the CKOPT Fuse will control internal capaci­tors also when internal RC Oscillator is selected as main clock source. For ATmega8A Rev.
G, CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. Cus­tomers who want compatibility between Rev. G and older revisions, must ensure that
CKOPT is unprogrammed (CKOPT = 1).

8159CS–AVR–07/09

16

ATmega8A

5. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg­ister triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

8159CS–AVR–07/09

17

10. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section refers to the document revision.

10.1 Rev.8159C – 07/09

1.

Updated “Errata” on page 298.

2.

Updated the last page with Atmel’s new addresses.

10.2 Rev.8159BS – 05/09

1.

Updated “System and Reset Characteristics” on page 247 with new BODLEVEL values

ATmega8A

2.

3.

4.

5.

10.3 Rev.8159AS – 08/08

1. Initial revision (Based on the ATmega8/L datasheet 2486T-AVR-05/08)

2. Changes done compared to ATmega8/L datasheet 2486T-AVR-05/08:

Updated “ADC Characteristics” on page 251 with new V

values.

INT

Updated “Typical Characteristics” view.

Updated “Errata” on page 298. ATmega8A, rev L.

Created a new Table Of Contents.

– All Electrical Characteristics are moved to “Electrical Characteristics” on

page 244.

– Updated “DC Characteristics” on page 244 with new

0.6V) and typical value for

I

.

CC

V

Max (0.9V and

OL

– Added “Speed Grades” on page 246.

– Added a new sub section “System and Reset Characteristics” on page 247.

– Updated “System and Reset Characteristics” on page 247 with new

BODLEVEL = 0 (3.6V, 4.0V and 4.2V).

– Register descriptions are moved to sub section at the end of each chapter.

– New graphics in “Typical Characteristics” on page 252.

–New “Ordering Information” on page 294.

V

BOT

8159CS–AVR–07/09

18

Headquarters International

Atmel Corporation

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8159CS–AVR–07/09