Atmel ATmega8A Datasheet

Features

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 8K Bytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1K Byte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package

• Eight Channels 10-bit Accuracy

– 6-channel ADC in PDIP package

• Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF

• Operating Voltages

– 2.7 - 5.5V for ATmega8A

• Speed Grades

– 0 - 16 MHz for ATmega8A

• Power Consumption at 4 Mhz, 3V, 25°C

– Active: 3.6 mA
– Idle Mode: 1.0 mA
– Power-down Mode: 0.5 µA

®

8-bit Microcontroller

(1)

8-bit
with 8K Bytes
In-System
Programmable
Flash

ATmega8A

Summary

8159CS–AVR–07/09

1. Pin Configurations

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

(INT1) PD3

(XCK/T0) PD4

GND
VCC
GND

VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)

32313029282726

25

9101112131415

16

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP1) PB0

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

(MISO) PB4

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

TQFP Top View

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

(RESET) PC6

(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3

(XCK/T0) PD4

VCC

GND
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0

PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
GND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)

PDIP

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

32313029282726

25

9101112131415

16

MLF Top View

(INT1) PD3

(XCK/T0) PD4

GND
VCC
GND

VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP1) PB0

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

(MISO) PB4

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

NOTE:
The large center pad underneath the MLF
packages is made of metal and internally
connected to GND. It should be soldered
or glued to the PCB to ensure good
mechanical stability. If the center pad is
left unconneted, the package might
loosen from the PCB.

Figure 1-1. Pinout ATmega8A

ATmega8A

8159CS–AVR–07/09

2

INTERNAL

OSCILLATOR

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

OSCILLATOR

TIMERS/

COUNTERS

INTERRUPT

UNIT

STACK

POINTER

EEPROM

SRAM

STATUS

REGISTER

USART

PROGRAM
COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

PROGRAMMING

LOGIC

SPI

ADC

INTERFACE

COMP.

INTERFACE

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

GENERAL
PURPOSE

REGISTERS

X

Y

Z

ALU

+

-

PORTB DRIVERS/BUFFERS

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

XTAL1

XTAL2

CONTROL

LINES

VCC

GND

MUX &

ADC

AGND

AREF

PC0 - PC6 PB0 - PB7

PD0 - PD7

AVR CPU

TWI

RESET

ATmega8A

2. Overview

The ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR RISC architec­ture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves
throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power con­sumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

8159CS–AVR–07/09

3

ATmega8A

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

The ATmega8A provides the following features: 8K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general pur­pose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with
compare modes, internal and external interrupts, a serial programmable USART, a byte oriented
Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages)
with 10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial
port, and five software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the device is
sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchro­nous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,
the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows
very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The
Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a
conventional non-volatile memory programmer, or by an On-chip boot program running on the
AVR core. The boot program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash Section will continue to run while the
Application Flash Section is updated, providing true Read-While-Write operation. By combining
an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega8A is a powerful microcontroller that provides a highly-flexible and cost-effective solu­tion to many embedded control applications.

The ATmega8A AVR is supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators,
and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

8159CS–AVR–07/09

4

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil­lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1
input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in “Alternate Functions of Port B” on page

58 and “System Clock and Clock Options” on page 24.

2.2.4 Port C (PC5:PC0)

Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

2.2.5 PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char­acteristics of PC6 differ from those of the other pins of Port C.

ATmega8A

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 25-3 on page 247. Shorter pulses are not guaran­teed to generate a Reset.

The various special features of Port C are elaborated on page 61.

2.2.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8A as listed on page

63.

2.2.7 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 25-3 on page

247. Shorter pulses are not guaranteed to generate a reset.

2.2.8 AV

CC

AVCC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be
externally connected to V
nected to V

, even if the ADC is not used. If the ADC is used, it should be con-

CC

through a low-pass filter. Note that Port C (5:4) use digital supply voltage, VCC.

CC

2.2.9 AREF

8159CS–AVR–07/09

AREF is the analog reference pin for the A/D Converter.

5

2.2.10 ADC7:6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.

ATmega8A

8159CS–AVR–07/09

6