– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments
– 4/8/16/32K Bytes of In-System Self-Programmable Flash progam memory
(ATmega48PA/88PA/168PA/328P)
– 256/512/512/1K Bytes EEPROM (ATmega48PA/88PA/168PA/328P)
– 512/1K/1K/2K Bytes Internal SRAM (ATmega48PA/88PA/168PA/328P)
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.
ATmega48PA/88PA/168PA/328P
1.1.4Port C (PC5:0)
1.1.5PC6/RESET
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1
input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page
76 and ”System Clock and Clock Options” on page 26.
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PC5..0 output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 28-3 on page 308. Shorter pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page
79.
1.1.6Port D (PD7:0)
8161DS–AVR–10/09
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
3
ATmega48PA/88PA/168PA/328P
The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page
82.
1.1.7AV
CC
AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally
connected to V
, even if the ADC is not used. If the ADC is used, it should be connected to V
CC
through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC.
1.1.8AREF
AREF is the analog reference pin for the A/D Converter.
1.1.9ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.
CC
8161DS–AVR–10/09
4
2.Overview
2.1Block Diagram
ATmega48PA/88PA/168PA/328P
The ATmega48PA/88PA/168PA/328P is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48PA/88PA/168PA/328P achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
Figure 2-1.Block Diagram
Powe r
RESET
Comp.
VCC
debugWIRE
PROGRAM
CPU
Internal
Bandgap
LOGIC
SRAMFlash
AVC C
AREF
GND
2
6
GND
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
EEPROM
8bit T/C 2
DATA B US
Supervision
POR / BOD &
16bit T/C 18bit T/C 0A/D Conv.
Analog
8161DS–AVR–10/09
USART 0
SPITWI
PORT C (7)PORT B (8)PORT D (8)
RESET
XTAL[1..2]
ADC[6..7]PC[0..6]PB[0..7]PD[0..7]
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
5
ATmega48PA/88PA/168PA/328P
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega48PA/88PA/168PA/328P provides the following features: 4/8/16/32K bytes of InSystem Programmable Flash with Read-While-Write capabilities, 256/512/512/1K bytes
EEPROM, 512/1K/1K/2K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external
interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial
port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable
Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the
register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing
the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize
switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is
running while the rest of the device is sleeping. This allows very fast start-up combined with low
power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega48PA/88PA/168PA/328P is a powerful microcontroller that
provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega48PA/88PA/168PA/328P AVR is supported with a full suite of program and system
development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators,
In-Circuit Emulators, and Evaluation kits.
2.2Comparison Between ATmega48PA, ATmega88PA, ATmega168PA and ATmega328P
The ATmega48PA, ATmega88PA, ATmega168PA and ATmega328P differ only in memory
sizes, boot loader support, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the three devices.
ATmega88PA, ATmega168PA and ATmega328P support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can
only execute from there. In ATmega48PA, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash.
8161DS–AVR–10/09
6
3.Resources
4.Data Retention
ATmega48PA/88PA/168PA/328P
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note:1.
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
Note:1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega48PA/88PA/168PA/328P is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. Only valid for ATmega88PA.
––––––––
––––––––
8161DS–AVR–10/09
11
ATmega48PA/88PA/168PA/328P
6.Instruction Set Summary
MnemonicsOperandsDescriptionOperationFlags#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADDRd, RrAdd two RegistersRd ← Rd + RrZ,C,N,V,H1
ADCRd, RrAdd with Carry two RegistersRd ← Rd + Rr + CZ,C,N,V,H1
ADIWRdl,KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2
SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1
SUBIRd, KSubtract Constant from Register Rd ← Rd - KZ,C,N,V,H1
SBCRd, RrSubtract with Carry two RegistersRd ← Rd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1
SBIWRdl,KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S2
ANDRd, RrLogical AND RegistersRd ← Rd • RrZ,N,V1
ANDIRd, KLogical AND Register and ConstantRd ← Rd • KZ,N,V1
ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1
ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1
EORRd, RrExclusive OR RegistersRd ← Rd ⊕ RrZ,N,V1
COMRdOne’s ComplementRd ← 0xFF − RdZ,C,N,V1
NEGRdTwo’s ComplementRd ← 0x00 − RdZ,C,N,V,H1
SBRRd,KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1
CBRRd,KClear Bit(s) in RegisterRd ← Rd • (0xFF - K)Z,N,V1
INCRdIncrementRd ← Rd + 1Z,N,V1
DECRdDecrementRd ← Rd − 1 Z,N,V1
TSTRdTest for Zero or MinusRd ← Rd • Rd Z,N,V1
CLRRdClear RegisterRd ← Rd ⊕ RdZ,N,V1
SERRdSet RegisterRd ← 0xFFNone1
MULRd, RrMultiply UnsignedR1:R0 ← Rd x RrZ,C2
MULSRd, RrMultiply SignedR1:R0 ← Rd x RrZ,C2
MULSURd, RrMultiply Signed with UnsignedR1:R0 ← Rd x RrZ,C2
FMULRd, RrFractional Multiply UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSRd, RrFractional Multiply SignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSURd, RrFractional Multiply Signed with UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
BRANCH INSTRUCTIONS
RJMPkRelative JumpPC ← PC + k + 1None2
IJMPIndirect Jump to (Z)PC ← Z None2
(1)
JMP
RCALLkRelative Subroutine Call PC ← PC + k + 1None3
ICALLIndirect Call to (Z)PC ← ZNone3
(1)
CALL
RETSubroutine ReturnPC ← STACKNone4
RETIInterrupt ReturnPC ← STACKI4
CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC ← PC + 2 or 3None1/2/3
CPRd,RrCompareRd − RrZ, N,V,C,H1
CPCRd,RrCompare with CarryRd − Rr − CZ, N,V,C,H1
CPIRd,KCompare Register with ImmediateRd − KZ, N,V,C,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3 None1/2/3
SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2/3
SBICP, bSkip if Bit in I/O Register Clearedif (P(b)=0) PC ← PC + 2 or 3 None1/2/3
SBISP, bSkip if Bit in I/O Register is Setif (P(b)=1) PC ← PC + 2 or 3None1/2/3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None1/2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC ←PC+k + 1None1/2
BREQ kBranch if Equal if (Z = 1) then PC ← PC + k + 1None1/2
BRNE kBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2
BRCS kBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2
BRCC kBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2
BRSH kBranch if Same or Higher if (C = 0) then PC ← PC + k + 1None1/2
BRLO kBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2
BRMI kBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2
BRPL kBranch if Plus if (N = 0) then PC ← PC + k + 1None1/2
BRGE kBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/2
BRLT kBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None1/2
BRHS kBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2
BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2
BRTS kBranch if T Flag Setif (T = 1) then PC ← PC + k + 1None1/2
BRTC kBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2
BRVS kBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2
BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/2
kDirect JumpPC ← kNone3
kDirect Subroutine Call PC ← kNone4
8161DS–AVR–10/09
12
ATmega48PA/88PA/168PA/328P
MnemonicsOperandsDescriptionOperationFlags#Clocks
BRIE kBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None1/2
BRID kBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2
32M1-A32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
8161DS–AVR–10/09
18
8.Packaging Information
2325 Orchard Parkway
San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
B
32A
10/5/2001
PIN 1 IDENTIFIER
0˚~7˚
PIN 1
L
C
A1
A2A
D1
D
e
E1E
B
Notes:1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm,
2.4 x 2.4 mm Exposed Pad, Thermally Enhanced
Plastic Very Thin Quad Flat No Lead Package (VQFN)
10/24/08
SIDE VIEW
Pin 1 ID
BOTTOM VIEW
TOP VIEW
Note:
The terminal #1 ID is a Laser-marked Feature.
D
E
e
K
A1
C
A
D2
E2
y
L
1
2
3
b
1
2
3
0.45
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
b 0.17 0.22 0.27
C 0.20 REF
D 3.95 4.00 4.05
D2 2.35 2.40 2.45
E 3.95 4.00 4.05
E2 2.35 2.40 2.45
e 0.45
L 0.35 0.40 0.45
y 0.00 – 0.08
K 0.20 – –
R 0.20
0.4 Ref
(4x)
ATmega48PA/88PA/168PA/328P
8161DS–AVR–10/09
20
8.332M1-A
2325 Orchard Parkway
San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,
E
32M1-A
5/25/06
3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
D1
D
E1
E
e
b
A3
A2
A1
A
D2
E2
0.08
C
L
1
2
3
P
P
0
1
2
3
A 0.80 0.90 1.00
A1 – 0.02 0.05
A2 – 0.65 1.00
A3 0.20 REF
b 0.180.230.30
D
D1
D2 2.953.103.25
4.905.005.10
4.704.754.80
4.704.754.80
4.905.005.10
E
E1
E2 2.953.103.25
e 0.50 BSC
L 0.30 0.40 0.50
P – – 0.60
– – 12o
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0
Pin 1 ID
Pin #1 Notch
(0.20 R)
K0.20––
K
K
ATmega48PA/88PA/168PA/328P
8161DS–AVR–10/09
21
8.428P3
2325 Orchard Parkway
San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
B
28P3
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
B2
(4 PLACES)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A––4.5724
A10.508––
D34.544– 34.798 Note 1
E7.620– 8.255
E1 7.112– 7.493Note 1
B0.381–0.533
B11.143–1.397
B20.762–1.143
L3.175–3.429
C0.203–0.356
eB––10.160
e 2.540 TYP
Note:1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
ATmega48PA/88PA/168PA/328P
8161DS–AVR–10/09
22
9.Errata
9.1Errata ATmega48PA
The revision letter in this section refers to the revision of the ATmega48PA device.
9.1.1Rev. D
No known errata.
9.2Errata ATmega88PA
The revision letter in this section refers to the revision of the ATmega88PA device.
9.2.1Rev. F
No known errata.
9.3Errata ATmega168PA
The revision letter in this section refers to the revision of the ATmega168PA device.
9.3.1Rev E
No known errata.
ATmega48PA/88PA/168PA/328P
9.4Errata ATmega328P
The revision letter in this section refers to the revision of the ATmega328P device.
9.4.1Rev D
No known errata.
9.4.2Rev C
Not sampled.
9.4.3Rev B
•
Unstable 32 kHz Oscillator
1. Unstable 32 kHz Oscillator
The 32 kHz oscillator does not work as system clock.
The 32 kHz oscillator used as asynchronous timer is inaccurate.
Problem Fix/ Workaround
None
9.4.4Rev A
•
Unstable 32 kHz Oscillator
1. Unstable 32 kHz Oscillator
The 32 kHz oscillator does not work as system clock.
8161DS–AVR–10/09
The 32 kHz oscillator used as asynchronous timer is inaccurate.
Problem Fix/ Workaround
None
23
10. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
10.1Rev. 8161D – 10/09
1.Inserted Table 8-8 on page 32, Capacitance for Low-frequency Crystal Oscillator.
10.2Rev. 8161C – 05/09
1.Updated ”Features” on page 1 for ATmega48PA/88PA/168PA/328P.
2.Updated ”Overview” on page 5 included the Table 2-1 on page 6.
3.Updated ”AVR Memories” on page 16 included ”Register Description” on page 21 and inserted
Figure 7-1 on page 17.
4.Updated ”Register Description” on page 44.
5.Updated ”System Control and Reset” on page 46.
ATmega48PA/88PA/168PA/328P
6.Updated ”Interrupts” on page 57.
7.Updated ”External Interrupts” on page 70.
8.Updated ”Boot Loader Support – Read-While-Write Self-Programming, ATmega88PA,
9.Inserted
10.Inserted ”ATmega328P DC Characteristics” on page 316.
11.
12.
13.
14.
15.
16.
10.3Rev. 8161B – 01/09
1.Updated ”Features” on page 1 for ATmega48PA and updated the book accordingly.
2.Updated ”Overview” on page 5 included the Table 2-1 on page 6.
3.Updated ”AVR Memories” on page 16 included ”Register Description” on page 21 and inserted
ATmega168PA and ATmega328P” on page 277.
”ATmega168PA DC Characteristics” on page 315.
Inserted ”ATmega168PA Typical Characteristics” on page 375.
Inserted ”ATmega328P Typical Characteristics” on page 399.
Inserted Ordering Information for ”ATmega168PA” on page 432.
Inserted Ordering Information for ”ATmega328P” on page 433.
Inserted ”Errata ATmega328P” on page 438.
Editing updates.
Figure 7-1 on page 17.
8161DS–AVR–10/09
4.Updated ”Register Description” on page 44.
5.Updated ”System Control and Reset” on page 46.
6.Updated ”Interrupts” on page 57.
24
7.Updated ”External Interrupts” on page 70.
8.Inserted Typical characteristics for ”ATmega48PA Typical Characteristics” on page 327.
9.
10.
11.
12.
13.
10.4Rev. 8161A – 11/08
1.Initial revision (Based on the ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08).
2.Changes done compared to ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08:
ATmega48PA/88PA/168PA/328P
Updated figure names in Typical characteristics for ”ATmega88PA Typical Character-
istics” on page 351.
Inserted ”ATmega48PA DC Characteristics” on page 314.
Updated Table 28-1 on page 317 by removing the footnote from Vcc/User calibration
Updated Table 28-7 on page 323 by removing Max value (2.5 LSB) from Absolute
accuracy, V
Inserted Ordering Information for ”ATmega48PA” on page 430.
– Updated ”DC Characteristics” on page 313 with new typical values for I
– Updated ”Speed Grades” on page 316.
– New graphics in ”Typical Characteristics” on page 326.
–New ”Ordering Information” on page 430.
= 4V, VCC = 4V, ADC clock = 200 kHz.
REF
CC
.
8161DS–AVR–10/09
25
HeadquartersInternational
Atmel Corporation
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San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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