Atmel ATmega164P/V, ATmega324P/V, ATmega644P/V Datasheet

Features

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier

• High Endurance Non-volat ile Memory segments

– 16/32/64K Bytes of In-System Self-programmable Flash program memory
– 512B/1K/2K Bytes EEPROM
– 1/2/4K Bytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits thr ough the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC

• Differential mode with selectable gain at 1x, 10x or 200x
– Byte-oriented Two-wire Serial Interface
– Two Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power -save, Power-down, Standby and

Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

• Operating Voltages

– 1.8 - 5.5V for ATmega164P/324P/644PV
– 2.7 - 5.5V for ATmega164P/324P/644P

• Speed Grades

– ATmega164P/324P/644PV: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V
– ATmega164P/324P/644P: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V

• Power Consumption at 1 MHz, 1.8V, 25°C for ATmega164P/324P/644P

– Active: 0.4 mA
– Power-down Mode: 0.1µA
– Power-save Mode: 0.6µA (Including 32 kHz RTC)

®

8-bit Microcontroller

8-bit

Microcontroller
with 16/32/64K
Bytes In-System
Programmable
Flash

ATmega164P/V
ATmega324P/V
ATmega644P/V

Preliminary
Summary

8011GS–AVR–08/07

ATmega164P/324P/644P

1. Pin Configurations

Figure 1-1. Pinout ATmega164P/324P/644P

PDIP

(PCINT8/XCK0/T0) PB0

(PCINT9/CLKO/T1) PB1

(PCINT10/INT2/AIN0) PB2

(PCINT11/OC0A/AIN1) PB3

(PCINT12/OC0B/SS) PB4

(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND
XTAL2
XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

TQFP/QFN/MLF

PB4 (SS/OC0B/PCINT12)

PB3 (AIN1/OC0A/PCINT11)

PB2 (AIN0/INT2/PCINT10)

PB1 (T1/CLKO/PCINT9)

PB0 (XCK0/T0/PCINT8)

GND

VCC

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
PC3 (TMS/PCINT19)
PC2 (TCK/PCINT18)
PC1 (SDA/PCINT17)
PC0 (SCL/PCINT16)
PD7 (OC2A/PCINT31)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND
XTAL2
XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

VCC

GND

(PCINT16/SCL) PC0

(PCINT29/OC1A) PD5

(PCINT31/OC2A) PD7

(PCINT30/OC2B/ICP) PD6

(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT17/SDA) PC1

(PCINT18/TCK) PC2

PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVC C
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)

(PCINT19/TMS) PC3

Note: The large center pad underneath the QFN/MLF package should be soldered to ground on the

board to ensure good mechanical stability.

2

8011GS–AVR–08/07

2. Overview

PC5..0

PA7..0

TOSC1/PC6TOSC2/PC7

The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the sys­tem designer to optimize power consumption versus pr ocessing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

ATmega164P/324P/644P

RESET

XTAL1

VCC

GND

XTAL2

Power

Supervision

POR / BOD &

RESET

Watchdog

Timer

Watchdog

Oscillator

Oscillator

Circuits /

Clock

Generation

EEPROM

JTAG/OCD

PORT A (8)

A/D

Converter

TWI

Internal

Bandgap reference

CPU

SRAMFLASH

PB7..0

PORT B (8)

Analog

Comparator

SPI

8bit T/C 0

16bit T/C 1

8bit T/C 2

USART 0

USART 1

8011GS–AVR–08/07

PORT C (8)

PORT D (8)

PD7..0

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting

3

ATmega164P/324P/644P

architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

The ATmega164P/324P/644P provides the following features: 16/32/64K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1/2/4K
bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time
Counter (RTC), three flexible Timer/Counters with compare modes an d PWM, 2 USARTs, a byte
oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage
with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial
port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip
Debug system and programming and six software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system
to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power­save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all
I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC
conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On­chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control app lications.

The ATmega164P/324P/644P AVR is supported with a full suite of program and system devel­opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.

2.2 Comparison Between ATmega164P, ATmega324P and ATmega644P

Table 2-1. Differences between ATmega164P and AT meg a6 44 P

Device Flash EEPROM RAM

ATmega164P 16 Kbyte 512 Bytes 1 Kbyte
ATmega324P 32 Kbyte 1 Kbyte 2 Kbyte
ATmega644P 64 Kbyte 2 Kbyte 4 Kbyte

2.3 Pin Descriptions

2.3.1 VCC

Digital supply voltage.

4

8011GS–AVR–08/07

2.3.2 GND

Ground.

2.3.3 Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Conver ter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source current if
the pull-up resistors are activated. The Port A pins are tri-st ated when a reset co ndition becomes
active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega164P/324P/644P as
listed on page 80.

2.3.4 Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

ATmega164P/324P/644P

Port B also serves the functions of various special features of the ATmega164P/324P/644P as
listed on page 82.

2.3.5 Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the
ATmega164P/324P/644P as listed on page 85.

2.3.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port D also serves the functions of various special features of the ATmega164P/324P/644P as
listed on page 87.

2.3.7

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characteristics” on page 331. Shorter pulses are not guaranteed to generate a rese t.

2.3.8 XTAL1

8011GS–AVR–08/07

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

5

ATmega164P/324P/644P

2.3.9 XTAL2

2.3.10 AVCC

2.3.11 AREF

3. Resources

4. Data Retention

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the Analog-to-digital Convert er. It should be exte r­nally connected to V
to V

through a low-pass filter.

CC

This is the analog reference pin for the Analog-to-digital Converter.

A comprehensive set of development tools, application notes and datasheetsare available for
download on http://www.atmel.com/avr.

Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.

, even if the ADC is not used. If the ADC is used, it should be connected

CC

6

8011GS–AVR–08/07

ATmega164P/324P/644P

5. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved - - - - - - ­(0xFE) Reserved - - - - - - - ­(0xFD) Reserved - - - - - - - ­(0xFC) Reserved - - - - - - - ­(0xFB) Reserved - - - - - - ­(0xFA) Reserved - - - - - - - ­(0xF9) Reserved - - - - - - ­(0xF8) Reserved - - - - - - - ­(0xF7) Reserved - - - - - - - ­(0xF6) Reserved - - - - - - - ­(0xF5) Reserved - - - - - - ­(0xF4) Reserved - - - - - - - ­(0xF3) Reserved - - - - - - - ­(0xF2) Reserved
(0xF1) Reserved
(0xF0) Reserved - - - - - - - ­(0xEF) Reserved - - - - - - -

(0xEE) Reserved - - - - - - - ­(0xED) Reserved - - - - - - - ­(0xEC) Reserved - - - - - - - ­(0xEB) Reserved - - - - - - ­(0xEA) Reserved - - - - - - - ­(0xE9) Reserved - - - - - - - ­(0xE8) Reserved - - - - - - - ­(0xE7) Reserved - - - - - - ­(0xE6) Reserved - - - - - - - ­(0xE5) Reserved - - - - - - - ­(0xE4) Reserved - - - - - - - ­(0xE3) Reserved - - - - - - ­(0xE2) Reserved - - - - - - - ­(0xE1) Reserved - - - - - - ­(0xE0) Reserved - - - - - - ­(0xDF) Reserved - - - - - - - ­(0xDE) Reserved - - - - - - - ­(0xDD) Reserved - - - - - - - ­(0xDC) Reserved - - - - - - ­(0xDB) Reserved - - - - - - - ­(0xDA) Reserved
(0xD9) Reserved
(0xD8) Reserved - - - - - - - ­(0xD7) Reserved
(0xD6) Reserved
(0xD5) Reserved
(0xD4) Reserved - - - - - - - ­(0xD3) Reserved
(0xD2) Reserved
(0xD1) Reserved - - - - - - - ­(0xD0) Reserved
(0xCF) Reserved
(0xCE) UDR1 USART1 I/O Data Register 189
(0xCD) UBRR1H
(0xCC) UBRR1L USART1 Baud Rate Register Low Byte 193/206
(0xCB) Reserved
(0xCA) UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 191/205
(0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 190/204
(0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 189/204
(0xC7) Reserved
(0xC6) UDR0 USART0 I/O Data Register 189
(0xC5) UBRR0H
(0xC4) UBRR0L USART0 Baud Rate Re gister Low Byte 193/206
(0xC3) Reserved

- - - - - - - -

- - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - USART1 Baud Rate Register High Byte 193/206

- - - - - - - -

- - - - - - - -

- - - - USART0 Baud Rate Register High Byte 193/206

- - - - - - - -

8011GS–AVR–08/07

7

ATmega164P/324P/644P

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 191/205
(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 190/204
(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 189/204
(0xBF) Reserved - - - - - - - ­(0xBE) Reserved - - - - - - - ­(0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0
(0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN
(0xBB) TWDR 2-wire Serial Interface Data Register 234
(0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 235
(0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 234
(0xB8) TWBR 2-wire Serial Interface Bit Rate Register 232
(0xB7) Reserved - - - - - - - ­(0xB6) ASSR - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB 157
(0xB5) Reserved - - - - - - - ­(0xB4) OCR2B Timer/Counter2 Output Compare Register B 157
(0xB3) OCR2A Timer/Counter2 Output Compare Register A 157
(0xB2) TCNT2 Timer/Counter2 (8 Bit) 156
(0xB1) TCCR2B FOC2A FOC2B
(0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0
(0xAF) Reserved - - - - - - - ­(0xAE) Reserved - - - - - - - ­(0xAD) Reserved - - - - - - - ­(0xAC) Reserved - - - - - - - ­(0xAB) Reserved - - - - - - - ­(0xAA) Reserved - - - - - - - ­(0xA9) Reserved - - - - - - - ­(0xA8) Reserved - - - - - - - ­(0xA7) Reserved - - - - - - - ­(0xA6) Reserved - - - - - - - ­(0xA5) Reserved - - - - - - - ­(0xA4) Reserved - - - - - - - ­(0xA3) Reserved - - - - - - - ­(0xA2) Reserved - - - - - - - ­(0xA1) Reserved - - - - - - - ­(0xA0) Reserved - - - - - - - ­(0x9F) Reserved - - - - - - - ­(0x9E) Reserved - - - - - - - ­(0x9D) Reserved - - - - - - - ­(0x9C) Reserved - - - - - - - ­(0x9B) Reserved - - - - - - - ­(0x9A) Reserved - - - - - - - -

(0x99) Reserved - - - - - - - -

(0x98) Reserved - - - - - - - -

(0x97) Reserved - - - - - - - -

(0x96) Reserved

(0x95) Reserved

(0x94) Reserved - - - - - - - -

(0x93) Reserved

(0x92) Reserved

(0x91) Reserved

(0x90) Reserved - - - - - - - ­(0x8F) Reserved
(0x8E) Reserved
(0x8D) Reserved - - - - - - - ­(0x8C) Reserved
(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 136
(0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 136

(0x89) OCR1AH Timer/Count er1 - Output Compare Register A High Byte 136

(0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 136

(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 137

(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 137

(0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 136

(0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 136

(0x83) Reserved - - - - - - - -

(0x82) TCCR1C FOC1A FOC1B - - - - - -135

(0x81) TCCR1B ICNC1 ICES1

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - WGM22 CS22 CS21 CS20 155

- - WGM21 WGM20 152

- WGM13 WGM12 CS12 CS11 CS10 134

-TWIE 232

-235

8

8011GS–AVR–08/07

ATmega164P/324P/644P

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 132
(0x7F) DIDR1 - - - - - -AIN1DAIN0D 239
(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 259
(0x7D) Reserved - - - - - - - ­(0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 255
(0x7B) ADCSRB
(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 257

(0x79) ADCH ADC Data Register High byte 258

(0x78) ADCL ADC Data Register Low byte 258

(0x77) Reserved

(0x76) Reserved - - - - - - - -

(0x75) Reserved - - - - - - - -

(0x74) Reserved - - - - - - - -

(0x73) PCMSK3 PCINT31 PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 70

(0x72) Reserved - - - - - - - -

(0x71) Reserved - - - - - - - -

(0x70) TIMSK2 - - - - - OCIE2B OCIE2A TOIE2 158
(0x6F) TIMSK1
(0x6E) TIMSK0
(0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 70
(0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 70
(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 71
(0x6A) Reserved - - - - - - - -

(0x69) EICRA - - ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 67

(0x68) PCICR - - - - PCIE3 PCIE2 PCIE1 PCIE0 69

(0x67) Reserved - - - - - - - -

(0x66) OSCCAL Oscillator Calibration Register 40

(0x65) Reserved - - - - - - - -

(0x64) PRR PRTWI PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI PRUSART0 PRADC 48

(0x63) Reserved - - - - - - - -

(0x62) Reserved - - - - - - - -

(0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 40

(0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 59

0x3F (0x5F) SREG I T H S V N Z C 10
0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 11
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11
0x3C (0x5C) Reserved - - - - - - - ­0x3B (0x5B) RAMPZ - - - - - - - RAMPZ0 14
0x3A (0x5A) Reserved - - - - - - - ­0x39 (0x59) Reserved - - - - - - - ­0x38 (0x58) Reserved - - - - - - - ­0x37 (0x57) SPMCSR SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN 291
0x36 (0x56) Reserved - - - - - - - ­0x35 (0x55) MCUCR JTD BODS BODSE PUD - - IVSEL IVCE 91/275
0x34 (0x54) MCUSR
0x33 (0x53) SMCR
0x32 (0x52) Reserved - - - - - - - ­0x31 (0x51) OCDR On-Chip Debu g Re gister 265
0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 257
0x2F (0x4F) Reserved
0x2E (0x4E) SPDR SPI 0 Data Register 170
0x2D (0x4D) SPSR SPIF0 WCOL0
0x2C (0x4C) SPCR SPIE0 SPE0 DORD0 MSTR0 CPOL0 CPHA0 SPR01 SPR00 168
0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 28
0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 28
0x29 (0x49) Reserved
0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B 109
0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 108
0x26 (0x46) TCNT0 Timer/Counter0 (8 Bit) 108
0x25 (0x45) TCCR0B FOC0A FOC0B - - WGM02 CS02 CS01 CS00 107
0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0
0x23 (0x43) GTCCR TSM - - - - - PSR2 PSR54310 159
0x22 (0x42) EEARH
0x21 (0x41) EEARL EEPROM Address Register Low Byt e 23
0x20 (0x40) EEDR EEPROM Data Re gi ste r 23
0x1F (0x3F) EECR - - EEPM1 EEPM0 EERIE EEMWE EEWE EERE 23

-ACME- - - ADTS2 ADTS1 ADTS0 238

- - - - - - - -

- -ICIE1- - OCIE1B OCIE1A TOIE1 137

- - - - - OCIE0B OCIE0A TOIE0 109

- - - JTRF WDRF BORF EXTRF PORF 58/275

- - - - SM2 SM1 SM0 SE 47

- - - - - - - -

- - - - -SPI2X0 169

- - - - - - - -

- - WGM01 WGM00 109

- - - - EEPROM Address Register High Byte 23

8011GS–AVR–08/07

9

ATmega164P/324P/644P

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 28
0x1D (0x3D) EIMSK - - - - - INT2 INT1 INT0 68
0x1C (0x3C) EIFR - - - - - INTF2 INTF1 INTF0 68
0x1B (0x3B) PCIFR - - - - PCIF3 PCIF2 PCIF1 PCIF0 69
0x1A (0x3A) Reserved - - - - - - - ­0x19 (0x39) Reserved
0x18 (0x38) Reserved
0x17 (0x37) TIFR2 - - - - -OCF2bOCF2ATOV2 159
0x16 (0x36) TIFR1 - -ICF1- - OCF1B OCF1A TOV1 138
0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 109
0x14 (0x34) Reserved - - - - - - - ­0x13 (0x33) Reserved - - - - - - - ­0x12 (0x32) Reserved - - - - - - - ­0x11 (0x31) Reserved - - - - - - - ­0x10 (0x30) Reserved - - - - - - - ­0x0F (0x2F) Reserved - - - - - - - ­0x0E (0x2E) Reserved - - - - - - - ­0x0D (0x2D) Reserved
0x0C (0x2C) Reserved
0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 92
0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 92
0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 92
0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 92
0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 92
0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 92
0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 91
0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 91
0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 91
0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 91
0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 91
0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 91

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg­isters, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F on ly.

4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis­ters as data space using LD and ST instructions, $20 must be added to these addresses. The A Tmega164P/324P/644P is a
complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the
IN and OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions

can be used.

10

8011GS–AVR–08/07

ATmega164P/324P/644P

6. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
JMP k Direct Jump PC ← kNone3
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 4
ICALL Indirect Call to (Z) PC ← ZNone4
CALL k Direct Su broutine Call PC ← kNone5
RET Subroutine Return PC ← STACK None 5
RETI Interrupt Return PC ← STACK I 5
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Registe r is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/ 2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleare d if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

8011GS–AVR–08/07

11

ATmega164P/324P/644P

Mnemonics Operands Description Operation Flags #Clocks

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← TNone1
SEC Set Carry C ← 1C1
CLC Clear Carry C ← 0 C 1
SEN Set Negative Flag N ← 1N1
CLN Clear Negative Flag N ← 0 N 1
SEZ Set Zero Flag Z ← 1Z1
CLZ Clear Zero Flag Z ← 0 Z 1
SEI Global Interrupt Enable I ← 1I1
CLI Global Interrupt Disable I ← 0 I 1
SES Set Signed Test Flag S ← 1S1
CLS Clear Signed Test Flag S ← 0 S 1
SEV Set Twos Complement Overflow. V ← 1V1
CLV Clear Twos Complement Overflow V ← 0 V 1
SET Set T in SREG T ← 1T1
CLT Clear T in SREG T ← 0 T 1
SEH Set Half Carry Flag in SREG H ← 1H1
CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word
LDI Rd, K Load Immediate Rd ← KNone1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
ELPM Extended Load Program Memory R0 ← (RAMPZ:Z) None 3

Rd+1:Rd ← Rr+1:Rr

None 1

12

8011GS–AVR–08/07

ATmega164P/324P/644P

Mnemonics Operands Description Operation Flags #Clocks

ELPM Rd, Z Extended Load Program Memory Rd ← (Z) None 3
ELPM Rd, Z+ Extended Load Program Memory Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1 None 3
SPM Store Program Memory (Z) ← R1:R0 None ­IN Rd, P In Port Rd ← PNone1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A

8011GS–AVR–08/07

13

ATmega164P/324P/644P

7. Ordering Information

7.1 ATmega164P

Speed (MHz)

(3)

10 1.8 - 5.5V

20 2.7 - 5.5V

Power Supply Ordering Code Package

ATmega164PV-10AU
ATmega164PV-10PU
ATmega164PV-10MU

ATmega164P-20AU
ATmega164P-20PU
ATmega164P-20MU

(2)
(2)

(2)

(2)
(2)

(2)

44A
40P6
44M1

44A
40P6
44M1

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 329.

CC

(1)

Operational Range

Industrial

o

C to 85oC)

(-40

Industrial

o

C to 85oC)

(-40

44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

14

Package Type

8011GS–AVR–08/07

ATmega164P/324P/644P

7.2 ATmega324P

Speed (MHz)

(3)

10 1.8 - 5.5V

20 2.7 - 5.5V

Power Supply Ordering Code Package

ATmega324PV-10AU
ATmega324PV-10PU
ATmega324PV-10MU

ATmega324P-20AU
ATmega324P-20PU
ATmega324P-20MU

(2)
(2)

(2)

(2)
(2)

(2)

44A
40P6
44M1

44A
40P6
44M1

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 329.

CC

(1)

Operational Range

Industrial

o

C to 85oC)

(-40

Industrial

o

C to 85oC)

(-40

Package Type

44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

8011GS–AVR–08/07

15

ATmega164P/324P/644P

7.3 ATmega644P

Speed (MHz)

(3)

10 1.8 - 5.5V

20 2.7 - 5.5V

Power Supply Ordering Code Package

ATmega644PV-10AU
ATmega644PV-10PU
ATmega644PV-10MU

ATmega644P-20AU
ATmega644P-20PU
ATmega644P-20MU

(2)
(2)

(2)

(2)
(2)

(2)

44A
40P6
44M1

44A
40P6
44M1

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 329.

CC

(1)

Operational Range

Industrial

o

C to 85oC)

(-40

Industrial

o

C to 85oC)

(-40

44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

16

Package Type

8011GS–AVR–08/07

8. Packaging Information

8.1 44A

PIN 1

PIN 1 IDENTIFIER

ATmega164P/324P/644P

B

e

E1 E

D1

D

C

0˚~7˚

A1

L

Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A2 A

SYMBOL

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 11.75 12.00 12.25

D1 9.90 10.00 10.10 Note 2

E 11.75 12.00 12.25

E1 9.90 10.00 10.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

NOM

MAX

NOTE

2325 Orchard Parkway

R

San Jose, CA 95131

8011GS–AVR–08/07

TITLE

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

10/5/2001

DRAWING NO.

44A

REV.

B

17

ATmega164P/324P/644P

8.2 40P6

PIN

1

E1

A1

B

REF

E

B1

C

L

SEATING PLANE

A

D

e

0º ~ 15º

eB

Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC.

2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

2325 Orchard Parkway

R

San Jose, CA 95131

TITLE

40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual

Inline Package (PDIP)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – – 4.826

A1 0.381 – –

D 52.070 – 52.578 Note 2

E 15.240 – 15.875

E1 13.462 – 13.970 Note 2

B 0.356 – 0.559

B1 1.041 – 1.651

L 3.048 – 3.556

C 0.203 – 0.381

eB 15.494 – 17.526

e 2.540 TYP

MIN

NOM

MAX

DRAWING NO.

40P6

NOTE

09/28/01

REV.

B

18

8011GS–AVR–08/07

8.3 44M1

ATmega164P/324P/644P

D

Marked Pin# 1 ID

E

SEATING PLANE

TOP VIEW

K

L

D2

Pin #1 Corner

1
2
3

Option A

E2

Option B

K

b

e

Option C

BOTTOM VIEW

Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.

Pin #1
Triangle

Pin #1
Chamfer
(C 0.30)

Pin #1
Notch
(0.20 R)

A1

A3

A

SIDE VIEW

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A 0.80 0.90 1.00

A1 – 0.02 0.05

A3 0.25 REF

b 0.18 0.23 0.30

D

D2 5.00 5.20 5.40

E

E2 5.00 5.20 5.40

e 0.50 BSC

L 0.59 0.64 0.69

K 0.20 0.26 0.41

MIN

6.90 7.00 7.10

6.90 7.00 7.10

NOM

MAX

NOTE

2325 Orchard Parkway

R

San Jose, CA 95131

8011GS–AVR–08/07

TITLE

44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.20 mm Exposed Pad, Micro Lead Frame Package (MLF)

DRAWING NO.

44M1

5/27/06

REV.

G

19

ATmega164P/324P/644P

9. Errata

9.1 ATmega164P Rev. A

No known Errata.

9.2 ATmega324P Rev. A

No known Errata.

9.3 ATmega644P Rev. A

No known Errata.

20

8011GS–AVR–08/07

10. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.

10.1 Rev. 8011G- 08/07

1. Updated ”Features” on page 1

2. Added ”Data Retention” on page 8.

3. Updated ”SPH and SPL – Stack Pointer High and Stack pointer Low” on page 14.

4. LCD reference removed from table note in ”Sleep Modes” on page 42.

5. Updated code example in ”Bit 0 – IVCE: Interrupt Vector Change Enable” on page 65.

6. Removed reference to External Memory Interface in ”Alternate Functions of Port A” on

page 80.

7. Updated ”Data Reception – The USART Receiver” on page 180.

8. Updated ”ADCSRB – ADC Control and Status Register B” on page 238.

9. Updated overview in ”ADC - Analog-to-digital Converter” on page 240.

10. Added ”ATmega644P Typical Characteristic” on page 388.

11. Updated Figure 28-31 on page 354, Figure 28-32 on page 355,Figure 28-33 on page

355

12. Updated notes in Table 8-3 on page 32.Table 8 -8 on page 35, Table 8-9 on page 36,
and Table 8-11 on page 37.

13. Updated Table 13-7 on page 84 , Table 13-8 on page 84, Table 13-10 on page 86,

Table 13-11 on page 87, Table 13-14 on page 90, Table 27-1 on page 327,Table 27-2
on page 327,Table 27-5 on page 330, Table 27-9 on page 332, and Table 27-12 on
page 336

14. Updated ”ATmega324P DC Characteristics” on page 3 27 an d ”A Tmega644P DC Char-

acteristics” on page 328.

15. Updated Table 27-7 on page 331 and Table 8-13 on page 37.

ATmega164P/324P/644P

10.2 Rev. 8011F- 04/07

1. Updated ”Watchdog Timer Configuration” on page 59.

10.3 Rev. 8011E - 04/07

1. Updated ”GTCCR – General Timer/Counter Control Register” on page 159.

2. Updated ”EECR – The EEPROM Control Register” on page 23.

8011GS–AVR–08/07

21

ATmega164P/324P/644P

10.4 Rev. 8011D - 02/07

1. Updated “Pinout ATmega164P/324P/644P” on page 2.

2. Updated ”Power-down Mode” on page 44.

3. Updated note in Table 11-1 on page 68.

4. Updated Table 23-1 on page 272.

5. Updated ”Boot Size Configuration

6. Updated V

7. Updated note 3 and 4 in ”DC Characteristics” on page 325.

8. Added note to ”ATmega164P DC Characteristics” on page 32 7.

9. Added note to ”ATmega324P DC Characteristics” on page 32 7.

10. Updated Figure 27-13 on page 345 and Figure 27-60 on page 370.

10.5 Rev. 8011C - 10/06

1. Updated ”DC Characteristics” on page 325.

10.6 Rev. 8011B - 09/06

1. Updated ”DC Characteristics” on page 325.

(1)

” on page 289.

limits in ”DC Characteristics” on page 325.

OL

10.7 Rev. 8011A - 08/06

1. Initial revision.

22

8011GS–AVR–08/07

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