– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20MIPS Throughput at 20MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 16/32/64/128KBytes of In-System Self-programmable Flash program memory
– 512/1K/2K/4KBytes EEPROM
– 1/2/4/16KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/ 100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
• QTouch
• JTAG (IEEE std. 1149.1 Compliant) Interface
• Peripheral Features
• Special Microcontroller Features
• I/O and Packages
• Operating Voltages
• Speed Grades
• Power Consumption at 1MHz, 1.8V, 25°C
®
library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
Differential mode with selectable gain at 1x, 10x or 200x
– Byte-oriented Two-wire Serial Interface
– Two Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and
Note:The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on
the board to ensure good mechanical stability.
2
ATmega164A/PA/324A/PA/644A/PA/1284/P
Top viewBottom view
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
A18
B15
A17
B14
A16
B13
A15
B12
A14
B11
A13
A12
B10
A11
B9
A10
B8A9 B7A8 B6
A7
A24
B20
A23
B19
A22
B18
A21
B17
A20
B16
A19
A18
B15
A17
B14
A16
B13
A15
B12
A14
B11
A13
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
A19
B16
A20
B17
A21
B18
A22
B19
A23
B20
A24
1.2Pinout - DRQFN for ATmega164A/164PA/324A/324PA
Figure 1-2.DRQFN - Pinout
Table 1-1.DRQFN - Pinout
A1PB5A7PD3A13PC4A19PA 3
B1PB6B6PD4B11PC5B16PA 2
A2PB7A8PD5A14PC6A20PA 1
B2RESET
A3VCCA9PD7A15AVC CA21VCC
B3GNDB8VCCB13GNDB18GND
A4XTAL2A10GNDA16AREFA22PB0
B4XTAL1B9PC0B14PA 7B19PB1
A5PD0A11PC1A17PA 6A23PB2
B5PD1B10PC2B15PA 5B20PB3
8272CS–AVR–06/11
A6PD2A12PC3A18PA 4A24PB4
B7PD6B12PC7B17PA 0
3
ATmega164A/PA/324A/PA/644A/PA/1284/P
A
B
C
D
E
F
G
1234567
A
B
C
D
E
F
G
7654321
Top viewBottom view
1.3Pinout - VFBGA for ATmega164A/164PA/324A/324PA
Figure 1-3.VFBGA - Pinout
Table 1-2.BGA - Pinout
1234567
AGNDPB4PB2GNDVCCPA2GND
BPB6PB5PB3PB0PA0PA3PA5
CVCCRESETPB7PB1PA1PA6AREF
DGNDXTAL2PD0GNDPA4PA7GND
EXTAL1PD1PD5PD7PC5PC7AVCC
FPD2PD3PD6PC0PC2PC4PC6
GGNDPD4VCCGNDPC1PC3GND
8272CS–AVR–06/11
4
2.Overview
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit
microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
2.1Block Diagram
Figure 2-1.Block Diagram
VCC
Powe r
RESET
Supervision
POR / BOD &
RESET
ATmega164A/PA/324A/PA/644A/PA/1284/P
PA7..0
PORT A (8)
PB7..0
PORT B (8)
GND
XTAL1
XTAL2
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
A/D
Converter
EEPROM
JTAG/OCD
TWI
PORT C (8)
Internal
Bandgap reference
CPU
SRAMFLASH
Analog
Comparator
SPI
8bit T/C 0
16bit T/C 1
8bit T/C 2
16bit T/C 3
PORT D (8)
USART 0
16bit T/C 1
USART 1
8272CS–AVR–06/11
TOSC1/PC6TOSC2/PC7
PC5..0
PD7..0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
5
ATmega164A/PA/324A/PA/644A/PA/1284/P
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following features:
16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities,
512/1K/2K/4Kbytes EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general
purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit
ADC with optional differential input stage with programmable gain, programmable Watchdog
Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface,
also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode
saves the register contents but freezes the Oscillator, disabling all other chip functions until the
next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to
run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption. In Extended Standby mode, both the main Oscillator
and the Asynchronous Timer continue to run.
Atmel offers the QTouch
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key
Suppression
®
(AKS™) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.
®
library for embedding capacitive touch buttons, sliders and wheels
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control
applications.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of
program and system development tools including: C compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
8272CS–AVR–06/11
6
ATmega164A/PA/324A/PA/644A/PA/1284/P
2.2Comparison Between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA,
ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P
Table 2-1.Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A,
ATmega644PA, ATmega1284 and ATmega1284P
DeviceFlashEEPROMRAMUnits
ATmega164A16 K5121 K
ATmega164PA16 K5121 K
ATmega324A32 K1 K2 K
ATmega324PA32 K1 K2 K
ATmega644A64 K2 K4 K
ATmega644PA64 K2 K4 K
ATmega1284128 K4 K16 K
ATmega1284P128 K4 K16 K
2.3Pin Descriptions
2.3.1VCC
bytes
Digital supply voltage.
2.3.2GND
Ground.
2.3.3Port A (PA7:PA0)
Port A serves as analog inputs to the Analog-to-digital Converter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source current if
the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port A also serves the functions of various special features of the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 80.
2.3.4Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 82.
2.3.5Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
8272CS–AVR–06/11
7
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 85.
2.3.6Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 88.
2.3.7RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset
Characteristics” on page 337. Shorter pulses are not guaranteed to generate a reset.
ATmega164A/PA/324A/PA/644A/PA/1284/P
2.3.8XTAL1
2.3.9XTAL2
2.3.10AVCC
2.3.11AREF
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected to V
to V
through a low-pass filter.
CC
, even if the ADC is not used. If the ADC is used, it should be connected
CC
This is the analog reference pin for the Analog-to-digital Converter.
8272CS–AVR–06/11
8
3.Resources
A comprehensive set of development tools, application notes and datasheetsare available for
download on http://www.atmel.com/avr.
4.About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
The code examples assume that the part specific header file is included before compilation. For
I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and
"STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
Note:1.
5.Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
ATmega164A/PA/324A/PA/644A/PA/1284/P
6.Capacitive touch sensing
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR
QTouch and QMatrix
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library
for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information
and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the
Atmel QTouch Library User Guide - also available for download from the Atmel website.
®
®
acquisition methods.
microcontrollers. The QTouch Library includes support for the
Notes:1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-
isters, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-
ters as data space using LD and ST instructions, $20 must be added to these addresses.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units
than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O
space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. USART in SPI Master Mode.
6. Only available in the ATmega164PA/324PA/644PA/1284P.
-----OCF2B OCF2ATOV2162
--ICF1 --OCF1B OCF1ATOV1139
8272CS–AVR–06/11
13
ATmega164A/PA/324A/PA/644A/PA/1284/P
8.Instruction Set Summary
MnemonicsOperandsDescriptionOperationFlags#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADDRd, RrAdd two RegistersRd ← Rd + RrZ,C,N,V,H1
ADCRd, RrAdd with Carry two RegistersRd ← Rd + Rr + CZ,C,N,V,H1
ADIWRdl,KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2
SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1
SUBIRd, KSubtract Constant from Register Rd ← Rd - KZ,C,N,V,H1
SBCRd, RrSubtract with Carry two RegistersRd ← Rd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1
SBIWRdl,KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S2
ANDRd, RrLogical AND RegistersRd ← Rd • RrZ,N,V1
ANDIRd, KLogical AND Register and ConstantRd ← Rd • KZ,N,V1
ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1
ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1
EORRd, RrExclusive OR RegistersRd ← Rd ⊕ RrZ,N,V1
COMRdOne’s ComplementRd ← 0xFF − RdZ,C,N,V1
NEGRdTwo’s ComplementRd ← 0x00 − RdZ,C,N,V,H1
SBRRd,KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1
CBRRd,KClear Bit(s) in RegisterRd ← Rd • (0xFF - K)Z,N,V1
INCRdIncrementRd ← Rd + 1Z,N,V1
DECRdDecrementRd ← Rd − 1 Z,N,V1
TSTRdTest for Zero or MinusRd ← Rd • Rd Z,N,V1
CLRRdClear RegisterRd ← Rd ⊕ RdZ,N,V1
SERRdSet RegisterRd ← 0xFFNone1
MULRd, RrMultiply UnsignedR1:R0 ← Rd x RrZ,C2
MULSRd, RrMultiply SignedR1:R0 ← Rd x RrZ,C2
MULSURd, RrMultiply Signed with UnsignedR1:R0 ← Rd x RrZ,C2
FMULRd, RrFractional Multiply UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSRd, RrFractional Multiply SignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSURd, RrFractional Multiply Signed with UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
BRANCH INSTRUCTIONS
RJMPkRelative JumpPC ← PC + k + 1None2
IJMPIndirect Jump to (Z)PC ← Z None2
JMPkDirect JumpPC ← kNone3
RCALLkRelative Subroutine Call PC ← PC + k + 1None4
ICALLIndirect Call to (Z)PC ← ZNone4
CALLkDirect Subroutine Call PC ← kNone5
RETSubroutine ReturnPC ← STACKNone5
RETIInterrupt ReturnPC ← STACKI5
CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC ← PC + 2 or 3None1/2/3
CPRd,RrCompareRd − RrZ, N,V,C,H1
CPCRd,RrCompare with CarryRd − Rr − CZ, N,V,C,H1
CPIRd,KCompare Register with ImmediateRd − KZ, N,V,C,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3 None1/2/3
SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2/3
SBICP, bSkip if Bit in I/O Register Clearedif (P(b)=0) PC ← PC + 2 or 3 None1/2/3
SBISP, bSkip if Bit in I/O Register is Setif (P(b)=1) PC ← PC + 2 or 3None1/2/3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None1/2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC←PC+k + 1None1/2
BREQ kBranch if Equal if (Z = 1) then PC ← PC + k + 1None1/2
BRNE kBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2
BRCS kBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2
BRCC kBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2
BRSH kBranch if Same or Higher if (C = 0) then PC ← PC + k + 1None1/2
BRLO kBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2
BRMI kBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2
BRPL kBranch if Plus if (N = 0) then PC ← PC + k + 1None1/2
BRGE kBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/2
BRLT kBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None1/2
BRHS kBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2
BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2
BRTS kBranch if T Flag Setif (T = 1) then PC ←
BRTC kBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2
BRVS kBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2
PC + k + 1None1/2
8272CS–AVR–06/11
14
ATmega164A/PA/324A/PA/644A/PA/1284/P
MnemonicsOperandsDescriptionOperationFlags#Clocks
BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/2
BRIE kBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None1/2
BRID kBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2
44M144-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
8272CS–AVR–06/11
24
10. Packaging Information
2325 Orchard Parkway
San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
C
44A
2010-10-20
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1
A2A
D1
D
e
E1E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
10.144A
ATmega164A/PA/324A/PA/644A/PA/1284/P
8272CS–AVR–06/11
25
10.240P6
2325 Orchard Parkway
San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
40P6
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A––4.826
A10.381––
D52.070–52.578 Note 2
E15.240–15.875
E113.462–13.970 Note 2
B0.356–0.559
B11.041–1.651
L3.048–3.556
C0.203– 0.381
eB15.494–17.526
e2.540 TYP
Notes:1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch
Ball Grid Array Package (VFBGA)
3/14/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A – – 1.00
A1 0.20 – –
A2 0.65 – –
D 4.90 5.00 5.10
D1 3.90 BSC
E 4.90 5.00 5.10
E1 3.90 BSC
b 0.30 0.35 0.40
e 0.65 BSC
TOP VIEW
SIDE VIEW
A1 BALL ID
G
F
E
D
C
B
A
12 3 4 5 6
7
A
A1
A2
D
E
0.10
E1
D1
49 - Ø0.35 ± 0.05
e
A1 BALL CORNER
BOTTOM VIEW
be
ATmega164A/PA/324A/PA/644A/PA/1284/P
8272CS–AVR–06/11
29
11. Errata
11.1Errata for ATmega164A
11.1.1Rev. E
No known Errata.
11.2Errata for ATmega164PA
11.2.1Rev. E
No known Errata.
11.3Errata for ATmega324A
11.3.1Rev. F
No known Errata.
11.4Errata for ATmega324PA
11.4.1Rev. F
ATmega164A/PA/324A/PA/644A/PA/1284/P
No known Errata.
11.5Errata for ATmega644A
11.5.1Rev. F
No known Errata.
11.6Errata for ATmega644PA
11.6.1Rev. F
No known Errata.
11.7Errata for ATmega1284
11.7.1Rev. B
No known Errata.
11.8Errata for ATmega1284P
11.8.1Rev. B
No known Errata.
8272CS–AVR–06/11
30
ATmega164A/PA/324A/PA/644A/PA/1284/P
12. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
12.1Rev. 8272C - 06/11
1.Updated ”ATmega1284P DC Characteristics” on page 334.
12.2Rev. 8272B - 05/11
1.Added Atmel QTouch Library Support and QTouch Sensing Capability Features.
2.Replaced Figure 1-1 on page 2 by an updated “Pinout” that includes Timer/Counter3.
3.Replaced Figure 7-1 on page 10 by an updated “Block Diagram of the AVR Architecture” that
includes Timer/Counter3.
4.Added ”RAMPZ – Extended Z-pointer Register for ELPM/SPM
5.Added ”PRR1 – Power Reduction Register 1” on page 49.
6.Renamed PRR to ”PRR0 – Power Reduction Register 0” on page 48.
7.Updated ”PCIFR – Pin Change Interrupt Flag Register” on page 69. PCICR replaces EIMSR in
the PCIF3, PCIF2, PCIF1 and PCIF0 bit description.
8.Updated ”PCMSK3 – Pin Change Mask Register 3” on page 70. PCIE3 replaces PCIE2 in the bit
description.
9.Updated ”Alternate Functions of Port B” on page 82 to include Timer/Counter3
10.Updated ”Alternate Functions of Port D” on page 88 to include Timer/Counter3
(1)
” on page 15.
11.Added ”TCNT3H and TCNT3L –Timer/Counter3” on page 136
12.Added ”OCR3AH and OCR3AL – Output Compare Register3 A” on page 137
13.Added ”OCR3BH and OCR3BL – Output Compare Register3 B” on page 137
14.Added ”TIMSK3 – Timer/Counter3 Interrupt Mask Register” on page 139
15.Updated All “SPI – Serial Peripheral Interface” “Register Description” to reflect ATmega1284 and
ATmega1284P.
16.Updated ”Addressing the Flash During Self-Programming” on page 284 to include RAMPZ
register.
17.Updated Table 27-16 on page 314. t
18.BODS and BODSE bits denoted as R/W
19.Description of external pin modes below table 16-9 removed.
20.Updated ”Register Summary” on page 10 to include Timer/Counter3.
21.Updated the datasheet with Atmel new style guide.
WD_EEPROM
is 3.6ms instead of 9ms.
8272CS–AVR–06/11
31
12.3Rev. 8272A - 01/10
1.Initial revision (Based on ATmega164PA/324PA/644PA/1284P datasheet 8252G-AVR-11/09 and
, Atmel logo and combinations thereof, AVR®, QTouch®, QMatrix®, AVR Studio® and others are registered trademarks or trade-
marks of Atmel Corporation or its subsidiaries. Windows
®
and others are registered trademarks of Microsoft Corporation in U.S. and
other countries. Other terms and product names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to
any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL
TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY
EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL
HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or com-
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Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
8272CS–AVR–06/11
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