ATMEL AT94S User Manual
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Features
• Multichip Module Containing Field Pr o gram mab le System Lev el Integ rated Circuit
(FPSLIC
• 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
Programming (ISP)
• Field Programmable System Level Integrated Circuit (FPSLIC)
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM
• Patented AVR Enhanced RISC Architecture
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
• JTAG (IEEE Std. 1149.1 Compliant) Interface
• AVR Fixed Peripherals
• Support for FPGA Custom Peripherals
• Up to 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks
• Multiple Oscillator Circuits
• V
• 5V Tolerant I/O
• 3.3V 33 MHz PCI Compliant FPGA I/O
• High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification
™
) and Secure Configuration EEPROM Memory
®
– A T40K SRAM -based FPGA w ith Embedde d High-perf ormance RI SC AVR
Extensive Data and Instruction SRAM
– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
– High-performance DSP Optimized FPGA Core Cell
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and
Handheld Applications
– 120+ Powerful Instructions – Most Single Clock Cycle Execution
– High-performance Hardware Multiplier for DSP-based Systems
– Approaching 1 MIPS per MHz Performance
– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
– Low-power Idle, Power-save, and Power-down Modes
– 100 µA Standby and Typical 2-3 mA per MHz Active
– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
– Extensive On-chip Debugging Support
– Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
– Industry-standard 2-wire Serial Interface
– Two Programmable Serial UARTs
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly
Accessible to FPGA
– FPGA Macro Library of Custom Peripherals
– Two FPGA Clocks Driven from AVR Logic
– FPGA Global Clock Access Available from FPGA Core
– Programmable Watchdog Timer with On-chip Oscillator
– Oscillator to AVR Internal Clock Circuit
– Software-selectable Clock Frequency
– Oscillator to Timer/Counter for Real-time Clock
: 3.0V - 3.6V
CC
– 20 mA Sink/Source High-performance I/O Structures
– All FPGA I/O Individually Programmable
®
Designs
Core and
™
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
Program
Storage
EEPROM
AT94S
Secure Series
Programmable
SLI
Rev. 2314D– FPSLI–2/04
1
Description The AT94S Series (Secure FPSLIC family) shown in Table 1 is a combination of the
popular Atmel AT40K Series SRAM FPGAs, the AT17 Series Configuration Memories
and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripherals. Extensive data an d instructio n SRAM as well as devi ce control and manageme nt
logic are included in this multi-chip module (MCM).
The embedded AT40K FPGA cor e is a f ully 3.3V P CI-compl iant, SRAM -based FP GA
with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port
SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss
of data) and 5,000 to 40,000 usable gates.
Table 1. The AT94S Series Fa mi ly
Device AT94S05AL AT94S10AL AT94S40AL
Configuration Memory Size 1 Mbit 1 Mbit 1 Mbit
FPGA Gates 5K 10K 40K
FPGA Core Cells 256 576 2304
FPGA SRAM Bits 2048 4096 18432
FPGA Registers (Total) 436 846 2862
Maximum FPGA User I/O 95 143 287
AVR Prog r am ma ble I/O Lines 8 16 16
Program SRAM Bytes 4K - 16K 20K - 32K 20K - 32K
Data SRAM Bytes 4K - 16K 4K - 16K 4K - 16K
Hardware Multiplier (8-bit) Yes Yes Yes
2-wire Serial Interface Yes Yes Yes
UARTs 222
Watchdog Timer Yes Yes Yes
Timer/Counters 333
Real-time Clock Yes Yes Yes
JTAG ICE Yes Yes Yes
Typical AVR
Throughput
Operating Voltage 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V
@ 25 MHz 19 MIPS 19 MIPS 19 MIPS
@ 40 MHz 30 MIPS 30 MIPS 30 MIPS
2
AT94S Secure Family
2314D–FPSLI–2/04
Figure 1. AT94S Architecture
AT94S Secure Family
PROGRAMMABLE I/O
Configuration Logic
Configuration
EEPROM
I/O
For ISP
and Chip
Erase
Up to 16K x 16
Program
SRAM Memory
Up to 16
Decoded
Address Lines
5 - 40K Gates FPGA
with
Multiply
Up to
16K x 8
Data
SRAM
2-wire Serial
Unit
Two Serial
UARTs
Two 8-bit
Timer/Counters
Up to 16 Interrupt Lines
4 Interrupt Lines
I/O
I/O
16 Prog. I/O
Lines
I/O
The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by executing powerful instruct ions in a single-clock-c ycle, and allows system des igners to
optimize power consumption versus processing spe ed. The AVR core is based on an
enhanced RISC architec ture that combines a rich instr uction set with 32 genera l-purpose working register s. All 32 registers are dire ctly connec ted to the Arithme tic Logic
Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one cloc k cycle. The resulti ng architectur e is more code-eff icient while
achieving throughpu ts u p to te n tim es fas ter tha n conventional CISC micro con tr ol lers at
the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA
configuration SRAM and AVR instruction code SRAM are automatically loaded at system power-up using Atmel’s in-system programmable AT17 Series EEPROM
configuration memories, which are part of the AT94S Multi-chip Module (MCM).
™
State-of-the-art FPSLIC design tools, System Design er
, were developed in conjunction with the FPSLIC ar chitecture to help redu ce overall time-to-ma rket by int egrating
microcontroller development and debugging, FPGA development, place and route, and
complete system co-verification in one easy-to-use software tool.
2314D–FPSLI–2/04
3
Internal Architecture For details of the A T94S Secure FPS LIC architectur e, please refer to th e AT94K
FPSLIC datash eet and th e AT17 Se ries Co nfigura tion Me mory dat ashee t, avai lable on
the Atmel web site a t http://www. atmel.com. This docum ent only d escribes the differences between the AT94S Secure FPSLIC and the AT94K FPSLIC.
FPSLIC and
Configurator
Interface
Programming and
Configuration Timing
Characteristics
• Fully In-System Programmable and Re-programmable
• When Security Bit Set:
– Data Verification Disabled
– Data Transfer to FPSLIC not Externally Visible
– Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip
Erase
• When Security Bit Cleared:
– Entire Chip Erase Performed
– In-System Programming En abled
– Data Verification Enabled
External Data pins allo w for In-Sys tem Pro grammin g of the dev ice and se tting of th e
EEPROM-based security bit. When the security bit is set (active) this programming connection will only respond to a device erase command. Data cannot be read out of the
external programming/data pins when the security bit is set. The part can be re-programmed, but only after first being erased.
Atmel’s Configurator Programming Software (CPS), available from the Atmel web site
(http://www.atmel.com/dyn/products/tools_card.asp?tool_id= 3191), creates the programming algorithm for the embedded configu rator; however, if you are planning to
write your own software or use other means to program the embedded configurator, the
section below includes the algorithm and other details.
The FPSLIC Configurator The FPSLIC Configurator is a serial EEPROM memory which is used to load program-
mable devices. Thi s document describes the features needed to program th e
Configurator from within its programming mode (i.e., when SER_EN
Reference schematics are supplied for ISP applications.
is driven Low).
Serial Bus Overview The serial bus is a two-wire bus; one wire (cSCK) functions as a clock and is provided
by the programmer, the second wire (cSDA) is a bi-directional signal and is used to provide data and control information.
Information is transmitted on the serial bus in messages. Each MESSAGE is preceded
by a Start Condition and ends with a Stop Condition. The message consists of an integer number of b ytes, each by te consisting of 8 bits of data , followed by a ninth
Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted
byte. This is possible because devices may only drive the cSDA line Low. The system
must provide a small pull-up current (1 k
The MESSAGE FOR MAT for read and wr ite in stru ction s consi sts of the bytes sho wn in
“Bit Format” on page 5.
While writing, the progr ammer is res pons ible fo r i ssuin g the in struc tion and data . Wh ile
reading, the programmer issues the instruction and acknowledges the data from the
Configurator as necessary.
Ω equivalent) for the cSDA line.
4
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a
byte-by-byte basis.
The factory blanks devices to all zeros before shipping. The array cannot otherwise be
“initialized” except by expl icitly writing a known v alue to each loc ation using the seria l
protocol described herein.
Bit Format Data on the cSDA pin may change only during the cSCK Low time; whereas Start and
Stop Conditions are identified as transitions during the cSCK High time.
Write Instruction Message Format
Start and Stop
Conditions
START
CONDITION
DEVICE
ADDRESS
MS EEPROM
ADDRESS BYTE
(NEXT) EEPROM
ADDRESS BYTE
ACK BIT
(CONFIGURATOR)
LS EEPROM
ADDRESS BYTE
DATA
BYTE 1
DATA
BYTE n
STOP
CONDITION
Current Address Read (Extended to Sequential Read) Instruction Message Format
START
CONDITION
DEVICE
ADDRESS
ACK BIT
(CONFIGURATOR)
DATA
BYTE 1
(PROGRAMMER)
DATA
BYTE n
ACK BIT
STOP
CONDITION
The Start Condition is indicated by a high-to-low transition of the cSDA line when the
cSCK line is High. Similar ly, the Stop Con dition is generated by a low-to-hig h transitio n
of the cSDA line when the cSCK line is High, as shown in Figure 2.
The Start Condition will return the device to the state where it is waiting for a Device
Address (its normal quiescent mode).
The Stop Condition i nit iates an internally ti med wr ite s ignal whose maximum durat ion is
(refer to AC Characteristics table for actual value). During this time, the Configurator
t
WR
must remain in programming mode (i .e. , SER_ EN
is driven Low). cSDA and cSCK lines
are ignored until the cycle is completed. Since the write cycle typically completes in less
than t
seconds, we recommend the use of “polling” as described in later sections.
WR
Input levels to all other pins should be held constant until the write cycle has been
completed.
Acknowledge Bit The Acknowledge (ACK) Bit shown in Figure 2 is provided by the Configurator receiving
the byte. The receiving Configurator can accept the byte by asserting a Low v alue on
the cSDA line, or it ca n refus e th e by te b y as ser tin g ( al lowing the s ig nal to be ex ternal ly
pulled up to) a High value on the cSDA line. All bytes from accepted messages must be
terminated by either an Acknowledge Bit or a Stop Condition. Following an ACK Bit,
when the cSDA line is released during an exchange of control between the Configurator
and the programmer, the cSDA line may be pulled High temporarily due to the open-collector output nature of the li ne. Contro l of the lin e must r esume befor e the nex t rising
edge of the clock.
2314D–FPSLI–2/04
5
Bit Ordering Protocol The most significant bit is the first bit of a byte transm itted on the cSDA li ne for the
Device Address Byte and the EEPROM Address Bytes. It is followed by the lesser significant bits until the eighth bit, th e lea st signif ic ant bit, is tr ansmi tte d. Howe ve r, for Da ta
Bytes (both wri ting an d readin g), the first bit t ransm itted is the lea st signi ficant bit. This
protocol is shown in the diagrams below.
Device Addre ss Byte The contents of the Device Address Byte are shown below, along with the order in which
the bits are clocked into the device.
The CE pin cannot be used for device selection in programming mode (i.e., when
SER_EN
Figure 2. Start and Stop Conditions
cSCK
is drive Low).
cSDA
8th Bit
Byte n
ACK BIT
STOP
Condition
t
WR
START
Condition
Device Address Byte
MSB LSB
1010011R/W
1st 2nd 3rd 4th 5th 6th 7th 8th
Where:R/W = 1 Read
= 0 Write
EEPROM Address
Byte Order
MSB LSB MSB LSB MSB LSB
0000000A
1st 2nd 3rd 4th 5th 6th 7th 8th 1st 2nd 3rd 4th 5th 6th 7th 8th 1st 2nd 3rd 4th 5th 6th 7th 8th
E16
ACK A
E15AE14AE13AE12AE11AE10AE9AE8
ACK AE7AE6AE5AE4AE3AE2AE1A
512-Kbit/1-Mbit Page Length
512-Kbit Address Space
1-Mbit Address Space
ACK
E0
The EEPROM Address consists of three bytes on the 1-Mbit part. Each Address Byte is
followed by an Ackno wledge Bi t (provid ed by the Config urator ). These byte s define th e
normal address space of the Con figurator. The or der in which each byte is clocked into
the Configurator is also indicated. Un used bits in a n Address Byte must be set to “0”.
Exceptions to this are when reading Device and Manufacturer Codes.
6
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Programming Summary:
Write to Whole Device
START
SER_EN ≤ Low
PAGE_COUNT ≤ 0
Send Start Condition
BYTE_COUNT ≤ 0
Send Device Address
($A6)
Yes
Send MSB of
EEPROM Address
Middle Byte
EEPROM Address
Send LSB of
EEPROM Address
(1)
Yes
Yes
(1)
ACK?
ACK?
ACK?
ACK?
No
No
No
No
Notes: 1. The 1-Mbit part requires three EEPROM address
bytes; all three bytes must be individually ACK’d by
the EEPROM.
2. Data byte received/sent LSB to MSB.
EEPROM Address is Defined as:
AT17LV010 0000 000x9x8x7x6x5x4x3x2x1x0000 0000
Note: where Xn ... X0 is (PAGE_COUNT)\b
T_BYTE
AT17LV010 128
T_PAGE
AT17LV010 1024
START CONDITION
cSCK
cSDA
STOP CONDITION
No
Verify Final Write
Cycle Completion
Send Device Address
Low-power (Standby)
Power-Cycle EEPROM
Send Data Byte
BYTE_COUNT ≤
BYTE_COUNT+1
BYTE_COUNT =
T_BYTE?
Send Stop Condition
PAGE_COUNT ≤
PAGE_COUNT+1
Send Start Condition
($A7)
SER_EN ≤ High
(Latches 1st Byte for
FPGA Download
Operations)
Yes
(2)
Yes
ACK?
No
cSCK
cSDA
DATA BIT
cSCK
cSDA
Yes
PAGE_COUNT =
T_PAGE?
No
ACK BIT
cSCK
ACK
Yes
Yes
ACK?
1st Data Byte
Value Changed Due
to Write?
cSDA
No
No
2314D–FPSLI–2/04
END
7
Programming Summary:
Read from Whole Device
START
SER_EN ≤ Low
Send Start Condition
Notes: 1. The 1-Mbit part requires three EEPROM address
bytes; all three bytes must be individually ACK’d by
the EEPROM.
2. Data byte received/sent LSB to MSB
EEPROM Address is Defined as:
AT17LV010 00 00 00 \h
TT_BYTE
AT17LV010 131072 \d
Send Device Address
Random Access Setup
Middle Byte
EEPROM Address
Send MSB of
EEPROM Address
Send LSB of
EEPROM Address
Send Start condition
BYTE_COUNT ≤ 0
Send Device Address
Read Data Byte
BYTE_COUNT ≤
BYTE_COUNT+1
($A6)
($A7)
START CONDITION
ACK?
Yes
ACK?
Yes
No
No
cSCK
cSDA
STOP CONDITION
cSCK
(1)
Yes
(1)
ACK?
ACK?
No
No
cSDA
SAMPLE DATA BIT
cSCK
Yes
cSDA
ACK BIT
ACK?
Yes
(2)
No
cSCK
cSDA
ACK
Send ACK
Sequential Read from Current Address
Sent Stop Condition
SER_EN ≤ High
Low-power (Standby)
END
8
AT94S Secure Family
No
Yes
BYTE_COUNT=
TT_BYTE?
2314D–FPSLI–2/04
AT94S Secure Family
Data Byte
LSB MSB
D0 D1 D2 D3 D4 D5 D6 D7
1st 2nd 3rd 4th 5th 6th 7th 8th
The organization of th e Dat a By te i s sho wn above. Note that in this c ase , the Data B y te
is clocked into the device LSB first and MSB last.
Writing Writing to the normal address space takes place in pages. A page is 128-bytes long in
the 1-Mbit part. The page boundaries are, respectively, addresses where A
are all zero, and AE6 down to AE0 are all zero. Writing can start at any address
A
EOS
within a page and th e numb er of byt es wr itten m ust be 12 8 for the 1- Mbit par t. The fir st
byte is written at the transmitt ed addre ss. The add ress is increm ented in the Configurator following the receipt of each Data Byte. O nly the lower 7 bits of the addr ess are
incremented. Th us, after writing to the last byte addre ss within the given page, the
address will roll over to the first byte address of the same page. A Write Instruction consists of:
a Start Condition
a Device Address Byte with R/W
An Acknowledge Bit from the Configurator
MS Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
Next Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
LS Byte of EEPROM Address
An Acknowledge Bit from the Configurator
One or more Data Bytes (sent to the
Configurator)
Each followed by an Acknowledge Bit from the
Configurator
a Stop Condition
= 0
down to
E0
2314D–FPSLI–2/04
WRITE POLLING: On receipt of the Stop Condition, the Configurato r enters an internally-timed write cycle. While the Configurator is busy with this write cycle, it will not
acknowledge any transfers. The programmer can start the next page write by sending
the Start Condition foll owed by the Device A ddress, in effect poll ing the Confi gurator. If
this is not acknowledged, then the programmer should abandon the transfer without
asserting a Stop Condition. The programmer can then repeatedly initiate a write instruction as above, until an acknowledge is received. When the Acknowledge Bit is received,
the write instruction should continue by sending the first EEPROM Address Byte to the
Configurator.
An alternative to write polling would be to wait a period of t
before sending the next
WR
page of data or exiting the programming mode. All signals must be maintained duri ng
the entire write cycle.
9
Reading Read instructions are initiated similarly to write instructions. However, with the R/W bit in
the Device Addres s set to on e. There are three variant s of the r ead instr uction : curren t
address read, random read and sequential read.
For all reads, it is important to understand that the internal Data Byte address counter
maintains the las t addre ss access ed duri ng the prev ious re ad or writ e operat ion, incr emented by one. This address remains valid between operations as long as the chi p
power is maintained and the device remains in 2-wire access mode (i.e., SER_EN
is
driven Low). If the last operation was a read at address n, then the current address
would be n + 1. If the fina l operati on w as a write at addr ess n , then the curren t addre ss
would again be n + 1 with one exception. If address n was the last byte address in the
page, the incremented address n + 1 would “roll over” to the first byte address on the
next page.
CURRENT ADDRESS READ: Once the Device Address (with the R/W
select bit set to
High) is clocke d in and a cknowle dged by th e Conf igur ator, the Data Byte at th e curre nt
address is serially clocked out by the Configurator in response to the clock from the programmer. The programmer generates a Stop Condition to accept the single byte of data
and terminate the read instruction.
A Current Address Read instruction consists of
a Start Condition
a Device Address with R/W
An Acknowledge Bit from the Configurator
a Data Byte from the Configurator
a Stop Condition from the programmer.
= 1
RANDOM READ: A Random Read i s a Curre nt Ad dr ess Read preceded by an abor te d
write instruction. The write instruction is only initiated for the purpose of loading the
EEPROM Address Bytes. Once the Device Address Byte and the EEPROM Address
Bytes are clocked in and acknowledged by the Configurator, the programmer immediately initiates a Current Address Read.
A Random Address Read instruction consists of :
a Start Condition
a Device Address with R/W
An Acknowledge Bit from the Configurator
MS Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
Next Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
LS Byte of EEPROM Address
An Acknowledge bit from the Configurator
a Start Condition
a Device Address with R/W
An Acknowledge Bit from the Configurator
a Data Byte from the Configurator
a Stop Condition from the programmer.
= 0
= 1
10
AT94S Secure Family
2314D–FPSLI–2/04
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