ATMEL AT90S4414-8AI, AT90S4414-8AC, AT90S4414-4PI, AT90S4414-4JI, AT90S4414-4JC Datasheet
...
Features
®
•
R
AV
- High Performance and Low Power RISC Architecture
•
118 Powerful Instructions - Most Single Clock Cycle Execution
•
4K bytes of In-System Reprogrammable Flash
– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Eras e Cycles
•
256 bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
•
256 bytes Internal SRAM
•
32 x 8 General Purpose Working Registers
•
32 Programmable I/O Lines
•
Programmable Serial UART
•
SPI Serial Interface
•
VCC: 2.7 - 6.0V
•
Fully Static Operation
– 0 - 8 MHz, 4.0 - 6.0V
– 0 - 4 MHz, 2.7 - 4.0V
•
Up to 8 MIPS Throughput at 8 MHz
•
One 8-Bit Timer/Counter with Separate Prescaler
•
One 16-Bit Timer/Counter with Separate Prescaler
and Compare and Capture Modes
•
Dual PWM
•
External and Internal Interrupt Sources
•
Programmable Watchdog Timer with On-Chip Oscillator
•
On-Chip Analog Comparator
•
Low Power Idle and Power Down Modes
•
Programming Lock for Software Security
8-Bit
Microcontr oller
with 4K bytes
In-System
Programmable
Flash
AT90S4414
Description
The AT90S4414 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture . By exe cuting powe rful instruc tions in a single clock
cycle, the AT90S4414 achieves throughpu ts approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture that combines a rich
instruction set w ith 32 gener al purpose working regis ters. All the 32 registe rs are
directly connected to the A rithmetic Logic Unit (ALU ), all owi ng two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
(continued)
Pin Configurations
Preliminary
Rev. 0840DS–07/98
Note: This is a summary document. For the complete 76 page
datasheet, please visit our web site at
literature@atmel.com
mail at
and request literature #0840D.
www.atmel.com
or e-
1
Block Diagram
Figure 1.
The AT90S4414 Block Diagram
The AT90S4414 provides the following features: 4K bytes
of In-System Programmable Flash, 256 bytes EEPROM,
256 bytes SRAM, 32 gen eral purpo se I/O li nes, 3 2 general
purpose working registers, flexible timer/counters with
compare modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer
with internal oscillator, an SPI serial port and two software
selectable pow er saving modes. T he Idl e Mode sto ps the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt syste m to contin ue functioning . The power
down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset.
2
AT90S4414
The device is manufac tured using Atmel’ s high density
non-volatile m emory tech nology. The on-chip In-S ystem
Programmable Flash allows the program memory to be
reprogrammed in-sys tem th ro ugh an S PI se rial i nterface or
by a conventional n onvolatile memo ry programmer. By
combining an enhanced RISC 8-bit CPU wit h In-System
Programmable Flash on a monolithic chip, the Atmel
AT90S4414 is a powerful microcontroller that provides a
highly flexible and co st effect ive solution to many em bedded control applications.
AVR
The AT90S4414
gram and system development tools including: C compilers, macro assemblers, program debugger/si mulators, incircuit emulators, and evaluati on kits.
is supported with a full suite of pro-
AT90S4414
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0
Port A is an 8 -bit b idirec tional I/O port. Port p ins ca n provide internal pull-up resistors (selected for each bit). The
Port A output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs
and are externally pull ed low, they will source c urrent if the
internal pull-up resistors are activated.
Port A serves as Multiplexed Address/Data input/output
when using external SRAM.
Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O pins with internal pull-up
resistors. The Port B output buffers can sink 20 mA. As
inputs, Port B pins t hat a re ex ter nally pu ll ed l ow wi ll sour c e
current if the pull-up resistors are activated.
Port B also serves the fu nction s of vario us speci al feat ures
of the AT90S4414 as listed on page 45.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port C output buffers can sink 20 mA. As
inputs, Port C pins that are exter nal ly pul led low wil l sour ce
current if the pull-up resistors are activated.
Port C als o s erv es as Addr es s ou tp ut when us ing ext ern al
SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port D output buffers can sink 20 mA. As
inputs, Port D pins that are exter nal ly pul led low wil l sour ce
current if the pull-up resistors are activated.
Port D also serves th e fu nc tion s of v ario us sp ec ial fea tur es
of the AT90S4414 as listed on page 51.
RESET
Reset input. A low on th is pi n for two machi ne cy cles wh ile
the oscillator is running resets the device.
XTAL1
Input to the inverting os cillator amplifi er and input to th e
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
ICP
ICP is the input pin for the Time r/Counter1 Inpu t Capture
function.
)
OC1B
OC1B is the output pin for the Timer/Counter1 Output
CompareB function
ALE
ALE is the Address Latch Enable used when the Ex ternal
Memory is enabled. The ALE strob e is used to latch the
low-order address (8 bits) into an address latch during the
first access cy cle, and the A D0-7 pins a re used for data
during the second access cycle.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 3.
Figure 2.
Figure 3.
Oscillator Connec tio ns
External Clock Drive Configuration
3
Loading...