ATMEL AT90LS2343-4SI, AT90LS2343-4SC, AT90LS2343-4PI, AT90LS2343-4PC, AT90S2343-10SI Datasheet
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Features
•
Utilizes the
•
AVR
- High Performance and Low Power RISC Architecture
•
118 Powerful Instructions - Most Single Clock Cycle Execution
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2K bytes of In-System Programmable ISP Flash
– SPI Serial Interface for In-System Programming
– Endurance: 1,000 Write/Eras e Cycles
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128 bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
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128 bytes Internal RAM
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32 x 8 General Purpose Working Registers
– 3 AT90S/LS2323 Programmable I/O Lines
– 5 AT90S/LS2343 Programmable I/O Lines
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VCC: 4.0 - 6.0V AT90S2323/AT90S2343
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VCC: 2.7 - 6.0V AT90LS2323/AT90LS2343
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Power-On Reset Circuit
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Speed Grades: 0 - 10 MHz AT90S2323/AT90S2343
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Speed Grades: 0 - 4 MHz AT90LS2323/AT90LS2343
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Up to 10 MIPS Throughput at 10 MHz
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One 8-Bit Timer/Counter with Separate Prescaler
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External and Internal Interrupt Sources
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Programmable Watchdog Timer with On-Chip Oscillator
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Low Power Idle and Power Down Modes
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Programming Lock for Flash Program and EEPROM Data Security
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Selectable On-Chip RC Oscillator
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8-Pin Device
®
AVR
Enhanced RISC Architecture
8-Bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
AT90S2323
Description
The AT90S/LS2323 and AT90S/LS2343 is a low-power CMOS 8-bit microcontrollers
based on the
in a single cloc k cycl e, the AT 90S/LS 2323 and A T90S/ LS2343 achieves throug hputs
approaching 1 MIPS per MHz allo wing the system desi gner to optimize powe r consumption versus processing speed.
The AVR core combines a rich instr uction set with 32 gene ral purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two indep endent r egisters to be acce ssed in one singl e instr uction execute d
in one clock cycle. Th e resulting arc hitecture is mor e code efficie nt while achievin g
throughputs up to ten times faster than conventional CISC microcontrollers.
®
AVR
enhanced RISC arch itectu re. By exec uting pow erful in struc tions
Pin Configuration
PDIP/SOIC
RESET
(CLOCK) PB3
PB4
GND
1
2
3
4
AT90S/LS2343 AT90S/LS2323
8
VCC
7
PB2 (SCK/T0)
6
PB1 (MISO/INT0)
5
PB0 (MOSI)
RESET
XTAL1
XTAL2
GND
1
2
3
4
8
VCC
7
PB2 (SCK/T0)
6
PB1 (MISO/INT0)
5
PB0 (MOSI)
AT90LS2323
AT90S2343
AT90LS2343
Preliminary
A T90S/LS2323
Rev. 1004AS–05/98
Note: This is a summary document. For the complete 34 page
document, please visit our website at
literature@atmel.com
and request literature #1004A.
www.atmel.com
or e-mail at
1
Block Diagram
Figure 1. The AT90S/LS2343 Block Diagram
VCC
GND
PROGRAM
COUNTER
STACK
POINTER
8-BIT DATA BUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
TIMING AND
CONTROL
RESET
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
SPI
DATA REGISTER
PORTB
PORTB DRIVERS
PB0 - PB4
MCU CONTROL
REGISTER
TIMER/
COUNTER
INTERRUPT
UNIT
EEPROM
DATA DIR.
REG. PORTB
OSCILLATOR
2
AT90S/LS2323 and AT90S/LS2343
Figure 2. The AT90S/LS2323 Block Diagram
VCC
GND
PROGRAM
COUNTER
STACK
POINTER
AT90S/LS2323 and AT90S/LS2343
8-BIT DATA BUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
TIMING AND
CONTROL
RESET
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
SPI
DATA REGISTER
PORTB
PORTB DRIVERS
Description
The AT90S/LS2323 and AT90S/LS2343 provides the following features: 2K bytes of In-System Programmable
Flash, 128 bytes EEPROM, 128 bytes SRAM, 3
(AT90S/LS2323) / 5 (AT90S/LS2343) general purpose I/O
lines, 32 general purpose workin g registers, an 8-bit
timer/counter, internal a nd externa l interru pts, progr ammable Watchdog Timer with internal oscillator, an SPI serial
port for Fla sh Memory down loading and two software
selectable power savi ng modes. The Idle Mo de stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to conti nue functioning. The pow er
down mode saves the register contents but freezes the
oscillator, disabling all other chip func tions until the next
interrupt or hardware reset.
The device is manufac tured using Atmel’s high density
non-volatile memory technology. The on-chip Flash allows
the program memory to be reprogrammed in-system
through an SPI serial interface. By combining an 8-bit RISC
CPU with ISP Flash on a monolithic chip, the Atmel
AT90S/LS2323 an d AT90S/LS234 3 is a powerful mi cro-
MCU CONTROL
REGISTER
TIMER/
COUNTER
INTERRUPT
UNIT
EEPROM
OSCILLATOR
DATA DIR.
REG. PORTB
PB0 - PB2
controller that provides a highly flexibl e and cost effective
solution to many embedded control applications.
The AT90S/LS2323 and AT90S/LS2343 AVR is supported
with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Comparison Between AT90S/LS2323
and AT90S/LS2343
The AT90S/LS2323 is intended for use with external quartz
crystal or ceramic resonator as the clock source. The startup time is fuse selectable as either 1 ms (suitable for
ceramic resonator) or 16 ms (suitable for crystal). The
device has three I/0 pins.
The AT90S/LS2343 is intended for use with either an external clock source or the internal RC oscillator as clock
source. The device has five I/0 pins.
3
Table 1 summarizes the differences in features of the two
devices.
Table 1. Feature Difference Summary
Part AT90S/LS2323 AT90S/LS2343
On-chip oscillator
amplifier
Internal RC Clock no yes
PB3 usable never internal clock mode
PB4 usable never always
Startup time 1 ms / 16 ms 16 µs fixed
yes no
Pin Descriptions AT90S/LS2323
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB2..PB0)
Port B is a 3-bit bi-directional I/O port. Port pins can provide
internal pull-up resistors (selected for each bit).
RESET
Reset input. A low on thi s pin for t wo m achine c ycles while
the oscillator is running resets the device.
XTAL1
Input to the inverting os cillator ampl ifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Pin Descriptions AT90S/LS2343
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB4..PB0)
Port B is a 5-bit bi-directional I/O port. Port pins can provide
internal pull-up resistors (selected for each bit). W hen the
device is clocked from an external clock source, PB3 is
used as the clock input.
RESET
Reset input. A low on thi s pin for t wo m achine c ycles while
the oscillator is running resets the device.
CLOCK
Clock signal input in external clock mode.
Clock Sources
The AT90S/LS2323 contains an inverting amplifier which
can be configured for us e as an on-chip oscillato r, as
shown in Figure 3. XTAL1 and XTAL2 ar e input and ou tput
respectively. Either a quartz crystal or a ceramic resonator
may be used. It is recommended to use the AT90S/LS2343
if an external clock source is used, since this gives an extra
I/O pin.
The AT90S/LS2343 can be clocked by an external clo ck
signal, as shown in Figure 4, or by the on-chip RC oscillator. This RC oscillator runs at a nominal frequency of 1
MHz (VCC = 5V). A fuse bit - RCEN - in the Flash mem ory
selects the on-chip RC oscillator as the clock source when
programmed ('0'). The AT90S/LS2343 is shipped with this
bit programmed.
Figure 3. Oscillator Connection
Figure 4. External Clock Drive Configuration
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AT90S/LS2323 and AT90S/LS2343
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