ATMEL AT89S53-33AC, AT89S53-24PI, AT89S53-24PC, AT89S53-24JI, AT89S53-24JC Datasheet

Features

•

Compatible with MCS-51™ Products

•

12K Bytes of In-System Reprogrammable Downloadable Flash Memory

– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles

•

4.0V to 6V Operating Range

•

Fully Static Operation: 0 Hz to 24 MHz

•

Three-Level Program Memory Lock

•

256 x 8-bit Internal RAM

•

32 Programmable I/O Lines

•

Three 16-bit Timer/Counters

•

Nine Interrupt Sources

•

Programmable UART Serial Channel

•

SPI Serial Interface

•

Low Power Idle and Power Down Modes

•

Interrupt Recovery From Power Down

•

Programmable Watchdog Timer

•

Dual Data Pointer

•

Power Off Flag

8-Bit
Microcontroller
with 12K Bytes
Flash

Description

The AT89S53 is a low-power, hi gh- perfo rm anc e CM OS 8-bi t mi croc om pute r with 12K
bytes of Downloadable Flash programmable and erasable read only memory. The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard 80C51 instruction set and pinout. The on­chip Downloadable Fla sh al lows the program memory to be re progr am med in -sy st em
through an SPI serial interfac e or by a conventi onal nonv olatile memory pr ogram mer.
By combining a versatile 8-bit CPU with Downloadable Flash on a monolithic chip, the
Atmel AT89S53 is a powerful microcomputer which provides a highly flexible and cost
effective solution to many embedded control applications.

The AT89S53 provides the following standard features: 12K bytes of Downloadable
Flash, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two Data Point­ers, three 16-bit timer/co unters, a six-ve ctor two-level inter rupt architecture, a ful l
duplex serial port, on-chip oscillator, and clock c ircuitry. In addition, the AT89S53 is
designed with static logic for operation down to zero frequency and supports two soft­ware selectable power sa ving modes. The Id le Mode stops the CPU while allowing
the RAM, timer/counters, serial port, and interrupt system to continue functioning. The
Power Down Mode saves the RAM contents but freezes the osc illator, disabl ing all
other chip functions until the next interrupt or hardware reset.

The Downloadab le Flash ca n be c hanged a si ngle byte a t a ti me and is acc essibl e
through the SPI serial interface. Holding RESET active forces the SPI bus into a serial
programming interface and allows the program memory to be written to or read from
unless Lock Bit 2 has been activated.

AT89S53

0787B-B–12/97

4-217

Pin Configurations

PDIP

1

(T2) P1.0

2
3

P1.2

4

P1.3

5
6
7
8
9

RST

10
11
12
13
14

(T0) P3.4

15

(T1) P3.5

16
17
18

XTAL2

19

XTAL1

20

GND

TQFP

P1.4 (SS)

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)NCVCC

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

1213141516171819202122

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(T2 EX) P1.1

(SS) P1.4
(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(WR) P3.6

(RD) P3.7

NC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P0.0 (AD0)

VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

33
32
31
30
29
28
27
26
25
24
23

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

PLCC

P1.4 (SS)

P1.3

P1.2

P1.1 (T2 EX)

65432

7
8
9
10
11
12

NC

13
14
15
16
17

1819202122232425262728

XTAL2

XTAL1

(RD) P3.7

(WR) P3.6

P1.0 (T2)NCVCC

1

4443424140

NC

GND

(A8) P2.0

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

(A9) P2.1

(A10) P2.2

(A11) P2.3

P0.3 (AD3)

39

P0.4 (AD4)

38

P0.5 (AD5)

37

P0.6 (AD6)

36

P0.7 (AD7)

35

EA/VPP

34

NC

33

ALE/PROG

32

PSEN

31

P2.7 (A15)

30

P2.6 (A14)

29

P2.5 (A13)

(A12) P2.4

GND

GND

XTAL2

XTAL1

(A8) P2.0

(RD) P3.7

(WR) P3.6

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

Pin Description

V

CC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high­impedance inputs.

Port 0 can also be configu red to be the multiplex ed low­order address/data bus during accesses to ex ternal pro­gram and data memory. In this mode, P0 has internal pul­lups.

4-218

AT89S53

Port 0 also receives the code bytes during Flash program­ming and outputs the code bytes durin g program verifica ­tion. External pullu ps are require d duri ng prog ram ve rifica ­tion.

Port 1

Port 1 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are writte n to Po rt 1 pi ns, they a re pul led high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

IL

Some Port 1 pins p rovide additi onal functions. P1.0 and
P1.1 can be config ured to be th e timer/count er 2 ext ernal
count input (P1.0/T2) and the timer/counter 2 trigger input
(P1.1/T2EX), respectively.

Block Diagram

AT89S53

V

CC

GND

B

REGISTER

RAM ADDR.

REGISTER

P0.0 - P0.7

PORT 0 DRIVERS

RAM

ACC

TMP2 TMP1

PORT 0

LATCH

P2.0 - P2.7

PORT 2 DRIVERS

PORT 2

LATCH

STACK

POINTER

FLASH

PROGRAM
ADDRESS
REGISTER

BUFFER

PSEN

ALE/PROG

EA / V

RST

PC

ALU

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PSW

TIMING

AND

PP

CONTROL

OSC

INSTRUCTION

REGISTER

WATCH

DOG

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

SPI

PORT

INCREMENTER

PROGRAM
COUNTER

DPTR

PROGRAM

LOGIC

4-219

Pin Description

Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured
as the SPI slave port select, data input/output and shift
clock input/output pins as shown in the following table.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2),

clock-out

P1.1 T2EX (Timer/Counter 2 capture/reload trigger

and direction control)
P1.4 SS
P1.5 MOSI (Master data output, slave data input pin

(Slave port select input)

for SPI channel)

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
P3.7 RD

(external interrupt 0)

(external data memory write strobe)

(external data memory read strobe)

P1.6 MISO (Master data input, slave data output pin

for SPI channel)
P1.7 SCK (Master clock output, slave clock input pin

for SPI channel)

Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port 2

Port 2 is an 8-bit bidire ction al I/O por t w ith inter nal pullu ps.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins , they are p ulled hi gh by
the internal pullups and can be used as inputs. As inputs ,
Port 2 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

IL

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addre sses (MO VX @
DPTR). In this application, Port 2 uses strong internal pul­lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3

Port 3 is an 8 bit b idirec tional I/O port with i nternal pul lups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins , they are p ulled hi gh by
the internal pullups and can be used as inputs. As inputs ,
Port 3 pins that are externally being pulled low will source
current (I

) because of the pullups.

IL

Port 3 also se rves the fu nctio ns of vari ous sp ecial f eat ures
of the AT89S53, as shown in the following table.

Port 3 also receives some control signals for Flash pro­gramming and verification.

RST

Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.

ALE/PROG

Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem­ory. This pin is also the program pulse input (PROG

) during

Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6

the oscillator frequency and may be used for external tim­ing or clocking purposes. Note, however, that one ALE
pulse is skipped d ur in g ea ch ac c ess to ex ter na l d ata mem ­ory.

If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8 EH. With the bit se t, ALE is activ e only du r­ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro­gram memory.

When the AT89S53 is executing code from external pro­gram memory, PSEN
cycle, except that two PSEN

is activated twice each machine

activations are skipped during

each access to external data memory.

/V

EA

PP

External Access Enable. EA must be strapped to GN D in
order to enable the device to fetch code from external pro­gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA

will be

internally latched on reset.

should be strapped to VCC for internal program execu-

EA
tions. This pin also recei ves the 12-volt programmi ng
enable voltage ( V

) during Flash prog ramming when 12-

PP

volt programming is selected.

4-220

AT89S53

AT89S53

XTAL1

Input to the inverting os cillator ampl ifier and input to the
internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special Func­tion Register (SFR) space is shown in Table 1.

Note that not all of the address es are occupied, and unoc­cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indeterminate
effect.

Table 1.

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H

AT89S53 SFR Map and Reset Values

B

00000000

ACC

00000000

PSW

00000000

T2CON

00000000

T2MOD

XXXXXX00

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

SPCR

000001XX

TH2

00000000

0F7H

0E7H

0D7H

0CFH

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

SPSR

00XXXXXX

TL0

00000000

DP0L

00000000

TL1

00000000

DP0H

00000000

TH0

00000000

DP1L

00000000

TH1

00000000

DP1H

00000000

WCON

00000010

SPDR

XXXXXXXX

PCON

0XXX0000

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

4-221

User software shou ld not write 1s to these unlisted loca­tions, since they may be u sed in future products to invoke
new features. In that case, the reset or inactive values of the
new bits will always be 0.

Timer 2 Registers

Control and status b its ar e con tai ned in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 9) for Timer 2. The register pa ir (RC AP 2H, RCA P2 L)
are the Capture/Reload registers for Timer 2 in 16 bit cap­ture mode or 16-bit auto-reload mode.

Watchdog Control Register

The WCON register con tains
control bits for the Watchdog Timer (shown in Table 3). The
DPS bit selects one of two DPTR registers available.

SPI Registers

Control and status bits for the Serial Periph­eral Interface are contained in registers SPCR (shown in
Table 4) and SPSR (shown in Table 5). The SPI data bits
are contained in the SPDR register. Writing the SPI data
register during serial data transfer sets the Write Collision
bit, WCOL, in the SPSR register. The SPDR is double buff­ered for writing and the values in SPDR are not changed by
Reset.

Interrupt Registers

The global interrupt enable bit and the
individual interrupt enable bits are in the IE register. In addi­tion, the individual interrupt enable bit for the SPI is in the
SPCR register. Two priorities ca n be set for each of the si x
interrupt sources in the IP register.

Table 2.

T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable

Symbol Function

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK =

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if

TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0

T2CON—Timer/Counter 2 Control Register

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

Bit

76543210

1 or TCLK = 1.

When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.

Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

Timer or counter selec t f or Timer 2 . C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).

causes automatic reloads to occur when Tim er 2 ov erflo ws or negativ e trans itions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

CP/RL2

4-222

AT89S53

AT89S53

Dual Data Pointer Registers

To facilitate accessing exter­nal data memory, two banks of 16 bit Data Pointer Regis ­ters are provided: DP0 at SFR address locations 82H-83H
and DP1 at 84H-85H. Bit DPS = 0 in SFR WCO N selec ts

Power Off Flag

The Power Off Flag (POF) is located at
bit_4 (PCON.4) in the PCON SFR. PO F is set to “ 1” durin g
power up. It can be set and reset under software control
and is not affected by RESET.

DP0 and DPS = 1 selects DP1. The user should always ini­talize the DPS bit to the appropriate value before accessing
the respective Data Pointer register.

Table 3.

WCON Address = 96H Reset Value = 0000 0010B

Bit

Symbol Function

PS2
PS1
PS0

DPS Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the

WDTRST Watchdo g Timer Res et. Each time th is bit is set to “1” b y user so ftwar e, a pul se is gen erated to reset the w atchdo g timer .

WCON—Watchdog Control Register

PS2 PS1 PS0 res erved reserved DPS WDTRST WDTEN

76543210

Prescaler Bits f or the Watchdog Time r. When all thre e bits are set to “0”, the w atc hdo g ti me r ha s a n om ina l p eriod of 1 6
ms. When all three bits are set to “1”, th e nominal period is 2048 ms.

second bank, DP1

The WDTRST bit is then automatically reset to “0” in the next instruction cycle. The WDTRST bit is Write-Only.

WDTEN Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.

4-223

Table 4

. SPCR—SPI Control Register

SPCR Address = D5H Reset Value = 0000 01XXB

SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0

Bit

Symbol Function

SPIE SPI Interrupt Enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES

SPE SPI Enable. SPI = 1 enables the SPI channel and connects SS

DORD Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.
MSTR Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode.
CPOL Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not

CPHA Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and

SPR0
SPR1

76543210

= 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts.

, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and

P1.7. SPI = 0 disables the SPI channel.

transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.

slave. Please refer to figure on SPI Clock Phase and Polarity Control.
SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have

no effect on the slave. The relationship between SCK and the oscillator frequency, F
SPR1SPR0SCK = F

004
0116
1064
11128

divided by

OSC.

, is as follows:

OSC.

Table 5.

SPSR Address = AAH Reset Value = 00XX XXXXB

Symbol Function

SPIF SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and

WCOL Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer,

4-224

SPSR—SPI Status Register

SPIFWCOL——————

Bit

76543210

ES = 1. The SPIF bit is cleared by reading the SPI status register with SPIF and WCOL bits set, and then accessing
the SPI data register.

the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF
bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register.

AT89S53

AT89S53

Table Table 6.

SPDR Address = 86H Reset Value = unchanged

Bit

Data Memory - RAM

The AT89S53 implements 256 bytes of RAM. The upper
128 bytes of RAM occupy a parallel space to the Special
Function Registers. That means the upper 128 bytes have
the same addresses as the SFR sp ace but ar e physic ally
separate from SFR space.

When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.

For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instru ct ion , where R0 contains 0A0H, acc es s es
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect
addressing, so the upper 128 byte s of data RAM are avail ­able as stack space.

SPDR—SPI Data Register

SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0

76543210

Programmable Watchdog Timer

The programmable Watchdog Timer (WDT) operates from
an independent oscillator. T he prescaler bits, PS0, PS1
and PS2 in SFR W CON are us ed to set th e period of the
Watchdog Timer from 16 ms to 2048 ms. The available
timer periods are shown in the following table and the
actual timer periods (at V
nominal.

The WDT is disabled by Power-on Reset and during Power
Down. It is enable d by setting the WDTE N bit in SFR
WCON (addres s = 96 H). The W DT is reset by setti ng the
WDTRST bit in WCO N. When the WDT times out without
being reset or disabled, an in terna l RST pu ls e is gene rated
to reset the CPU.

Table 7.

Watchdog Timer Period Selection

WDT Prescaler Bits Period (nominal)

PS2 PS1 PS0

000 16 ms
001 32 ms
010 64 ms
011 128 ms
100 256 ms
101 512 ms

= 5V) are within ±30% of the

CC

1 1 0 1024 ms
1 1 1 2048 ms

4-225

Timer 0 and 1

Timer 0 and Timer 1 in the AT89S53 operate the same way
as Timer 0 and Timer 1 in the AT89C51, AT89C52 and
AT89C55. For further information, see the October 1995
Microcontroller Data Book, page 2-4 5, section titled,
“Timer/Counters.”

Timer 2

Timer 2 is a 16 bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 8.

Timer 2 consists of two 8- bi t regi st er s, TH2 and TL2. I n the
Timer function, the TL2 r egister is incremented ever y
machine cycle. Since a machine cycle consists of 12 oscil­lator periods, the count rate is 1/12 of the oscillator fre­quency.

In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In thi s func tion, the extern al i nput is sa mpled
during S5P2 of every machin e cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator periods ) ar e requi r ed to r ec og niz e a 1 -t o- 0 tran si ­tion, the maximum count rate is 1/24 of the oscillator fre­quency. To ensure that a gi ven level is sam pled at least
once before it changes, the level should be held for at least
one full machine cycle.

in the SFR T2 C ON (sh o w n i n Ta bl e 2).

Table 8.

Timer 2 Operating Modes

RCLK + TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-Reload
0 1 1 16-bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)

Capture Mode

In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16 bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 performs the same operation, but a l­to-0 transition at external input T2EX also causes the cur­rent value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, resp ective ly. In addi tion, th e transit ion at T2E X
causes bit EXF2 in T2CON to be set. The EXF2 bit, like
TF2, can generate an interrupt. The capture mode is illus­trated in Figure 1.

Auto-Reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when
configured in its 16 bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 9). Upon reset, the DCEN bit
is set to 0 so that ti mer 2 will defa ult to count u p. When
DCEN is set, Timer 2 can coun t up or down, depend ing on
the value of the T2EX pin.

Figure 2 shows Timer 2 automatically co unting up when
DCEN = 0. In this mod e, two options are selecte d by bit

Figure 1.

T2EX PIN

4-226

Timer 2 in Capture Mode

OSC

T2 PIN

÷12

TRANSITION

DETECTOR

AT89S53

C/T2 = 0

C/T2 = 1

EXEN2

CONTROL

TR2

CAPTURE

CONTROL

TH2 TL2

RCAP2LRCAP2H

EXF2

TF2

OVERFLOW

TIMER 2

INTERRUPT