Atmel AT89C52 User Manual

8-Bit
Microcontroller
with 8 Kbytes
Flash

AT89C52

Features

Compatible with MCS-51TM Products

•

8 Kbytes of In-System Reprogrammable Fl as h Me mory

•

Endurance: 1,000 Wri te/Erase Cycles

Fully Static Operati on : 0 Hz to 24 MHz

•

Three-Level Program Mem ory Loc k

•

256 x 8-Bit Internal RAM

•

32 Programmable I/O Lines

•

Three 16-Bit Timer/Counters

•

Eight Interrupt Sources

•

Programmable Serial Ch an ne l

•

Low Power Idle and Power Down Modes

•

Description

The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8
Kbytes of Flash programmable and erasable read only memory (PEROM). The de­vice is manufactured using Atmel’s high density nonvolatile memory tec hnology and
is compatible with the industry standard 80C51 and 80C52 instruction set and pinout.
The on-chip Flash allows the program memory to be reprogrammed in-system or by
a conventional nonvolatile memory programmer. By combining a vers atile 8-bit CPU
with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer
which provides a highly flexible and cost effective solution to many embedded control
applications.

(continued)

Pin Configurations

PQFP/TQFP

SS)

INDEX
CORNER

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

NC

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(

NC

P1.3

P1.2

P1.0 (T2)

VCC

P1.1 (T2 EX)

P1.4

424340

44

1
2
3
4
5
6
7
8
9
10
11

13

12

(WR) P3.6

14

(RD) P3.7

41

15

XTAL2

16

XTAL1

39

17

GND

38

18

GND

(A8) P2.0

37

19

P0.0 (AD0)

P0.1 (AD1)

36

35

21

20

(A9) P2.1

(A10) P2.2

P0.2 (AD2)

P0.3 (AD3)

34

33
32

30
29

28
27
26
25
24
23

22

(A11) P2.3

(A12) P2.4

31

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA/VPP

NC

ALE/PROG
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

(T2) P1.0

(T2 EX) P1.1

(SS) P1.4
(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(WR) P3.6

(RD) P3.7 P2.3 (A11)

INDEX
CORNER

(MOSI) P1.5

(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

PDIP/Cerdip

1
2

P1.2

3

P1.3

4
5
6
7
8

RST

9
10
11
12
13
14
15
16

XTAL2 P2.2 (A10)
XTAL1 P2.1 (A9)

17
18
19

GND P2.0 (A8)

20

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA/VPP
ALE/PROG
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)

V

CC

40

PLCC/LCC

SS)

NC

VCC

P0.2 (AD2)

P0.3 (AD3)

P0.1 (AD1)

P0.0 (AD0)

P1.0 (T2)

P1.1 (T2 EX)

P1.2

P1.3

P1.4 (

2

1

23

22

GND

XTAL1

NC

424340

252827

26

(A9) P2.1

(A8) P2.0

41

(A10) P2.2

39

38
37

36
35
34
33
32
31
30

(A11) P2.3

(A12) P2.4

65444

3

7
8
9
10
11

NC

12
13
14
15
16
17 29

21

181920 24

XTAL2

(RD) P3.7

(WR) P3.6

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA/VPP

NC

ALE/PROG
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

0313E

Block Diagram

V

CC

GND

RAM ADDR.

REGISTER

B

REGISTER

ACC

TMP2

P0.0 - P0.7

PORT 0 DRIVERS

RAM

PORT 0

LATCH

TMP1

PORT 2 DRIVERS

PORT 2

LATCH

POINTER

P2.0 - P2.7

FLASH

STACK

PROGRAM

ADDRESS

REGISTER

BUFFER

PSEN

ALE/PROG

EA / V

RST

PC

ALU

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PSW

TIMING

AND

PP

CONTROL

OSC

INSTRUCTION

REGISTER

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

INCREMENTER

PROGRAM

COUNTER

DPTR

2 AT89C52

(continued)

AT89C52

Description (Continued)

The AT89C52 provides the following standard features: 8
Kbytes of Flash, 256 bytes of RAM, 32 I/O lines , thr ee 16­bit timer/counters, a six-vector two-level interr upt architec­ture, a full duplex serial port, on-chip oscillator, and clock
circuitry. In addition, the AT89C52 is designed with static
logic for operation down to zero frequency and supports
two soft ware selectable p ower saving modes. The Idle
Mode stops the CPU while allowing the RAM, timer/count­ers, serial port, and interrupt system to continue function­ing. The Power Down Mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions un­til the next hardware reset.

Pin Description

V

CC

Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an

output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-im­pedance inputs.

Port 0 can also be configured to be the multiplexed low-or­der address/data bus during accesses to external pro­gram and data memory. In this mode, P0 has internal pul­lups.

Port 0 also receives the code bytes during Flash program­ming and outputs the code bytes during program verifica­tion. External pullups are required during program verifica­tion.

Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I

In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.

Port Pin

P1.0

P1.1

) because of the internal pullups.

IL

Alternate Functions

T2 (external count input to
Timer/Counter 2), clock-out

T2EX (Timer/Counter 2 capture/reload
trigger and direction control)

Port 1 also receives the low-order address bytes during
Flash programming and program verification.

Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I

Port 2 emits the high-order address byte during fetches
from external pro gram memory and during accesses to
external data memory that use 16-bit addresses (MOVX
@ DPTR). In this application, Port 2 uses strong internal
pullups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MO VX @ RI), Port
2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I

Port 3 also serves the functions of various special features
of the AT89C51, as shown in the following table.

Port Pin

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2
P3.3
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6
P3.7

Port 3 also receives some control signals for Flash pro­gramming and programming verification.

RST
Reset inp ut. A high on this pin for t wo machine cycles

while the oscillator is running resets the device.
ALE/
Address Latch Enable is an output pulse for latching the

low byte of the address during accesses to external mem­ory. This pin is also the program pulse input (
ing Flash programming.

) because of the internal pullups.

IL

) because of the pullups.

IL

Alternate Functions

INT0 (external interrupt 0)
INT1 (external interrupt 1)

WR (external data memory write strobe)
RD (external data memory read strobe)

PROG

PROG) dur-

3

EA/V

Pin Description (Continued)

In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency and may be used for external
timing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data
memory.

If desired, ALE operation can be disabled by setting bit 0
of SFR location 8EH. With the bit set, ALE is active only
during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no ef­fect if the microcrontroller is in external execution mode.

PSEN
Program Store Enable is the read strobe to external pro-

gram memory.
When the AT89C52 is executing code from external pro-

gram memory,
cle, except that two

PSEN is activated twice each machine cy-

PSEN activations are skipped during

PP

External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro­gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is pr ogrammed,

EA will be

internally latched on reset.
EA should be strapped to VCC for internal program execu-

tions.
This pin also receives the 12-volt programming enable

voltage (V

) during Flash programming when 12-volt pro-

PP

gramming is selected.
XTAL1
Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.

each access to external data memory.

Table 1. AT89C52 SFR Map and Reset Values

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

B

00000000

ACC

00000000

PSW

00000000

T2CON

00000000

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111

T2MOD

XXXXXX00

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

RCAP2L

00000000

TL0

00000000

DPL

00000000

RCAP2H

00000000

TL1

00000000

DPH

00000000

TL2

00000000

TH0

00000000

TH2

00000000

TH1

00000000

PCON

0XXX0000

0F7H

0E7H

0D7H

0CFH

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

4 AT89C52

AT89C52

Special Function Registers

A map of the on-chip memory area called the Special
Function Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc­cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi­nate effect.

User software should not write 1s to these unlisted loca­tions, since they may be used in future products to invoke

new features. In that case, the reset or inactive values of
the new bits will always be 0.

Timer 2 Registers Control and status bits are contained
in registers T2C ON (shown in Table 2) and T2MOD
(shown in Table 4) for Timer 2. The register pair
(RCAP2H, RCAP2L) are the Capture/Reload registers for
Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.

Table 2. T2CON—Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/

Bit76543210

T2 CP/RL2

Symbol Function

TF2 Timer 2 overflow flag set by a Ti me r 2 ove rfl ow an d mu st be cl ea red by so ft ware . TF2 will not be set when

EXF2 Timer 2 external fla g se t whe n ei th er a ca pture or reload is caused by a ne ga ti ve transition on T2EX and

RCLK

either RCLK = 1 or TCLK = 1.

EXEN2 = 1. When Timer 2 interrupt is enab le d, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routi ne . EXF2 must be cle ared by software. EXF2 does not cau se an interrupt in up/down coun ter
mode (DCEN = 1).

Receive clock enable. When set, causes the se ria l po rt to use Timer 2 ov erf lo w p ul se s fo r its rece ive cl oc k in
serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on

TR2 Start/Stop control for Ti me r 2. TR2 = 1 sta rts the timer.

T2

C/

RL2 Capture/Reloa d se le ct . CP/RL2 = 1 causes captures to occu r on ne ga ti ve transitions at T2EX if EXEN2 = 1.

CP/

Data Memory

The AT89C52 implements 256 bytes of on-chip RAM. The
upper 128 bytes occupy a parallel address space to the
Special Function Registers. That means the upper 128
bytes have the same addresses as the SFR space but ar e
physically separate from SFR space.

When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct ad­dressing access SFR space.

Transmit clock enable. When set , causes the se rial port to us e Timer 2 overf low pulses f or its transmi t clock
in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

T2EX if Timer 2 is not being used to cl ock th e se ria l po rt. EXEN2 = 0 cause s Ti mer 2 to ig no re even ts at
T2EX.

Timer or counter select for Timer 2. C/
edge triggered).

CP/RL2 = 0 causes automatic relo ad s to occ ur whe n Timer 2 overflows or negat iv e transitions occur at
T2EX when EXEN2 = 1. When eithe r RCLK or T CLK = 1, thi s bi t is ignored and the timer is forced to
auto-reload on Timer 2 overf lo w.

T2 = 0 for timer function. C/T2 = 1 for external event counter (falling

For example, the f ollowing direct addressing instruction
accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data
Instructions that use indirect addressing access the upper

128 bytes of RAM. For example, the following indirect ad­dressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose ad­dress is 0A0H).

MOV @R0, #data
Note that stack operations are examples of indirect ad-

dressing, so the upper 128 bytes of data RAM are avail­able as stack space.

5

Timer 0 and 1

(continued)

Timer 0 and Timer 1 in the AT89C52 operate the same
way as Timer 0 and Timer 1 in the AT89C51.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as
either a timer or an event counter. The type of operation is
selected by bit C/

2). Timer 2 has three operating modes: capture, auto-re­load (up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table

3.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the

Timer function, the TL2 register is incremented every ma­chine cycle. Since a machine cycle consists of 12 oscilla­tor periods, the count rate is 1/12 of the oscillator fre­quency.

In the Counter function, the register is incremented in re­sponse to a l-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples

Table 3. Timer 2 Operating Modes

RCLK + TCLK CP/RL2 TR2 MODE
0 0 1 16-Bit Auto-Reload
0 1 1 16-Bit Capture
1 X 1 Bau d Rate Generator
X X 0 (Off)

T2 in the SFR T2CON (shown in Table

show a high in one cycle and a low in the next cy cle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in
which the transition was detected. Since two machine cy­cles (24 oscillator periods) are required to recognize a 1­to-0 transition, the maximum count rate is 1/24 of the os­cillator frequency. To ensure that a given level is sampled
at least once before it changes, the level should be held
for at least one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 performs the same operation, but a
l-to-0 transition at external input T2EX also cause s the
current value in TH2 and TL2 to be captured into RCAP2H
and RCAP2L, respectively. In addition, the transition at
T2EX causes bit EXF2 in T2CON to be set. T he E XF2 bit,
like TF2, can generate an interrupt. The capture mode is
illustrated in Figure 1.

Auto-Reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located
in the SFR T2MOD (see Table 4). Upon reset, the DCEN
bit is set to 0 so that timer 2 will default to count up. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.

Figure 2 shows Timer 2 automatically counting up when
DCEN = 0. In this mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The

Figure 1. Timer 2 in Capture Mode

OSC

T2 PIN

T2EX PIN

÷12

C/T2 = 0

C/T2 = 1

TRANSITION

DETECTOR

6 AT89C52

EXEN2

CONTROL

TR2

CAPTURE

CONTROL

TH2 TL2

RCAP2LRCAP2H

EXF2

TH2

OVERFLOW

TIMER 2

INTERRUPT

Auto-Reload (Up or Down Counter) ( Continued)

overflow also causes the timer registers to be reloaded
with the 16-bit value in RCAP2H and RCAP2L. The values
in RCAP2H and RCAP2L are preset by software. If
EXEN2 = 1, a 16-bit reload can be triggered either by an
overflow or by a l-to-0 transition at external input T2EX.
This transition also sets the EXF2 bit. Both the TF2 and
EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down,
as shown in Figure 3. In this mode, the T2EX pin controls
the direction of the count. A logic 1 at T2EX makes Timer
2 count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16-bit value in

Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)

AT89C52

RCAP2H and RCAP2L to be reloaded into the timer regis­ters, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit
and causes 0FFFFH to be reloaded into the timer regis­ters.

The EXF2 bit toggles whenever Timer 2 overflows or un­derflows and can be used as a 17th bit of resolution. In this
operating mode, EXF2 does not flag an interrupt.

OSC

T2 PIN

T2EX PIN

÷12

C/T2 = 0

C/T2 = 1

TRANSITION

DETECTOR

EXEN2

Table 4. T2MOD—Timer 2 Mode Control Register

CONTROL

TR2

RELOAD

CONTROL

TH2 TL2

RCAP2LRCAP2H

OVERFLOW

TIMER 2

INTERRUPT

TF2

EXF2

T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable

——————T2OEDCEN

Bit76543210

Symbol Function

— Not implemented, reserved for future use.
T2OE Timer 2 Output Enable bit.
DCEN When set, this bit allows Timer 2 to be config ure d as an up/d own cou nt er.

7