ATMEL AT89C51RE2 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• 80C52 Compatible

– 8051 Instruction Compatible – Six 8-bit I/O Ports (64 pins or 68 Pins Versions) – Four 8-bit I/O Ports (44 Pins Version) – Three 16-bit Timer/Counters – 256 bytes Scratch Pad RAM – 11 Interrupt Sources With 4 Priority Levels

• ISP (In-System Programming) Using Standard V

• Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply

• Boot ROM Contains Serial Loader for In-System Programming

• High-speed Architecture

– In Standard Mode:

40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)

– In X2 Mode (6 Clocks/Machine Cycle)

20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution) 30 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)

• 128K bytes On-chip Flash Program/Data Memory

– 128 bytes Page Write with auto-erase – 100k Write Cycles

• On-chip 8192 bytes Expanded RAM (XRAM)

– Software Selectable Size (0, 256, 512, 768, 1024, 1792, 2048, 4096, 8192 bytes)

• Dual Data Pointer

• Extended stack pointer to 512 bytes

• Variable Length MOVX for Slow RAM/Peripherals

• Improved X2 Mode with Independant Selection for CPU and Each Peripheral

• Keyboard Interrupt Interface on Port 1

• SPI Interface (Master/Slave Mode)

• 8-bit Clock Prescaler

• Programmable Counter Array with:

– High Speed Output – Compare/Capture – Pulse Width Modulator – Watchdog Timer Capabilities

• Asynchronous Port Reset

• Two Full Duplex Enhanced UART with Dedicated Internal Baud Rate Generator

• Low EMI (inhibit ALE)

• Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag

• Power Control Modes: Idle Mode, Power-down Mode

• Power Supply: 2.7V to 5.5V

• Temperature Ranges: Industrial (-40 to +85°C)

• Packages: PLCC44, VQFP44

Power Supply

8-bit Flash Microcontroller

AT89C51RE2

Description

AT89C51RE2 is a high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit microcontroller. It contains a 128 Kbytes Flash memory block for program.

The 128 Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin.

The AT89C51RE2 retains all features of the Atmel 80C52 with 256 bytes of internal RAM, a 10source 4-level interrupt controller and three timer/counters.

In addition, the AT89C51RE2 has a Programmable Counter Array, an XRAM of 8192 bytes, a Hardware Watchdog Timer, SPI and Keyboard, two serial channels that facilitates multiprocessor communication (EUART), a speed improvement mechanism (X2 mode) and an extended stack mode that allows the stack to be extended in the lower 256 bytes of XRAM.

The fully static design of the AT89C51RE2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.

The AT89C51RE2 has 2 software-selectable modes of reduced activity and 8-bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.

The added features of the AT89C51RE2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers.

Table 1. Memory Size and I/O pins

AT89C51RE2 Flash (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O

PLCC44

VQFP44

128K 8192 8192 + 256 34

7663C–8051–05/08

Block Diagram

Timer 0

INT

RAM

256x8

RxD_0

TxD_0

PSEN

ALE/

XTALA2

XTALA1

EUART

CPU

Timer 1

INT1

Ctrl

INT0

(2)

C51

CORE

(2) (2) (2) (2)

Port 0P0Port 1

Port 2

Port 3

XRAM

8192 x 8

IB-bus

PCA

RESET

PROG

Watch

Dog

PCA

ECI

Vss

VCC

(2)(2)

(1)

(1): Alternate function of Port 1

(2): Alternate function of Port 3

(1)

Timer2

T2EX

(1) (1)

Flash

128Kx8

Keyboard

(1)

Keyboard

MISO

MOSI

SCK

(3): Alternate function of Port 6

(3)

Port4

(1)

BOOT

4K x8

ROM

Regulator

POR / PFD

Port 5

Parallel I/O Ports &

External Bus

SPI

POR

PFD

XTALB2

XTALB1(1)

EUART_1

RxD_1

TxD_1

Figure 1. Block Diagram

AT89C51RE2

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AT89C51RE2

Pin Configurations

43 42 41 40 3944

38 37 36 35 34

P1.4/CEX1

P1.0/T2/XTALB1

P1.1/T2EX/SS

P1.3/CEX0

P1.2/ECI

Rx_OCD

VCC

P0.0/AD0

P0.2/AD2

P0.3/AD3

P0.1/AD1

P0.4/AD4

P0.6/AD6

P0.5/AD5

P0.7/AD7

ALE

PSEN

P6.1/TxD_1

P2.7/A15

P2.5/A13

P2.6/A14

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7/CEX4/MOSI

RST

P3.0/RxD_0

P6.0/RxD_1

P3.1/TxD_0

P3.2/INT0

P3.3/INT1

P3.4/T0 P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

VSS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

Tx_OCD

12 13 17161514 201918 21 22

33 32

26 25

3 4

7 8

VQFP44

PLCC44

AT89C51RE2

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7/CEx4/MOSI

RST

P3.0/RxD_0

P6.0/RxD_1

P3.1/TxD_0

P3.2/INT0

P3.3/INT1

P3.4/T0 P3.5/T1

7 8

14 15

P1.4/CEX1

P1.3/CEX0

5 4 3 2 1 6

P1.0/T2

P1.1/T2EX/SS

P1.2/ECI

Rx_OCD

VCC

P0.0/AD0

44 43 42 41 40

18 19 23222120 262524 27 28

VSS

XTAL2

P3.7/RD

P3.6/WR

XTAL1

P2.0/A8

P2.1/A9

Tx_OCD

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

P6.1/TxD_1

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.2/A10

P2.3/A11

P2.4/A12

7663C–8051–05/08

Table 2. Pin Description

Pin Number

AT89C51RE2

Mnemonic

Vss1 39 I Optional Ground: Contact the Sales Office for ground connection.

P0.0-P0.7 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them

P1.0-P1.7 2-9 40-44

22 16 I Ground: 0V reference

44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down operation

1-3

2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout

3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control

4 42 I ECI (P1.2): External Clock for the PCA

5 43 I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0

Type Name and FunctionLCC VQFP 1.4

float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes.

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification.

Alternate functions for TSC8x54/58 Port 1 include:

6 44 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1

7 1 I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2

8 2 I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3

9 3 I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4

P2.0-P2.7 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

P3.0-P3.7 11,

13-19

11 5 I RXD_0 (P3.0): Serial input port

13 7 O TXD_0 (P3.1): Serial output port

7-13

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification:

P2.0 to P2.5 for RB devices

P2.0 to P2.6 for RC devices

P2.0 to P2.7 for RD devices.

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below.

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14 8 I INT0 (P3.2): External interrupt 0

AT89C51RE2

Pin Number

Mnemonic

15 9 I INT1 (P3.3): External interrupt 1

16 10 I T0 (P3.4): Timer 0 external input

17 11 I T1 (P3.5): Timer 1 external input

18 12 O WR (P3.6): External data memory write strobe

19 13 O RD (P3.7): External data memory read strobe

P6.0-P6.1

Reset 10 4 I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

ALE/PROG 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

12,34 6, 28

12 6 I RXD_1 (P6.0): Serial input port

34 28 O TXD_1 (P6.1): Serial output port

Type Name and FunctionLCC VQFP 1.4

Port 6: Port 6 is an 2-bit bidirectional I/O port with internal pull-ups. Port 6 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 6 pins that are externally pulled low will source current because of the internal pull-ups. Port 6 also serves some special features as listed below.

device. An internal diffused resistor to V capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset.

address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches.

permits a power-on reset using only an external

PSEN 32 26 O Program Store ENable: The read strobe to external program memory. When executing

EA 35 29 I External Access Enable: EA must be externally held low to enable the device to fetch code

XTAL1 21 15 I

XTAL2 20 14 O Crystal 2: Output from the inverting oscillator amplifier

Tx_OCD 23 17 O Tx_OCD: On chip debug Serial output port

Rx_OCD 1 39 I Rx_OCD: On chip debug Serial input port

code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.

from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset.

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

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AT89C51RE2

SFR Mapping

The Special Function Registers (SFRs) of the AT89C51RE2 fall into the following categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP

• I/O port registers: P0, P1, P2, P3, P4, P5, P6

• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

• Serial I/O port registers: SADDR_0, SADEN_0, SBUF_0, SCON_0, SADDR_1, SADEN_1, SBUF_1, SCON_1,

• PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4)

• Power and clock control registers: PCON, CKAL, CKCON0_1

• Hardware Watchdog Timer registers: WDTRST, WDTPRG

• Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1

• Keyboard Interface registers: KBE, KBF, KBLS

• SPI registers: SPCON, SPSTR, SPDAT

• BRG (Baud Rate Generator) registers: BRL_0, BRL_1, BDRCON_0, BDRCON_1

• Memory register: FCON, FSTA

• Clock Prescaler register: CKRL

• Others: AUXR, AUXR1, CKCON0, CKCON1, BMSEL

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AT89C51RE2

Table 3. C51 Core SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

ACC E0h Accumulator

B F0h B Register

PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P

SP 81h Stack Pointer

DPL 82h Data Pointer Low byte

DPH 83h Data Pointer High byte

Table 4. System Management SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

PCON 87h Power Control

AUXR 8Eh Auxiliary Register 0 - - M0 XRS2 XRS1 XRS0

AUXR1 A2h Auxiliary Register 1 EES SP9 U2 - GF2 0 - DPS

CKRL 97h Clock Reload Register - - - - - - - -

BMSEL 92h Bank Memory Select MBO2 MBO1 MBO0 - FBS2 FBS1 FBS0

CKCON0 8Fh Clock Control Register 0 - WDX2 PCAX2 SIX2_0 T2X2 T1X2 T0X2 X2

CKCON1 AFh Clock Control Register 1 - - - - - - SIX2_1 SPIX2

SMOD1_0 SMOD0_0

- POF GF1 GF0 PD IDL

EXTRA

Table 5. Interrupt SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0

IEN1 B1h Interrupt Enable Control 1 - - - - ES_1 ESPI ETWI EKBD

IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H

IPL0 B8h Interrupt Priority Control Low 0 - PPCL PT2L PSL PT1L PX1L PT0L PX0L

IPH1 B3h Interrupt Priority Control High 1 - - - - PSH_1 SPIH IE2CH KBDH

IPL1 B2h Interrupt Priority Control Low 1 - - - - PSL_1 SPIL IE2CL KBDL

Table 6. Port SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

P0 80h 8-bit Port 0

P1 90h 8-bit Port 1

P2 A0h 8-bit Port 2

P3 B0h 8-bit Port 3

P4 C0h 8-bit Port 4

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AT89C51RE2

Table 6. Port SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

P5 E8h 8-bit Port 5

P6 F8h 2-bit Port 5 - - - - - -

Table 7. Flash and EEPROM Data Memory SFR

Mnemonic Add Name 7 6 5 4 3 2 1 0

FCON D1h Flash Controller Control FPL3 FPL2 FPL1 FPL0 FPS FMOD2 FMOD1 FMOD0

FSTA D3h Flash Controller Status FMR FSE FLOAD FBUSY

Table 8. Timer SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

TCON 88h Timer/Counter 0 and 1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

TL0 8Ah Timer/Counter 0 Low Byte

TH0 8Ch Timer/Counter 0 High Byte

TL1 8Bh Timer/Counter 1 Low Byte

TH1 8Dh Timer/Counter 1 High Byte

WDTRST A6h WatchDog Timer Reset

WDTPRG A7h WatchDog Timer Program - - - - - WTO2 WTO1 WTO0

T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

T2MOD C9h Timer/Counter 2 Mode - - - - - - T2OE DCEN

RCAP2H CBh

RCAP2L CAh

TH2 CDh Timer/Counter 2 High Byte

TL2 CCh Timer/Counter 2 Low Byte

Timer/Counter 2 Reload/Capture High byte

Timer/Counter 2 Reload/Capture Low byte

Table 9. PCA SFRs

Mnemo

-nic Add Name 7 6 5 4 3 2 1 0

CCON D8h PCA Timer/Counter Control CF CR - CCF4 CCF3 CCF2 CCF1 CCF0

CMOD D9h PCA Timer/Counter Mode CIDL WDTE - - - CPS1 CPS0 ECF

CL E9h PCA Timer/Counter Low byte

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AT89C51RE2

Table 9. PCA SFRs (Continued)

Mnemo

-nic Add Name 7 6 5 4 3 2 1 0

CH F9h PCA Timer/Counter High byte

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

DAh

PCA Timer/Counter Mode 0

DBh

PCA Timer/Counter Mode 1

DCh

PCA Timer/Counter Mode 2

DDh

PCA Timer/Counter Mode 3

DEh

PCA Timer/Counter Mode 4

FAh

PCA Compare Capture Module 0 H

FBh

PCA Compare Capture Module 1 H

FCh

PCA Compare Capture Module 2 H

FDh

PCA Compare Capture Module 3 H

FEh

PCA Compare Capture Module 4 H

EAh

PCA Compare Capture Module 0 L

EBh

PCA Compare Capture Module 1 L

ECh

PCA Compare Capture Module 2 L

EDh

PCA Compare Capture Module 3 L

EEh

PCA Compare Capture Module 4 L

CCAP0H7

CCAP1H7

CCAP2H7

CCAP3H7

CCAP4H7

CCAP0L7

CCAP1L7

CCAP2L7

CCAP3L7

CCAP4L7

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CCAP0H6

CCAP1H6

CCAP2H6

CCAP3H6

CCAP4H6

CCAP0L6

CCAP1L6

CCAP2L6

CCAP3L6

CCAP4L6

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CCAP0H5

CCAP1H5

CCAP2H5

CCAP3H5

CCAP4H5

CCAP0L5

CCAP1L5

CCAP2L5

CCAP3L5

CCAP4L5

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

CCAP0H4

CCAP1H4

CCAP2H4

CCAP3H4

CCAP4H4

CCAP0L4

CCAP1L4

CCAP2L4

CCAP3L4

CCAP4L4

MAT0

MAT1

MAT2

MAT3

MAT4

CCAP0H3

CCAP1H3

CCAP2H3

CCAP3H3

CCAP4H3

CCAP0L3

CCAP1L3

CCAP2L3

CCAP3L3

CCAP4L3

TOG0

TOG1

TOG2

TOG3

TOG4

CCAP0H2

CCAP1H2

CCAP2H2

CCAP3H2

CCAP4H2

CCAP0L2

CCAP1L2

CCAP2L2

CCAP3L2

CCAP4L2

PWM0

PWM1

PWM2

PWM3

PWM4

CCAP0H1

CCAP1H1

CCAP2H1

CCAP3H1

CCAP4H1

CCAP0L1

CCAP1L1

CCAP2L1

CCAP3L1

CCAP4L1

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

CCAP0H0

CCAP1H0

CCAP2H0

CCAP3H0

CCAP4H0

CCAP0L0

CCAP1L0

CCAP2L0

CCAP3L0

CCAP4L0

Table 10. Serial I/O Port SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SCON_0 98h Serial Control 0 FE/SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0

SBUF_0 99h Serial Data Buffer 0

SADEN_0 B9h Slave Address Mask 0

SADDR_0 A9h Slave Address 0

BDRCON_0 9Bh Baud Rate Control 0 BRR_0 TBCK_0 RBCK_0 SPD_0 SRC_0

BRL_0 9Ah Baud Rate Reload 0

SCON_1 C0h Serial Control 1 FE_1/SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1

SBUF_1 C1h Serial Data Buffer 1

SADEN_1 BAh Slave Address Mask 1

SADDR_1 AAh Slave Address 1

BDRCON_1 BCh Baud Rate Control 1 SMOD1_1 SMOD0_1 BRR_1 TBCK_1 RBCK_1 SPD_1 SRC_1

BRL_1 BBh Baud Rate Reload 1

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AT89C51RE2

Table 11. SPI Controller SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPSCR C4h SPI Status SPIF OVR MODF SPTE UARTM SPTEIE MODFIE

SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0

Table 12. Keyboard Interface SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0

KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0

KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0

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AT89C51RE2

Table 13. SFR Mapping

addressable Non Bit addressable

Table below shows all SFRs with their address and their reset value.

Bit

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

C0h

F8h

F0h

E8h

E0h

D8h

D0h

C8h

U2(AUXR1.5)

B8h

XXXX XX11CH0000 0000

0000 0000

1111 1111CL0000 0000

ACC

0000 0000

CCON

00X0 0000

PSW

0000 0000

T2CON

0000 0000

SCON_1

0000 0000

1111 1111

IPL0

X000 000

CMOD

00XX X000

FCON

0000 0000

T2MOD

XXXX XX00

SBUF_1

0000 0000

SADEN_0

0000 0000

CCAP0H

XXXX XXXX

CCAP0L

XXXX XXXX

CCAPM0

X000 0000

RCAP2L

0000 0000

SADEN1

0000 0000

CCAP1H

XXXX XXXX

CCAP1L

XXXX XXXX

CCAPM1

X000 0000

FSTA

xxxx x000

RCAP2H

0000 0000

SPCON

0001 0100

BRL_1

0000 0000

CCAP2H

XXXX XXXX

CCAP2L

XXXX XXXX

CCAPM2

X000 0000

TL2

0000 0000

SPSCR

0000 0000

BDRCON_1

XXX0 0000

CCAP3H

XXXX XXXX

CCAP3L

XXXX XXXX

CCAPM3

X000 0000

TH2

0000 0000

SPDAT

XXXX XXXX

CCAP4H

XXXX XXXX

CCAP4L

XXXX XXXX

CCAPM4

X000 0000

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B0h

A8h

A0h

98h

90h

88h

80h

1111 1111

IEN0

0000 0000

1111 1111

SCON_0

0000 0000

1111 1111

TCON

0000 0000

1111 1111

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

IEN1

XXXX 0000

SADDR_0

0000 0000

SBUF_0

XXXX XXXX

TMOD

0000 0000

0000 0111

IPL1

XXXX 0000

SADDR_1

0000 0000

AUXR1

000x 11x0

BRL_0

0000 0000

BMSEL

0000 0YYY

TL0

0000 0000

DPL

0000 0000

IPH1

XXXX 0111

BDRCON_0

XXX0 0000

TL1

0000 0000

DPH

0000 0000

KBLS

0000 0000

TH0

0000 0000

KBE

0000 0000

TH1

0000 0000

WDTRST

XXXX XXXX

KBF

0000 0000

AUXR

XX00 1000

Reserved

IPH0

X000 0000

CKCON1

XXXX XX00

WDTPRG

XXXX X000

CKRL

1111 1111

CKCON0

0000 0000

PCON

00X1 0000

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B7h

AFh

A7h

9Fh

97h

8Fh

87h

AT89C51RE2

XTAL1

CKCON0

8 bit Prescaler

OSC

FXTAL

XTAL1:2

CLK CPU

CLK PERIPH

CKRL

Enhanced Features

X2 Feature

In comparison to the original 80C52, the AT89C51RE2 implements some new features, which are

• X2 option

• Dual Data Pointer

• Extended RAM

• Extended stack

• Programmable Counter Array (PCA)

• Hardware Watchdog

• SPI interface

• 4-level interrupt priority system

• power-off flag

• ONCE mode

• ALE disabling

• Enhanced features on the UART and the timer 2

The AT89C51RE2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages:

• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

• Save power consumption while keeping same CPU power (oscillator power saving).

• Save power consumption by dividing dynamically the operating frequency by 2 in operating and idle modes.

• Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software.

Description The clock for the whole circuit and peripherals is first divided by two before being used by the

CPU core and the peripherals.

This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.

Figure 2 shows the clock generation block diagram. X2 bit is validated on the rising edge of the XTAL1÷2 to avoid glitches when switching from X2 to STD mode. Figure 3 shows the switching mode waveforms.

Figure 2. Clock Generation Diagram

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AT89C51RE2

Figure 3. Mode Switching Waveforms

XTAL1:2

XTAL1

CPU clock

X2 bit

X2 ModeSTD Mode STD Mode

OSC

The X2 bit in the CKCON0 register (see Table 14) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of the Fuse Configuration Byte (FCB). By default, Standard mode is active. Setting the X2 bit activates the X2 feature (X2 mode).

The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (See Table 14.) and SPIX2 bit in the CKCON1 register (see Table 15) allows a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode.

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AT89C51RE2

Table 14. CKCON0 Register

CKCON0 - Clock Control Register (8Fh)

7 6 5 4 3 2 1 0

- WDX2 PCAX2 SIX2_0 T2X2 T1X2 T0X2 X2

Bit

Number

7 - Reserved

6 WDX2

5 PCAX2

4 SIX2_0

3 T2X2

Bit

Mnemonic Description

Watchdog Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART0 Clock (Mode 0 and 2)

Timer2 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

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Timer1 Clock

2 T1X2

1 T0X2

0 X2

Timer0 Clock

CPU Clock

Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is cleared.

Reset Value = X000 000’HSB. X2’b (See “Fuse Configuration Byte: FCB”) Not bit addressable

AT89C51RE2

Table 15. CKCON1 Register

CKCON1 - Clock Control Register (AFh)

7 6 5 4 3 2 1 0

- - - - - - SIX2_1 SPIX2

Bit

Number

7 - Reserved

6 - Reserved

5 - Reserved

4 - Reserved

3 - Reserved

2 - Reserved

1 SIX2_1

0 SPIX2

Bit

Mnemonic Description

Enhanced UART1 Clock (Mode 0 and 2)

SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Reset Value = XXXX XX00b Not bit addressable

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AT89C51RE2

External Data Memory

AUXR1(A2H)

DPS

DPH(83H) DPL(82H)

DPTR0

DPTR1

Dual Data Pointer Register DPTR

Figure 4. Use of Dual Pointer

The additional data pointer can be used to speed up code execution and reduce code size.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 16) that allows the program code to switch between them (Refer to Figure 4).

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AT89C51RE2

Table 16. AUXR1 register

AUXR1- Auxiliary Register 1(0A2h)

7 6 5 4 3 2 1 0

EES SP9 U2 - GF2 0 - DPS

Bit

Number

7 EES

6 SP9

5 U2

4 -

3 GF2 This bit is a general purpose user flag. *

2 0 Always cleared.

1 -

0 DPS

Bit

Mnemonic Description

Enable Extended Stack

This bit allows the selection of the stack extended mode.

Set to enable the extended stack

Clear to disable the extended stack (default value)

Stack Pointer 9th Bit

This bit has no effect when the EES bit is cleared.

Set when the stack pointer belongs to the XRAM memory space

Cleared when the stack pointer belongs to the 256bytes of internal RAM.

P4 bit addressable

Clear to map SCON_1 register at C0h sfr address

Set to map P4 port register at C0h address.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Cleared to select DPTR0. Set to select DPTR1.

Reset Value: XX0X XX0X0b

Not bit addressable

Note: *Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

ASSEMBLY LANGUAGE

; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address

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AT89C51RE2

0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

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AT89C51RE2

Memory Architecture

128K bytes

Flash memory

FM0

Hardware Security (1 byte)

Column Latches (128 bytes)

user space

4K bytes

ROM

1FFFFh

00000h

RM0

Fuse Configuration Byte(1 byte)

FCB

HSB

256 bytes

IRAM

XRAM

8K bytes

AT89C51RE2 features several on-chip memories:

• Flash memory: containing 128 Kbytes of program memory (user space) organized into 128 bytes pages.

• Boot ROM: 4K bytes for boot loader.

• 8K bytes internal XRAM

Physical memory organisation

Figure 5. Physical memory organisation

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AT89C51RE2

XRAM

Upper

128 bytes

Internal

Ram

Lower

128 bytes

Internal

Ram

Special Function Register

80h 80h

0FFh to 1FFFh

0FFh

External

Data

Memory

0000

00FFh up to 1FFFh

0FFFFh

indirect accesses

direct accesses

direct or indirect

accesses

7Fh

Expanded RAM (XRAM)

The AT89C51RE2 provides additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage.

AT89C51RE2 devices have expanded RAM in external data space configurable up to 8192bytes (see Table 17.).

The AT89C51RE2 has internal data memory that is mapped into four separate segments.

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable only.

4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register (see Table 17).

The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space.

Figure 6. Internal and External Data Memory Address

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When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.

• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2).

• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h).

• The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table 17. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM.

AT89C51RE2

• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the use of DPTR.

• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may be located in the 256 lower bytes of the XRAM by activating the extended stack mode (see EES bit in AUXR1).

The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals.

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AT89C51RE2

Registers

Table 17. AUXR Register

AUXR - Auxiliary Register (8Eh)

7 6 5 4 3 2 1 0

- - M0 XRS2 XRS1 XRS0 EXTRAM AO

Bit

Number

7 -

6 -

5 M0

4-2 XRS2:0

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Pulse length

Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods (default).

Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock periods.

XRAM Size

XRS2 XRS1 XRS0 XRAM size 0 0 0 256 bytes

0 0 1 512 bytes

0 1 0 768 bytes

0 1 1 1024 bytes

1 0 0 1792 bytes

1 0 1 2048 bytes

1 1 0 4096 bytes

1 1 1 8192 bytes (default)

EXTRAM bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

1 EXTRAM

0 AO

Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected.

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used.

Reset Value = XX01 1100b Not bit addressable

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AT89C51RE2

Extended Stack

00h

FFh

0000h

FFFFh

256 bytes

IRAM

00h

FFh

Logical MCU Address

256 SP values rollover within 256B of IRAM

00h

FFh

0000h

256 bytes

IRAM

00h

FFh

512 SP Values rollover in:

00FFh

00h

FFh

256B of IRAM + lower 256B of XRAM

XRAM

SP Value

FFFFh

Logical MCU Address

XRAM

SP Value

Standard C51 Stack mode EES = 0 Extended Stack mode Stack EES = 1

SP9=1

SP9=0

The lowest bytes of the XRAM may be used to allow extension of the stack pointer.

The extended stack allows to extend the standard C51 stack over the 256 bytes of internal RAM. When the extended stack mode is activated (EES bit in AUXR1), the stack pointer (SP) can grow in the lower 256 bytes of the XRAM area.

The stack extension consists in a 9 bits stack pointer where the ninth bit is located in SP9 (bit 6 of AUXR1). The SP9 then indicates if the stack pointer belongs to the internal RAM (SP9 cleared) or to the XRAM memory (SP9 set).

To ensure backward compatibility with standard C51 architecture, the extended mode is disable at chip reset.

Figure 7. Stack modes

Figure 8. AUXR1 register

AUXR1- Auxiliary Register 1(0A2h)

7 6 5 4 3 2 1 0

EES SP9 U2 - GF2 0 - DPS

Bit

Number

7 EES

Bit

Mnemonic Description

Enable Extended Stack

Set to enable the extended stack

Clear to disable the extended stack (default value)

This bit allows the selection of the stack extended mode.

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AT89C51RE2

Bit

Number

6 SP9

5 U2

4 -

3 GF2 This bit is a general purpose user flag. *

2 0 Always cleared.

1 -

0 DPS

Bit

Mnemonic Description

Stack Pointer 9th Bit

This bit has no effect when the EES bit is cleared.

Set when the stack pointer belongs to the XRAM memory space

Cleared when the stack pointer belongs to the 256bytes of internal RAM. Set and cleared by hardware. Can only be read.

P4 bit addressable

Clear to map SCON_1 register at C0h sfr address

Set to map P4 port register at C0h address.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Cleared to select DPTR0. Set to select DPTR1.

Reset Value = 00XX 00X0b Not bit addressable

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AT89C51RE2

Flash Memory

General Description

Features

Flash memory organization

The Flash memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 128K bytes of program memory organized in 1024 pages of 128 bytes. This memory is both parallel and serial In-System Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash.

The programming does not require external high programming voltage. The necessary high programming voltage is generated on-chip using the standard VCC pins of the microcontroller.

• Flash internal program memory.

• Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space. This configuration provides flexibility to the user.

• Default loader in Boot Flash allows programming via the serial port without the need of a user provided loader.

• Up to 64K byte external program memory if the internal program memory is disabled (EA =

0).

• Programming and erase voltage with standard 5V or 3V VCC supply.

AT89C51RE2 features several on-chip memories:

• Flash memory FM0: containing 128 Kbytes of program memory (user space) organized into 128 bytes pages.

• Boot ROM RM0: 4K bytes for boot loader.

• 8K bytes internal XRAM

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AT89C51RE2

128K bytes

Flash memory

FM0

Hardware Security (1 byte)

Column Latches (128 bytes)

user space

Extra Row FM0 (128 bytes)

4K bytes

ROM

1FFFFh

00000h

RM0

Fuse Configuration Byte(1 byte)

FCB

HSB

Physical memory organisation

Figure Physical memory organisation

On-Chip Flash memory

The AT89C51RE2 implements up to 128K bytes of on-chip program/code memory. Figure 1 and Figure 2. shows the partitioning of internal and external program/code memory spaces according to EA value.

The memory partitioning of the 8051 core microcontroller is typical a Harvard architecture where program and data areas are held in separate memory areas. The program and data memory areas use the same physical address range from 0000H-FFFFH and a 8 bit instruction code/data format.

To access more than 64kBytes of code memory, without modifications of the MCU core, and development tools, the bank switching method is used.

The internal program memory is expanded to 128kByte in the ´Expanded Configuration’, the data memory remains in the ´Normal Configuration´. The program memory is split into four 32 kByte banks (named Bank 0-2). The MCU core still addresses up to 64kBytes where the upper 32Kbytes can be selected between 3 32K bytes bank of on-chip flash memory. The lower 32K bank is used as common area for interrupt subroutines, bank switching and functions calls between banks.

The AT89C51RE2 also implements an extra upper 32K bank (Bank3) that allows external code execution.

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AT89C51RE2

Figure 1. Program/Code Memory Organization EA=1

0000h

7FFFh

8000h

FFFFh

8000h

FFFFh

8000h

FFFFh

8000h

FFFFh

32K

Common

upper 32K

Bank 0

upper 32K

Bank 1

upper 32K

Bank 2

upper 32K

Bank 3 Optional External Memory

On-Chip flash code memory

External code memory

00000h

07FFFh

08000h

0FFFFh

10000h

17FFFh

18000h

1FFFFh

Logical MCU Address

Physical Flash Address

Logical MCU Address

Physical Flash Address

Logical MCU Address

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AT89C51RE2

0000h

FFFFh

64K

Common

On-Chip flash code memory

External code memory

00000h

0FFFFh

Logical MCU Address

External Physical Memory Address

When EA=0, the on-chip flash memory is disabled and the MCU core can address only up to 64kByte of external memory (none of the on-chip flash memory FM0 banks or RM0 can be mapped and executed).

Figure 2. Program/Code Memory Organization EA=0

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AT89C51RE2

On-Chip ROM

0000h

7FFFh

8000h

FFFFh

8000h

FFFFh

8000h

FFFFh

8000h

FFFFh

Bank 0

On-Chip flash code memory

External code memory

00000h

07FFFh

08000h

0FFFFh

10000h

17FFFh

18000h

1FFFFh

Logical MCU Address

Physical Address

Logical MCU Address

Physical Address

Logical MCU Address

Bank 1 Bank 2 Bank 3

Logical MCU Address

ROM Address

Bank BOOT

(Ext)

0000h

On-Chip ROM memory (RM0)

1000h

0000h

1000h

bootloader

The On-chip ROM bootloader (RM0) is enable only for ISP operations after reset (bootloader execution). The RM0 memory area belongs to a logical addressable memory space called ‘Bank Boot’.

RM0 cannot be activated from the On-chip flash memory. It means that it is not possible activate the Bank Boot area by software (it prevents any RM0 execution and flash corruption from the user application).

RM0 logical area consists in an independent code execution memory area of 4K bytes starting at logical 0x0000 address (it allows the use of the interrupts in the bootloader execution).

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