ATMEL AT89C51RC User Manual

BDTIC www.bdtic.com/ATMEL

Features

• Compatible with MCS

• 32K Bytes of Reprogrammable Flash Memory

• Endurance: 1000 Write/Erase Cycles

• 4V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 512 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Eight Interrupt Sources

• Programmable Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Hardware Watchdog Timer

• Dual Data Pointer

• Power-off Flag

• Green (Pb/Halide-free) Packaging Option

®

-51 Products

8-bit
Microcontroller
with 32K Bytes
Flash

AT89C51RC

1. Description

The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontroller with
32K bytes of Flash programmable read-only memory and 512 bytes of RAM. The
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry-standard 80C51 and 80C52 instruction set and
pinout. The on-chip Flash allows the program memory to be user programmed by a
conventional nonvolatile memory programmer. A total of 512 bytes of internal RAM
are available in the AT89C51RC. The 256-byte expanded internal RAM is accessed
via MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The
other 256-byte RAM segment is accessed the same way as the Atmel AT89-series
and other 8052-compatible products. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51RC is a powerful microcomputer which pro­vides a highly-flexible and cost-effective solution to many embedded control
applications.

The AT89C51RC provides the following standard features: 32K bytes of Flash, 512
bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89C51RC is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port, and interrupt system to con­tinue functioning. The Power-down mode saves the RAM contents but freezes the
oscillator, disabling all other chip functions until the next external interrupt or hardware
reset.

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2. Pin Configurations

2.1 44A – 44-lead TQFP

2.2 44J – 44-lead PLCC

P1.5
P1.6
P1.7
RST

(RXD) P3.0

NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)NCVCC

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

1213141516171819202122

GND

GND

XTAL2

XTAL1

(RD) P3.7

(WR) P3.6

P0.0 (AD0)

(A8) P2.0

(A9) P2.1

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

(A10) P2.2

(A11) P2.3

(A12) P2.4

33
32
31
30
29
28
27
26
25
24
23

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

2.3 40P6 – 40-lead PDIP

P1.5
P1.6
P1.7
RST

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

P1.4

P1.3

P1.2

P1.1 (T2 EX)

65432
7
8
9
10
11
12

NC

13
14
15
16
17

1819202122232425262728

XTAL2

XTAL1

(RD) P3.7

(WR) P3.6

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST

XTAL2
XTAL1

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

(T2) P1.0

(T2EX) P1.1

(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(WR) P3.6

(RD) P3.7

P1.0 (T2)NCVCC

1

4443424140

NC

GND

(A8) P2.0

P0.0 (AD0)

P0.1 (AD1)

(A9) P2.1

(A10) P2.2

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P0.2 (AD2)

P0.3 (AD3)

39
38
37
36
35
34
33
32
31
30
29

(A11) P2.3

(A12) P2.4

VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

2

AT89C51RC

1920C–MICRO–03/05

3. Block Diagram

V

CC

GND

P0.0 - P0.7

PORT 0 DRIVERS

AT89C51RC

P2.0 - P2.7

PORT 2 DRIVERS

PSEN

ALE/PROG

EA / V

RST

RAM ADDR.

REGISTER

B

REGISTER

TIMING

AND

PP

CONTROL

ACC

INSTRUCTION

REGISTER

RAM

TMP2

PSW

ALU

PORT 0

LATCH

TMP1

PORT 2

LATCH

STACK

POINTER

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

FLASH

PROGRAM

ADDRESS

REGISTER

BUFFER

PC

INCREMENTER

PROGRAM
COUNTER

DUAL
DPTR

1920C–MICRO–03/05

OSC

WATCH

DOG

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

3

4. Pin Description

4.1 VCC

Supply voltage.

4.2 GND

Ground.

4.3 Port 0

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses
to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur­ing program verification. External pull-ups are required during program verification.

4.4 Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter­nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low
will source current (I

In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow­ing table.

) because of the internal pull-ups.

IL

4.5 Port 2

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2), clock-out

P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter­nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low
will source current (I

Port 2 emits the high-order address byte during fetches from external program memory and dur­ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash program­ming and verification.

) because of the internal pull-ups.

IL

4

AT89C51RC

1920C–MICRO–03/05

4.6 Port 3

AT89C51RC

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter­nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (I

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89C51RC, as shown in the
following table.

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0

) because of the pull-ups.

IL

(external interrupt 0)

4.7 RST

4.8 ALE/PROG

P3.3 INT1

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR

P3.7 RD

(external interrupt 1)

(external data memory write strobe)

(external data memory read strobe)

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO
bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit
DISRTO, the RESET HIGH out feature is enabled.

Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG

) during Flash

programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur­ing each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

4.9 PSEN

1920C–MICRO–03/05

Program Store Enable is the read strobe to external program memory.

When the AT89C51RC is executing code from external program memory, PSEN
twice each machine cycle, except that two PSEN

activations are skipped during each access to

external data memory.

is activated

5

4.10 EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA

should be strapped to VCC for internal program executions.

EA

will be internally latched on reset.

This pin also receives the 12-volt programming enable voltage (V

) during Flash programming.

PP

4.11 XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

4.12 XTAL2

Output from the inverting oscillator amplifier.

5. Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1.

Table 5-1. AT89C51RC SFR Map and Reset Values

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

B

00000000

ACC

00000000

0F7H

0E7H

0D0H

0C8H

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

PSW

00000000

T2CON

00000000

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111

T2MOD

XXXXXX00

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

RCAP2L

00000000

AUXR1

XXXXXXX0

TL0

00000000

DP0L

00000000

RCAP2H

00000000

TL1

00000000

DP0H

00000000

TL2

00000000

TH0

00000000

DP1L

00000000

TH2

00000000

TH1

00000000

DP1H

00000000

WDTRST

XXXXXXXX

AUXR

XXX00X00

PCON

0XXX0000

0D7H

0CFH

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

6

AT89C51RC

1920C–MICRO–03/05

AT89C51RC

Note that not all of the addresses are occupied, and unoccupied addresses may not be imple­mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.

Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 5-

2) and T2MOD (shown in Table 13-1 and Table 5-4) for Timer 2. The register pair (RCAP2H,

RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto­reload mode.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can
be set for each of the six interrupt sources in the IP register.

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,
two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H­83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should always initialize the DPS bit to the appropriate value before accessing the
respective Data Pointer Register.

Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF
is set to “1” during power up. It can be set and reset under software control and is not affected by
reset.

1920C–MICRO–03/05

7

Table 5-2. T2CON – Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B

Bit Addressable

Bit

Symbol Function

TF2

EXF2

RCLK

TCLK

EXEN2

TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.

C/T2

CP/RL2

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

76543210

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK
= 1 or TCLK = 1.

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).

Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1.
When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

CP/RL2

8

AT89C51RC

1920C–MICRO–03/05

AT89C51RC

Table 5-3. AUXR: Auxiliary Register

AUXR Address = 8EH Reset Value = XXX00X00B

Not Bit Addressable

– – – WDIDLE DISRTO – EXTRAM DISALE

Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DISALE Disable/Enable ALE

DISALE Operating Mode

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency

1 ALE is active only during a MOVX or MOVC instruction

EXTRAM Internal/External RAM access using MOVX @ Ri/@DPTR

EXTRAM Operating Mode

0 Internal ERAM (00H-FFH) access using MOVX @ Ri/@DPTR

1 External data memory access

DISRTO Disable/Enable Reset out

DISRTO Operating Mode

0 Reset pin is driven High after WDT times out

1 Reset pin is input only

WDIDLE Disable/Enable WDT in IDLE mode

WDIDLE Operating Mode

0 WDT continues to count in IDLE mode

1 WDT halts counting in IDLE mode

Table 5-4. AUXR1: Auxiliary Register 1

AUXR1 Address = A2H Reset Value = XXXXXXX0B

Not Bit Addressable

––– – – – –DPS

Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DPS Data Pointer Register Select

DPS

0 Selects DPTR Registers DP0L, DP0H

1 Selects DPTR Registers DP1L, DP1H

1920C–MICRO–03/05

9

6. Memory Organization

The MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.

7. Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory.

7.1 Data Memory

On the AT89C51RC, if EA
7FFFH are directed to internal memory and fetches to addresses 8000H through FFFFH are to
external memory.

The AT89C51RC has internal data memory that is mapped into four separate segments: the
lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes special function register (SFR) and
256 bytes expanded RAM (ERAM).

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly
addressable.

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly address­able only.

4. The 256-byte expanded RAM (ERAM, 00H-FFH) is indirectly accessed by MOVX
instructions, and with the EXTRAM bit cleared.

The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128
bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same
address space as the SFR. This means they have the same address, but are physically sepa­rate from the SFR space.

When an instruction accesses an internal location above address 7FH, the CPU knows whether
the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used
in the instruction. Instructions that use direct addressing access SFR space. For example:

is connected to VCC, program fetches to addresses 0000H through

10

MOV 0A0H, # data

accesses the SFR at location 0S0H (which is P2). Instructions that use indirect addressing
access the Upper 128 bytes of data RAM. For example:

MOV@R0, # data

where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data
RAM are available as stack space.

The 256 bytes of ERAM can be accessed by indirect addressing, with EXTRAM bit cleared and
MOVX instructions. This part of memory is physically located on-chip, logically occupying the
first 256 bytes of external data memory.

AT89C51RC

1920C–MICRO–03/05

AT89C51RC

With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in combina­tion with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not
affect ports P0, P2, P3.6 (WR

MOVX@R0, # data

where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory.
An access to external data memory locations higher than FFH (i.e. 0100H to FFFFH) will be per­formed with the MOVX DPTR instructions in the same way as in the standard 80C51, i.e., with
P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals (see Figure

7-1).

Figure 7-1. Internal and External Data Memory Address (with EXTRAM = 0)

FF

00

), and P3.7 (RD). For example, with EXTRAM = 0,

FFFF

0100
0000

ERAM
256 BYTES

FF

80

00

UPPER
128 BYTES
INTERNAL
RAM

LOWER
128 BYTES
INTERNAL
RAM

FF

SPECIAL
FUNCTION
REGISTER

80

EXTERNAL
DATA
MEMORY

With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be similar to the standard 80C51.
MOVX@Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins
can be used to output higher-order address bits. This is to provide the external paging capability.
MOVX@DPTR will generate a 16-bit address. Port 2 outputs the high-order 8 address bits (the
contents of DP0H), while Port 0 multiplexes the low-order 8 address bits (the contents of DP0L)
with data. MOVX@Ri and MOVX@DPTR will generate either read or write signals on P3.6 (WR
and P3.7 (RD

).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the ERAM.

8. Hardware Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 13-bit counter and the WatchDog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over­flows, it will drive an output RESET HIGH pulse at the RST pin.

)

1920C–MICRO–03/05

11