• Hardware Watchdog Timer (One-time enabled with Reset-Out)
• Power Control Modes:
– Idle Mode
– Power-down Mode
– Power-Off Flag
• Power Supply:
– 2.7 to 3.6 (3V Version)
– 2.7 to 5.5V (5V Version)
• Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)
• Packages: PLC44, VQFP44
Power Supply
cc
8-bit Flash
Microcontroller
with 2-wire
Interface
AT89C51IC2
Rev. 4301D–8051–02/08
1
DescriptionAT89C51IC2 is a high performance Flash version of the 80C51 8-bit microcontrollers. It
contains a 32K bytes Flash memory block for program and data.
The 32K bytes Flash memory can be programmed either in parallel mode or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard VCC pin.
The AT89C51IC2 retains all features of the 80C52 with 256 bytes of internal RAM, a
10-source 4-level interrupt controller and three timer/counters.
In addition, the AT89C51IC2 has a 32 kHz Subsidiary clock Oscillator, a Programmable
Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a 2-wire interface, an SPI Interface, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and a speed improvement
mechanism (X2 mode).
The fully static design of the AT89C51IC2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The AT89C51IC2 has 2 software-selectable modes of reduced activity and 8-bit clock
prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen
while the peripherals and the interrupt system are still operating. In the power-down
mode the RAM is saved and all other functions are inoperative.
The added features of the AT89C51IC2 make it more powerful for applications that need
pulse width modulation, high speed I/O and counting capabilities such as alarms, motor
control, corded phones, smart card readers.
Table 1. Memory Size
PLCC44
VQFP44 1.4Flash (bytes)XRAM (bytes)
T89C51IC232k1024128034
TOTAL RAM
(bytes)I/O
2
AT89C51IC2
4301D–8051–02/08
Block Diagram
Timer 0
INT
RAM
256
T0
T1
RxD
TxD
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
C51
CORE
(2) (2)(2) (2)
Port 0
Port 1
P1
P4
IB-bus
Reset
Vss
Vcc
(2)(2)
Flash
32K x 8
x8
ECI
PCA
(1)(1)
Port 2
P3
PCATimer 2
BRG
Port 3
Port 12
P0
P2
EA
RD
WR
ALE/PROG
PSEN
(2)
(2)
+
Parallel I/O Ports & Ext Bus
Watch
Dog
Key
Board
SPI
SS
(1)
SCK
(1)
MOSI
(1)
MISO
(1)
T2EX
(1)
T2
(1)
Two-Wire
SDA
SCL
Figure 1. Block Diagram
AT89C51IC2
(1): Alternate function of Port 1
(2): Alternate function of Port 3
4301D–8051–02/08
3
SFR MappingThe Special Function Registers (SFRs) of the AT89C51IC2 fall into the following
KBF9Eh Keyboard Flag RegisterKBF7KBF6KBF5KBF4KBF3KBF2KBF1KBF0
8
AT89C51IC2
4301D–8051–02/08
Table 12. SFR Mapping
Bit
addressableNon Bit addressable
0/81/9 2/A3/B 4/C5/D6/E 7/F
AT89C51IC2
Table below shows all SFRs with their address and their reset value.
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
B
0000 0000
ACC
0000 0000
CCON
00X0 0000
PSW
0000 0000
T2CON
0000 0000
PI2 bit
addressable
XXXX XX11
IPL0
X000 000
P3
1111 1111
CH
0000 0000
CL
0000 0000
CMOD
00XX X000
FCON (1)
XXXX 0000
T2MOD
XXXX XX00
SADEN
0000 0000
IEN1
XXXX X000
CCAP0H
XXXX XXXX
CCAP0L
XXXX XXXX
CCAPM0
X000 0000
RCAP2L
0000 0000
IPL1
XXXX X000
CCAP1H
XXXX XXXX
CCAP1L
XXXX XXXX
CCAPM1
X000 0000
RCAP2H
0000 0000
SPCON
0001 0100
IPH1
XXXX X111
CCAPL2H
XXXX XXXX
CCAPL2L
XXXX XXXX
CCAPM2
X000 0000
TL2
0000 0000
SPSTA
0000 0000
CCAPL3H
XXXX XXXX
CCAPL3L
XXXX XXXX
CCAPM3
X000 0000
TH2
0000 0000
SPDAT
XXXX XXXX
CCAPL4H
XXXX XXXX
CCAPL4L
XXXX XXXX
CCAPM4
X000 0000
IPH0
X000 0000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
A8h
A0h
98h
90h
88h
80h
4301D–8051–02/08
IEN0
0000 0000
1111 1111
SCON
0000 0000
1111 1111
TCON
0000 0000
1111 1111
SADDR
0000 0000
P2
SBUF
XXXX XXXX
P1
TMOD
0000 0000
P0
0/81/9 2/A3/B 4/C5/D6/E 7/F
SP
0000 0111
AUXR1
XXXX X0X0
BRL
0000 0000
TL0
0000 0000
DPL
0000 0000
BDRCON
XXX0 0000
SSCON
0000 0000
TL1
0000 0000
DPH
0000 0000
KBLS
0000 0000
SSCS
1111 1000
TH0
0000 0000
KBE
0000 0000
SSDAT
1111 1111
TH1
0000 0000
CKSEL
XXXX XXX0
WDTRST
XXXX XXXX
KBF
0000 0000
SSADR
1111 1110
AUXR
XX0X 0000
OSSCON
XXXX X001
CKCON1
XXXX XXX0
WDTPRG
XXXX X000
CKRL
1111 1111
CKCON0
0000 0000
PCON
00X1 0000
reserved
AFh
A7h
9Fh
97h
8Fh
87h
9
Pin Configurations
Figure 2. Pin Configurations
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD
PI2.1/SDA
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
P1.4/CEX1
P1.3/CEX0
5 4 3 2 1 6
P1.1/T2EX/SS
P1.2/ECI
P1.0/T2/XTALB1
XTALB2
VCC
44 43 42 41 40
PLCC44
P0.0/AD0
18 192322212026252427 28
NIC*
VSS
XTAL2
XTAL1
P3.7/RD
P3.6/WR
P2.0/A8
P2.1/A9
P0.3/AD3
P0.2/AD2
P0.1/AD1
39
P0.4/AD4
38
P0.5/AD5
37
P0.6/AD6
36
P0.7/AD7
35
EA
34
PI2.0/SCL
33
ALE/PROG
32
PSEN
31
P2.7/A15
30
P2.6/A14
29
P2.5/A13
P2.2/A10
P2.3/A11
P2.4/A12
10
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
AT89C51IC2
RST
P3.0/RxD
PI2.1/SDA
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P1.4/CEX1
P1.3/CEX0
43 42 41 40 394438 37 36 35 34
1
2
3
4
5
6
7
8
9
10
11
P1.0/T2/XTALB1
P1.1/T2EX/SS
P1.2/ECI
XTALB2
VQFP44 1.4
VCC
12 131716151420191821 22
VSS
NIC*
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P2.0/A8
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
33
32
P0.5/AD5
31
P0.6/AD6
30
P0.7/AD7
29
EA
28
PI2.0/SCL
27
ALE/PROG
26
PSEN
25
P2.7/A15
24
P2.6/A14
23
P2.5/A13
P2.1/A9
P2.3/A11
P2.2/A10
P2.4/A12
4301D–8051–02/08
Table 13. Pin Description for 40/44 Pin Packages
AT89C51IC2
Pin Number
Mnemonic
V
SS
V
CC
P0.0 - P0.743 - 3637 - 30I/OPort 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
P1.0 - P1.72 - 940 - 44
2216IGround: 0V reference
4438I
1 - 3
240I/OP1.0: Input/Output
341I/OP1.1: Input/Output
Type
Name and FunctionPLCC44VQFP44 1.4
Power Supply: This is the power supply voltage for normal, idle and power-down
operation
them float and can be used as high impedance inputs. Port 0 must be polarized to VCC
or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data
memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also
inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes.
I/OPort 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current because
of the internal pull-ups. Port 1 also receives the low-order address byte during memory
programming and verification.
Alternate functions for AT89C51IC2 Port 1 include:
IXTALB1 (P1.0): Sub Clock input to the inverting oscillator amplifier
IT2EX: Timer/Counter 2 Reload/Capture/Direction Control
ISS
442I/OP1.2: Input/Output
IECI: External Clock for the PCA
543I/OP1.3: Input/Output
I/OCEX0: Capture/Compare External I/O for PCA module 0
644I/OP1.4: Input/Output
I/OCEX1: Capture/Compare External I/O for PCA module 1
71I/OP1.5: Input/Output
I/OCEX2: Capture/Compare External I/O for PCA module 2
I/OMISO: SPI Master Input Slave Output line
82I/OP1.6: Input/Output
I/OCEX3: Capture/Compare External I/O for PCA module 3
I/OSCK: SPI Serial Clock
: SPI Slave Select
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI
is in slave mode, MISO outputs data to the master controller.
SCK outputs clock to the slave peripheral
4301D–8051–02/08
11
Table 13. Pin Description for 40/44 Pin Packages (Continued)
Pin Number
Mnemonic
93I/OP1.7: Input/Output:
XTALA12115I
XTALA22014OCrystal A 2: Output from the inverting oscillator amplifier
XTALB1240I
XTALB2139OCrystal B 2: (Sub Clock) Output from the inverting oscillator amplifier
P2.0 - P2.724 - 3118 - 25I/OPort 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
Type
Name and FunctionPLCC44VQFP44 1.4
I/OCEX4: Capture/Compare External I/O for PCA module 4
I/OMOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is
in slave mode, MOSI receives data from the master controller.
Crystal A 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
Crystal B 1: (Sub Clock) Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current because
of the internal pull-ups. Port 2 emits the high-order address byte during fetches from
external program memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting
1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri),
port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order
address bits during EPROM programming and verification.
P3.0 - P3.711,
13 - 19
115IRXD (P3.0): Serial input port
137OTXD (P3.1): Serial output port
148IINT0
159IINT1 (P3.3): External interrupt 1
1610IT0 (P3.4): Timer 0 external input
1711IT1 (P3.5): Timer 1 external input
1812OWR (P3.6): External data memory write strobe
1913ORD (P3.7): External data memory read strobe
PI2.0 - PI2.1
34, 1228, 6
3428I/OSCL (PI2.0):2-wire Serial Clock
126I/OSDA (PI2.1):2-wire Serial Data
5,
7 - 13
I/OPort 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current because
of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as
listed below.
(P3.2): External interrupt 0
Port I2: Port I2 is an open drain. It can be used as inputs (must be polarized to Vcc
with external resistor to prevent any parasitic current consumption).
SCL output the serial clock to slave peripherals
SCL input the serial clock from master
12
AT89C51IC2
4301D–8051–02/08
Table 13. Pin Description for 40/44 Pin Packages (Continued)
AT89C51IC2
Pin Number
Mnemonic
RST104I/O
ALE/PROG3327O (I)Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
PSEN3226OProgram Strobe ENable: The read strobe to external program memory. When execut-
EA3529IExternal Access Enable: EA must be externally held low to enable the device to fetch
Type
Name and FunctionPLCC44VQFP44 1.4
SDA is the bidirectional 2-wire data line
Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to V
external capacitor to VCC. This pin is an output when the hardware watchdog forces a
system reset.
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory. This pin is also the program pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE
will be inactive during internal fetches.
ing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external
data memory. PSEN is not activated during fetches from internal program memory.
code from external program memory locations 0000H to FFFFH (RD). If security level 1
is programmed, EA will be internally latched on Reset.
permits a power-on reset using only an
SS
4301D–8051–02/08
13
Oscillators
Overview Two oscillators are available for CPU:
•OSCA used for high frequency: Up to 48 MHz @5V +/- 10%
•OSCB used for low frequency: 32.768 kHz
Several operating modes are available and programmable by software:
•to switch OSCA to OSCB and vice-versa
•to stop OSCA or OSCB to reduce consumption
In order to optimize the power consumption and the execution time needed for a specific
task, an internal prescaler feature has been implemented between the selected oscillator and the CPU.
RegistersTable 14. CKSEL Register
CKSEL - Clock Selection Register (85h)
76543210
-------CKS
Bit
Number
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2-Reserved
1-Reserved
0CKS
Bit
Mnemonic Description
CPU Oscillator Select Bit: (CKS)
Cleared, CPU and peripherals connected to OSCB
Set, CPU and peripherals connected to OSCA
Programmed by hardware after a Power-up regarding Hardware Security Byte
(HSB).HSB.OSC (Default setting, OSCA selected)
Reset Value = 0000 000’HSB.OSC’b (see Hardware Security Byte (HSB) Table 84)
Not bit addressable
14
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Table 15. OSCCON Register
OSCCON- Oscillator Control Register (86h)
76543210
-----SCLKT0OscBEnOscAEn
Bit
Number
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2SCLKT0
1OscBEn
0OscAEn
Bit
Mnemonic Description
Sub Clock Timer0
Cleared by software to select T0 pin
Set by software to select T0 Sub Clock
Cleared by hardware after a Power Up
OscB enable bit
Set by software to run OscB
Cleared by software to stop OscB
Programmed by hardware after a Power-up regarding HSB.OSC (Default
cleared, OSCB stopped)
OscA enable bit
Set by software to run OscA
Cleared by software to stop OscA
Programmed by hardware after a Power-up regarding HSB.OSC(Default Set,
OSCA runs)
4301D–8051–02/08
Reset Value = XXXX X0’HSB.OSC
’’HSB.OSC’b (see Hardware Security Byte (HSB)
Table 84)
Not bit addressable
Table 16. CKRL Register
CKRL - Clock Reload Register
76543210
--------
Bit
Number Mnemonic Description
7:0CKRL
Clock Reload Register:
Prescaler value
Reset Value = 1111 1111b
Not bit addressable
15
Table 17. PCON Register
PCON - Power Control Register (87h)
76543210
SMOD1SMOD0-POFGF1GF0PDIDL
Bit
Number
7SMOD1
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
Bit
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
General purpose Flag
Cleared by software for general purpose usage.
Set by software for general purpose usage.
General purpose Flag
Cleared by software for general purpose usage.
Set by software for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
16
Reset Value = 00X1 0000b
Not bit addressable
AT89C51IC2
4301D–8051–02/08
Functional Block
XtalA2
XtalA1
XtalB1
XtalB2
OscBEn
OscB
OscA
CLK
CLK
Idle
CPU clock
OscAEn
CKS
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
1
0
:128
Sub
Clock
:2
X2
0
1
FOSCA
PERIPH
CPU
FOSCB
OSCCON
OSCCON
CKCON0
CKSEL
PwdOscA
PwdOscB
CKRL=0xFF?
1
0
Diagram
Figure 3. Functional Oscillator Block Diagram
AT89C51IC2
Operating Modes
ResetA hardware RESET puts the Clock generator in the following state:
The selected oscillator depends on OSC bit in Hardware Security Byte (HSB) (see HSB
Table 84)
Functional Modes
HSB.OSC = 1 (Oscillator A selected)
•OscAEn = 1 & OscBEn = 0: OscA is running, OscB is stopped.
•CKS = 1: OscA is selected for CPU.
HSB.OSC = 0 (Oscillator B selected)
•OscAEn = 0 & OscBEn = 1: OscB is running, OscA is stopped.
•CKS = 0: OscB is selected for CPU.
Normal Modes•CPU and Peripherals clock depend on the software selection using CKCON0,
CKCON1 and CKRL registers
•CKS bit in CKSEL register selects either OscA or OscB
•CKRL register determines the frequency of the OscA clock.
4301D–8051–02/08
17
•It is always possible to switch dynamically by software from OscA to OscB, and vice
versa by changing CKS bit.
Idle Modes•IDLE modes are achieved by using any instruction that writes into PCON.0 bit (IDL)
•IDLE modes A and B depend on previous software sequence, prior to writing into
PCON.0 bit:
•IDLE MODE A: OscA is running (OscAEn = 1) and selected (CKS = 1)
•IDLE MODE B: OscB is running (OscBEn = 1) and selected (CKS = 0)
•The unused oscillator OscA or OscB can be stopped by software by clearing
OscAEn or OscBEn respectively.
•IDLE mode can be canceled either by Reset, or by activation of any enabled
interruption
•In both cases, PCON.0 bit (IDL) is cleared by hardware
•Exit from IDLE modes will leave Oscillators control bits (OscEnA, OscEnB, CKS)
unchanged.
Power Down Modes•POWER DOWN modes are achieved by using any instruction that writes into
PCON.1 bit (PD)
•POWER DOWN modes A and B depend on previous software sequence, prior to
writing into PCON.1 bit:
•Both OscA and OscB will be stopped.
•POWER DOWN mode can be cancelled either by a hardware Reset, an external
interruption, or the keyboard interrupt.
•By Reset signal: The CPU will restart according to OSC bit in Hardware Security Bit
(HSB) register.
•By INT0 or INT1 interruption, if enabled: (standard behavioral), request on Pads
must be driven low enough to ensure correct restart of the oscillator which was
selected when entering in Power down.
•By keyboard Interrupt if enabled: a hardware clear of the PCON.1 flag ensure the
restart of the oscillator which was selected when entering in Power down.
Note:The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock.
SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode)
SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use
as periodic interrupt for time clock.
20
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
XTALA1
2
CKCON0
X2
8 bit Prescaler
F
OSCA
F
XTAL
XTALA1:2
F
CLK CPU
F
CLK PERIPH
CKSEL
CKS
F
OSCB
CKRL
0
1
0
1
Enhanced FeaturesIn comparison to the original 80C52, the AT89C51IC2implements some new features,
which are:
•The X2 option
•The Dual Data Pointer
•The extended RAM
•The Programmable Counter Array (PCA)
•The Hardware Watchdog
•The SPI interface
•The 2-wire interface
•The 4 level interrupt priority system
•The power-off flag
•The Power On Reset
•The ONCE mode
•The ALE disabling
•Some enhanced features are also located in the UART and the timer 2
X2 Feature and OSCA
Clock Generation
The AT89C51IC2 core needs only 6 clock periods per machine cycle. This feature
called ”X2” provides the following advantages:
•Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
•Save power consumption while keeping same CPU power (oscillator power saving).
•Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
•Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTALA1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
DescriptionThe clock for the whole circuit and peripherals is first divided by two before being used
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTALA1 input. In X2 mode, as this divider
is bypassed, the signals on XTALA1 must have a cyclic ratio between 40 to 60%.
Figure 5. shows the clock generation block diagram.x2 bit is validated on the rising edge
of the XTALA1÷2 to avoid glitches when switching from X2 to STD mode. Figure 6.
shows the switching mode waveforms.
Figure 5. Clock Generation Diagram
4301D–8051–02/08
21
Figure 6. Mode Switching Waveforms
XTALA1:2
XTALA1
CPU clock
X2 bit
X2 ModeSTD ModeSTD Mode
F
OSCA
The X2 bit in the CKCON0 register (see Table 19) allow to switch from 12 clock periods
per instruction to 6 clock periods and vice versa. At reset, the speed is setting according
to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is actived. Setting
the X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UartX2, PcaX2, WdX2 and I2CX2 bits in the CKCON0 register
(See Table 19.) and SPIX2 bit in the CKCON1 register (see Table 20) allow to switch
from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast
peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only
in X2 mode.
More information about the X2 mode can be found in the application note "How to take
advantage of the X2 features in TS80C51 microcontroller?"
22
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Table 19. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
76543210
SPIX2WDX2PCAX2SIX2T2X2T1X2T0X2X2
Bit
Number
7I2CX2
6WDX2
5PCAX2
4SIX2
3T2X2
2T1X2
Bit
Mnemonic Description
2-wire clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Watchdog clock (This control bit is validated when the CPU clock X2 is set;
when X2 is low, this bit has no effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array clock (This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer2 clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4301D–8051–02/08
Timer0 clock (This control bit is validated when the CPU clock X2 is set; when
1T0X2
0X2
X2 is low, this bit has no effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
CPU clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2" bits.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), Default setting, X2 is cleared.
Reset Value = 0000 000’HSB.X2’b
Not bit addressable
23
Table 20. CKCON1 Register
CKCON1 - Clock Control Register (AFh)
76543210
-------SPIX2
Bit
Number
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2-Reserved
1-Reserved
0SPIX2
Bit
Mnemonic Description
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reset Value = XXXX XXX0b
Not bit addressable
24
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
External Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
Dual Data Pointer
Register
Figure 7. Use of Dual Pointer
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 21) that allows the program
code to switch between them (Refer to Figure 7).
Table 21. AUXR1 register
AUXR1- Auxiliary Register 1(0A2h)
76543210
--ENBOOT-GF30-DPS
Bit
Number
7-
6-
5ENBOOT
4-
3GF3This bit is a general purpose user flag.*
20Always cleared.
1-
0DPS
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Boot Flash
Cleared to disable boot rom.
Set to map the boot rom between F800h - 0FFFFh.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
4301D–8051–02/08
Reset Value: XXXX XX0X0b
Not bit addressable
Note:*Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
25
ASSEMBLY LANGUAGE ; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
26
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
XRAM
Upper
128 bytes
Internal
Ram
Lower
128 bytes
Internal
Ram
Special
Function
Register
80h80h
00
0FFh or 3FFh
0FFh
00
0FFh
External
Data
Memory
0000
00FFh up to 03FFh
0FFFFh
indirect accesses
direct accesses
direct or indirect
accesses
7Fh
Expanded RAM
(XRAM)
The AT89C51IC2 provides additional Bytes of random access memory (RAM) space for
increased data parameter handling and high level language usage.
AT89C51IC2 devices have expanded RAM in external data space; maximum size and
location are described in Table 22.
Table 22. Expanded RAM
Address
XRAM size
AT89C51IC2102400h3FFh
StartEnd
The AT89C51IC2 h as inte rnal da ta memo ry that is mapped into f our sep arate
segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the
EXTRAM bit cleared in the AUXR register (see Table 22)
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. That means they have the same address, but are
physically separate from SFR space.
Figure 8. Internal and External Data Memory Address
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
•Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
4301D–8051–02/08
27
•Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
•The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 22. This can be
useful if external peripherals are mapped at addresses already used by the internal
XRAM.
•With EXTRAM = 0,
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done by the use of
DPTR.
•With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port2 outputs the high-order eight address bits (the contents of DPH) while
Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and
MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7
(RD).
the XRAM is indirectly addressed, using the MOVX instruction in
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are exten ded from 6 to 30 clock periods. This is useful to access external slow
peripherals.
28
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Table 23. AUXR Register
AUXR - Auxiliary Register (8Eh)
76543210
--M0-XRS1XRS0EXTRAMAO
Bit
Number
7-
6-
5M0
4-
3XRS1XRAM Size
2XRS0
1EXTRAM
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Pulse length
Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock
periods.
Reserved
The value read from this bit is indeterminate. Do not set this bit
XRS1
00256 bytes (default)
01 512 bytes
10768 bytes
111024 bytes
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
XRS0XRAM size
4301D–8051–02/08
ALE Output bit
0AO
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used) (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
Reset Value = XX0X 00’HSB.XRAM’0b
Not bit addressable
29
Timer 2The Timer 2 in the AT89C51IC2 is the standard C52 the Timer 2.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2
and TL2 are cascaded. It is controlled by T2CON (Table 24) and T2MOD (Table 25)
registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F
(timer operation) or external pin T2 (counter operation) as the timer clock input. Setting
TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2
Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes.
Timer 2 includes the following enhancements:
•Auto-reload mode with up or down counter
•Programmable clock-output
(T2CON).
Auto-Reload ModeThe auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto-
matic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the
Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an
Up/down timer/counter as shown in Figure 9. In this mode the T2EX pin controls the
direction of count.
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
OSC
/12
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the direction of
the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit
resolution.
In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 10). The input clock increments TL2 at frequency F
CLK PERIPH
/2. The
timer repeatedly counts to overflow from a loaded value. At overflow, the contents of
RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2
overflows do not generate interrupts. The formula gives the clock-out frequency as a
function of the system oscillator frequency and the value in the RCAP2H and RCAP2L
registers:
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz
(F
CLK PERIPH
16)
/2
to 4 MHz (F
T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
•Set T2OE bit in T2MOD register.
CLK PERIPH
/4). The generated clock signal is brought out to
•Clear C/T2 bit in T2CON register.
•Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
•To start the timer, set TR2 run control bit in T2CON register.
It is possible to use timer 2 as a baud rate generator and a clock generator simultane o usly. For this con f iguratio n, t he baud rates and cloc k f requencie s are n o t
independent since both functions use the values in the RCAP2H and RCAP2L registers.
4301D–8051–02/08
31
Figure 10. Clock-Out Mode C/T2 = 0
:6
EXF2
TR2
OVEFLOW
T2EX
TH2
(8-bit)
TL2
(8-bit)
TIMER 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2
F
CLK PERIPH
T2CON
T2CON
T2CON
T2MOD
INTERRUPT
QD
Toggle
EXEN2
32
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Table 24. T2CON Register
T2CON - Timer 2 Control Register (C8h)
76543210
TF2EXF2RCLKTCLKEXEN2TR2C/T2#CP/RL2#
Bit
Number
7TF2
6EXF2
5RCLK
4TCLK
3EXEN2
2TR2
Bit
Mnemonic Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin
if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1)
Receive Clock bit
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to turn on timer 2.
4301D–8051–02/08
Timer/Counter 2 select bit
1C/T2#
0CP/RL2#
Cleared for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload
on timer 2 overflow.
Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin
if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
Bit addressable
CLK PERIPH
).
33
Table 25. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
76543210
------T2OEDCEN
Bit
Number
7-
6-
5-
4-
3-
2-
1T2OE
0DCEN
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 Output Enable bit
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
Down Counter Enable bit
Cleared to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.
Reset Value = XXXX XX00b
Not bit addressable
34
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Programmable
Counter Array PCA
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/capture modules. Its clock input can be programmed to count
any one of the following signals:
•Peripheral clock frequency (F
•Peripheral clock frequency (F
CLK PERIPH
CLK PERIPH
) ÷ 6
) ÷ 2
•Timer 0 overflow
•External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
•rising and/or falling edge capture
•software timer
•high-speed output
•pulse width modulator
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog
Timer", page 46).
When the compare/capture modules are programmed in the capture mode, software
timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If the port is not used for the PCA, it can still be used for
standard I/O.
PCA componentExternal I/O Pin
16-bit CounterP1.2 / ECI
16-bit Module 0P1.3 / CEX0
16-bit Module 1P1.4 / CEX1
16-bit Module 2P1.5 / CEX2
16-bit Module 3P1.6 / CEX3
The PCA timer is a common time base for all five modules (See Figure 11). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 26) and can be programmed to run at:
•1/6 the
peripheral clock frequency (F
•1/2 the peripheral clock frequency (F
CLK PERIPH
CLK PERIPH
)
)
•The Timer 0 overflow
•The input on the ECI pin (P1.2)
4301D–8051–02/08
35
Figure 11. PCA Timer/Counter
CIDLCPS1 CPS0 ECF
It
CHCL
16 bit up counter
To PCA
modules
Fclk periph /6
Fclk periph / 2
T0 OVF
P1.2
Idle
CMOD
0xD9
WDTE
CFCR
CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
overflow
36
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Table 26. CMOD Register
CMOD - PCA Counter Mode Register (D9h)
76543210
CIDLWDTE---CPS1CPS0ECF
Bit
Number
7CIDL
6WDTE
5-
4-
3-
2CPS1PCA Count Pulse Select
1CPS0
0ECF
Bit
Mnemonic Description
Counter Idle Control
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
Watchdog Timer Enable
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
CPS0Selected PCA input
4301D–8051–02/08
Reset Value = 00XX X000b
Not bit addressable
The CMOD register includes three additional bits associated with the PCA (See
Figure 11 and Table 26).
•The CIDL bit which allows the PCA to stop during idle mode.
•The WDTE bit which enables or disables the watchdog function on module 4.
•The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA
timer (CF) and each module (Refer to Table 27).
•Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
•Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
•Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
37
Table 27. CCON Register
CCON - PCA Counter Control Register (D8h)
76543210
CFCR-CCF4CCF3CCF2CCF1CCF0
Bit
Number
7CF
6CR
5-
4CCF4
3CCF3
2CCF2
1CCF1
Bit
Mnemonic Description
PCA Counter Overflow flag
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF
may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Module 4 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 3 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 2 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 1 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
38
AT89C51IC2
PCA Module 0 interrupt flag
0CCF0
Must be cleared by software.
Set by hardware when a match or capture occurs.
Reset Value = 00X0 0000b
Not bit addressable
The watchdog timer function is implemented in module 4 (See Figure 14).
The PCA interrupt system is shown in Figure 12.
4301D–8051–02/08
Figure 12. PCA Interrupt System
CFCR
CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Module 4
Module 3
Module 2
Module 1
Module 0
ECF
PCA Timer/Counter
ECCFn
CCAPMn.0CMOD.0
IEN0.6IEN0.7
To Interrupt
priority decoder
ECEA
AT89C51IC2
PCA Modules: each one of the five compare/capture modules has six possible func-
tions. It can perform:
•16-bit Capture, positive-edge triggered
•16-bit Capture, negative-edge triggered
•16-bit Capture, both positive and negative-edge triggered
•16-bit Software Timer
•16-bit High Speed Output
•8-bit Pulse Width Modulator
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 28). The
registers contain the bits that control the mode that each module will operate in.
•The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module.
•PWM (CCAPMn.1) enables the pulse width modulation mode.
•The TOG bit (CCAPMn.2) when set causes the CEX output associated with the
module to toggle when there is a match between the PCA counter and the module's
capture/compare register.
•The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the module's
capture/compare register.
•The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occur for either transition.
•The last bit in the register ECOM (CCAPMn.6) when set enables the comparator
function.
4301D–8051–02/08
39
Table 28 shows the CCAPMn settings for the various PCA functions.
Table 28. CCAPMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
76543210
-ECOMnCAPPnCAPNnMATnTOGnPWMnECCFn
Bit
Number
7-
6ECOMn
5CAPPn
4CAPNn
3MATn
2TOGn
1PWMn
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
Capture Positive
Cleared to disable positive edge capture.
Set to enable positive edge capture.
Capture Negative
Cleared to disable negative edge capture.
Set to enable negative edge capture.
Match
When MATn = 1, a match of the PCA counter with this module's
compare/capture register causes the
CCFn bit in CCON to be set, flagging an interrupt.
Toggle
When TOGn = 1, a match of the PCA counter with this module's
compare/capture register causes the
CEXn pin to toggle.
Pulse Width Modulation Mode
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
40
AT89C51IC2
Enable CCF interrupt
0CCF0
Cleared to disable compare/capture flag CCFn in the CCON register to generate
an interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Reset Value = X000 0000b
Not bit addressable
4301D–8051–02/08
AT89C51IC2
Table 29. PCA Module Modes (CCAPMn Registers)
ECOMn CAPPn CAPNnMATnTOGnPWMmECCFn Module Function
0000000 No Operation
X10000X
X01000X
X11000X
100100X
100110X 16-bit High Speed Output
1000010 8-bit PWM
1001X0X Watchdog Timer (module 4 only)
16-bit capture by a positive-edge
trigger on CEXn
16-bit capture by a negative trigger
on CEXn
16-bit capture by a transition on
CEXn
16-bit Software Timer / Compare
mode.
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output (See Table 30 &
Table 31).
Table 30. CCAPnH Registers (n = 0-4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
76543210
--------
Bit
Number
7-0-
Bit
Mnemonic Description
PCA Module n Compare/Capture Control
CCAPnH Value
Reset Value = 0000 0000b
Not bit addressable
4301D–8051–02/08
41
Table 31. CCAPnL Registers (n = 0-4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
76543210
--------
Bit
Number
7-0-
Bit
Mnemonic Description
PCA Module n Compare/Capture Control
CCAPnL Value
Reset Value = 0000 0000b
Not bit addressable
Table 32. CH Register
CH - PCA Counter Register High (0F9h)
76543210
--------
Bit
Number
7-0-
Bit
Mnemonic Description
PCA counter
CH Value
Reset Value = 0000 0000b
Not bit addressable
Table 33. CL Register
42
AT89C51IC2
CL - PCA Counter Register Low (0E9h)
76543210
--------
Bit
Number
7-0-
Bit
Mnemonic Description
PCA Counter
CL Value
Reset Value = 0000 0000b
Not bit addressable
4301D–8051–02/08
AT89C51IC2
CFCR
CCON
0xD8
CHCL
CCAPnHCCAPnL
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Coun ter/Timer
ECOMn
CCAPMn, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
Cex.n
Capture
PCA Capture ModeTo use one of the PCA modules in the capture mode either one or both of the CCAPM
bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the module's
capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(Refer to Figure 13).
Figure 13. PCA Capture Mode
16-bit Software Timer/
Compare Mode
4301D–8051–02/08
The PCA modules can be used as software timers by setting both the ECOM and MAT
bits in the modules CCAPMn register. The PCA timer will be compared to the module's
capture registers and when a match occurs an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 14).
43
Figure 14. PCA Compare Mode and PCA Watchdog Timer
CHCL
CCAPnHCCAPnL
ECOMn
CCA PMn, n = 0 to 4
0xDA to 0xDE
CAPNn MA Tn TOGn PWMn ECCFnCAPPn
16 bit comparator
Match
CCON
0xD8
PCA IT
Enable
PCA counter/timer
RESET *
CIDLCPS1 CP S0ECF
CMOD
0xD9
WDTE
Reset
Write to
CCAPnL
Write to
CCAPnH
CFCCF2 CCF1 CCF0
CR
CCF3CCF4
10
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (See Figure 15).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
44
AT89C51IC2
4301D–8051–02/08
Figure 15. PCA High Speed Output Mode
CHCL
CCAPnHCCAPnL
ECOMn
CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn P WMn ECCFnCAPPn
16 bit comparator
Match
CFCR
CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
Enable
CEXn
PCA counter/timer
Write to
CCAPnH
Reset
Writ e to
CCAPnL
1
0
AT89C51IC2
Pulse Width Modulator
Mode
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
All of the PCA modules can be used as PWM outputs. Figure 16 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the
modules will have the same frequency of output because they all share the PCA timer.
The duty cycle of each module is independently variable using the module's capture
register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output
will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in
the module's CCAPMn register must be set to enable the PWM mode.
4301D–8051–02/08
45
Figure 16. PCA PWM Mode
CL
CCAPnH
CCAPnL
ECOMn
CCAPMn, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
8 bit comparator
CEXn
“0”
“1”
Enable
PCA counter/timer
Overflow
PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA module that can be programmed as a watchdog. However, this module can still be
used for other modes if the watchdog is not needed. Figure 14 shows a diagram of how
the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just
like the other compare modes, this 16-bit value is compared to the PCA timer value. If a
match is allowed to occur, an internal reset will be generated. This will not cause the
RST pin to be driven high.
In order to hold off the reset, the user has three options:
1. periodically change the compare value so it will never match the PCA timer,
2. periodically change the PCA timer value so it will never match the compare values, or
3. disable the watchdog by clearing the WDTE bit before a match occurs and then reenable it.
The first two options are more reliable because the watchdog timer is never disabled as
in option #3. If the program counter ever goes astray, a match will eventually occur and
cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
46
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART framing error control
SM0 to UART mode control (SMOD0 = 0)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD
D7D6D5D4D3D2D1D0
FE
SMOD0=1
Serial I/O PortThe serial I/O port in the AT89C51IC2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
•Framing error detection
•Automatic address recognition
Framing Error DetectionFraming bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 17).
Figure 17. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 37.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 18. and Figure 19.).
Figure 18. UART Timings in Mode 1
4301D–8051–02/08
47
Figure 19. UART Timings in Modes 2 and 3
RI
SMOD0=0
Data byteNinth
bit
Stop
bit
Start
bit
RXD
D8D7D6
D5D4D3
D2
D1D0
RI
SMOD0=1
FE
SMOD0=1
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s address and is terminated by a
valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Given AddressEach device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t-care bits (defined by zeros) to form the
device’s given address. The don’t-care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 11111111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
48
AT89C51IC2
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
1111 1101b
SADEN
Given1111 00X1b
4301D–8051–02/08
AT89C51IC2
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast AddressA broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e.g.:
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Reset AddressesOn reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial
port will reply to any address, and so, that it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition.
Table 34. SADEN Register
SADEN - Slave Address Mask Register (B9h)
4301D–8051–02/08
76543210
Reset Value = 0000 0000b
Not bit addressable
49
Table 35. SADDR Register
RCLK
/ 16
RBCK
INT_BRG
0
1
TIMER1
0
1
0
1
TIMER2
INT_BRG
TIMER1
TIMER2
TIMER_BRG_RX
Rx Clock
/ 16
0
1
TIMER_BRG_TX
Tx Clock
TBCK
TCLK
SADDR - Slave Address Register (A9h)
76543210
Reset Value = 0000 0000b
Not bit addressable
Baud Rate Selection for
UART for mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
When the internal Baud Rate Generator is used, the Baud Rates are determined by the
BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
•The baud rate for UART is token by formula:
4301D–8051–02/08
51
Table 37. SCON Register
SCON - Serial Control Register (98h)
76543210
FE/SM0SM1SM2RENTB8RB8TIRI
Bit
Number
7
6SM1
5SM2
4REN
3TB8
Bit
Mnemonic Description
Framing Error bit (SMOD0=1)
FE
SM0
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
o transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
XTAL
XTAL
/12 (or F
/64 or F
/6 in mode X2)
XTAL
/32
XTAL
52
AT89C51IC2
Receiver Bit 8 / Ninth bit received in modes 2 and 3
2RB8
1TI
0RI
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of
the stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 18. and
Figure 19. in the other modes.
Reset Value = 0000 0000b
Bit addressable
4301D–8051–02/08
AT89C51IC2
Table 38. Example of computed value when X2=1, SMOD1=1, SPD=1
Baud RatesF
BRLError (%)BRLError (%)
1152002471.232430.16
576002381.232300.16
384002291.232170.16
288002201.232040.16
192002030.631780.16
96001490.311000.16
4800431.23--
= 16.384 MHzF
OSCA
OSCA
= 24MHz
Table 39. Example of computed value when X2=0, SMOD1=0, SPD=0
Baud RatesF
BRLError (%)BRLError (%)
48002471.232430.16
24002381.232300.16
12002201.232023.55
6001850.161520.16
= 16.384 MHzF
OSCA
OSCA
= 24MHz
The baud rate generator can be used for mode 1 or 3 (refer to Figure 20.), but also for
mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 46.)
4301D–8051–02/08
53
UART RegistersTable 40. SADEN Register
SADEN - Slave Address Mask Register for UART (B9h)
76543210
Reset Value = 0000 0000b
Table 41. SADDR Register
SADDR - Slave Address Register for UART (A9h)
76543210
Reset Value = 0000 0000b
Table 42. SBUF Register
SBUF - Serial Buffer Register for UART (99h)
76543210
Reset Value = XXXX XXXXb
Table 43. BRL Register
BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
76543210
Reset Value = 0000 0000b
54
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Table 44. T2CON Register
T2CON - Timer 2 Control Register (C8h)
76543210
TF2EXF2RCLKTCLKEXEN2TR2C/T2#CP/RL2#
Bit
Number
7TF2
6EXF2
5RCLK
4TCLK
3EXEN2
2TR2
Bit
Mnemonic Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1)
Receive Clock bit for UART
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit for UART
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to turn on timer 2.
4301D–8051–02/08
Timer/Counter 2 select bit
1C/T2#
0CP/RL2#
Cleared for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
timer 2 overflow.
Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin
if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
Bit addressable
CLK PERIPH
).
55
Table 45. PCON Register
PCON - Power Control Register (87h)
76543210
SMOD1SMOD0-POFGF1GF0PDIDL
Bit
Number
7SMOD1
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
Bit
Mnemonic Description
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
56
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Table 46. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
76543210
---BRRTBCKRBCKSPDSRC
Bit
Number
7-
6-
5-
4BRR
3TBCK
2RBCK
1SPD
0SRC
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
Transmission Baud rate Generator Selection bitfor UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Reception Baud Rate Generator Selection bitfor UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Baud Rate Speed Control bitfor UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0for UART
Cleared to select F
mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
/12 as the Baud Rate Generator (F
OSC
CLK PERIPH
/6 in X2
4301D–8051–02/08
Reset Value = XXX0 0000b
Not bit addressable
57
Interrupt SystemThe AT89C51IC2 has a total of 10 interrupt vectors: two external interrupts (INT0 and
IE1
0
3
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
Low priority
interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IPL
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
KBD IT
SPI IT
0
3
0
3
0
3
TWI IT
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt,
Two Wire Interface (I2C) interrupt, Keyboard interrupt and the PCA global interrupt.
These interrupts are shown in Figure 22.
Figure 22. Interrupt Control System
58
AT89C51IC2
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 51 and Table 49). This register also
contains a global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 52) and in the
Interrupt Priority High register (Table 50 and Table 51) shows the bit values and priority
levels associated with each combination.
4301D–8051–02/08
AT89C51IC2
RegistersThe PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located
at address 0043H, the I2C interrupt vector at 0043H and Keyboard interrupt vector is
located at address 003BH. All other vectors addresses are the same as standard C52
devices.
Table 47. Priority Level Bit Values
IPH.xIPL.xInterrupt Level Priority
000 (Lowest)
011
102
113 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
4301D–8051–02/08
59
Table 48. IENO Register
IEN0 - Interrupt Enable Register (A8h)
76543210
EAECET2ESET1EX1ET0EX0
Bit
Number
7EA
6EC
5ET2
4ES
3ET1
2EX1
1ET0
Bit
Mnemonic Description
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
PCA interrupt enable bit
Cleared to disable.
Set to enable.
Timer 2 overflow interrupt Enable bit
Cleared to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
Serial port Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
External interrupt 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0EX0
External interrupt 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
60
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Table 49. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
76543210
-PPCLPT2LPSLPT1LPX1LPT0LPX0L
Bit
Number
7-
6PPCL
5PT2L
4PSL
3PT1L
2PX1L
1PT0L
0PX0L
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA interrupt Priority bit
Refer to PPCH for priority level.
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
Serial port Priority bit
Refer to PSH for priority level.
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
External interrupt 1 Priority bit
Refer to PX1H for priority level.
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Reset Value = X000 0000b
Bit addressable
4301D–8051–02/08
61
Table 50. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
76543210
-PPCHPT2HPSHPT1HPX1HPT0HPX0H
Bit
Number
7-
6PPCH
5PT2H
4PSH
3PT1H
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power ManagementTwo power reduction modes are implemented in the AT89C51IC2: the Idle mode and
the Power-down mode. These modes are detailed in the following sections. In addition
to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “Enhanced Features”.
ResetIn order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter… and to unpredictable behavior of
the microcontroller. A proper device reset initializes the AT89C51IC2 and vectors the
CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset by
simply connecting an external capacitor to V
be applied either directly on the RST pin or indirectly by an internal reset source such as
the watchdog timer. Resistor value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C51IC2 datasheet.
Figure 23. Reset Circuitry and Power-On Reset
as shown in Figure 23. A warm reset can
DD
Cold Reset2 conditions are required before enabling a CPU start-up:
•V
must reach the specified VDD range
DD
•The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be maintained till both of the above conditions are met. A
reset is active when the level V
is reached and when the pulse width covers the
IH1
period of time where VDD and the oscillator are not stabilized. 2 parameters have to be
taken into account to determine the reset pulse width:
•VDD rise time,
•Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen. Table 1 gives some capacitor values examples for a minimum R
50 KΩ and different oscillator startup and VDD rise times.
4301D–8051–02/08
RST
of
67
Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor
R
RST
RST
VSS
To CPU Core
and Peripherals
VDD
+
P
VDD
From WDT
Reset Source
VSS
VDD
RST
1K
To Other
On-board
Circuitry
(1)
Oscillator
VDD Rise Time
Start-Up Time
1 ms10 ms100 ms
5 ms820 nF1.2 µF12 µF
20 ms2.7 µF3.9 µF12 µF
Note:These values assume VDD starts from 0V to the nominal value. If the time between 2
on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
Warm ResetTo achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
Watchdog ResetAs detailed in Section “Hardware Watchdog Timer”, page 102, the WDT generates a 96-
clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of
the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ
resistor must be added as shown Figure 24.
Figure 24. Reset Circuitry for WDT Reset-out Usage
68
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Reset Recommendation
to Prevent Flash
Corruption
An example of bad initialization situation may occur in an instance where the bit
ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since
this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet
due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program
Counter is accidently in the range of the boot memory addresses then a Flash access
(write or erase) may corrupt the Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage (power
supply failure, power supply switched off).
Idle ModeAn instruction that sets PCON.0 indicates that it is the last instruction to be executed
before going into Idle mode. In Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during idle. The port pins hold the
logical states they had at the time Idle was activated. ALE and PSEN hold at logic high
level.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will
cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will
be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during idle. For example, an instruction that activates idle can
also set one or both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down ModeTo save maximum power, a Power-down mode can be invoked by software (see PCON
register).
In Power-down mode, the oscillator is stopped and the instruction that invoked Powerdown mode is the last instruction executed. The internal RAM and SFRs retain their
value until the Power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from Powerdown. To properly terminate Power-down, the reset or external interrupt should not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from
Power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power down mode, 1024
clocks are necessary to exit to power down mode and enter in operating mode.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 25. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the first
input will be released. In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will
be the one following the instruction that puts the AT89C51IC2 into Power-down mode.
Exit from Power-down by reset redefines all the SFRs, exit from Power-down by external interrupt does no affect the SFRs.
Exit from Power-down by either reset or external interrupt does not affect the internal
RAM content.
Note:If idle mode is activated with Power-down mode (IDL and PD bits set), the exit sequence
Table 55 shows the state of ports during idle and power-down modes.
Table 55. State of Ports
ModeProgram MemoryALEPSENPORT0PORT1PORT2PORT3
IdleInternal11Port Data
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
(1)
Port DataPort DataPort Data
IdleExternal11FloatingPort DataAddressPort Data
Power DownInternal00Port Data
Power DownExternal00FloatingPort DataPort DataPort Data
(1)
Port DataPort DataPort Data
Port 0 can force a 0 level. A "one" will leave port floating.
70
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
0
1
2
3
Slave 3
MISO
MOSI
SCK
SS
Slave 4
MISO
MOSI
SCK
SS
Slave 2
MISO
MOSI
SCK
SS
VDD
Master
Serial Port Interface
(SPI)
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial
communication between the MCU and peripheral devices, including other MCUs.
FeaturesFeatures of the SPI Module include the following:
•Full-duplex, three-wire synchronous transfers
•Master or Slave operation
•Eight programmable Master clock rates
•Serial clock with programmable polarity and phase
•Master Mode fault error flag with MCU interrupt capability
•Write collision flag protection
Signal DescriptionFigure 26 shows a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices.
Figure 26. SPI Master/Slaves Interconnection
The Master device selects the individual Slave devices by using four pins of a parallel
pins of the Slave devices.
Master Output Slave Input
(MOSI)
port to control the four SS
This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave Output
(MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
SPI Serial Clock (SCK)This signal is used to synchronize the data movement both in and out of the devices
Slave Select (SS
)Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay
through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one Byte on the serial lines.
low for any message for a Slave. It is obvious that only one Master (SS high level) can
71
4301D–8051–02/08
drive the network. The Master may select each Slave device by software through port
pins (Figure 27). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS
pin could be used as a general-purpose if the following conditions are met:
•The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set
•The Device is configured as a Slave with CPHA and SSDIS control bits set
(1)
.
(2)
. This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
Note:1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because
in this mode, the SS is used to start the transmission.
Baud RateIn Master mode, the baud rate can be selected from a baud rate generator which is con-
trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is
selected from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 56 gives the different clock rates selected by SPR2:SPR1:SPR0.
Table 56. SPI Master Baud Rate Selection
SPR2SPR1SPR0Clock RateBaud Rate Divisor (BD)
000F
001F
010F
011F
100F
101F
110F
111Don’t UseNo BRG
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
/22
/44
/88
/1616
/3232
/6464
/128128
72
AT89C51IC2
4301D–8051–02/08
Functional DescriptionFigure 27 shows a detailed structure of the SPI Module.
Shift Register
01
234567
Internal Bus
Pin
Control
Logic
MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit signal
SS
FCLK PERIPH
/32
/8
/16
Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA
SPR0
SPR1
CPOLMSTRSSDISSPEN
SPR2
SPCON
WCOLMODFSPIF
-----
Figure 27. SPI Module Block Diagram
AT89C51IC2
Operating ModesThe Serial Peripheral Interface can be configured in one of the two modes: Master
mode or Slave mode. The configuration and initialization of the SPI Module is made
through one register:
•The Serial Peripheral Control register (SPCON)
Once the SPI is configured, the data exchange is made using:
•SPCON
•The Serial Peripheral STAtus register (SPSTA)
•The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
4301D–8051–02/08
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 28).
Master ModeThe SPI operates in Master mode when the Master bit, MSTR
is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register
(SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift
register. The Byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another Byte shifts in from the Slave on the Master’s MISO pin.
The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA
becomes set. At the same time that SPIF becomes set, the received Byte from the Slave
is transferred to the receive data register in SPDAT. Software clears SPIF by reading
the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
(1)
, in the SPCON register
Slave ModeThe SPI operates in Slave mode when the Master bit, MSTR
(2)
, in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to ’0’. SS must remain low until the transmission is complete.
In a Slave SPI Module, data enters the shift register under the control of the SCK from
the Master SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an
overflow condition, Slave software must then read the SPDAT before another Byte
(3)
enters the shift register
. A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to
the data register is late, the SPI transmits the data already in the shift register from the
previous transmission. The maximum SCK frequency allowed in slave mode is
/4.
F
CLK PERIPH
Transmission FormatsSoftware can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock Polarity (CPOL
( 4)
) and the Clock Phase
(CPHA4). CPOL defines the default SCK line level in idle state. It has no significant
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 29 and Figure 30).
The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
74
AT89C51IC2
1.The SPI Module should be configured as a Master before it is enabled (SPEN set). Also,
the Master SPI should be configured before the Slave SPI.
2.The SPI Module should be configured as a Slave before it is enabled (SPEN set).
3.The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
4.Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
4301D–8051–02/08
Figure 29. Data Transmission Format (CPHA = 0)
MSBbit6bit5bit4bit3bit2bit1LSB
bit6bit5bit4bit3bit2bit1MSBLSB
13245678
Capture Point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Number
MSBbit6bit5bit4bit3bit2bit1LSB
bit6bit5bit4bit3bit2bit1
MSBLSB
13245678
Capture Point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Number
Byte 1Byte 2
Byte 3
MISO/MOSI
Master SS
Slave SS
(CPHA = 1)
Slave SS
(CPHA = 0)
Figure 30. Data Transmission Format (CPHA = 1)
AT89C51IC2
Figure 31. CPHA/SS
4301D–8051–02/08
Timing
As shown in Figure 29, the first SCK edge is the MSB capture strobe. Therefore, the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each Byte transmitted (Figure 31).
Figure 30 shows an SPI transmission in which CPHA is ’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 31). This format may be preffered in systems having only one Master and
only one Slave driving the MISO data line.
75
Error ConditionsThe following flags in the SPSTA signal SPI error conditions:
Mode Fault (MODF)Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)
pin is inconsistent with the actual mode of the device. MODF is set to warn that there
may be a multi-master conflict for system control. In this case, the SPI system is
affected in the following ways:
•An SPI receiver/error CPU interrupt request is generated
•The SPEN bit in SPCON is cleared. This disables the SPI
•The MSTR bit in SPCON is cleared
When SS
Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set
when the SS signal becomes ’0’.
However, as stated before, for a system with one Master, if the SS pin of the Master
device is pulled low, there is no way that another Master attempts to drive the network.
In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in
the SPCON register and therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set,
followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared.
Write Collision (WCOL)A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA
and an access to SPDAT.
Overrun ConditionAn overrun condition occurs when the Master device tries to send several data Bytes
and the Slave devise has not cleared the SPIF bit issuing from the previous data Byte
transmitted. In this case, the receiver buffer contains the Byte sent after the SPIF bit was
last cleared. A read of the SPDAT returns this Byte. All others Bytes are lost.
This condition is not detected by the SPI peripheral.
SS Error Flag (SSERR)A Synchronous Serial Slave Error occurs when SS
goes high before the end of a
received data in slave mode. SSERR does not cause in interruption, this bit is cleared
by writing 0 to SPEN bit (reset of the SPI state machine).
InterruptsTwo SPI status flags can generate a CPU interrupt requests:
Table 57. SPI Interrupts
FlagRequest
SPIF (SP data transfer)SPI Transmitter Interrupt request
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated.
Figure 32 gives a logical view of the above statements.
76
AT89C51IC2
4301D–8051–02/08
Figure 32. SPI Interrupt Requests Generation
SSDIS
MODF
CPU Interrupt Request
SPI Receiver/error
CPU Interrupt Request
SPI Transmitter
SPI
CPU Interrupt Request
SPIF
AT89C51IC2
Registers
Serial Peripheral Control
Register (SPCON)
There are three registers in the Module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
•The Serial Peripheral Control Register does the following:
•Selects one of the Master clock rates
•Configure the SPI Module as Master or Slave
•Selects serial clock polarity and phase
•Enables the SPI Module
•Frees the SS pin for a general-purpose
Table 58 describes this register and explains the use of each bit
Table 58. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
76543210
SPR2SPENSSDISMSTRCPOLCPHASPR1SPR0
Bit NumberBit MnemonicDescription
7SPR2
6SPEN
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
4301D–8051–02/08
5SSDIS
4MSTR
3CPOL
2CPHA
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is generated
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
.
77
Bit NumberBit MnemonicDescription
SPR2 SPR1 SPR0 Serial Peripheral Rate
1
0SPR0
SPR1
00 0F
00 1 F
01 0 F
01 1F
100F
10 1F
110F
1 11Invalid
Reset Value = 0001 0100b
Not bit addressable
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
/2
/4
/8
/16
/32
/64
/128
Serial Peripheral Status Register
(SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
•Data transfer complete
•Write collision
•Inconsistent logic level on SS pin (mode fault error)
Table 59 describes the SPSTA register and explains the use of every bit in the register.
Table 59. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
76543210
SPIFWCOLSSERRMODF----
Bit
Number
7SPIF
6WCOL
Bit
Mnemonic Description
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision Flag
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
78
AT89C51IC2
5SSERR
4MODF
3-
2-
Synchronous Serial Slave Error Flag
Set by hardware when SS is deasserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4301D–8051–02/08
AT89C51IC2
Serial Peripheral DATa Register
(SPDAT)
Bit
Number
1-
0-
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X0 XXXXb
Not Bit addressable
The Serial Peripheral Data Register (Table 60) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 60. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
76543210
R7R6R5R4R3R2R1R0
Reset Value = Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there
is no on-going exchange. However, special care should be taken when writing to them
while a transmission is on-going:
•Do not change SPR2, SPR1 and SPR0
•Do not change CPHA and CPOL
•Do not change MSTR
•Clearing SPEN would immediately disable the peripheral
•Writing to the SPDAT will cause an overflow.
4301D–8051–02/08
79
Keyboard InterfaceThe AT89C51IC2 implements a keyboard interface allowing the connection of a
P1:x
KBE.x
KBF.x
KBLS.x
0
1
Vcc
Internal Pullup
P1.0
Keyboard Interface
Interrupt Request
KBD
IEN1
Input Circuitry
P1.1Input Circuitry
P1.2Input Circuitry
P1.3Input Circuitry
P1.4Input Circuitry
P1.5Input Circuitry
P1.6Input Circuitry
P1.7Input Circuitry
KBDIT
8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on
both high or low level. These inputs are available as alternate function of P1 and allow to
exit from idle and power down modes.
The keyboard interface interfaces with the C51 core through 3 special function registers:
KBLS, the Keyboard Level Selection register (Table 63), KBE, The Keyboard interrupt
Enable register (Table 62), and KBF, the Keyboard Flag register (Table 61).
Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IEN1) allows global enable or disable of the keyboard interrupt (see Figure 33). As detailed in Figure 34 each keyboard
input has the capability to detect a programmable level according to KBLS.x bit value.
Level detection is then reported in interrupt flags KBF.x that can be masked by software
using KBE.x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage
of P1 inputs for other purpose.
Figure 33. Keyboard Interface Block Diagram
Figure 34. Keyboard Input Circuitry
Power Reduction ModeP1 inputs allow exit from idle and power down modes as detailed in Section “Power
Management”, page 67.
80
AT89C51IC2
4301D–8051–02/08
RegistersTable 61. KBF Register
KBF-Keyboard Flag Register (9Eh)
76543210
KBF7KBF6KBF5KBF4KBF3KBF2KBF1 KBF0
AT89C51IC2
Bit
Number
7KBF7
6KBF6
5KBF5
4KBF4
3KBF3
2KBF2
Bit
Mnemonic Description
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.
Must be cleared by software.
4301D–8051–02/08
Keyboard line 1 flag
1KBF1
0KBF0
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.
Must be cleared by software.
Reset Value= 0000 0000b
This register is read only access, all flags are automatically cleared by reading the
register.
81
Table 62. KBE Register
KBE-Keyboard Input Enable Register (9Dh)
76543210
KBE7KBE6KBE5KBE4KBE3KBE2KBE1 KBE0
Bit
Number
7KBE7
6KBE6
5KBE5
4KBE4
3KBE3
2KBE2
1KBE1
Bit
Mnemonic Description
Keyboard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
Keyboard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
Keyboard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
Keyboard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
Keyboard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
Keyboard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
Keyboard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
0KBE0
Keyboard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
Reset Value= 0000 0000b
82
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
Table 63. KBLS Register
KBLS-Keyboard Level Selector Register (9Ch)
76543210
KBLS7KBLS6KBLS5KBLS4KBLS3KBLS2KBLS1 KBLS0
Bit
Number
7KBLS7
6KBLS6
5KBLS5
4KBLS4
3KBLS3
2KBLS2
1KBLS1
Bit
Mnemonic Description
Keyboard line 7 Level Selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
Keyboard line 6 Level Selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
Keyboard line 5 Level Selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
Keyboard line 4 Level Selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
Keyboard line 3 Level Selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
Keyboard line 2 Level Selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
Keyboard line 1 Level Selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
0KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
Reset Value= 0000 0000b
4301D–8051–02/08
83
2-wire Interface (TWI)This section describes the 2-wire interface. In the rest of the section SSLC means Two-
SCL
SDA
device2device1deviceNdevice3
...
wire. The 2-wire bus is a bi-directional 2-wire serial communication standard. It is
designed primarily for simple but efficient integrated circuit (IC) control. The system is
comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information
between the ICs connected to them. The serial data transfer is limited to 400Kbit/s in
standard mode. Various communication configuration can be designed using this bus.
Figure 35 shows a typical 2-wire bus configuration. All the devices connected to the bus
can be master and slave.
Figure 35. 2-wire Bus Configuration
84
AT89C51IC2
4301D–8051–02/08
Figure 36. Block Diagram
Address Register
Comparator
Timing &
Control
logic
Arbitration &
Sink Logic
Serial clock
generator
Shift Register
Control Register
Status Register
Status
Decoder
Input
Filter
Output
Stage
Input
Filter
Output
Stage
ACK
Status
Bits
8
8
7
8
Internal Bus
Timer 1
overflow
F
CLK PERIPH
/4
Interrupt
SDA
SCL
SSADR
SSCON
SSDAT
SSCS
PI2.1
PI2.0
AT89C51IC2
4301D–8051–02/08
85
DescriptionThe CPU interfaces to the 2-wire logic via the following four 8-bit special function regis-
SDA
SCL
S
start
condition
MSB
12
7
89
ACK
acknowledgement
signal from receiver
acknowledgement
signal from receiver
123-89
ACK
stop
condition
P
clock line held low
while interrupts are serviced
ters: the Synchronous Serial Control register (SSCON; Table 73), the Synchronous
Serial Data register (SSDAT; Table 74), the Synchronous Serial Control and Status register (SSCS; Table 75) and the Synchronous Serial Address register (SSADR Table 78).
SSCON is used to enable SSLC, to program the bit rate (see Table 66), to enable slave
modes, to acknowledge or not a received data, to send a START or a STOP condition
on the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables
SSLC.
In write mode, SSCS is used to select the 2-wire interface and to select the bit rate
source. In read mode, SSCS contains a status code which reflects the status of the 2wire logic and the 2-wire bus. The three least significant bits are always zero. The five
most significant bits contains the status code. There are 26 possible status codes. When
SSCS contains F8h, no relevant state information is available and no serial interrupt is
requested. A valid status code is available in SSCS one machine cycle after SI is set by
hardware and is still present one machine cycle after SI has been reset by software.
Table 68.to Table 72. give the status for the master modes and miscellaneous states.
SSDAT contains a byte of serial data to be transmitted or a byte which has just been
received. It is addressable while it is not in process of shifting a byte. This occurs when
2-wire logic is in a defined state and the serial interrupt flag is set. Data in SSDAT
remains stable as long as SI is set. While data is being shifted out, data on the bus is
simultaneously shifted in; SSDAT always contains the last byte present on the bus.
SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which
SSLC will respond when programmed as a slave transmitter or receiver. The LSB is
used to enable general call address (00h) recognition.
Figure 37 shows how a data transfer is accomplished on the 2-wire bus.
Figure 37. Complete data transfer on 2-wire bus
The four operating modes are:
•Master Transmitter
•Master Receiver
•Slave transmitter
•Slave receiver
Data transfer in each mode of operation is shown in Table 68 to Table 72 and Figure 38.
to Figure 41.. These figures contain the following abbreviations:
86
AT89C51IC2
S : START condition
4301D–8051–02/08
AT89C51IC2
R : Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P : STOP condition
In Figure 38 to Figure 41, circles are used to indicate when the serial interrupt flag is set.
The numbers in the circles show the status code held in SSCS. At these points, a service routine must be executed to continue or complete the serial transfer. These service
routines are not critical since the serial transfer is suspended until the serial interrupt
flag is cleared by software.
When the serial interrupt routine is entered, the status code in SSCS is used to branch
to the appropriate service routine. For each status code, the required software action
and details of the following serial transfer are given in Table 68 to Table 72.
Master Transmitter ModeIn the master transmitter mode, a number of data bytes are transmitted to a slave
receiver (Figure 38). Before the master transmitter mode can be entered, SSCON must
be initialised as follows:
Table 64. SSCON Initialization
CR2SSIESTASTOSIAACR1CR0
bit rate1000Xbit ratebit rate
CR0, CR1 and CR2 define the internal serial bit rate if external bit rate generator is not
used. SSIE must be set to enable SSLC. STA, STO and SI must be cleared.
The master transmitter mode may now be entered by setting the STA bit. The 2-wire
logic will now test the 2-wire bus and generate a START condition as soon as the bus
becomes free. When a START condition is transmitted, the serial interrupt flag (SI bit in
SSCON) is set, and the status code in SSCS will be 08h. This status must be used to
vector to an interrupt routine that loads SSDAT with the slave address and the data
direction bit (SLA+W).
When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, SI is set again and a number of status code in SSCS
are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if
the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each
of these status code is detailed in Table 68. This scheme is repeated until a STOP condition is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to
Table 7 to Table 11. After a repeated START condition (state 10h) SSLC
may switch to
the master receiver mode by loading SSDAT with SLA+R.
Master Receiver ModeIn the master receiver mode, a number of data bytes are received from a slave transmit-
ter (Figure 39). The transfer is initialized as in the master transmitter mode. When the
START condition has been transmitted, the interrupt routine must load SSDAT with the
7-bit slave address and the data direction bit (SLA+R). The serial interrupt flag SI must
then be cleared before the serial transfer can continue.
87
4301D–8051–02/08
When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, the serial interrupt flag is set again and a number of
status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and
also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate
action to be taken for each of these status code is detailed in Table 69. This scheme is
repeated until a STOP condition is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to
Table 7 to Table 11. After a repeated START condition (state 10h) SSLC may switch to
the master transmitter mode by loading SSDAT with SLA+W.
Slave Receiver ModeIn the slave receiver mode, a number of data bytes are received from a master transmit-
ter (Figure 40). To initiate the slave receiver mode, SSADR and SSCON must be loaded
as follows:
The upper 7 bits are the address to which SSLC will respond when addressed by a master. If the LSB (GC) is set SSLC will respond to the general call address (00h); otherwise
it ignores the general call address.
CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable
SSLC. The AA bit must be set to enable the own slave address or the general call
address acknowledgement. STA, STO and SI must be cleared.
When SSADR and SSCON have been initialised, SSLC waits until it is addressed by its
own slave address followed by the data direction bit which must be at logic 0 (W) for
SSLC to operate in the slave receiver mode. After its own slave address and the W bit
have been received, the serial interrupt flag is set and a valid status code can be read
from SSCS. This status code is used to vector to an interrupt service routine.The appropriate action to be taken for each of these status code is detailed in Table 70. The slave
receiver mode may also be entered if arbitration is lost while SSLC is in the master
mode (states 68h and 78h).
If the AA bit is reset during a transfer, SSLC will return a not acknowledge (logic 1) to
SDA after the next received data byte. While AA is reset, SSLC does not respond to its
own slave address. However, the 2-wire bus is still monitored and address recognition
may be resume at any time by setting AA. This means that the AA bit may be used to
temporarily isolate SSLC from the 2-wire bus.
Slave Transmitter ModeIn the slave transmitter mode, a number of data bytes are transmitted to a master
receiver (Figure 41). Data transfer is initialized as in the slave receiver mode. When
SSADR and SSCON have been initialized, SSLC waits until it is addressed by its own
88
AT89C51IC2
4301D–8051–02/08
AT89C51IC2
slave address followed by the data direction bit which must be at logic 1 (R) for SSLC to
operate in the slave transmitter mode. After its own slave address and the R bit have
been received, the serial interrupt flag is set and a valid status code can be read from
SSCS. This status code is used to vector to an interrupt service routine. The appropriate
action to be taken for each of these status code is detailed in Table 71. The slave transmitter mode may also be entered if arbitration is lost while SSLC is in the master mode.
If the AA bit is reset during a transfer, SSLC will transmit the last byte of the transfer and
enter state C0h or C8h. SSLC is switched to the not addressed slave mode and will
ignore the master receiver if it continues the transfer. Thus the master receiver receives
all 1’s as serial data. While AA is reset, SSLC does not respond to its own slave
address. However, the 2-wire bus is still monitored and address recognition may be
resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate SSLC from the 2-wire bus.
Miscellaneous StatesThere are two SSCS codes that do not correspond to a define SSLC hardware state
(Table 72 ). These codes are discuss hereafter.
Status F8h indicates that no relevant information is available because the serial interrupt
flag is not set yet. This occurs between other states and when SSLC is not involved in a
serial transfer.
Status 00h indicates that a bus error has occurred during an SSLC serial transfer. A bus
error is caused when a START or a STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions happen during the serial transfer of an
address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To
recover from a bus error, the STO flag must be set and SI must be cleared. This causes
SSLC to enter the not addressed slave mode and to clear the STO flag (no other bits in
SSCON are affected). The SDA and SCL lines are released and no STOP condition is
transmitted.
NotesSSLC interfaces to the external 2-wire bus via two port pins: SCL (serial clock line) and
SDA (serial data line). To avoid low level asserting on these lines when SSLC is
enabled, the output latches of SDA and SLC must be set to logic 1.
Table 67. Bit frequency configuration
Bit Frequency ( kHz)
CR2CR1CR0F
0004762.5256
00153.571.5224
01062.583192
01175100160
100--Unused
101100133.3120
110200266.660
1110.5 <. < 62.50.67 <. < 83
= 12 MHzF
OSCA
= 16 MHzF
OSCA
divided by
OSCA
96 · (256 - reload valueTimer 1)
(reload value range: 0-254 in mode 2)
4301D–8051–02/08
89
Figure 38. Format and State in the Master Transmitter Mode
SSLAWADataAP
08h18h
28h
MT
SSLAW
AP
AP
R
MR
10h
20h
30h
A or A
continues
38h38h
A
continues
68h
Other master
Other master
78hB0hTo corresponding
states in slave mode
Successfull
transmission
to a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Not acknowledge
received after a data
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
byte
A or A
continues
Other master
DataA
n
From master to slave
From slave to master
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
90
AT89C51IC2
4301D–8051–02/08
Status
Code
SSSTA
08h
Status of the Twowire Bus and Twowire Hardware
A START condition has
been transmitted
AT89C51IC2
Table 68. Status in master transmitter mode
Application software response
To SSCON
SSSTASSSTOSSISSAA
Write SLA+WX00XSLA+W will be transmitted.
Next Action Taken by Two-wire HardwareTo/From SSDAT
A repeated START
10h
condition has been
transmitted
SLA+W has been
18h
transmitted; ACK has
been received
SLA+W has been
20h
transmitted; NOT ACK
has been received
Data byte has been
28h
transmitted; ACK has
been received
Data byte has been
30h
transmitted; NOT ACK
has been received
Write SLA+W
Write SLA+R
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SLA+W will be transmitted.
X
SLA+R will be transmitted.
X
Logic will switch to master receiver mode
Data byte will be transmitted.
X
Repeated START will be transmitted.
X
STOP condition will be transmitted and SSSTO flag
X
will be reset.
STOP condition followed by a START condition will
X
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
X
Repeated START will be transmitted.
X
STOP condition will be transmitted and SSSTO flag
X
will be reset.
STOP condition followed by a START condition will
X
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
X
Repeated START will be transmitted.
X
STOP condition will be transmitted and SSSTO flag
X
will be reset.
STOP condition followed by a START condition will
X
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
X
Repeated START will be transmitted.
X
STOP condition will be transmitted and SSSTO flag
X
will be reset.
STOP condition followed by a START condition will
X
be transmitted and SSSTO flag will be reset.
Arbitration lost in
38h
SLA+W or data bytes
4301D–8051–02/08
No SSDAT action
No SSDAT action
0
1
0
0
0
0
Two-wire bus will be released and not addressed
X
slave mode will be entered.
A START condition will be transmitted when the bus
X
becomes free.
91
Figure 39. Format and State in the Master Receiver Mode
SSLARA
Data
08h
40h
58h
SSLAR
AP
W
MT
10h
48h
A or A
continues
38h38h
A
continues
68h
Other master
Other master
78hB0h
To corresponding
states in slave mode
Successfull
transmission
to a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost and
addressed as slave
A
continues
Other master
n
From master to slave
From slave to master
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
A
Data
PA
50h
MR
Arbitration lost in slave
address or acknowledge bit
DataA
92
AT89C51IC2
4301D–8051–02/08
Status
Code
SSSTA
08h
Status of the Twowire Bus and Twowire Hardware
A START condition has
been transmitted
AT89C51IC2
Table 69. Status in master receiver mode
Application software response
To SSCON
SSSTASSSTOSSISSAA
Write SLA+RX00XSLA+R will be transmitted.
Next Action Taken by Two-wire HardwareTo/From SSDAT
A repeated START
10h
condition has been
transmitted
Arbitration lost in
38h
SLA+R or NOT ACK
bit
SLA+R has been
40h
transmitted; ACK has
been received
SLA+R has been
48h
transmitted; NOT ACK
has been received
Data byte has been
50h
received; ACK has
been returned
Data byte has been
58h
received; NOT ACK
has been returned
Write SLA+R
Write SLA+W
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
Read data byte
Read data byte
Read data byte
Read data byte
Read data byte
X
X
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SLA+R will be transmitted.
X
SLA+W will be transmitted.
X
Logic will switch to master transmitter mode.
Two-wire bus will be released and not addressed
X
slave mode will be entered.
A START condition will be transmitted when the bus
X
becomes free.
01Data byte will be received and NOT ACK will be
returned.
Data byte will be received and ACK will be returned.
Repeated START will be transmitted.
X
STOP condition will be transmitted and SSSTO flag
X
will be reset.
STOP condition followed by a START condition will
X
be transmitted and SSSTO flag will be reset.
01Data byte will be received and NOT ACK will be
returned.
Data byte will be received and ACK will be returned.
Repeated START will be transmitted.
X
STOP condition will be transmitted and SSSTO flag
X
will be reset.
STOP condition followed by a START condition will
X
be transmitted and SSSTO flag will be reset.
4301D–8051–02/08
93
Figure 40. Format and State in the Slave Receiver Mode
SSLAWA
DataA
Data
P or S
A
P or S
A
General CallA
DataA
Data
P or S
A
A
60h
68h
80h
80h
A0h
88h
70h90h
90h
A0h
P or S
A
98h
A
78h
DataA
n
From master to slave
From slave to master
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
Reception of the own
slave address and one or
more data bytes. All are
acknowledged.
Last data byte received
is not acknowledged.
Arbitration lost as master
and addressed as slave
Reception of the general call
address and one or more data
bytes.
Last data byte received is
not acknowledged.
Arbitration lost as master and
addressed as slave by general call
94
AT89C51IC2
4301D–8051–02/08
Table 70. Status in slave receiver mode
Application Software Response
AT89C51IC2
Status
Code
(SSCS)
60h
68h
70h
78h
80h
Status of the 2-wire bus and
2-wire hardware
Own SLA+W has been
received; ACK has been
returned
Arbitration lost in SLA+R/W as
master; own SLA+W has been
received; ACK has been
returned
General call address has been
received; ACK has been
returned
Arbitration lost in SLA+R/W as
master; general call address
has been received; ACK has
been returned
Previously addressed with
own SLA+W; data has been
received; ACK has been
returned
To/from SSDATTo SSCON
STASTOSIAA
No SSDAT action or
No SSDAT action
No SSDAT action or
No SSDAT action
No SSDAT action or
No SSDAT action
No SSDAT action or
No SSDAT action
No SSDAT action or
No SSDAT action
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Next Action Taken By 2-wire Software
0
0
0
0
0
0
0
0
0
0
Data byte will be received and NOT ACK will be
0
returned
Data byte will be received and ACK will be
1
returned
Data byte will be received and NOT ACK will be
0
returned
Data byte will be received and ACK will be
1
returned
Data byte will be received and NOT ACK will be
0
returned
Data byte will be received and ACK will be
1
returned
Data byte will be received and NOT ACK will be
0
returned
Data byte will be received and ACK will be
1
returned
Data byte will be received and NOT ACK will be
0
returned
Data byte will be received and ACK will be
1
returned
88h
90h
Previously addressed with
own SLA+W; data has been
received; NOT ACK has been
returned
Previously addressed with
general call; data has been
received; ACK has been
returned
Read data byte or
Read data byte or
Read data byte or
Read data byte
Read data byte or
Read data byte
Switched to the not addressed slave mode; no
0
0
0
0
0
0
1
0
0
1
0
0
X
0
0
X
0
0
recognition of own SLA or GCA
0
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
0
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1. A START condition will be
transmitted when the bus becomes free
Data byte will be received and NOT ACK will be
0
returned
Data byte will be received and ACK will be
1
returned
4301D–8051–02/08
95
Application Software Response
Status
Code
(SSCS)
98h
A0h
Status of the 2-wire bus and
2-wire hardware
Previously addressed with
general call; data has been
received; NOT ACK has been
returned
A STOP condition or repeated
START condition has been
received while still addressed
as slave
To/from SSDATTo SSCON
STASTOSIAA
Read data byte or
Read data byte or
Read data byte or
Read data byte
No SSDAT action or
No SSDAT action or
No SSDAT action or
No SSDAT action
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
Next Action Taken By 2-wire Software
Switched to the not addressed slave mode; no
0
0
0
0
0
0
0
0
recognition of own SLA or GCA
0
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
0
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1. A START condition will be
transmitted when the bus becomes free
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
0
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
0
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1. A START condition will be
transmitted when the bus becomes free
96
AT89C51IC2
4301D–8051–02/08
Figure 41. Format and State in the Slave Transmitter Mode
SSLAR
A
DataA
Data
P or S
A
A8h
B8hC0h
P or S
A
C8h
All 1’s
A
B0h
DataA
n
From master to slave
From slave to master
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
Reception of the
own slave address
and one or more
data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (AA=0)
AT89C51IC2
Status
Code
(SSCS)
A8h
B0h
B8h
Status of the 2-wire bus and
2-wire hardware
Own SLA+R has been
received; ACK has been
returned
Arbitration lost in SLA+R/W as
master; own SLA+R has been
received; ACK has been
returned
Data byte in SSDAT has been
transmitted; NOT ACK has
been received
Table 71. Status in slave transmitter mode
Application Software Response
To/from SSDATTo SSCON
Load data byte or
Load data byte
Load data byte or
Load data byte
Load data byte or
STASTOSIAA
X
0
X
0
X
0
X
0
X
0
0
0
0
0
0
Load data byte
X
0
0
Next Action Taken By 2-wire Software
Last data byte will be transmitted and NOT ACK
0
will be received
Data byte will be transmitted and ACK will be
1
received
Last data byte will be transmitted and NOT ACK
0
will be received
Data byte will be transmitted and ACK will be
1
received
Last data byte will be transmitted and NOT ACK
0
will be received
Data byte will be transmitted and ACK will be
1
received
4301D–8051–02/08
97
Application Software Response
Status
Code
(SSCS)
C0h
C8h
Status of the 2-wire bus and
2-wire hardware
Data byte in SSDAT has been
transmitted; NOT ACK has
been received
Last data byte in SSDAT has
been transmitted (AA=0); ACK
has been received
To/from SSDATTo SSCON
STASTOSIAA
No SSDAT action or
No SSDAT action or
No SSDAT action or
No SSDAT action
No SSDAT action or
No SSDAT action or
No SSDAT action or
No SSDAT action
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
Next Action Taken By 2-wire Software
Switched to the not addressed slave mode; no
0
0
0
0
0
0
0
0
recognition of own SLA or GCA
0
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
0
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1. A START condition will be transmitted
when the bus becomes free
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
0
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
0
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
1
GC=logic 1. A START condition will be transmitted
when the bus becomes free
98
AT89C51IC2
Table 72. Miscellaneous status
Application Software Response
To/from
Status
Code
(SSCS)
F8h
00h
Status of the 2-wire
bus and 2-wire
hardware
No relevant state
information
available; SI= 0
Bus error due to an
illegal START or
STOP condition
SSDAT
No SSDAT
action
No SSDAT
action
To SSCON
Next Action Taken By 2-wire
STA STO SIAA
No SSCON actionWait or proceed current transfer
010X
Software
Only the internal hardware is
affected, no STOP condition is
sent on the bus. In all cases,
the bus is released and STO is
reset.
4301D–8051–02/08
RegistersTable 73. SSCON Register
SSCON - Synchronous Serial Control register (93h)
76543210
CR2SSIESTASTOSIAACR1CR0
AT89C51IC2
Bit
Number
7CR2
6SSIE
5STA
4ST0
3SI
2AA
1CR1
Bit
Mnemonic Description
Control Rate bit 2
See Table 67.
Synchronous Serial Interface Enable bit
Clear to disable SSLC.
Set to enable SSLC.
Start flag
Set to send a START condition on the bus.
Stop flag
Set to send a STOP condition on the bus.
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level
on SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on
SDA).
This bit has no effect when in master transmitter mode.
Control Rate bit 1
See Table 67.
4301D–8051–02/08
0CR0
Control Rate bit 0
See Table 67.
Table 74. SSDAT (095h) - Syncrhonous Serial Data register (read/write)
SD7SD6SD5SD4SD3SD2SD1SD0
76543210
Bit
Number
7SD7Address bit 7 or Data bit 7.
6SD6Address bit 6 or Data bit 6.
5SD5Address bit 5 or Data bit 5.
4SD4Address bit 4 or Data bit 4.
3SD3Address bit 3 or Data bit 3.
2SD2Address bit 2 or Data bit 2.
Bit
Mnemonic Description
99
Bit
Number
1SD1Address bit 1 or Data bit 1.
0SD0Address bit 0 (R/W) or Data bit 0.
Bit
Mnemonic Description
Table 75. SSCS (094h) read - Synchronous Serial Control and Status Register