ATMEL AT89C51IC2 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• 80C52 Compatible

–

8051 Pin and Instruction Compatible – Four 8-bit I/O ports + 2 I/O 2-wire Interface (TWI) Pins – Three 16-bit Timer/Counters – 256 bytes Scratch Pad RAM – 10 Interrupt Sources with 4 Priority Levels – Dual Data Pointer

• Variable Length MOVX for Slow RAM/Peripherals

• ISP (In-System-Programming) Using Standard V

• Boot ROM Contains Low Level Flash Programming Routines and a Default Serial

Loader

• High-speed Architecture

– In Standard Mode:

40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– In X2 mode (6 Clocks/machine cycle)

20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)

30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only) – 32K Bytes On-chip Flash Program/Data Memory – Byte and Page (128 Bytes) Erase and Write – 100K Write Cycles

• On-chip 1024 Bytes Expanded RAM (XRAM)

– Software Selectable Size (0, 256, 512, 768, 1024 Bytes) – 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility

• Keyboard Interrupt Interface on Port P1

• 400-Kbits/s Multimaster 2-wire Interface

• SPI Interface (Master/Slave Mode)

• Sub-clock 32 kHz Crystal Oscillator

• 8-bit clock Prescaler

• Improved X2 Mode With Independant Selection for CPU and Each Peripheral

• Programmable Counter Array 5 Channels with:

igh Speed Output

– H – Compare/Capture – Pulse Width Modulator – Watchdog Timer Capabilities

• Asynchronous Port Reset

• Full-duplex Enhanced UART

• Dedicated Baud Rate Generator for UART

• Low EMI (Inhibit ALE)

• Hardware Watchdog Timer (One-time enabled with Reset-Out)

• Power Control Modes:

– Idle Mode – Power-down Mode – Power-Off Flag

• Power Supply:

– 2.7 to 3.6 (3V Version) – 2.7 to 5.5V (5V Version)

• Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)

• Packages: PLC44, VQFP44

Power Supply

8-bit Flash Microcontroller with 2-wire Interface

AT89C51IC2

Rev. 4301D–8051–02/08

Description AT89C51IC2 is a high performance Flash version of the 80C51 8-bit microcontrollers. It

contains a 32K bytes Flash memory block for program and data.

The 32K bytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin.

The AT89C51IC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 10-source 4-level interrupt controller and three timer/counters.

In addition, the AT89C51IC2 has a 32 kHz Subsidiary clock Oscillator, a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a 2-wire interface, an SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode).

The fully static design of the AT89C51IC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.

The AT89C51IC2 has 2 software-selectable modes of reduced activity and 8-bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.

The added features of the AT89C51IC2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers.

Table 1. Memory Size

PLCC44

VQFP44 1.4 Flash (bytes) XRAM (bytes)

T89C51IC2 32k 1024 1280 34

TOTAL RAM

(bytes) I/O

AT89C51IC2

4301D–8051–02/08

Block Diagram

Timer 0

INT

RAM

256

RxD

TxD

XTAL2

XTAL1

EUART

CPU

Timer 1

INT1

Ctrl

INT0

C51

CORE

(2) (2) (2) (2)

Port 0

Port 1

IB-bus

Reset

Vss

Vcc

(2)(2)

Flash

32K x 8

ECI

PCA

(1)(1)

Port 2

PCA Timer 2

BRG

Port 3

Port 12

ALE/PROG

PSEN

(2)

Parallel I/O Ports & Ext Bus

Watch

Dog

Key

Board

SPI

(1)

SCK

(1)

MOSI

(1)

MISO

(1)

T2EX

(1)

Two-Wire

SDA

SCL

Figure 1. Block Diagram

AT89C51IC2

(1): Alternate function of Port 1

(2): Alternate function of Port 3

4301D–8051–02/08

SFR Mapping The Special Function Registers (SFRs) of the AT89C51IC2 fall into the following

categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP

• I/O port registers: P0, P1, P2, P3, PI2

• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON

• PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4)

• Power and clock control registers: PCON

• Hardware Watchdog Timer registers: WDTRST, WDTPRG

• Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1

• Keyboard Interface registers: KBE, KBF, KBLS

• SPI registers: SPCON, SPSTR, SPDAT

• 2-wire Interface registers: SSCON, SSCS, SSDAT, SSADR

• BRG (Baud Rate Generator) registers: BRL, BDRCON

• Flash register: FCON

• Clock Prescaler register: CKRL

• 32 kHz Sub Clock Oscillator registers: CKSEL, OSSCON

AT89C51IC2

4301D–8051–02/08

AT89C51IC2

Table 2. C51 Core SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

ACC E0h Accumulator

B F0h B Register

PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P

SP 81h Stack Pointer

DPL 82h Data Pointer Low byte

DPH 83h Data Pointer High byte

Table 3. System Management SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

PCON 87h Power Control SMOD1 SMOD0 - - GF1 GF0 PD IDL

AUXR 8Eh Auxiliary Register 0 - - M0 XRS1 XRS0

AUXR1 A2h Auxiliary Register 1 - -

CKRL 97h Clock Reload Register - - - - - - - -

CKSEL 85h Clock Selection Register - - - - - - - CKS

OSCON 86h Oscillator Control Register - - - - - SCLKT0 OscBEn OscAEn

CKCKON0 8Fh Clock Control Register 0 TWIX2 WDTX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

CKCKON1 AFh Clock Control Register 1 - - - - - - - SPIX2

ENBOO

- GF3 0 - DPS

EXTRA

Table 4. Interrupt SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0

IEN1 B1h Interrupt Enable Control 1 - - - - - ESPI ETWI KBD

IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PHS PT1H PX1H PT0H PX0H

IPL0 B8h Interrupt Priority Control Low 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L

IPH1 B3h Interrupt Priority Control High 1 - - - - - SPIH TWIH KBDH

IPL1 B2h Interrupt Priority Control Low 1 - - - - - SPIL TWIL KBDL

4301D–8051–02/08

Table 5. Port SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

P0 80h 8-bit Port 0

P1 90h 8-bit Port 1

P2 A0h 8-bit Port 2

P3 B0h 8-bit Port 3

Table 6. Timer SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

TCON 88h Timer/Counter 0 and 1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

TL0 8Ah Timer/Counter 0 Low Byte

TH0 8Ch Timer/Counter 0 High Byte

TL1 8Bh Timer/Counter 1 Low Byte

TH1 8Dh Timer/Counter 1 High Byte

WDTRST A6h WatchDog Timer Reset

WDTPRG A7h WatchDog Timer Program - - - - - WTO2 WTO1 WTO0

T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

T2MOD C9h Timer/Counter 2 Mode - - - - - - T2OE DCEN

RCAP2H CBh

RCAP2L CAh

TH2 CDh Timer/Counter 2 High Byte

TL2 CCh Timer/Counter 2 Low Byte

Timer/Counter 2 Reload/Capture High byte

Timer/Counter 2 Reload/Capture Low byte

Table 7. PCA SFRs

Mnemo

-nic Add Name 7 6 5 4 3 2 1 0

CCON D8h PCA Timer/Counter Control CF CR - CCF4 CCF3 CCF2 CCF1 CCF0

CMOD D9h PCA Timer/Counter Mode CIDL WDTE - - - CPS1 CPS0 ECF

CL E9h PCA Timer/Counter Low byte

CH F9h PCA Timer/Counter High byte

AT89C51IC2

4301D–8051–02/08

AT89C51IC2

Table 7. PCA SFRs (Continued)

Mnemo

-nic Add Name 7 6 5 4 3 2 1 0

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

DAh

PCA Timer/Counter Mode 0

DBh

PCA Timer/Counter Mode 1

DCh

PCA Timer/Counter Mode 2

DDh

PCA Timer/Counter Mode 3

DEh

PCA Timer/Counter Mode 4

FAh

PCA Compare Capture Module 0 H

FBh

PCA Compare Capture Module 1 H

FCh

PCA Compare Capture Module 2 H

FDh

PCA Compare Capture Module 3 H

FEh

PCA Compare Capture Module 4 H

EAh

PCA Compare Capture Module 0 L

EBh

PCA Compare Capture Module 1 L

ECh

PCA Compare Capture Module 2 L

EDh

PCA Compare Capture Module 3 L

EEh

PCA Compare Capture Module 4 L

CCAP0H7

CCAP1H7

CCAP2H7

CCAP3H7

CCAP4H7

CCAP0L7

CCAP1L7

CCAP2L7

CCAP3L7

CCAP4L7

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CCAP0H6

CCAP1H6

CCAP2H6

CCAP3H6

CCAP4H6

CCAP0L6

CCAP1L6

CCAP2L6

CCAP3L6

CCAP4L6

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CCAP0H5

CCAP1H5

CCAP2H5

CCAP3H5

CCAP4H5

CCAP0L5

CCAP1L5

CCAP2L5

CCAP3L5

CCAP4L5

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

CCAP0H4

CCAP1H4

CCAP2H4

CCAP3H4

CCAP4H4

CCAP0L4

CCAP1L4

CCAP2L4

CCAP3L4

CCAP4L4

MAT0

MAT1

MAT2

MAT3

MAT4

CCAP0H3

CCAP1H3

CCAP2H3

CCAP3H3

CCAP4H3

CCAP0L3

CCAP1L3

CCAP2L3

CCAP3L3

CCAP4L3

TOG0

TOG1

TOG2

TOG3

TOG4

CCAP0H2

CCAP1H2

CCAP2H2

CCAP3H2

CCAP4H2

CCAP0L2

CCAP1L2

CCAP2L2

CCAP3L2

CCAP4L2

PWM0

PWM1

PWM2

PWM3

PWM4

CCAP0H1

CCAP1H1

CCAP2H1

CCAP3H1

CCAP4H1

CCAP0L1

CCAP1L1

CCAP2L1

CCAP3L1

CCAP4L1

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

CCAP0H0

CCAP1H0

CCAP2H0

CCAP3H0

CCAP4H0

CCAP0L0

CCAP1L0

CCAP2L0

CCAP3L0

CCAP4L0

Table 8. Serial I/O Port SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

SBUF 99h Serial Data Buffer

SADEN B9h Slave Address Mask

SADDR A9h Slave Address

BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC

BRL 9Ah Baud Rate Reload

Table 9. SPI Controller SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPSTA C4h SPI Status SPIF WCOL SSERR MODF - - - -

SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0

4301D–8051–02/08

Table 10. Two-Wire Interface Controller SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SSCON 93h Synchronous Serial control SSCR2 SSPE SSSTA SSSTO SSI SSAA SSCR1 SSCR0

SSCS 94h Synchronous Serial Status SSC4 SSC3 SSC2 SSC1 SSC0 0 0 0

SSDAT 95h Synchronous Serial Data SSD7 SSD6 SSD5 SSD4 SSD3 SSD2 SSD1 SSD0

SSADR 96h Synchronous Serial Address SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSGC

Table 11. Keyboard Interface SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0

KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0

KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0

AT89C51IC2

4301D–8051–02/08

Table 12. SFR Mapping

Bit

addressable Non Bit addressable

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

AT89C51IC2

Table below shows all SFRs with their address and their reset value.

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

0000 0000

ACC

0000 0000

CCON

00X0 0000

PSW

0000 0000

T2CON

0000 0000

PI2 bit

addressable

XXXX XX11

IPL0

X000 000

1111 1111

0000 0000

CMOD

00XX X000

FCON (1)

XXXX 0000

T2MOD

XXXX XX00

SADEN

0000 0000

IEN1

XXXX X000

CCAP0H

XXXX XXXX

CCAP0L

XXXX XXXX

CCAPM0

X000 0000

RCAP2L

0000 0000

IPL1

XXXX X000

CCAP1H

XXXX XXXX

CCAP1L

XXXX XXXX

CCAPM1

X000 0000

RCAP2H

0000 0000

SPCON

0001 0100

IPH1

XXXX X111

CCAPL2H

XXXX XXXX

CCAPL2L

XXXX XXXX

CCAPM2

X000 0000

TL2

0000 0000

SPSTA

0000 0000

CCAPL3H

XXXX XXXX

CCAPL3L

XXXX XXXX

CCAPM3

X000 0000

TH2

0000 0000

SPDAT

XXXX XXXX

CCAPL4H

XXXX XXXX

CCAPL4L

XXXX XXXX

CCAPM4

X000 0000

IPH0

X000 0000

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

A8h

A0h

98h

90h

88h

80h

4301D–8051–02/08

IEN0

0000 0000

1111 1111

SCON

0000 0000

1111 1111

TCON

0000 0000

1111 1111

SADDR

0000 0000

SBUF

XXXX XXXX

TMOD

0000 0000

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

0000 0111

AUXR1

XXXX X0X0

BRL

0000 0000

TL0

0000 0000

DPL

0000 0000

BDRCON

XXX0 0000

SSCON

0000 0000

TL1

0000 0000

DPH

0000 0000

KBLS

0000 0000

SSCS

1111 1000

TH0

0000 0000

KBE

0000 0000

SSDAT

1111 1111

TH1

0000 0000

CKSEL

XXXX XXX0

WDTRST

XXXX XXXX

KBF

0000 0000

SSADR

1111 1110

AUXR

XX0X 0000

OSSCON

XXXX X001

CKCON1

XXXX XXX0

WDTPRG

XXXX X000

CKRL

1111 1111

CKCON0

0000 0000

PCON

00X1 0000

reserved

AFh

A7h

9Fh

97h

8Fh

87h

Pin Configurations

Figure 2. Pin Configurations

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7/CEx4/MOSI

RST

P3.0/RxD

PI2.1/SDA

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0 P3.5/T1

7 8

14 15

P1.4/CEX1

P1.3/CEX0

5 4 3 2 1 6

P1.1/T2EX/SS

P1.2/ECI

P1.0/T2/XTALB1

XTALB2

VCC

44 43 42 41 40

PLCC44

P0.0/AD0

18 19 23222120 262524 27 28

NIC*

VSS

XTAL2

XTAL1

P3.7/RD

P3.6/WR

P2.0/A8

P2.1/A9

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

PI2.0/SCL

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.2/A10

P2.3/A11

P2.4/A12

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7/CEX4/MOSI

AT89C51IC2

RST

P3.0/RxD

PI2.1/SDA

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P1.4/CEX1

P1.3/CEX0

43 42 41 40 3944 38 37 36 35 34

7 8

P1.0/T2/XTALB1

P1.1/T2EX/SS

P1.2/ECI

XTALB2

VQFP44 1.4

VCC

12 13 17161514 201918 21 22

VSS

NIC*

XTAL1

XTAL2

P3.7/RD

P3.6/WR

P2.0/A8

P0.0/AD0

P0.2/AD2

P0.3/AD3

P0.1/AD1

P0.4/AD4

33 32

P0.5/AD5

P0.6/AD6

P0.7/AD7

PI2.0/SCL

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.1/A9

P2.3/A11

P2.2/A10

P2.4/A12

4301D–8051–02/08

Table 13. Pin Description for 40/44 Pin Packages

AT89C51IC2

Pin Number

Mnemonic

P0.0 - P0.7 43 - 36 37 - 30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

P1.0 - P1.7 2 - 9 40 - 44

22 16 I Ground: 0V reference

44 38 I

1 - 3

2 40 I/O P1.0: Input/Output

3 41 I/O P1.1: Input/Output

Type

Name and FunctionPLCC44 VQFP44 1.4

Power Supply: This is the power supply voltage for normal, idle and power-down

operation

them float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes.

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification.

Alternate functions for AT89C51IC2 Port 1 include:

I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout

I XTALB1 (P1.0): Sub Clock input to the inverting oscillator amplifier

I T2EX: Timer/Counter 2 Reload/Capture/Direction Control

I SS

4 42 I/O P1.2: Input/Output

I ECI: External Clock for the PCA

5 43 I/O P1.3: Input/Output

I/O CEX0: Capture/Compare External I/O for PCA module 0

6 44 I/O P1.4: Input/Output

I/O CEX1: Capture/Compare External I/O for PCA module 1

7 1 I/O P1.5: Input/Output

I/O CEX2: Capture/Compare External I/O for PCA module 2

I/O MISO: SPI Master Input Slave Output line

8 2 I/O P1.6: Input/Output

I/O CEX3: Capture/Compare External I/O for PCA module 3

I/O SCK: SPI Serial Clock

: SPI Slave Select

When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller.

SCK outputs clock to the slave peripheral

4301D–8051–02/08

Table 13. Pin Description for 40/44 Pin Packages (Continued)

Pin Number

Mnemonic

9 3 I/O P1.7: Input/Output:

XTALA1 21 15 I

XTALA2 20 14 O Crystal A 2: Output from the inverting oscillator amplifier

XTALB1 2 40 I

XTALB2 1 39 O Crystal B 2: (Sub Clock) Output from the inverting oscillator amplifier

P2.0 - P2.7 24 - 31 18 - 25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that

Type

Name and FunctionPLCC44 VQFP44 1.4

I/O CEX4: Capture/Compare External I/O for PCA module 4

I/O MOSI: SPI Master Output Slave Input line

When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller.

Crystal A 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

Crystal B 1: (Sub Clock) Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification.

P3.0 - P3.7 11,

13 - 19

11 5 I RXD (P3.0): Serial input port

13 7 O TXD (P3.1): Serial output port

14 8 I INT0

15 9 I INT1 (P3.3): External interrupt 1

16 10 I T0 (P3.4): Timer 0 external input

17 11 I T1 (P3.5): Timer 1 external input

18 12 O WR (P3.6): External data memory write strobe

19 13 O RD (P3.7): External data memory read strobe

PI2.0 - PI2.1

34, 12 28, 6

34 28 I/O SCL (PI2.0): 2-wire Serial Clock

12 6 I/O SDA (PI2.1): 2-wire Serial Data

7 - 13

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below.

(P3.2): External interrupt 0

Port I2: Port I2 is an open drain. It can be used as inputs (must be polarized to Vcc

with external resistor to prevent any parasitic current consumption).

SCL output the serial clock to slave peripherals

SCL input the serial clock from master

AT89C51IC2

4301D–8051–02/08

Table 13. Pin Description for 40/44 Pin Packages (Continued)

AT89C51IC2

Pin Number

Mnemonic

RST 10 4 I/O

ALE/PROG 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

PSEN 32 26 O Program Strobe ENable: The read strobe to external program memory. When execut-

EA 35 29 I External Access Enable: EA must be externally held low to enable the device to fetch

Type

Name and FunctionPLCC44 VQFP44 1.4

SDA is the bidirectional 2-wire data line

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to V external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset.

address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches.

ing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.

code from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset.

permits a power-on reset using only an

4301D–8051–02/08

Oscillators

Overview Two oscillators are available for CPU:

• OSCA used for high frequency: Up to 48 MHz @5V +/- 10%

• OSCB used for low frequency: 32.768 kHz

Several operating modes are available and programmable by software:

• to switch OSCA to OSCB and vice-versa

• to stop OSCA or OSCB to reduce consumption

In order to optimize the power consumption and the execution time needed for a specific task, an internal prescaler feature has been implemented between the selected oscillator and the CPU.

Registers Table 14. CKSEL Register

CKSEL - Clock Selection Register (85h)

7 6 5 4 3 2 1 0

- - - - - - - CKS

Bit

Number

7 - Reserved

6 - Reserved

5 - Reserved

4 - Reserved

3 - Reserved

2 - Reserved

1 - Reserved

0 CKS

Bit

Mnemonic Description

CPU Oscillator Select Bit: (CKS)

Cleared, CPU and peripherals connected to OSCB

Set, CPU and peripherals connected to OSCA

Programmed by hardware after a Power-up regarding Hardware Security Byte (HSB).HSB.OSC (Default setting, OSCA selected)

Reset Value = 0000 000’HSB.OSC’b (see Hardware Security Byte (HSB) Table 84) Not bit addressable

AT89C51IC2

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AT89C51IC2

Table 15. OSCCON Register

OSCCON- Oscillator Control Register (86h)

7 6 5 4 3 2 1 0

- - - - - SCLKT0 OscBEn OscAEn

Bit

Number

7 - Reserved

6 - Reserved

5 - Reserved

4 - Reserved

3 - Reserved

2 SCLKT0

1 OscBEn

0 OscAEn

Bit

Mnemonic Description

Sub Clock Timer0

Cleared by software to select T0 pin

Set by software to select T0 Sub Clock

Cleared by hardware after a Power Up

OscB enable bit

Set by software to run OscB

Cleared by software to stop OscB

Programmed by hardware after a Power-up regarding HSB.OSC (Default cleared, OSCB stopped)

OscA enable bit

Set by software to run OscA

Cleared by software to stop OscA

Programmed by hardware after a Power-up regarding HSB.OSC(Default Set, OSCA runs)

4301D–8051–02/08

Reset Value = XXXX X0’HSB.OSC

’’HSB.OSC’b (see Hardware Security Byte (HSB) Table 84) Not bit addressable

Table 16. CKRL Register

CKRL - Clock Reload Register

7 6 5 4 3 2 1 0

- - - - - - - -

Bit

Number Mnemonic Description

7:0 CKRL

Clock Reload Register:

Prescaler value

Reset Value = 1111 1111b Not bit addressable

Table 17. PCON Register

PCON - Power Control Register (87h)

7 6 5 4 3 2 1 0

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit

Number

7 SMOD1

6 SMOD0

5 -

4 POF

3 GF1

2 GF0

1 PD

0 IDL

Bit

Mnemonic Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0

Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

General purpose Flag

Cleared by software for general purpose usage. Set by software for general purpose usage.

General purpose Flag

Cleared by software for general purpose usage. Set by software for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs. Set to enter power-down mode.

Idle mode bit

Cleared by hardware when interrupt or reset occurs. Set to enter idle mode.

Reset Value = 00X1 0000b Not bit addressable

AT89C51IC2

4301D–8051–02/08

Functional Block

XtalA2

XtalA1

XtalB1

XtalB2

OscBEn

OscB

OscA

CLK

Idle

CPU clock

OscAEn

CKS

CKRL

Reload

8-bit

Prescaler-Divider

Reset

Peripheral Clock

:128

Sub Clock

FOSCA

PERIPH

CPU

FOSCB

OSCCON

CKCON0

CKSEL

PwdOscA

PwdOscB

CKRL=0xFF?

Diagram

Figure 3. Functional Oscillator Block Diagram

AT89C51IC2

Operating Modes

Reset A hardware RESET puts the Clock generator in the following state:

The selected oscillator depends on OSC bit in Hardware Security Byte (HSB) (see HSB

Table 84)

Functional Modes

HSB.OSC = 1 (Oscillator A selected)

• OscAEn = 1 & OscBEn = 0: OscA is running, OscB is stopped.

• CKS = 1: OscA is selected for CPU.

HSB.OSC = 0 (Oscillator B selected)

• OscAEn = 0 & OscBEn = 1: OscB is running, OscA is stopped.

• CKS = 0: OscB is selected for CPU.

Normal Modes • CPU and Peripherals clock depend on the software selection using CKCON0,

CKCON1 and CKRL registers

• CKS bit in CKSEL register selects either OscA or OscB

• CKRL register determines the frequency of the OscA clock.

4301D–8051–02/08

• It is always possible to switch dynamically by software from OscA to OscB, and vice

versa by changing CKS bit.

Idle Modes • IDLE modes are achieved by using any instruction that writes into PCON.0 bit (IDL)

• IDLE modes A and B depend on previous software sequence, prior to writing into

PCON.0 bit:

• IDLE MODE A: OscA is running (OscAEn = 1) and selected (CKS = 1)

• IDLE MODE B: OscB is running (OscBEn = 1) and selected (CKS = 0)

• The unused oscillator OscA or OscB can be stopped by software by clearing

OscAEn or OscBEn respectively.

• IDLE mode can be canceled either by Reset, or by activation of any enabled

interruption

• In both cases, PCON.0 bit (IDL) is cleared by hardware

• Exit from IDLE modes will leave Oscillators control bits (OscEnA, OscEnB, CKS)

unchanged.

Power Down Modes • POWER DOWN modes are achieved by using any instruction that writes into

PCON.1 bit (PD)

• POWER DOWN modes A and B depend on previous software sequence, prior to

writing into PCON.1 bit:

• Both OscA and OscB will be stopped.

• POWER DOWN mode can be cancelled either by a hardware Reset, an external

interruption, or the keyboard interrupt.

• By Reset signal: The CPU will restart according to OSC bit in Hardware Security Bit

(HSB) register.

• By INT0 or INT1 interruption, if enabled: (standard behavioral), request on Pads

must be driven low enough to ensure correct restart of the oscillator which was selected when entering in Power down.

• By keyboard Interrupt if enabled: a hardware clear of the PCON.1 flag ensure the

restart of the oscillator which was selected when entering in Power down.

Table 18. Overview

AT89C51IC2

PCON.1 PCON.0 OscBEn OscAEn CKS Selected Mode Comment

0 0 0 1 1

0 0 1 1 1

0 0 1 0 0

0 0 1 1 0

X X 0 0 X INVALID

X X X 0 1 INVALID

X X 0 X 0 INVALID

NORMAL MODE A, OscB stopped

NORMAL MODE A, OscB running

NORMAL MODE B, OscA stopped

NORMAL MODE B, OscA running

Default mode after power-up or Warm Reset

Default mode after power-up or Warm Reset + OscB running

OscB running and selected

OscB running and selected + OscA running

OscA & OscB cannot be stopped at the same time

OscA must not be stopped, as used for CPU and peripherals

OscB must not be stopped as used for CPU and peripherals

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AT89C51IC2

Table 18. Overview (Continued)

PCON.1 PCON.0 OscBEn OscAEn CKS Selected Mode Comment

0 1 X 1 1 IDLE MODE A

0 1 1 X 0 IDLE MODE B

1 X X 1 X

POWER DOWN MODE

The CPU is off, OscA supplies the peripherals, OscB can be disabled (OscBEn = 0)

The CPU is off, OscB supplies the peripherals, OscA can be disabled (OscAEn = 0)

The CPU and peripherals are off, OscA and OscB are stopped

Design Considerations

Oscillators Control • PwdOscA and PwdOscB signals are generated in the Clock generator and used to

control the hard blocks of oscillators A and B.

• PwdOscA =’1’ stops OscA

• PwdOscB =’1’ stops OscB

• The following tables summarize the Operating modes:

PCON.1 OscAEn PwdOscA Comments

0 1 0 OscA running

1 X 1

0 0 1

OscA stopped by

Power-down mode

OscA stopped by

clearing OscAEn

PCON.1 OscBEn PwdOscB Comments

0 1 0 OscB running

1 X 1

0 0 1

Power-down mode

Prescaler Divider • A hardware RESET puts the prescaler divider in the following state:

– CKRL = FFh: F

CLK CPU

= F

CLK PERIPH

• CKS signal selects OSCA or OSCB: F

= F

OSCA

CLK OUT

/2 (Standard C51 feature)

= F

OSCA

or F

OSCB

• Any value between FFh down to 00h can be written by software into CKRL register

in order to divide frequency of the selected oscillator:

– CKRL = 00h: minimum frequency

CLK CPU

= F

CLK PERIPH

= F

CLK PERIPH

= F = F

/1020 (Standard Mode)

OSCA

/510 (X2 Mode)

OSCA

– CKRL = FFh: maximum frequency

CLK CPU

= F = F

CLK PERIPH

= F = F

/2 (Standard Mode)

OSCA

(X2 Mode)

OSCA

OscB stopped by

clearing OscBEn

4301D–8051–02/08

– F

CP U

CL KPE RIP H

OS CA

2 255 CKRL–( )×

----------------------------------------------

CP U

CL KPE RIP H

OS CA

4 255 CKRL–( )×

----------------------------------------------

SCLKT0

FCLK PERIPH

T0 pin

Sub Clock

C/T

OSCCON

TMOD

Gate

INT0

TR0

Timer 0

Control

CLK CPU

and F

CLK PERIPH

In X2 Mode:

In X1 Mode:

Timer 0: Clock Inputs Figure 4. Timer 0: Clock Inputs

, for CKRL<>0xFF

Note: The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock.

SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode)

SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use as periodic interrupt for time clock.

AT89C51IC2

4301D–8051–02/08

AT89C51IC2

XTALA1

CKCON0

8 bit Prescaler

OSCA

XTAL

XTALA1:2

CLK CPU

CLK PERIPH

CKSEL

CKS

OSCB

CKRL

0 1

Enhanced Features In comparison to the original 80C52, the AT89C51IC2 implements some new features,

which are:

• The X2 option

• The Dual Data Pointer

• The extended RAM

• The Programmable Counter Array (PCA)

• The Hardware Watchdog

• The SPI interface

• The 2-wire interface

• The 4 level interrupt priority system

• The power-off flag

• The Power On Reset

• The ONCE mode

• The ALE disabling

• Some enhanced features are also located in the UART and the timer 2

X2 Feature and OSCA Clock Generation

The AT89C51IC2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages:

• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

• Save power consumption while keeping same CPU power (oscillator power saving).

• Save power consumption by dividing dynamically the operating frequency by 2 in

operating and idle modes.

• Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTALA1 signal and the main clock input of the core (phase generator). This divider may be disabled by software.

Description The clock for the whole circuit and peripherals is first divided by two before being used

by the CPU core and the peripherals.

This allows any cyclic ratio to be accepted on XTALA1 input. In X2 mode, as this divider is bypassed, the signals on XTALA1 must have a cyclic ratio between 40 to 60%.

Figure 5. shows the clock generation block diagram.x2 bit is validated on the rising edge of the XTALA1÷2 to avoid glitches when switching from X2 to STD mode. Figure 6. shows the switching mode waveforms.

Figure 5. Clock Generation Diagram

4301D–8051–02/08

Figure 6. Mode Switching Waveforms

XTALA1:2

XTALA1

CPU clock

X2 bit

X2 ModeSTD Mode STD Mode

OSCA

The X2 bit in the CKCON0 register (see Table 19) allow to switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is setting according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is actived. Setting the X2 bit activates the X2 feature (X2 mode).

The T0X2, T1X2, T2X2, UartX2, PcaX2, WdX2 and I2CX2 bits in the CKCON0 register (See Table 19.) and SPIX2 bit in the CKCON1 register (see Table 20) allow to switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode.

More information about the X2 mode can be found in the application note "How to take advantage of the X2 features in TS80C51 microcontroller?"

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AT89C51IC2

Table 19. CKCON0 Register

CKCON0 - Clock Control Register (8Fh)

7 6 5 4 3 2 1 0

SPIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit

Number

7 I2CX2

6 WDX2

5 PCAX2

4 SIX2

3 T2X2

2 T1X2

Bit

Mnemonic Description

2-wire clock (This control bit is validated when the CPU clock X2 is set; when

X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

4301D–8051–02/08

Timer0 clock (This control bit is validated when the CPU clock X2 is set; when

1 T0X2

0 X2

X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

CPU clock

Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals.

Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits.

Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is cleared.

Reset Value = 0000 000’HSB.X2’b Not bit addressable

Table 20. CKCON1 Register

CKCON1 - Clock Control Register (AFh)

7 6 5 4 3 2 1 0

- - - - - - - SPIX2

Bit

Number

7 - Reserved

6 - Reserved

5 - Reserved

4 - Reserved

3 - Reserved

2 - Reserved

1 - Reserved

0 SPIX2

Bit

Mnemonic Description

SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Reset Value = XXXX XXX0b Not bit addressable

AT89C51IC2

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AT89C51IC2

External Data Memory

AUXR1(A2H)

DPS

DPH(83H) DPL(82H)

DPTR0

DPTR1

Dual Data Pointer Register

Figure 7. Use of Dual Pointer

The additional data pointer can be used to speed up code execution and reduce code size.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 21) that allows the program code to switch between them (Refer to Figure 7).

Table 21. AUXR1 register

AUXR1- Auxiliary Register 1(0A2h)

7 6 5 4 3 2 1 0

- - ENBOOT - GF3 0 - DPS

Bit

Number

7 -

6 -

5 ENBOOT

4 -

3 GF3 This bit is a general purpose user flag.*

2 0 Always cleared.

1 -

0 DPS

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Enable Boot Flash

Cleared to disable boot rom.

Set to map the boot rom between F800h - 0FFFFh.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Cleared to select DPTR0. Set to select DPTR1.

4301D–8051–02/08

Reset Value: XXXX XX0X0b Not bit addressable

Note: *Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

ASSEMBLY LANGUAGE ; Block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

AT89C51IC2

4301D–8051–02/08

AT89C51IC2

XRAM

Upper

128 bytes

Internal

Ram

Lower

128 bytes

Internal

Ram

Special Function Register

80h 80h

0FFh or 3FFh

0FFh

External

Data

Memory

0000

00FFh up to 03FFh

0FFFFh

indirect accesses

direct accesses

direct or indirect

accesses

7Fh

Expanded RAM (XRAM)

The AT89C51IC2 provides additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage.

AT89C51IC2 devices have expanded RAM in external data space; maximum size and location are described in Table 22.

Table 22. Expanded RAM

Address

XRAM size

AT89C51IC2 1024 00h 3FFh

Start End

The AT89C51IC2 h as inte rnal da ta memo ry that is mapped into f our sep arate segments.

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable only.

4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register (see Table 22)

The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space.

Figure 8. Internal and External Data Memory Address

When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.

• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2).

4301D–8051–02/08

• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h).

• The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table 22. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM.

• With EXTRAM = 0, combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the use of DPTR.

• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD).

the XRAM is indirectly addressed, using the MOVX instruction in

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM.

The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are exten ded from 6 to 30 clock periods. This is useful to access external slow peripherals.

AT89C51IC2

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AT89C51IC2

Table 23. AUXR Register

AUXR - Auxiliary Register (8Eh)

7 6 5 4 3 2 1 0

- - M0 - XRS1 XRS0 EXTRAM AO

Bit

Number

7 -

6 -

5 M0

4 -

3 XRS1 XRAM Size

2 XRS0

1 EXTRAM

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Pulse length

Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods (default).

Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock periods.

Reserved

The value read from this bit is indeterminate. Do not set this bit

XRS1 0 0 256 bytes (default)

0 1 512 bytes

1 0 768 bytes

1 1 1024 bytes

EXTRAM bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected.

XRS0 XRAM size

4301D–8051–02/08

ALE Output bit

0 AO

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) (default) Set, ALE is active only during a MOVX or MOVC instruction is used.

Reset Value = XX0X 00’HSB.XRAM’0b Not bit addressable

Timer 2 The Timer 2 in the AT89C51IC2 is the standard C52 the Timer 2.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is controlled by T2CON (Table 24) and T2MOD (Table 25) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2

Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes.

Timer 2 includes the following enhancements:

• Auto-reload mode with up or down counter

• Programmable clock-output

(T2CON).

Auto-Reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto-

matic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 9. In this mode the T2EX pin controls the direction of count.

When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

OSC

/12

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when timer 2 overflows or underflows according to the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.

AT89C51IC2

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+ 116 hidden pages