ATMEL AT89C51RD2, AT89C51ED2 User Manual
Features
• 80C52 Compatible
– 8051 Instruction Compatible
– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
• Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
• ISP (In-System Programming) Using Standard V
• 2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Loader
• High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
• 64K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100k Write Cycles
• On-chip 1792 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes)
– 768 Bytes Selected at Reset for T89C51RD2 Compatibility
• On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
– 100K Write Cycles
• Dual Data Pointer
• Variable Length MOVX for Slow RAM/Peripherals
• Improved X2 Mode with Independent Selecti on for CPU and Each Peripheral
• Keyboard Interrupt Interface on Port 1
• SPI Interface (Master/Slave Mode)
• 8-bit Clock Prescaler
• 16-bit Programmable Counter Array
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
• Asynchronous Port Reset
• Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator
• Low EMI (Inhibit ALE)
• Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag
• Power Control Modes: Idle Mode, Power-down Mode
• Single Range Power Supply: 2.7V to 5.5V
• Industrial Temperature Range (-40 to +85°C)
• Packages: PLCC44, VQFP44, PLCC68, VQFP64, PDIL40
Power Supply
CC
8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2
Description
A T89C51RD2/ED2 is high p erformance CMOS Flash version o f the 80C51 CMOS single chip 8-bit microcontroller. It contains a 64-Kbyte Flash memory block for c ode and
for data.
The 64-Kbytes Flash memory can be programmed either in parallel mode or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard V
CC
pin.
Rev. 4235G–8051–08/05
1
The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of
internal RAM, a 9-source 4-level interrupt controller and three timer/counters. The
AT89C51ED2 provides 2048 bytes of EEPROM for nonvolatile data storage.
In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of
1792 bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile
serial channel that facilitates multiprocessor communication (EUART) and a speed
improvement mechanism (X2 Mode).
The fully static design of the AT89C51RD2/ED2 allows to reduce system power consumption by bringing the clock frequency down to any value, including DC, without loss
of data.
The AT89C51RD2/ED2 has 2 software-selectable modes of reduced activity and an 8bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU
is frozen while the peripherals and the interrupt system are still operating. In the Powerdown mode the RAM is saved and all other functions are inoperative.
The added features of the AT89C51RD2/ED2 make it more powerful for applications
that need pulse width modulation, high speed I/O and counting capabilities such as
alarms, motor control, corded phones, and smart card readers.
Table 1. Memory Size and I/O Pins
Package Flash (Bytes) XRAM (Bytes) Total RAM (Bytes) I/O
PLCC44/VQFP44/DIL40 64K 1792 2048 34
PLCC68/VQFP64 64K 1792 2048 50
2
AT89C51RD2/ED2
4235G–8051–08/05
Block Diagram
Figure 1. Block Diagram
RxD
TxD
AT89C51RD2/ED2
VSS
VCC
ECI
PCA
T2EX
T2
Keyboard
XTALA1
XTALA2
ALE/
PROG
PSEN
EA
RD
WR
(2)
(2)
CPU
RESET
(2)(2)
C51
CORE
T1
RAM
256x8
INT
Ctrl
INT0
EUART
Timer 0
Timer 1
(2) (2) (2) (2)
T0
Flash
64K x 8
IB-bus
Parallel I/O Ports &
External Bus
Port 1
P0
Port 2
P1
Port 0
INT1
(1): Alternate function of Port 1
(2): Alternate function of Port 3
XRAM
1792 x 8
Port 3
P2
(1)
Port4
P3
PCA
P4
(1)
Port 5
P5
(1) (1)
Timer2
(1)
Keyboard
SPI
(1)
(1)
(1)
SCK
MOSI
MISO
(1)
SS
Watch
-dog
BOOT
2K x 8
ROM
EEPROM*
2K x 8
(AT89C51ED2)
Regulator
POR / PFD
4235G–8051–08/05
3
SFR Mapping The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following
categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP
• I/O port registers: P0, P1, P2, P3, PI2
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 to 4)
• Power and clock control registers: PCON
• Hardware Watchdog Timer registers: WDTRST, WDTPRG
• Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• SPI registers: SPCON, SPSTR, SPDAT
• BRG (Baud Rate Generator) registers: BRL, BDRCON
• Clock Prescaler register: CKRL
• Others: AUXR, AUXR1, CKCON0, CKCON1
4
AT89C51RD2/ED2
4235G–8051–08/05
AT89C51RD2/ED2
Table 2. C51 Core SFRs
MnemonicAddName 76543210
ACC E0h Accumulator
B F0h B Register
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stack Pointer
DPL 82h Data Pointer Low Byte
DPH 83h Data Pointer High Byte
Table 3. System Management SFRs
MnemonicAddName 76543210
PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
AUXR1 A2h Auxiliary Register 1 - CKRL 97h Clock Reload Register -------CKCKON0 8Fh Clock Control Register 0 - WDTX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
CKCKON1AFhClock Control Register 1 -------SPIX2
ENBOOT
-GF30 -DPS
Table 4. Interrupt SFRs
MnemonicAddName 76543210
IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1 B1h Interrupt Enable Control 1 -----ESPI KBD
IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PHS PT1H PX1H PT0H PX0H
IPL0 B8h Interrupt Priority Control Low 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L
IPH1 B3hInterrupt Priority Control High 1-----SPIH KBDH
IPL1 B2hInterrupt Priority Control Low 1-----SPIL KBDL
Table 5. Port SFRs
MnemonicAddName 76543210
P0 80h 8-bit Port 0
P1 90h 8-bit Port 1
P2 A0h 8-bit Port 2
P3 B0h 8-bit Port 3
P4 C0h 8-bit Port 4
4235G–8051–08/05
5
Table 5. Port SFRs
MnemonicAddName 76543210
P5 D8h 8-bit Port 5
P5 C7h 8-bit Port 5 (byte addressable)
Table 6. Timer SFRs
MnemonicAddName 76543210
TCON 88h Timer/Counter 0 and 1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
TL0 8Ah Timer/Counter 0 Low Byte
TH0 8Ch Timer/Counter 0 High Byte
TL1 8Bh Timer/Counter 1 Low Byte
TH1 8Dh
WDTRST A6h WatchDog Timer Reset
WDTPRGA7hWatchDog Timer Program -----WTO2WTO1WTO0
T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MOD C9h Timer/Counter 2 Mode ------T2OEDCEN
RCAP2H CBh
RCAP2L CAh
TH2 CDh Timer/Counter 2 High Byte
TL2 CCh Timer/Counter 2 Low Byte
Timer/Counter 1 High Byte
Timer/Counter 2 Reload/Capture
High Byte
Timer/Counter 2 Reload/Capture
Low Byte
Table 7. PCA SFRs
Mnemo
-nicAddName 76543210
CCON D8h PCA Timer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA Timer/Counter Mode CIDL WDTE CPS1 CPS0 ECF
CL E9h PCA Timer/Counter Low Byte
CH F9h PCA Timer/Counter High Byte
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
6
DAh
PCA Timer/Counter Mode 0
DBh
PCA Timer/Counter Mode 1
DCh
PCA Timer/Counter Mode 2
DDh
PCA Timer/Counter Mode 3
DEh
PCA Timer/Counter Mode 4
AT89C51RD2/ED2
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
4235G–8051–08/05
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
AT89C51RD2/ED2
Table 7. PCA SFRs (Continued)
Mnemo
-nicAddName 76543210
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
FAh
PCA Compare Capture Module 0 H
FBh
PCA Compare Capture Module 1 H
FCh
PCA Compare Capture Module 2 H
FDh
PCA Compare Capture Module 3 H
FEh
PCA Compare Capture Module 4 H
EAh
PCA Compare Capture Module 0 L
EBh
PCA Compare Capture Module 1 L
ECh
PCA Compare Capture Module 2 L
EDh
PCA Compare Capture Module 3 L
EEh
PCA Compare Capture Module 4 L
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
Table 8. Serial I/O Port SFRs
MnemonicAddName 76543210
SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADEN B9h Slave Address Mask
SADDR A9h Slave Address
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC
BRL 9Ah Baud Rate Reload
Table 9. SPI Controller SFRs
MnemonicAddName 76543210
SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPSTA C4h SPI Status SPIF WCOL SSERR MODF
SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
Table 10. Keyboard Interface SFRs
MnemonicAddName 76543210
KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Table 11. EEPROM data Memory SFR (AT89C51ED2 only)
MnemonicAddName 76543210
EECON D2h EEPROM Data Control EEE EEBUSY
4235G–8051–08/05
7
Table 12. SFR Mapping
Bit
Addressable Non Bit Addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Table 12 shows all SFRs with their address and their reset value.
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
B
0000 0000
P5 bit
addressable
1111 1111
ACC
0000 0000
CCON
00X0 0000
PSW
0000 0000
T2CON
0000 0000
P4
1111 1111
IPL0
X000 000
P3
1111 1111
CH
0000 0000
CL
0000 0000
CMOD
00XX X000
FCON
XXXX 0000
T2MOD
XXXX XX00
SADEN
0000 0000
IEN1
XXXX X000
CCAP0H
XXXX XXXX
CCAP0L
XXXX XXXX
CCAPM0
X000 0000
EECON
xxxx xx00
RCAP2L
0000 0000
IPL1
XXXX X000
CCAP1H
XXXX XXXX
CCAP1L
XXXX XXXX
CCAPM1
X000 0000
RCAP2H
0000 0000
SPCON
0001 0100
IPH1
XXXX X111
CCAP2H
XXXX XXXX
CCAP2L
XXXX XXXX
CCAPM2
X000 0000
TL2
0000 0000
SPSTA
0000 0000
CCAP3H
XXXX XXXX
CCAP3L
XXXX XXXX
CCAPM3
X000 0000
TH2
0000 0000
SPDAT
XXXX XXXX
CCAP4H
XXXX XXXX
CCAP4L
XXXX XXXX
CCAPM4
X000 0000
P5 byte
Addressable
1111 1111
IPH0
X000 0000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
A8h
A0h
98h
90h
88h
80h
IEN0
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
SADDR
0000 0000
SBUF
XXXX XXXX
TMOD
0000 0000
SP
0000 0111
AUXR1
0XXX X0X0
BRL
0000 0000
TL0
0000 0000
DPL
0000 0000
BDRCON
XXX0 0000
TL1
0000 0000
DPH
0000 0000
KBLS
0000 0000
TH0
0000 0000
KBE
0000 0000
TH1
0000 0000
WDTRST
XXXX XXXX
KBF
0000 0000
AUXR
XX00 1000
CKCON1
XXXX XXX0
WDTPRG
XXXX X000
CKRL
1111 1111
CKCON0
0000 0000
PCON
00X1 0000
AFh
A7h
9Fh
97h
8Fh
87h
reserved
8
AT89C51RD2/ED2
4235G–8051–08/05
Pin Configurations
Figure 2. Pin Configurations
AT89C51RD2/ED2
P1.0/T2
P1.1/T2EX/SS
P1.2/ECI
P1.3CEX0
P1.4/CEX1
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7CEX4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
1
2
3
4
5
6
7
8
9
10
AT89C51ED2
11
PDIL40
12
13
14
15
16
17
18
19
20
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NIC*
P1.0/T2
P1.1/T2EX/SS
44 43 42 41 40
PLCC44
VCC
7
8
9
10
11
12
13
14
15
16
17
P1.4/CEX1
P1.3/CEX0
P1.2/ECI
5 4 3 2 1 6
A T89C51RD2/ED2
18 19 23222120 262524 27 28
NIC*
VSS
XTAL2
P3.6/WR
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE/PROG
PSEN
P2.7/AD15
P2.6/AD14
P2.5/AD13
P2.4/AD12
P2.3/AD11
P2.2/AD10
P2.1/AD9
P2.0/AD8
P3.7/RD
XTAL1
P2.0/A8
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
P3.2/INT0
P0.0/AD0
P0.1/AD1
P2.1/A9
P2.2/A10
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.3/INT1
P3.4/T0
P3.5/T1
P0.2/AD2
P2.3/A11
P0.3/AD3
39
P0.4/AD4
38
P0.5/AD5
37
P0.6/AD6
36
P0.7/AD7
35
EA
34
NIC*
33
ALE/PROG
32
PSEN
31
P2.7/A15
30
P2.6/A14
29
P2.5/A13
P2.4/A12
1
2
3
4
5
6
7
8
9
10
11
P1.4/CEX1
43 42 41 40 3944
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
A T89C51RD2/ED2
VQFP44 1.4
1213 17161514 201918 2122
VSS
XTAL1
XTAL2
P3.7/RD
P3.6/WR
NIC*
VCC
P0.0/AD0
P0.1/AD1
38 37 36 35 34
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P0.2/AD2
P0.3/AD3
P0.4/AD4
33
32
P0.5/AD5
31
P0.6/AD6
30
P0.7/AD7
29
EA
28
NIC*
27
ALE/PROG
26
PSEN
25
P2.7/A15
24
P2.6/A14
23
P2.5/A13
P2.3/A11
P2.4/A12
4235G–8051–08/05
9
P0.4/AD4
PSEN
NIC
P2.7/A15
P2.6/A14
P5.2
P5.1
P3.2/INT0
P3.3/INT1
P2.5/A13
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
P3.4/T0
P3.5/T1
P5.0
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
P2.0/A8
P4.6
NIC
VSS
P4.5
XTAL1
XTAL2
P3.7/RD
P4.4
P3.6/WR
P4.3
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
NIC
P0.7/AD7EANIC
ALE
98765
10
P5.5
P5.6
P5.7
VCC
NIC
P4.0
P4.1
P4.2
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
P1.0/T2
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
272829303132333435
P1.6/CEX3/SCK
P1.5/CEX2/MISO
P1.7/CEX4/MOSI
P5.4
P5.3
P0.5/AD5
P0.6/AD6
P0.7/AD7EANIC
ALE
PSEN#
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
P5.0
321
4
A T89C51ED2
PLCC68
NIC
NIC
NIC
RST
P3.0/RxD
68
6765646362
66
37383940414243
36
NIC
NIC
NIC
NIC
P3.1/TxD
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2
P4.0
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
646362616059585756
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
171819202122232425
P4.2
P1.6/CEX3/SCK
P1.5/CEX2/MISO
P1.7/A17/CEX4/MOSI
55
A T89C51ED2
VQFP64
26
NIC
NIC
NIC
RST
NIC
P3.0/RxD
5453525150
2728293031
NIC
P3.1/TxD
P3.3/INT1
P3.2/INT0
P3.4/T0
49
32
P3.5/T1
48
P2.4/A12
47
P2.3/A11
46
P4.7
45
P2.2/A10
44
P2.1/A9
43
P2.0/A8
42
P4.6
41
NIC
40
VSS
39
P4.5
38
XTAL1
37
XTAL2
36
P3.7/RD
35
P4.4
34
P3.6/WR
33
P4.3
NIC: Not Internaly Connected
10
AT89C51RD2/ED2
4235G–8051–08/05
Table 13. Pin Description
AT89C51RD2/ED2
Mnemonic
V
SS
V
CC
P0.0 - P0.7 43 - 36 37 - 30
P1.0 - P1.7 2 - 9 40 - 44
22 16 51 40 20 I Ground: 0V reference
44 38 17 8 40 I
1 - 3
2 40 19 10 1 I/O P1.0: Input/Output
Pin Number
15, 14,
12, 11,
9,6, 5, 3
19, 21,
22, 23,
25, 27,
28, 29
6, 5, 3,
2, 64,
61,60,59
10, 12,
13, 14,
16, 18,
19, 20
32-39
1-8
Type
Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
Power Supply: This is the power supply voltage for normal, idle and
power-down operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 must be polarized to V
current consumption. Port 0 is also the multiplexed low-order address
I/O
and data bus during access to external program and data memory. In this
application, it uses strong internal pull-up when emitting 1s. Port 0 also
inputs the code bytes during EPROM programming. External pull-ups are
required during program verification during which P0 outputs the code
bytes.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
I/O
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally
pulled low will source current because of the internal pull-ups. Port 1 also
receives the low-order address byte during memory programming and
verification.
Alternate functions for AT89C51RD2/ED2 Port 1 include:
I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
or VSS in order to prevent any parasitic
CC
3 41 21 12 2 I/O P1.1: Input/Output
I T2EX: Timer/Counter 2 Reload/Capture/Direction Control
I SS
: SPI Slave Select
4 42 22 13 3 I/O P1.2: Input/Output
I ECI: External Clock for the PCA
5 43 23 14 4 I/O P1.3: Input/Output
I/O CEX0: Capture/Compare External I/O for PCA module 0
6 44 25 16 5 I/O P1.4: Input/Output
I/O CEX1: Capture/Compare External I/O for PCA module 1
7 1 27 18 6 I/O P1.5: Input/Output
I/O CEX2: Capture/Compare External I/O for PCA module 2
I/O MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller.
8 2 28 19 7 I/O P1.6: Input/Output
I/O CEX3: Capture/Compare External I/O for PCA module 3
I/O SCK: SPI Serial Clock
4235G–8051–08/05
11
Table 13. Pin Description (Continued)
Pin Number
Mnemonic
9 3 29 20 8 I/O P1.7: Input/Output:
XTALA1 21 15 49 38 19 I
XTALA2 20 14 48 37 18 O XTALA 2: Output from the inverting oscillator amplifier
43, 44,
45, 47,
48, 50,
53, 54
25, 28,
29, 30,
31, 32,
34, 36
21-28
10-17
P2.0 - P2.7 24 - 31 18 - 25
P3.0 - P3.7 11,
13 - 195,7 - 13
54, 55,
56, 58,
59, 61,
64, 65
34, 39,
40, 41,
42, 43,
45, 47
Type
Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
I/O CEX4: Capture/Compare External I/O for PCA module 4
I/O MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral.
When SPI is in slave mode, MOSI receives data from the master controller.
XTALA 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 2 pins that are externally
pulled low will source current because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program
I/O
memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
I/O
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below.
115342510IRXD (P3.0): Serial input port
13 7 39 28 11 O TXD (P3.1): Serial output port
148402912IINT0
159413013IINT1
16 10 42 31 14 I T0 (P3.4): Timer 0 external input
17 11 43 32 15 I T1 (P3.5): Timer 1 external input
18 12 45 34 16 O WR
19 13 47 36 17 O RD
20, 24,
P4.0 - P4.7
P5.0 - P5.7
RST 10 4 30 21 9 I
--
--
26, 44,
46, 50,
53, 57
60, 62,
63, 7, 8,
10, 13,
16
11, 15,
17,33,
35,39,
42, 46
49, 51,
52, 62,
63, 1, 4,
7
- I/O
- I/O
(P3.2): External interrupt 0
(P3.3): External interrupt 1
(P3.6): External data memory write strobe
(P3.7): External data memory read strobe
Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
Reset: A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to V
power-on reset using only an external capacitor to V
put when the hardware watchdog forces a system reset.
CC
permits a
SS
. This pin is an out-
12
AT89C51RD2/ED2
4235G–8051–08/05
Table 13. Pin Description (Continued)
AT89C51RD2/ED2
Pin Number
Mnemonic
ALE/PRO
G
PSEN 32 26 67 55 29 O Program Strobe ENable: The read strobe to external program memory.
EA 35 29 2 58 31 I External Access Enable: EA
33 27 68 56 30 O (I)
Type
Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
Address Latch Enable/Program Pulse: Output pulse for latching the
low byte of the address during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
oscillator frequency, and can be used for external timing or clocking. Note
that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG
gramming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this
bit set, ALE will be inactive during internal fetches.
When executing code from the external program memory, PSEN
vated twice each machine cycle, except that two PSEN
skipped during each access to external data memory. PSEN
vated during fetches from internal program memory.
must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH. If security level 1 is programmed, EA
Reset.
) during Flash pro-
activations are
will be internally latched on
is acti-
is not acti-
4235G–8051–08/05
13
Port Types AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional out-
put that is common on the 80C51 and most of its derivatives. This output type can be
used as both an input and output without the need to reconfigure the port. This is possible because when the port output s a logic high, it is weakly driven, a llowing an ex ternal
device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink
a fairly large current. These features are somewhat similar to an open drain output
except that there are three pull-up transistors in the quasi-bidirectional output that serv e
different purposes. One of these pull-ups, called the "weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. The weak pull-up sources a very sm all
current that will pull the pin high if it is left floating. A second pull-up, called the "medium"
pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is
also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by a n
external device, the medium pull-up turns off, and only the weak pull-up remains on. In
order to pull the pin low under these conditions, the external device has to sink enough
current to overpower the medium pull-up and take the voltage on the port pin below its
input threshold.
The third pull-up is referred to as the "strong" pull-up. T his pull-up is used to speed u p
low-to-high transitions on a quasi-bidirectional port pin when the p ort latch chang es from
a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time, two
CPU clocks, in order to pull the port pin high quickly. Then it turns off again.
The DPU bit (bit 7 in AUXR register) allows to disable the permanent weak pull up of all
ports when latch data is logical 0.
The quasi-bidirectional port configuration is shown in Figure 3.
Figure 3. Quasi-Bidirectional Output
Port Latch
Data
2 CPU
Clock Delay
Input
Data
P
N
Strong
PP
Weak
DPU
AUXR.7
Medium
Pin
14
AT89C51RD2/ED2
4235G–8051–08/05
AT89C51RD2/ED2
Oscillator To optimize the power consumption and execution time needed for a specific task, an
internal prescaler feature has been implemented between the oscillator and the CPU
and peripherals.
Registers Table 14. CKRL Register
CKRL – Clock Reload Register (97h)
76543210
CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Mnemonic Description
7:0 CKRL
Clock Reload Register
Prescaler value
Reset Value = 1111 1111b
Not bit addressable
Table 15. PCON Register
PCON – Power Control Register (87h)
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemonic Description
7SMOD1
6SMOD0
5-
4POF
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial Port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Cleared by software to recognize the next reset type.
Set by hardware when V
also be set by software.
rises from 0 to its nominal voltage. Can
CC
4235G–8051–08/05
General-purpose Flag
3GF1
2GF0
1PD
0IDL
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
General-purpose Flag
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
Power-down Mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle Mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b Not bit addressable
15
Functional Block Diagram
Figure 4. Functional Oscillator Block Diagram
Reload
8-bit
Prescaler-Divider
1
0
CKRL = 0xFF?
CLK
Periph
CLK
CPU
Idle
Xtal1
Xtal2
Osc
Reset
CKRL
F
OSC
1
:2
0
X2
CKCON0
Prescaler Divider • A hardware RESET puts the prescaler divider in the following state:
• CKRL = FFh: F
CLK CPU
= F
CLK PERIPH
= F
/2 (Standard C51 feature)
OSC
• Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
• CKRL = 00h: minimum frequency
F
CLK CPU
F
CLK CPU
= F
CLK PERIPH
= F
CLK PERIPH
= F
= F
/1020 (Standard Mode)
OSC
/510 (X2 Mode)
OSC
• CKRL = FFh: maximum frequency
F
CLK CPU
F
CLK CPU
F
CLK CPU
and F
= F
CLK PERIPH
= F
CLK PERIPH
CLK PERIPH
= F
= F
/2 (Standard Mode)
OSC
(X2 Mode)
OSC
Peripheral Clock
CPU Clock
16
In X2 Mode, for CKRL<>0xFF:
F
CPU
F=
In X1 Mode, for CKRL<>0xFF then:
F
CPU
F=
AT89C51RD2/ED2
CLKPERIPH
CLKPERIPH
-----------------------------------------------=
2 255 CKRL–()×
-----------------------------------------------=
4 255 CKRL–()×
F
F
OSC
OSC
4235G–8051–08/05
AT89C51RD2/ED2
Enhanced Features In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new fea-
tures, which are
• X2 option
• Dual Data Pointer
• Extended RAM
• Programmable Counter Array (PCA)
• Hardware Watchdog
• SPI interface
• 4-level interrupt priority system
• Power-off flag
• ONCE mode
• ALE disabling
• Some enhanced features are also located in the UART and the Timer 2
X2 Feature The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
:
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description The clock for the whole circuit and peripherals is first divided by two before being used
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 5 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1 ÷ 2 to avoid glitches when switching from X2 to STD mode. Figure 6
shows the switching mode waveforms.
Figure 5. Clock Generation Diagram
CKRL
F
X2
OSC
0
1
8-bit Prescaler
F
CLK CPU
F
CLK PERIPH
XTAL1
FXTAL
XTAL1:2
2
CKCON0
4235G–8051–08/05
17
Figure 6. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 Bit
CPU Clock
The X2 bit in the CKCON0 register (see Table 16) allows a switch from 12 clock periods
per instruction to 6 clock periods and vice versa. At reset, the speed is set according to
X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the
X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (Table
16) and SPIX2 bit in the CKCON1 register (see Table 17) allows a switch from standard
peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6
clock periods per peripheral clock cycle). These bits are active only in X2 mode.
F
OSC
X2 ModeSTD Mode STD Mode
18
AT89C51RD2/ED2
4235G–8051–08/05
AT89C51RD2/ED2
Table 16. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
76543210
- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number
7 Reserved The values for this bit are indeterminite. Do not set this bit.
6WDX2
5 PCAX2
4SIX2
3T2X2
Bit
Mnemonic Description
Watchdog Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2)
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Timer2 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 Clock
2T1X2
1T0X2
0X2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Timer0 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode)
and to enable the individual peripherals’X2’ bits. Programmed by hardware after
Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is
cleared.
Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”)
Not bit addressable
4235G–8051–08/05
19
Table 17. CKCON1 Register
CKCON1 - Clock Control Register (AFh)
76543210
-------SPIX2
Bit
Number
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2-Reserved
1-Reserved
0 SPIX2
Bit
Mnemonic Description
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reset Value = XXXX XXX0b
Not bit addressable
20
AT89C51RD2/ED2
4235G–8051–08/05
AT89C51RD2/ED2
Dual Data Pointer Register (DPTR)
Figure 7. Use of Dual Pointer
AUXR1(A2H)
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-b it DPTR registers that addr ess the external
memory, and a single bit called DPS = AUXR1.0 (see Table 18) that allows the program
code to switch between them (Refer to Figure 7).
External Data Memory
07
DPS
DPTR1
DPTR0
DPH(83H) DPL(82H)
4235G–8051–08/05
21
Table 18. AUXR1 Register
AUXR1- Auxiliary Register 1(0A2h)
76543210
- - ENBOOT - GF3 0 - DPS
Bit
Number
7-
6-
5ENBOOT
4-
3GF3This bit is a general-purpose user flag.
20Always cleared
1-
0DPS
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Boot Flash
Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
(1)
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XX0X0b
Not bit addressable
Note: 1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
22
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
AT89C51RD2/ED2
4235G–8051–08/05
AT89C51RD2/ED2
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
4235G–8051–08/05
23
Expanded RAM (XRAM)
The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM)
space for increased data parameter handling and high level language usage.
AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up
to 1792 bytes (see Table 19).
The AT89C51RD2/ED2 internal data memory is mapped into four separate segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh ) are in dir ectly a ddressable
only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and
with the EXTRAM bit cleared in the AUXR register (see Table 19).
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect add ressing only. The Upper 128 b ytes occupy
the same address space as the SFR. That means they have the same address, but are
physically separate from SFR space.
Figure 8. Internal and External Data Memory Address
0FFh or 6FFh
00
XRAM
0FFh
Upper
128 Bytes
Internal
RAM
Indirect Accesses
80h 80h
7Fh
Lower
128 Bytes
Internal
RAM
Direct or Indirect
00
Accesses
0FFh
Special
Function
Register
Direct Accesses
00FFh up to 06FFh
0FFFFh
0000
External
Data
Memory
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
• Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
• The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 19. This can be
24
AT89C51RD2/ED2
4235G–8051–08/05
AT89C51RD2/ED2
useful if external peripherals are mapped at addresses already used by the internal
XRAM.
• With EXTRAM = 0,
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done by the use of
DPTR.
• With EXTRAM = 1
80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port2 outputs the high-or der eight ad dress bits (the co ntents of DPH) while
Port0 multiplexes the low-order eight address bit s (DPL) with dat a. MOVX @ Ri and
MOVX @DPTR will generate either read or write signals on P3.6 (WR
(RD
).
the XRAM is indirectly addressed, using the MOVX instruction in
, MOVX @Ri and MOVX @DPTR will be similar to the standard
) and P3.7
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
4235G–8051–08/05
25
Registers Table 19. AUXR Register
AUXR - Auxiliary Register (8Eh)
76543210
DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
Bit
Number
7DPU
6-
5M0
4XRS2XRAM Size
3XRS1
2XRS0
1 EXTRAM
Bit
Mnemonic Description
Disable Weak Pull-up
Cleared by software to activate the permanent weak pull-up (default)
Set by software to disable the weak pull-up (reduce power consumption)
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Pulse length
Cleared to stretch MOVX control: the RD
periods (default).
Set to stretch MOVX control: the RD
XRS2
0 0 0 256 bytes
0 0 1 512 bytes
0 1 0 768 bytes(default)
0 1 1 1024 bytes
1 0 0 1792 bytes
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
and the WR pulse length is 6 clock
and the WR pulse length is 30 clock periods.
XRS1 XRS0 XRAM size
26
0AO
Reset Value = 0X00 10’HSB. XRAM’0b
Not bit addressable
AT89C51RD2/ED2
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
4235G–8051–08/05
AT89C51RD2/ED2
Reset
Introduction The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and
Reset input.
Figure 9. Reset schematic
Power
Monitor
Hardware
Watchdog
PCA
Watchdog
RST
Internal Reset
Reset Input The Reset input can be used to force a reset pulse longer than the internal reset con-
trolled by the Power Monitor. RST input has a pull-down resistor allowing power-on
reset by simply connecting an external capacitor to V
value and input characteristics are discussed in the Section “DC Characteristics” of the
AT89C51RD2/ED2 datasheet.
Figure 10. Reset Circuitry and Power-On Reset
RST
VSS
RST
R
To internal reset
as shown in Figure 10. Resistor
CC
VDD
+
RST
4235G–8051–08/05
b. Power-on Reseta. RST input circuitry
27
Reset Output
Reset output can be generated by two sources:
• Internal POR/PFD
• Hardware watchdog timer
As detailed in Section “Hardware Watchdog Time r”, page 86, the WDT generates a 96clock period pulse on the RST pin.
In order to properly propagate this pulse to the rest of the application in case of external
capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be added as shown
Figure 11.
Figure 11. Recommended Reset Output Schematic
VDD
+
VDD
VSS
RST
RST
1K
AT89C51XD2
To other
on-board
circuitry
28
AT89C51RD2/ED2
4235G–8051–08/05
AT89C51RD2/ED2
Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories
and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them.
By generating the Reset the Power Monitor insures a correct start up when
AT89C51RD2/ED2 is powered up.
Description In order to startup and maintain the microcon troller in correct operating mode, V
to be stabilized in the V
nominal amplitude compatible with logic level VIH/VIL.
These parameters are controlled during the three phases: power-up , normal operation
and power going down. See Figure 12.
Figure 12. Power Monitor Block Diagram
Power On Reset
Power Fail Detect
Voltage Regulator
XTAL1
RST pin
PCA
Watchdog
operating range and the oscillator has to be stabilized with a
CC
VCC
CPU core
Regulated
Supply
Memories
Peripherals
(1)
Internal Reset
Hardware
Watchdog
CC
has
4235G–8051–08/05
Note: 1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock
period delay will extend the reset coming from the Power Fail Detect. If the power
falls below the Power Fail Detect threshold level, the Reset will be applied
immediately.
The Voltage regulator generates a regulated internal supply for the CPU core the memories and the peripherals. Spikes on the external Vcc are smoothed by the voltage
regulator.
29
Figure 13. Power Fail Detect
Vcc
VPFDP
VPFDM
Reset
The Power fail detect monitor the supply generated by the voltage regulator and generate a reset if this supply falls below a safety threshold as illustrated in the Figure 13
below.
t
Vcc
When the power is applied, the Power Monitor immediately asserts a reset. Once the
internal supply after the voltage regulator reach a safety level, the power monitor then
looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024
clock periods before the reset is de-asserted.
If the internal power supply falls below a safety level, a reset is immediately asserted.
.
30
AT89C51RD2/ED2
4235G–8051–08/05
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