• A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs
• Full CAN Controller
– Fully Compliant with CAN rev.# 2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 4 Independent Message Objects
-Each Message Object Programmable on Transmission or Reception
-Individual Tag and Mask Filters up to 29-bit Identifier/Channel
-8-byte Cyclic Data Regis ter (FIFO)/Message Object
-16-bit Status and Control Register/Message Object
-16-bit Time-Stamping Register/Message Object
-CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
-Access to Message Object Control and D ata Registers Via SFR
-Programmable Reception Buffer Length up to 4 Message Objects
-Priority Management of Reception of Hits on Several Message Objects
Simultaneously (Basic CAN Feature)
-Priority Management for Transmission
-Message Object Overrun Interrupt
– Supports
-Time Triggered Communication
-Autobaud and Listening Mode
-Programmable Automatic Reply Mode
• 1-Mbit/s Maximum Transfer Rate at 8 MHz
• Readable Error Counters
• Programmable Link to On-chip Timer for Time Stamping and Network Synchronization
• Independent Baud Rate Prescaler
• Data, Remote, Error and Overload Frame Handling
• Power-saving Modes
–Idle Mode
– Power-down Mode
• Power Supply: 3 Volts to 5.5 Volts
• Temperature Range: Industrial (-40° to +85°C)
• Packages: SOIC28, SOIC24, PLCC28, VQFP32
(1)
Crystal Frequency In X2 Mode
Enhanced 8-bit
Microcontroller
with CAN
Controller and
Flash
T89C51CC02
AT89C51CC02
Note:1. At BRP = 1 sampling point will be fixed.
Rev. 4126L–CAN–01/08
AT/T89C51CC02
DescriptionPart of the CANary
tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller.
In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
Besides the full CA N controll er T89C51CC02 p rovides 16K Bytes of Fl ash memory
including In-Sy stem Programm ing (ISP), 2K Byt es Boot Flash Mem ory, 2K Bytes
EEPROM and 512 Bytes RAM.
Special attention is payed to the reduction of the electro-magnetic emission of
T89C51CC02.
Block Diagram
RxD
TxD
TM
family of 8-bit microcon troll er s dedi ca ted to C AN ne twork appl ica-
VCCSupply Voltage
VAREFReference Voltage for ADC (input)
VAVCCSupply Voltage for ADC
VAGNDReference Ground for ADC (internaly connected with the VSS)
P1.0:7I/OPort 1:
Is an 8-bit bi-directional I/O port w ith internal pull -ups. Port 1 pins can be used for digit al input/o utput or as
analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled
high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that
are being pulled low externally will be the source of curren t (I
because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF
register (in this case the internal pull-ups are disconnected).
As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA
external clock input and the PCA module I/O.
P1.0/AN0/T2
Analog input channel 0,
External clock input for Timer/counter2.
P1.1/AN1/T2EX
Analog input channel 1,
Trigger input for Timer/counter2.
P1.2/AN2/ECI
Analog input channel 2,
PCA external clock inpu t.
P1.3/AN3/CEX0
Analog input channel 3,
PCA module 0 Entry of input/PWM output.
P1.4/AN4/CEX1
Analog input channel 4,
PCA module 1 Entry of input/PWM output.
P1.5/AN5
Analog input channel 5,
P1.6/AN6
Analog input channel 6,
P1.7/AN7
Analog input channel 7,
It can drive CMOS inputs without external pull-ups.
AT/T89C51CC02
, See section ’Electrical C haracteristic’)
IL
P2.0:1I/OPort 2:
4126L–CAN–01/08
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled
high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being
pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups.
In the T89C51CC02 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.
5
AT/T89C51CC02
Pin NameTypeDescription
P3.0:7I/OPort 3:
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled
high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that
are being pu lled low externally will be a source of current (I
because of the internal pull-ups.
The output latch corresponding to a secondary function must be programmed to one for that function to
operate (except for TxD and WR
P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface
P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface
P3.2/INT0
P3.3/INT1
P3.4/T0: Timer 0 counter input
P3.5/T1: Timer 1 counter input
P3.6: Regular I/O port pin
P3.7: Regular I/O port pin
P4.0:1I/OPort 4:
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled
high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being
pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up
transistor.
The output latch corresponding to a secondary function RxDC must be programmed to one for that
function to operate. The secondary functions are assigned to the two pins of port 4 as follows:
P4.0/TxDC:
Transmitter output of CAN controller
P4.1/RxDC:
Receiver input of CAN controller.
It can drive CMOS inputs without external pull-ups.
IL
). The secondary functions are assigned to the pins of port 3 as follows:
: External interrupt 0 input/timer 0 gate control input
: External interrupt 1 input/timer 1 gate control input
, See section ’Electrical Characteristic’)
RESETI/OReset:
A high level on this pin during two machine cycles while the oscillator is running resets the device. An
internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC.
XTAL1IXTAL1:
Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the
device from an external clock sourc e, XTAL1 should be driven, while XTAL2 is left unconnected. To
operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained.
XTAL2OXTAL2:
Output from the inverting oscillator amplifier.
6
4126L–CAN–01/08
AT/T89C51CC02
I/O ConfigurationsEach Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A
CPU ’write to latch’ signal initiates transfer of internal bus data into the type-D latch. A
CPU ’read latch’ signal transf ers the latched Q out put onto the intern al bus. Similarl y, a
’read pin’ signal transfers the logical level of the Port pin. Some Port data instructions
activate the ’read latch’ signal while others activate the ’read pin’ signal. Latch instructions are referred to as Read-Modify-Write instructions. Each I/O line may be
independently programmed as input or output.
Port StructureFigure 1 shows the structure of Ports, which have internal pull-ups. An external source
can pull the pin low. Each Port pin can be configured either for general-purpose I/O or
for its alternate input output function.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 1 to 4). To use a pin for general-purpose input, set the bit in the Px register.
This turns off the output FET drive.
To configure a pin for its al ter nat e fun ction, set the bit in the Px register . W hen the l atch
is set, the ’alterna te outpu t funct ion’ sig nal c ontrols the out put lev el (See Figur e 1) . The
operation of Ports is discussed further in ’Quasi-Bi-directional Port Operation’
paragraph.
Figure 1. Ports Structure
VCC
READ
LATCH
ALTERNATE
OUTPUT
FUNCTION
INTERNAL
PULL-UP (1)
P1.x
P2.x
INTERNAL
BUS
WRITE
TO
LATCH
READ
PIN
D
LATCH
CL
Q
ALTERNATE
INPUT
FUNCTION
P3.x
P4.x
Note:1. The internal pull-up can be disabled on P1 when analog function is selected.
(1)
4126L–CAN–01/08
7
AT/T89C51CC02
Read-Modify-Write
Instructions
Some instructions rea d the l atch data rath er th an the pin da ta. T he latch based inst ructions read the data, m odify the data an d then r ewrit e the latc h. T hese are called ’ReadModify-Write’ instructions. Below is a complete list of these special instructions (See
Table 1). When the destination operand is a Port or a Port bit, these instructions read
the latch rather than the pin:
Table 1. Read/Modify/Write Instructions
InstructionDescriptionExample
ANLLogical ANDANL P1, A
ORLLogical ORORL P2, A
XRLLogical EX-ORXRL P3, A
JBCJump if bit = 1 and clear bitJBC P1.1, LABEL
CPLComplement bitCPL P3.0
INCIncrementINC P2
DECDecrementDEC P2
DJNZDecrement and jump if not zeroDJNZ P3, LABEL
MOV Px.y, CMove carry bit to bit y of Port xMOV P1.5, C
CLR Px.yClear bit y of Port xCLR P2.4
SET Px.ySet bit y of Port xSET P3.3
Quasi Bi-directional Port
Operation
It is not obvious t hat t he l as t thr ee in str uc ti ons in thi s lis t a re Rea d -Modify-Write inst ru ctions. These instructions read the port (all 8 bits), modify the specifically addressed bit
and write the new byte back to the latch. These Read-Modify-Write instr uctions are
directed to the latc h rather than the p in in or der to av oid poss ible mi sinterpret ation of
voltage (and there fore, logic) levels at th e pin. For e xampl e, a P ort b it used to dri ve the
base of an external bipolar transistor cannot rise above the transistor’s base-emitter
junction voltage (a v al ue l owe r than VIL). With a logic one wr itt en t o th e bi t, a ttem pts by
the CPU to read the P ort a t the p in are misi nterpret ed as logi c ze ro. A r ead of the l atch
rather than the pins returns the correct logic one value.
Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as ’quasi-bidirectional’ Ports. When configured as an input, the pin impedance appears as logic one
and sources current in response to an external logic zero condition. Resets write logic
one to all Port latch es. If log ical zer o is subs equently w ritten to a P ort latch , it can b e
returned to input conditions by a logic one written to the latch.
Note:Port latch values change near the end of Read-Modify-Write insruction cycles. Output
buffers (and therefore the pin state) are updated early in the instruction after Read-Modify-Write instruction cycle.
Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1)
to aid this logic tran siti on S ee Fi gure 2. T his in cre ases s witc h s peed. Thi s ext ra p ull-u p
sources 100 times normal internal circuit current during 2 oscillator clock periods. The
internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist
of three p-channel FET (pFE T) devi ces. A pFE T is on when th e gate sen ses logic zero
and off when the gate senses log ic one. p FET # 1 is tur ned o n for two osc illator pe riods
immediately after a zero- to-one transition in the Port latc h. A logic one at the Port pin
turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form
a latch to drive logic one. pFET #2 is a very weak pull-up switched on whenever the
8
4126L–CAN–01/08
AT/T89C51CC02
associated nFET is switched off. This is tradition al CMOS switch conventio n. Current
strengths are 1/10 that of pFET #3.
Note:During Reset, pFET#1 is not avtivated. During Reset, only the weak pFET#3 pull up the
pin.
Figure 2. Internal Pull-up Configurations
2 Osc. PERIODS
VCCVCCVCC
OUTPUT DATA
INPUT DATA
READ PIN
p1(1)
n
p2
p3
P1.x
P2.x
P3.x
P4.x
4126L–CAN–01/08
9
AT/T89C51CC02
SFR MappingTables 3 through Table 11 show the Special Function Registers (SFRs) of the
T89C51CC02.
Table 2. C51 Core SFRs
MnemonicAddName76543210
ACCE0h Accumulator
BF0h B Register
PSWD0h Program Status WordCYACF0RS1RS0OVF1P
SP81h Stack Pointer
Data Pointer Low
DPL82h
DPH83h
Table 3. I/O Port SFRs
MnemonicAddName76543210
P190h Port 1
byte
LSB of DPTR
Data Pointer High
byte
MSB of DPTR
P2A0h Port 2 (x2)
P3B0h Port 3
P4C0h Port 4 (x2)
Table 4. Timers SFRs
MnemonicAddName76543210
TH08Ch
TL08Ah
TH18Dh
TL18Bh
TH2CDh
TL2CCh
TCON88h
Timer/Counter 0 High
byte
Timer/Counter 0 Low
byte
Timer/Counter 1 High
byte
Timer/Counter 1 Low
byte
Timer/Counter 2 High
byte
Timer/Counter 2 Low
byte
Timer/Counter 0 and
1 control
TF1TR1TF0TR0IE1IT1IE0IT0
TMOD89h
Timer/Counter 0 and
1 Modes
10
GATE1C/T1#M11M 01GATE0C/T0#M10M00
4126L–CAN–01/08
AT/T89C51CC02
Table 4. Timers SFRs (Continued)
MnemonicAddName76543210
T2CONC8h
T2MODC9h
RCAP2HCBh
RCAP2LCAh
WDTRSTA6h
WDTPRGA7h
Timer/Counter 2
control
Timer/Counter 2
Mode
Timer/Counter 2
Reload/Capture High
byte
Timer/Counter 2
Reload/Capture Low
byte
WatchDog Timer
Reset
WatchDog Timer
Program
TF2EXF2RCLKTCLKEXEN2TR2C/T2#CP/RL2#
T2OEDCEN
S2S1S0
Table 5. Serial I/O Port SFRs
MnemonicAddName76543210
SCON98h Serial Cont rolFE/SM0SM1SM2RENTB8RB8TIR I
SBUF99h Serial Data Buffer
SADENB 9h Slave Address Mask
SADDRA9h Slave Address
Table 6. PCA SFRs
MnemonicAddName76543210
CCOND8h
CMODD9h
CLE9h
CHF9h
CCAPM0
CCAPM1
CCAP0H
CCAP1H
DAh
DBh
FAh
FBh
PCA Timer/Counter
Control
PCA Timer/Counter
Mode
PCA Timer/Counter
Low byte
PCA Timer/Counter
High byte
PCA Timer/Counter
Mode 0
PCA Timer/Counter
Mode 1
PCA Compare
Capture Module 0 H
PCA Compare
Capture Module 1 H
CFCRCCF4CCF3CCF2CCF1CCF0
CIDLCPS1CPS0ECF
CCAP0H7
CCAP1H7
ECOM0
ECOM1
CCAP0H6
CCAP1H6
CAPP0
CAPP1
CCAP0H5
CCAP1H5
CAPN0
CAPN1
CCAP0H4
CCAP1H4
MAT0
MAT1
CCAP0H3
CCAP1H3
TOG0
TOG1
CCAP0H2
CCAP1H2
PWM0
PWM1
CCAP0H1
CCAP1H1
CCAP0H0
CCAP1H0
ECCF0
ECCF1
4126L–CAN–01/08
11
AT/T89C51CC02
Table 6. PCA SFRs (Continued)
MnemonicAddName76543210
CCAP0L
CCAP1L
PCA Compare
EAh
Capture Module 0 L
EBh
PCA Compare
Capture Module 1 L
CCAP0L7
CCAP1L7
CCAP0L6
CCAP1L6
CCAP0L5
CCAP1L5
CCAP0L4
CCAP1L4
CCAP0L3
CCAP1L3
CCAP0L2
CCAP1L2
CCAP0L1
CCAP1L1
CCAP0L0
CCAP1L0
Table 7. Interrupt SFRs
MnemonicAddName76543210
IEN0A8h
IEN1E8h
IPL0B8h
IPH0B7h
IPL1F8h
IPH1F7h
Interrupt Enable
Control 0
Interrupt Enable
Control 1
Interrupt Priorit y
Control Low 0
Interrupt Priorit y
Control High 0
Interrupt Priorit y
Control Low 1
Interrupt Priorit y
Control High1
EAECET2ESET1EX1ET0EX0
ETIMEADCECAN
PPCPT2PSPT1PX1PT0PX0
PPCHPT2HPSHPT1HPX1HPT0HPX0H
POVRLPADCLPCANL
POVRHPADCHPCANH
Table 8. ADC SFRs
MnemonicAddName76543210
ADCONF3h ADC ControlPSIDLEADENADEOCADSSTSCH2S CH1SCH0
ADCFF6h ADC ConfigurationCH7CH6CH5C H4CH3CH2CH 1CH0
ADCLKF2h ADC ClockPRS4PRS3PRS2PRS1PRS0
ADDHF5h ADC Data High byteADAT9A DAT8ADAT7ADAT6ADAT5ADAT4ADAT3ADAT2
ADDLF4h ADC Data Low byteADAT1ADAT0
Table 9. CAN SFRs
MnemonicAddName76543210
CANGCON ABh
CANGSTAAAh
CANGIT9Bh
CANBT1B4h CAN bit Timing 1BRP5BRP4BRP3BRP2BRP1BRP0
CANBT2B5h CAN bit Timing 2SJW1SJW0PRS2PRS1PRS0
CANBT3B6h CAN bit Timing 3PHS22PHS21PHS20PHS12PHS11PHS10SMP
Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFRs are those
whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.
2. AUXR1 bit ENBOOT is initialized with the content of the BLJB bit inverted.
4126L–CAN–01/08
CANGIT
0x00 0000
TL1
0000 0000
DPH
0000 0000
CANTEC
0000 0000
TH0
0000 0000
CANREC
0000 0000
TH1
0000 0000
CKCON
0000 0000
PCON
00x1 0000
9Fh
97h
8Fh
87h
15
AT/T89C51CC02
ClockThe T89C51CC02 core needs only 6 clock periods per machine cycle. This feature,
called “X2”, provides the following advantages:
•Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU
power.
•Saves power consumption while keeping the same CPU power (oscillator power
saving).
•Saves power consumption by dividing dynamic operating frequency by 2 in
operating and idle modes.
•Increases CPU power by 2 while keeping the same crystal frequency.
In order to keep the ori ginal C51 com patibil ity, a divider -by-2 is in serted betwe en the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by the software.
An extra feature is available to start after Reset in the X2 Mode. This feature can be
enabled by a bit X2B in the Hardware Sec urity Byte. Thi s bit is described in the section
’In-System Programming’.
DescriptionThe X2 bit in the CKCON regi ster (See T able 12) allows switching from 12 clock cycles
per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
(STD mode).
Setting this bit activates the X2 feature (X2 Mode) for the CPU Clock only (See Figure
3).
The Timers 0, 1 and 2, Uart, PCA, watchdog or CAN switch in X2 Mode only if the corresponding bit is cleared in the CKCON register.
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1
input. In X2 Mode, as thi s divid er is bypas s ed, t he s ig nal s o n XTA L1 m us t hav e a cy clic
ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2
bit is validat ed on th e XTAL1 ÷ 2 rising edge to avoid glitches when switching from the
X2 to the STD mode. Figure 4 shows the mode switching waveforms.
16
4126L–CAN–01/08
Figure 3. Clock CPU Generation Diagram
X
X
AT/T89C51CC02
X2B
Hardware Byte
On RESET
PCON.0
IDL
X2
CKCON.0
TAL1
÷2
0
1
CPU Core
Clock
TAL2
CPU
CLOCK
PD
PCON.1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
1
0
÷2
1
0
1
0
1
0
1
0
1
0
CPU Core Clock Symbol
and ADC
1
0
FT0 Clock
FT1 Clock
FT2 Clock
FUart Clock
FPca Cloc k
FWd Clock
FCan Clock
4126L–CAN–01/08
X2
CKCON.0
CANX2
CKCON.7
WDX2
CKCON.6
PCAX2
CKCON.5
SIX2
CKCON.4
T2X2
CKCON.3
T1X2
CKCON.2
PERIPH
CLOCK
Peripheral Clock Symbol
T0X2
CKCON.1
17
AT/T89C51CC02
Figure 4. Mode Switching Waveforms
XTAL1
XTAL2
X2 bit
CPU
clock
STD
Mode
(1)
X2
Mode
STD
Mode
Note:1. In order to prevent any incorrect operation while operating in the X2 Mode, users must be aware that all peripherals using
the clock frequency a s a time ref erence (UAR T, timers...) will have their time referen ce div ided b y 2. Fo r example , a free ru nning timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate
will have a 9600 baud rate.
18
4126L–CAN–01/08
RegisterTable 12. CKCON Register
CKCON (S:8Fh)
Clock Control Register
76543210
CANX2WDX2PCAX2SIX2T 2X2T1X2T0X2X2
AT/T89C51CC02
Bit
Number
7CANX2
6WDX2
5PCAX2
4SIX2
3T2X2
2T1X2
1T0X2
Bit
Mnemonic Description
CAN Clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Watchdog Clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Cloc k
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (MODE 0 and 2)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer 2 Clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer 1 Clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer 0 Clock
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
(1)
(1)
(1)
(1)
(1)
(1)
(1)
4126L–CAN–01/08
CPU Clock
0X2
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all
the peripherals.
Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the
individual peripherals ’X2’ bits.
Note:1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
has no effect.
Reset Value = 0000 0000b
19
AT/T89C51CC02
Power ManagementTwo power reduction modes are implemented in the A/T89C51CC02: the Idle mode and
0
the Power-do wn mode . These modes ar e detai led in th e follo wing se ction s. In ad dition
to these power redu cti on mo des , t he cl oc ks o f th e c ore and peripherals can be dy nam ically divided by 2 using the X2 Mode detailed in Section “Clock”.
Reset PinIn order to start- up (c old re se t) or to res tart (warm rese t) pro perly the m icroc ontroll er, a
high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of
the internal registers like S F Rs, P C, etc . and to unp re dicta ble behavior of the microcontroller. A warm reset ca n be applied either dir ectly o n the RST pin or indire ctly by an
internal reset source such as a watchdog, PCA, timer, etc.
At Power-up (cold reset)Two conditions are required before enabling a CPU start-up:
•VDD must reach the specified VDD range,
•The level on xtal1 input must be outside the specification (VIH, VIL).
If one of these two conditions are not met, the microcontroller d oes not start cor rectly
and can execute an instruct ion fetch fro m anywhe re in the progr am spac e. An active
level applied on the RST pin must be mainta ined unti l both of th e above c onditi ons are
met. A reset is active wh en the lev el VIH1 is reached an d when the pu lse wid th covers
the period of time where VDD and the oscillator are not stabilized. Two parameters have
to be taken into account to determine the reset pulse width:
•VDD rise time (vddrst),
•Oscillator startup time (oscrst).
To determine the capacitor the highest value of these two parameters has to be chosen.
The reset circuitry is shown in Figure 5.
Figure 5. Reset Circuitry
VDD
Crst
RST pin
Rrst
Reset input circuitry
Internal reset
Table 13 and Table 14 give some typical examples for three values of VDD rise times,
two values of oscillator start-up time and two pull-down resistor values.
Table 13. Minimum Reset Capacitor for a 50K Pull-down Resistor
oscrst/vddrst1ms10ms100ms
5ms820nF1.2µF12µF
20
20ms2.7µF3.9µF12µF
4126L–CAN–01/08
AT/T89C51CC02
Table 14. Minimum Reset Capacitor for a 15k Pull-down Resistor
oscrst/vddrst1ms10ms100ms
5ms2.7µF4.7µF47µF
20ms10µF15µF47µF
Note:These values assume VDD starts from 0v to the nominal value. If the time between two
on/off sequences is too fast, the power-supply decoupling capacitors may not be fully
discharged, leading to a bad reset sequence.
During a Normal
Operation (Warm Reset)
Reset pin must be maintained for at l ea st 2 m achi ne cy cl es (24 os c illat or c lock pe r iod s)
to apply a reset s equence duri ng normal o peration. The number of cl ock periods is
mode independent (X2 or X1).
Watchdog ResetA 1K resistor must be added in series with the capacitor to allow the use of watchdog
reset pulse output on the RST pin or when an external power-supply supervisor is used.
Figure 6 shows the reset circuitry when a capacitor is used.
Figure 6. Reset Circuitry for a Watchdog Configuration
VDD
Crst
1kRST pin
Rrst
Reset input circuitry
To other on-board circuitry
Figure 7 shows the reset circuitry when an external reset circuit is used.
watchdog
Internal reset
4126L–CAN–01/08
Figure 7. Reset Circuitry Example Using an External Reset Circuit
VDD
External reset
circuit
RST
1kRST pin
Rrst
Reset input circuitry
To other on-board circuitry
watchdog
Internal reset
21
AT/T89C51CC02
Reset Recommendation
to Prevent Flash
Corruption
When a Flash program memory is embedded on-chip, it is strongly recommended to
use an external reset chip (brown out device) to apply a reset (Figure 7). It prevents system malfunction during periods of insufficient power-supply voltage (power-supply
failure, power supply switched off, etc.).
Idle ModeIdle mode is a power reduction mode that reduces the power consumption. In this mode,
program execution halts. Idle mode freezes the cl ock to the CPU at known sta tes while
the peripherals continue to be clocked. The CPU status before entering Idle mode is
preserved, i.e., the program counter and program status word register retain their data
for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The
status of the Port pins during Idle mode is detailed in Table 15.
Entering Idle ModeTo enter Idle mode, set the IDL bi t in PCON register (See Table 16). The
A/T89C51CC02 enters Idle mode upon execution of the instruction that sets IDL bit. The
instruction that sets IDL bit is the last instruction executed.
Note:If IDL bit and PD bit are set simultaneously, the A/T89C51CC02 enters Power-down
mode. Then it does not go in Idle mode when exiting Power-down mode.
Exiting Idle ModeThere are two ways to exit Idle mode:
1.Generate an enabled interrupt.
Hardware clears IDL bit in PCON register which restores the clock to the CPU. Exe-
cution resumes with the interrupt service routine. Upon completion of the interrupt
service routine, pr o gr am exec uti on r e su mes with the instruction im med iat ely following the instruction that activated Idle mode. The general purpose flags (GF1 and
GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operati on o r dur i ng I dle mo de. Wh en Idle mode is exite d b y a n i nte rrup t,
the interrupt service routine may examine GF1 and GF0.
2.Generate a reset.
A logic high on the RST pin clears IDL bit in PCON register directly and asynchro-
nously. This restores the c lock to the CPU. Program execu tion momentarily
resumes with the inst ructio n immedia tely follow ing the in structi on that activ ated the
Idle mode and may continue for a number of clock cycles before the internal reset
algorithm takes control. Reset initializes the A/T89C51CC02 and vectors the CPU to
address C:0000h.
Power-down ModeThe Power-down mode places the A/T89C51 CC02 in a v ery low po wer state. Powe r-
Entering Power-down ModeTo enter Power-down mode, set PD bit in PCON register. The A/T89C51CC02 enters
22
Notes:1. Dur i ng the t im e th at ex e cuti o n re su me s, th e i nte r na l R AM ca n no t be ac ce ss ed ; ho w -
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated Idle
mode should not write to a Port pin or to the external RAM.
2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle.
down mode stops t he osci ll ator , freez es a ll c lock at k nown s tate s. The CPU st atus p rior
to entering Power-down mode is preserved, i.e., the program counter, program status
word register retain their data for the duration of Power-down mode. In addition, the
SFRs and RAM content s a re pres erv ed. T h e s tatu s of the Po rt pins dur in g P ower -do w n
mode is detailed in Table 15.
the Power-down mode upon execution of the instruction that sets PD bit. The instruction
that sets PD bit is the last instruction executed.
4126L–CAN–01/08
AT/T89C51CC02
Exiting Power-down ModeNote:If V
was reduced during the Power-down mode, do not exit Power-down mode until
DD
V
is restored to the normal operating level.
DD
There are two ways to exit the Power-down mode:
1.Generate an enabled external interrupt.
–The A/T89C51CC02 provides capability to exit from Power-down using
INT0#, INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTx# input,
execution resumes when the input is released (See Figure 8). Execution
resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes with the instruction immediately
following the instruction that activated Power-down mode.
Notes: 1. The external interrupt used to exit Power-down mode must be configured as level
sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,
the duration of the interrupt must be long enough to allow the oscillator to stabilize.
The execution will only resume when the interrupt is deasserted.
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
RAM content.
2.Generate a reset.
–A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the A/T89C51CC02 and
vectors the CPU to address 0000h.
Notes:1. Dur i ng the t im e th at ex e cuti o n re su me s, th e i nte r na l R AM ca n no t be ac ce ss ed ; ho w -
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
2. Exit from power-down by res et r edefines all the SFRs, b ut do es not af fect the internal
RAM content.
4126L–CAN–01/08
23
AT/T89C51CC02
Table 15. Pin Conditions in Special Operating Modes
ModePort 1Port 2Port 3Port 4
ResetHighHighHighHigh
Idle
(internal
code)
Idle
(external
code)
Power-
Down(inter
nal code)
Power-
Down
(external
code)
DataDataDataData
DataDataDataData
DataDataDataData
DataDataDataData
24
4126L–CAN–01/08
RegistersTable 16. PCON Register
PCON (S:87h)
Power Control Register
76543210
SMOD1SMOD0-POFGF1GF0PDIDL
AT/T89C51CC02
Bit
Number
7SMOD1
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
Bit
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Clear to recognize next reset type.
Set by hardware when V
software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-down Mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle Mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
rises from 0 to its nominal voltage. Can also be set by
CC
4126L–CAN–01/08
Reset Value = 00X1 0000b
Not bit addressable
25
AT/T89C51CC02
Data MemoryThe T89C51CC02 provides data memory access in two different spaces:
The internal space mapped in three separate segments:
•The lower 128 Bytes RAM segment.
•The upper 128 Bytes RAM segment.
•The expanded 256 Bytes RAM segment (XRAM).
A fourth internal segment is available but dedicated to Special Function Registers,
SFRs, (addresses 80h to FFh) accessible by direct addressing mode.
Figure 9 shows the internal data memory spaces organization.
Figure 9. Internal memory - RAM
FFh
00h
256 Bytes
Internal XRAM
FFh
80h80h
7Fh
00h
Upper
128 Bytes
Internal RAM
Indirect Addressing
Lower
128 Bytes
Internal RAM
Direct or Indirect
Addressing
FFh
Direct Addressing
Special
Function
Registers
Internal Space
Lower 128 Bytes RAMThe lower 128 Bytes of RAM (See Figure 10) are accessible from address 00h to 7Fh
using direct or indirect address ing modes. T he lowest 32 Bytes are grouped in to 4
banks of 8 registers (R0 to R7 ). Two bits RS0 and RS 1 in PSW re giste r (See Tabl e 18)
select which bank is in use according to Table 17. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines.
Table 17. Register Bank Selection
RS1RS0Description
00Register bank 0 from 00h to 07h
26
01Register bank 0 from 08h to 0Fh
10Register bank 0 from 10h to 17h
11Register bank 0 from 18h to 1Fh
The next 16 Bytes above the register banks form a block of bit-addressable memory
space. The C51 ins truction set i ncludes a wide s election o f singlebit instruct ions, and
the 128 bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00h to 7Fh.
Upper 128 Bytes RAMThe upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
addressing mode.
Expanded RAMThe on-chip 256 Bytes of expanded RAM (XRAM) are accessible from address 0000h to
00FFh using i ndirect ad dressing mode thro ugh MOVX in structio ns. In this a ddress
range.
Note:Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile
memory cells. This means that the RAM content is indeterminate after power-up and
must then be initialized properly.
4126L–CAN–01/08
27
AT/T89C51CC02
Dual Data Pointer
DescriptionThe T89C51CC02 imp lements a second data pointer for speeding up code exe cution
and reducing code size in case of intensive usage of external memory accesses.
DPTR0 and DPTR1 are Seen by the CPU as DPT R and are accessed using the SFR
addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1
register (See Figure 19) is used to select whether DPTR is the data pointer 0 or the data
pointer 1 (See Figure 11).
Figure 11. Dual Data Pointer Implementation
DPL0
DPL1
DPTR0
DPTR1
DPH0
DPH1
0
1
DPS
0
1
DPL
AUXR1.0
DPH
DPTR
ApplicationSoftware can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare…) are well served by
using one data pointer as a “source” pointer and the other one as a “destination” pointer.
Hereafter is an example of block move implementation using the two pointers and coded
in assembler. The latest C compiler takes als o advantag e of this feature b y providin g
enhanced algorithm libraries.
The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the
DPS bit in the AUXR 1 reg ister. H owever , note that th e INC i nstruc tion do es no t direc tly
force the DPS bit to a particular state, but simply toggles it. In simple routines, such as
the block move exa mple, o nly the f act that DP S is tog gled i n the pr oper s equenc e matters, not its actual value. In other words, the block move routine works the same whether
DPS is 0 or 1 on entry.
; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is
added
28
AUXR1EQU0A2h
move:movDPTR,#SOURCE ; address of SOURCE
incAUXR1 ; switch data pointers
movDPTR,#DEST ; address of DEST
mv_loop:incAUXR1; switch data pointers
movxA,@DPTR; get a byte from SOURCE
incDPTR; increment SOURCE address
incAUXR1; switch data pointers
movx@DPTR,A; write the byte to DEST
incDPTR; increment DEST address
jnzmv_loop; check for NULL terminator
end_move:
4126L–CAN–01/08
RegistersTable 18. PSW Register
PSW (S:D0h)
Program Status Word Register
76543210
CYACF0RS1RS0OVF1P
AT/T89C51CC02
Bit
Number
7CY
6AC
5F0User Definable Flag 0
4 - 3RS1:0
2OV
1F1User Definable Flag 1
0P
Bit
Mnemonic Description
Carry Flag
Carry out from bit 1 of ALU operands.
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
Register Bank Select bits
Refer to Table 17 for bits description.
Overflow Flag
Overflow set by arithmetic operations.
Parity bit
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
Reset Value = 0000 0000b
4126L–CAN–01/08
29
AT/T89C51CC02
Table 19. AUXR1 Register
AUXR1 (S:A2h)
Auxiliary Control Register 1
76543210
--ENBOOT-GF30-DPS
Bit
Number
7 - 6-
5ENBOOT
4-
3GF3General Purpose Flag 3
20
1-Reserved for Data Pointer Extension
0DPS
Bit
Mnemonic Description
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Enable Boot Flash
(1)
Set this bit to map the boot Flash between F800h -FFFFh
Clear this bit to disable boot Flash.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
Data Pointe r Select bit
Set to select second dual data pointer: DPTR1.
Clear to select first dual data pointer: DPTR0.
Reset Value = XXXX 00X0b
Note:1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming
section.
30
4126L–CAN–01/08
AT/T89C51CC02
EEPROM Data
Memory
Write Dat a i n the Column
Latches
The 2K bytes on-chi p EEPRO M memo ry bloc k is l ocated at addres ses 0000h to 07FF h
of the XRAM/XRAM memory space and is selected by setting control bits in the EECON
register. A read in the EEPROM memory is done with a MOVX instruction.
A physical write i n the E EPRO M memo ry is d one in two step s: write data in the co lumn
latches and transfer of all data latches into an EEPROM memory row (programming).
The number of data written on the page may vary from 1 up to 128 Bytes (the page
size). When programm ing, onl y the dat a writte n in the col umn latc h is pro grammed an d
a ninth bit is used to obtain this feature. This provides the capability to program the
whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth
bit is set when the writing th e corresponding b yte in a row and all these n inth bits are
reset after the writing of the complete EEPROM row.
Data is written by byte to the column latches as for an external RAM memory. Out of the
11 address bits of t he d ata poi nter, the 4 MSBs are used fo r pag e s ele ct ion ( row ) and 7
are used for byte selection. Between two EEPROM programming sessions, all the
addresses in the column lat ches mus t stay on the sa me p age, mea ning tha t the 4 MSB
must no be changed.
The following procedure is used to write to the column latches:
•Save and disable int er ru pt
•Set bit EEE of EECON register
•Load DPTR with the address to write
•Store A register with the data to be written
•Execute a MOVX @DPTR, A
•If needed loop the three last instructions until the end of a 128 Bytes page
•Restore interrupt
Note:The last page address used when loading the column latch is the one used to select the
page programming address.
ProgrammingThe EEPROM programming consists of the following actions:
•Write one or more Bytes of one page in the column latches. Normally, all Bytes must
belong to the same page; if not, the last page address will be latched and the others
discarded.
•Launch programming by writing the control sequence (50h followed by A0h) to the
EECON register.
•EEBUSY flag in EECON is then set by hardware to indicate that programming is in
progress and that the EEPROM segment is not available for reading.
•The end of programming is indicated by a hardware clear of the EEBUSY flag.
Note:The sequence 5xh and Axh must be executed without instructions between then other-
wise the programming is aborted.
Read DataThe following procedure is used to read the data stored in the EEPROM memory:
Write 5Xh followed by AXh to EEPL to launch the programming.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable EEPROM Space bit
Set to map the EEPROM space during MOVX instructions (Write in the column
latches)
Clear to map the XRAM space during MOVX.
Programming Busy Flag
Set by hardware when programming is in progress.
Cleared by hardware when programming is done.
Can not be set or cleared by software.
Reset Value = XXXX XX00b
Not bit addressable
4126L–CAN–01/08
33
AT/T89C51CC02
Program/Code
Memory
The T89C51CC02 implement 16K Bytes of on-chip program/code memory.
The Flash memory increa ses EP ROM and ROM func tional ity by in-cir cui t electric al era-
sure and programming. Thanks to the internal charge pump, the high voltage needed for
programming or erasing Flash ce lls is gene rated on-chip usi ng the standard V
DD
voltage. Thus, the Flash memory can be programmed using only one voltage and allows InSystem Progr ammi ng (IS P). Har dwar e prog rammin g mode is also availab le usi ng specific programming tool.
Figure 12. Program/Code Memory Organization
3FFFh
16K Bytes
Internal
Flash
0000h
Flash Memory
Architecture
T89C51CC02 features two on-chip Flash memories:
•Flash memory FM0:
•Flash memory FM1:
The FM0 can be program by both parallel programming and Serial ISP whereas FM1
supports only parallel programming by pr ogrammers. The ISP mod e is detailed in the
’In-System Programming’ section.
All Read/Write access operations on Flash memory by user application are managed by
a set of API described in the ’In-System Programming’ section.
containing 16K Bytes of program memory (user space) organized into 128 bytes
pages,
2K Bytes for boot loader and Application Programming Interfaces (API).
FFFFh
F800h
16K Bytes
Flash Memory
User Space
FM0
2K Bytes
Flash Memory
Boot Space
FM1
FM1 mapped between F800h and
FFFFh when bit ENBOOT is set in
AUXR1 register
34
0000h
4126L–CAN–01/08
AT/T89C51CC02
FM0 Memory ArchitectureThe Flash memory is made up of 4 blocks (See Figure 13):
1.The memory array (user space) 16K Bytes
2.The Extra Row
3.The Hardware security bits
4.The column latch registers
User SpaceThis space is composed of a 16K Bytes Flash memory organized in 128 pages of 128
Bytes. It contains the user’s application code.
Extra Row (XRow)This row is a pa rt of FM0 and has a size of 12 8 B yt es. T he ex tra r ow may con t ain i nfo r-
mation for boot loader usage.
Hardware Security ByteThe Hardware security Byte space is a part of FM0 and has a size of 1 byte.
The 4 MSB can be read/written by software, the 4 LSB can only be read by software and
written by hardware in parallel mode.
Column LatchesThe column latches, also part of FM0, have a size of full page (128 Bytes).
The column latches are the entrance buffers of the three previous memory locations
(user array, XROW and Hardware security byte).
Cross Flash Memory Access
Description
The FM0 memory can be programmed as describe on Table 21. Programming FM0
from FM0 is impossible.
The FM1 memory can be program only by parallel programming.
Table 21 show all software Flash access allowed.
Table 21. Cross Flash Memory Access
Code executing from
FM0
(user Flash)
FM1
(boot Flash)
Action
Readok-
Load column latchok-
Write--
Readokok
Load column latchok-
Writeok-
FM0
(user Flash)
FM1
(boot Flash)
4126L–CAN–01/08
35
AT/T89C51CC02
Overview of FM0
Operations
The CPU interfaces the Flash memory through the FCON register and AUXR1 register.
These registers are used to:
•Map the memory spaces in the adressable space
•Launch the programming of the memory spaces
•Get the status of the Flash memory (busy/not busy)
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a
page while bits 14 to 7 are used to select the programming address of the page.
Setting FPS bit takes precedence on the EEE bit in EECON register.
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 22. A MOVC instruction is then used for reading these spaces.
Launching ProgrammingFPL3:0 bits i n FCON regist er are us ed to s ecure th e launc h of pr ogrammi ng. A s pecific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5xh followed by Axh. Table 23 summarizes the memory
spaces to program according to FMOD1:0 bits.
Table 23. Programming Spaces
Write to FCON
OperationFPL3:0FPSFMOD1FMOD0
5x00No action
User
Extra Row
Hardware
Security
Byte
Reserved
Note:The sequence 5xh and Axh must be executing without instructions between them other-
wise the programming is aborted.
Interrupts that may occur during programming time must be disabled to avoid any spurious exit of the programming mode.
Ax00
5x01No action
Ax01
5x10No action
Ax10Write the fuse bits space
5x11No action
Ax11No action
Write the column latches in user
space
Write the column latches in extra row
space
36
4126L–CAN–01/08
AT/T89C51CC02
Status of the Flash MemoryThe bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
Selecting FM1The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.
Loading the Column LatchesAny num ber of data fr om 1 byte to 128 Bytes can be lo ade d i n the column latches. T his
provides the capability to program the whole memory by byte, by page or by any number
of Bytes in a page.
When progra mmin g is laun ched, a n aut omati c erase of the loc atio ns load ed in th e col umn latches is first performed, then programming is effectively done. Thus no page or
block erase is needed and only the loaded data are programmed in the corresponding
page.
The following procedure is used to load the column latches and is summarized in
Figure 14:
•Save then disable interrupt and map the column latch space by setting FPS bit.
•Load the DPTR with the address to load.
•Load Accumulator register with the data to load.
•Execute the MOVX @DPTR, A instruction.
•If needed loop the three last instructions until the page is completely loaded.
•unmap the column latch and Restore Interrupt
4126L–CAN–01/08
37
AT/T89C51CC02
Figure 14. Column Latches Loading Procedure
Column Latches
Loading
Save & Disable IT
EA = 0
Column Latches Mapping
FCON = 08h (FPS = 1)
Data Load
DPTR = Address
ACC = Data
Exec: MOVX @DPTR, A
Last Byte
to load?
Data Memory Mapping
FCON = 00h (FPS = 0)
(1)
Restore IT
Note:1. The last page address used when loading the column latch is the one used to select
the page programming address.
Programming the Flash Spaces
UserThe following procedure is used to program the User space and is summarized in
Figure 15:
•Load up to one page of data in the column latches from address 0000h to 3FFFh.
•Save then disable the interrupts.
•Launch the programming by writing the data sequence 50h followed by A0h in
FCON register.This step must be executed from FM1.
The end of the programming indicated by the FBUSY flag cleared.
•Restore the interrupts.
Extra RowThe following procedure is used to pr ogra m the Extra Row space a nd is summ arized i n
Figure 15:
•Load data in the column latches from address FF80h to FFFFh.
•Save then disable the interrupts.
•Launch the programming by writing the data sequence 52h followed by A2h in
FCON register. This step of the procedure must be executed from FM1.
The end of the programming indicated by the FBUSY flag cleared.
•Restore the interrupts.
38
4126L–CAN–01/08
Figure 15. Flash and Extra row Programming Procedure
Flash Spaces
Programming
Column Latches Load i n g
See Figure 14
Save & Disable IT
EA = 0
Launch Programming
FCON = 5xh
FCON = Axh
FBusy
Cleared?
AT/T89C51CC02
Hardware Security Byte
Clear Mode
FCON = 00h
End Programming
Restore IT
The following procedure is used to program the Hardware Security Byte space
and is summarized in Figure 16:
•Set FPS and map Hardware byte (FCON = 0x0C)
•Save then disable the interrupts.
•Load DPTR at address 0000h.
•Load Accumulator register with the data to load.
•Execute the MOVX @DPTR, A instruction.
•Launch the programming by writing the data sequence 54h followed by A4h in
FCON register. This step of the procedure must be executed from FM1.
The end of the programming indicated by the FBusy flag cleared.
•Restore the interrupts
4126L–CAN–01/08
39
AT/T89C51CC02
Figure 16. Hardware Programming Procedure
Flash Spaces
Programming
Save & Disable IT
EA = 0
FCON = 0Ch
Save & Disable IT
EA = 0
Launch Programming
FCON = 54h
FCON = A4h
Data Load
DPTR = 00h
ACC = Data
Exec: MOVX @DPTR, A
End Loading
Restore IT
FBusy
Cleared?
Clear Mode
FCON = 00h
End Programming
RestoreIT
Reading the Flash Spaces
UserThe following procedure is used to read the User space:
•Read one byte in Accumulator by executing MOVC A,@A+DPTR with A+DPTR is
the address of the code byte to read.
Note:FCON must be cleared (00h) when not used.
Extra RowThe following procedure is used to read the Extra Row space and is summarized in
Figure 17:
•Map the Extra Row space by writing 02h in FCON register.
•Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &
DPTR= FF80h to FFFFh.
•Clear FCON to unmap the Extra Row.
Hardware Security Byte
40
The following procedure is used to read the Hardware Security Byte and is summarized in Figure 17:
•Map the Hardware Security space by writing 04h in FCON register.
•Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &
DPTR= 0000h.
•Clear FCON to unmap the Hardware Security Byte.
4126L–CAN–01/08
Figure 17. Reading Procedure
Flash Spaces Reading
Flash Spaces Mapping
FCON = 00000aa0b
Data Read
DPTR = Address
Exec: MOVC A, @A+DPTR
Note:aa = 10 for the Hardware Security Byte.
ACC= 0
Clear Mode
FCON = 00h
AT/T89C51CC02
Flash Protection from Parallel
Programming
The three lock bits in Hardware Security Byte ( See ’In-System Prog ramming’ section)
are programmed according to Table 24 provide different level of protection for the onchip code and data located in FM0 and FM1.
The only way to write this bits are the parallel mode. They are set by default to level 3.
Table 24. Program Lock bit
Program Lock bits
Security
Level
1UUUNo program lock features enabled.
2PUUParallel programming of the Flash is disabled.
3UPU
4UUPSame as 3
LB0LB1LB2
Protection Description
Same as 2, also verify through parallel programming interface is
disabled. This is the factory defaul programming.
Note:1. Program Lock bits
U: unprogrammed
P: programmed
WARNING: Security level 2, 3 and 4 should only be programmed after Flash and Core
verification.
1. For DPTR higher than 007Fh o nly lo west 7 b its are dec oded, t hus th e behav ior is the sa me as for addre sses from
0000h to 007Fh
2. For DPTR higher than 007Fh o nly lo west 7 b its are dec oded, t hus th e behav ior is the sa me as for addre sses from
0000h to 007Fh
46
4126L–CAN–01/08
AT/T89C51CC02
h
In-System
Programming (ISP)
Flash Programming and
Erasure
With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash
technology the T89C51CC02 allows the system engineer the development of applications with a very high l evel of flex ibility . Th is fle xibili ty is based on the p ossibi lity t o alter
the customer program at any stages of a product’s life:
•Before mounting the chip on the PCB, FM0 flash can be programmed with the
application code. FM1 is always preprogrammed by Atmel with a bootloader (chip
can be ordered with CAN bootloader or UART bootloader).
•Once the chip is mounted on the PCB, it can be programmed by serial mode via the
CAN bus or UART.
Note:1. The user can also program his own bootloader in FM1.
This ISP allows code modification over the total lifetime of the product.
Besides the default Bootloa ders Atmel prov ide customers all the needed Applic ation-
Programming-Interfaces (API) which are nee ded for the ISP . The AP I a re loc at ed i n th e
Boot memory.
This allow the customer to have a full use of the 16-Kbyte user memory.
There are three methods for programming the Flash memory:
•The Atmel bootloader located in FM1 is activated by the application. Low level API
routines (located in FM1)will be used to program FM0. The interface used for serial
downloading to FM0 is the UART or the CAN. API can be called also by user’s
bootloader located in FM0 at [SBV]00h.
•A further method exist in activating the Atmel boot loader by hardware activation.
See the Section “Hardware Security Byte”.
•The FM0 can be programmed also by the parallel mode using a programmer.
(1)
Figure 18. Flash Memory Mapping
3FFFh
Custom
Bootloader
[SBV]00h
16K Bytes
Flash Memory
FM0
0000h
F800h
FFFFh
2K Bytes IAP
Bootloader
FM1
FM1 Mapped between F800h and FFFF
when API Called
4126L–CAN–01/08
47
AT/T89C51CC02
Boot Process
Software Boot Proc ess
Example
Figure 19. Hardware Boot Process Algorithm
Hardware
Many algorithms can be used for the software boot process. Below are descriptions of
the different flags and Bytes.
Boot Loader Jump bit (BLJB):
- This bit indicate s if on RESET the us er wants to jum p to this applic ation at addr ess
@0000h on FM0 or execute the boot loader at address @F800h on FM1.
- BLJB = 0 (i.e. boo tloader FM 1 execut ed after a res et) is t he d efault Atm el fac tory pr o-
gramming.
-To read or modify this bit, the APIs are used.
Boot Vector Address (SBV):
- This byte contains the MSB of the user boot loader address in FM0.
- The default value of SBV is FCh (no user boot loader in FM0).
- To read or modify this byte, the APIs are used.
Extra Byte (EB) & Boot Status Byte (BSB):
- These Bytes are reserved for customer use.
- To read or modify these Bytes, the APIs are used.
ENBOOT = 0
PC = 0000h
RESET
BLJB == 0
?
bit ENBOOT in AUXR1 Register
Is Initialized with BLJB Inverted.
Example, if BLJB=0, ENBOOT
is set (=1) during reset, thus the
bootloader is executed after the
reset.
Application
Software
in FM0
ApplicationProgramming-Interface
48
ENBOOT = 1
PC = F800h
Bootloader
in FM1
Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
by functions.
All these APIs are described in detail in the following documents on the Atmel web site.
–Datasheet Bootloader CAN T89C51CC02.
–Datasheet Bootloader UART T89C51CC02.
4126L–CAN–01/08
AT/T89C51CC02
XROW BytesThe EXTRA ROW (XROW) incl udes 128 bytes. Some of these bytes are us ed for spe-
cific purpose in conjonction with the bootloader.
Table 31. XROW Mapping
DescriptionDefault ValueAddress
Copy of the Manufacturer Code58h30h
Copy of the Device ID#1: Family codeD7h31h
Copy of the Device ID#2: Memories size and typeBBh60h
Copy of the Device ID#3: Name and RevisionFFh61h
Hardware ConditionsIt is possible to force the controller to ex ecute the bootl oader after a Res et with hard-
ware conditions.
During the first programming, the user can define a configuration on Port1 that will be
recognized by the chip as the hardware conditions during a Reset. If this condition is
met, the chip will start executing the bootloader at the end of the Reset.
See a detailed description in the applicable Document.
–Datasheet Bootloader CAN T89C51CC02.
–Datasheet Bootloader UART T89C51CC02.
Set this bit to start in standard mode
Clear this bit to start in X2 Mode.
Boot Loader Jump bit
- 1: To start the user ’s application on next RESET (@0000h) located in FM0,
- 0: To start the boot loader(@F800h) located in FM1.
Reserved
The value read from these bits are indeterminate.
After erasing the chip in parallel mode, the default value is : FFh
The erasing in ISP mode (from bootloader) does not modify this byte.
Notes:1. O nly the 4 MSB bi ts can be access ed by software .
2. The 4 LSB bits can only be accessed by parallel mode.
50
4126L–CAN–01/08
AT/T89C51CC02
Serial I/O PortThe T89C51CC02 I/O serial port is compatible with the I/O serial port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-dup lex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
•Framing error detection
•Automatic address recognition
Figure 20. Serial I/O Port Block Diagram
IB Bus
TXD
RXD
SBUF
Transmitter
Write SBUF
Mode 0 Transmit
RI
TI
SBUF
Receiver
Receive
Shift register
Read SBUF
Load SBUF
Serial Port
InterruptRequest
Framing Error DetectionFraming bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register.
Figure 21. Framing Error Block Diagram
SM0/FE
Set FE bit if Stop bit is 0 (Framing Error)
RITIRB8TB8RENSM2SM1
4126L–CAN–01/08
SM0 to UART Mode Control
SMOD1
To UART Framing Error Control
IDLPDGF0GF1POF-SMOD0
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register bit is set.
The software may examine the FE bit after ea ch reception to ch eck for data errors.
Once set, only softwa r e o r a r es et clea rs t he FE b it. Subsequently received fr am es wi th
valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the
stop bit instead of the last data bit (See Figure 22 and Figure 23).
51
AT/T89C51CC02
Figure 22. UART Timing in Mode 1
Automatic Address
Recognition
RXD
RI
SMOD0 = x
FE
SMOD0 = 1
Start
bit
Data Byte
D7D6D5D4D3D2D1D0
Stop
bit
Figure 23. UART Timing in Modes 2 and 3
RXD
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
Start
bit
Data ByteNinth
D8D7D6D5D4D3D2D1D0
Stop
bit
bit
The automatic addr es s rec ogn iti on feat ur e i s en abl ed when the multiprocess or c om munication feature is enabled (SM2 bit in SCON register is set).
Implemented in the hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address will the
receiver set the RI bit in the SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If necessary, the user can enab le the automati c address re cognition feat ure in mode 1.
In this configuration, the stop bit takes the place of the ninth data bit. bit RI is set only
when the received comma nd frame address matches the dev ice’s addr e ss and is term inated by a valid stop bit.
Given AddressEach device has an individual address that is specified in the SADDR register; the
52
To support automatic a ddr ess re co gni tio n, a dev ic e i s identified by a given add re ss an d
a broadcast address.
Note:The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form
the device’s given address. The don’t-care bits provide the flexibility to address one or
more slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 11111111b.
For example:
SADDR0101 0110b
1111 1100b
SADEN
Given0101 01XXb
4126L–CAN–01/08
AT/T89C51CC02
Here is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN
1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
Slave C:SADDR1111 0011b
1111 1001b
SADEN
Given1111 0XX1b
1111 1101b
SADEN
Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with sl ave A onl y, the ma ster mus t send an ad dres s where bi t 0 is clea r (e.g.
1111 0000b).
For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast AddressA broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e.g.:
SADDR 0101 0110b
SADEN 1111 1100b
SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN
1111 1010b
Given1111 1X11b,
4126L–CAN–01/08
Slave B:SADDR1111 0011b
Slave C:SADDR=1111 0010b
1111 1001b
SADEN
Given1111 1X11B,
1111 1101b
SADEN
Given1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the ma ster must se nd an add ress F Fh. To c ommun icate with sl aves A
and B, but not slave C, the master can send and address FBh.
53
AT/T89C51CC02
RegistersTable 33. SCON Register
SCON (S:98h)
Serial Control Register
76543210
FE/SM0SM1SM2RENTB8RB8TIRI
Bit
Number
7
6SM1
5SM2
4REN
3TB8
2RB8
Bit
Mnemonic Description
FE
SM0
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
Table 36. SBUF Register
SBUF (S:99h)
Serial Data Buffer
4126L–CAN–01/08
76543210
Bit
Number
7 - 0Data sent/received by Serial I/O Port
Bit
Mnemonic Description
Reset Value = 0000 0000b
Not bit addressable
55
AT/T89C51CC02
Table 37. PCON Register
PCON (S:87h)
Power Control Register
76543210
SMOD1SMOD0-POFGF1GF0PDIDL
Bit
Number
7SMOD1
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
Bit
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Clear to recognize next reset type.
Set by hardware when V
software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-down Mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle Mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
rises from 0 to its nominal voltage. Can also be set by
CC
56
Reset Value = 00X1 0000b
Not bit addressable
4126L–CAN–01/08
AT/T89C51CC02
Timers/CountersThe T89C51CC02 implements two general-purpose, 16-bit Timers/Counters. Such are
identified as Timer 0 and Timer 1, and can be indepen dently configure d to operat e in a
variety of modes as a Timer or an event Counter. When operating as a Timer, the
Timer/Counter runs for a programmed length of time, then issues an interrupt request.
When operating as a Counter, the Tim er/Counter counts n egative transit ions on an
external pin. After a preset number of counts, the Counter issues an interrupt request.
The various o perating modes o f each Ti mer/Count er are de scribed in the fo llowing
sections.
Timer/Counter
Operations
A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to
form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (See Figure 38)
turns the Timer on by allowing the selected input to increment TLx. When TLx overflows
it increments THx; when T Hx overflows it sets the T imer overflow f lag (TFx) in T CON
register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the cur rent co unt or to enter pr eset value s. They ca n be
read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the
divided-down peripheral clock or external pin T x as the source for the counted signal.
TRx bit must be cleared when changing the mode of operation, otherwise the behavior
of the Timer/Counter is unpredictable.
For Timer op erat ion (C/Tx # = 0 ), t he T ime r reg ist er co unts the div ided-d own peri phera l
clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock
periods). The Timer clock rate is f
PER
/6, i.e. f
/12 in standard m ode or f
OSC
OSC
/6 in X2
Mode.
For Counter operation (C/Tx # = 1), the T im er reg ister cou nts the neg ati ve tran si ti ons on
the Tx external input pin. The external input is sampled every peripheral cycles. When
the sample is high in one cycle and low in the next one, the Counter is incremented.
Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,
the maximum count rate is f
/12, i.e. f
PER
/24 in standard mode or f
OSC
/12 in X2 Mode.
OSC
There are no restrictions on the duty cycle of the external input signal, but to ensure that
a given level is sampl ed at least onc e before it changes, i t should be hel d for at leas t
one full peripheral cycle.
Timer 0Timer 0 functions as either a Timer or event Counter in four modes of operation.
Figure 24 through Figure 27 show the logical configuration of each mode.
Timer 0 is controlled by the four l ower bi ts of TMO D r egis ter (See F igure 39) and bits 0,
1, 4 and 5 of TCON register (See Figure 38). TMOD register selects the method of
Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10
and M00). TCON r egister pr ovides Ti mer 0 cont rol func tions: ove rflow flag (TF0), run
control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
For normal Timer ope ratio n (GAT E0 = 0) , se tting TR 0 allows TL 0 to be increme nted by
the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer
operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt request.
It is important to stop Timer/Counter before changing mode.
57
4126L–CAN–01/08
AT/T89C51CC02
Mode 0 (13-bit Timer)Mode 0 configures Timer 0 as an 13-bit Time r which is s et up as an 8-bit Timer (TH0
See section “C lock”
register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register
(See Figure 24). The upper three bits of TL0 register are indeterminate and should be
ignored. Prescaler overflow increments TH0 register.
Figure 24. Timer/Counter x (x= 0 or 1) in Mode 0
See section “Clock”
FTx
CLOCK
÷ 6
0
1
THx
(8 bits)
TLx
(5 bits)
Overflow
TFx
TCON Reg
Timer x
Interrupt
Request
Tx
C/Tx#
TMOD Reg
INTx#
GATEx
TMOD Reg
TRx
TCON Reg
Mode 1 (16-bit Timer)Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in
cascade (See Figure 25). The selected input increments TL0 register.
Figure 25. Timer/Counter x (x= 0 or 1) in Mode 1
FTx
CLOCK
Tx
INTx#
÷ 6
0
1
C/Tx#
TMOD Reg
THx
(8 bits)
TLx
(8 bits)
Overflow
TFx
TCON Reg
Timer x
Interrupt
Request
GATEx
TMOD Reg
Mode 2 (8-bit Timer with AutoReload)
58
TRx
TCON Reg
Mode 2 configures Timer 0 as an 8-b it Timer (TL0 register) tha t automatically reloads
from TH0 register (See Figure 26). TL0 overflow sets TF0 flag in TCON register and
reloads TL0 with the contents of TH0, which is preset by software. When the interrupt
request is servic ed, ha rdware clears TF0. The reload leaves TH0 unch anged. The next
reload value may be changed at any time by writing it to TH0 register.
4126L–CAN–01/08
Figure 26. Timer/Counter x (x= 0 or 1) in Mode 2
t
t
t
t
t
t
See section “Clock”
AT/T89C51CC02
FTx
CLOCK
÷ 6
0
1
TLx
(8 bits)
Overflow
TFx
TCON Reg
Timer x
Interrup
Reques
Tx
C/Tx#
TMOD Reg
INTx#
GATEx
TMOD Reg
TRx
TCON Reg
THx
(8 bits)
Mode 3 (Two 8-bit Timers)Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (See Figure 27). This mode is provided for applications requiring an additional 8bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a
Timer function (counting F
/6) and takes over use of the Timer 1 in terrupt (TF1) and
PER
run control (TR1) bits. Thus , operation of Tim er 1 is restricted when Timer 0 is in mod e
3.
Figure 27. Timer/Counter 0 in Mode 3: Two 8-bit Counters
FTx
CLOCK
T0
÷ 6
0
1
TL0
(8 bits)
Overflow
TF0
TCON.5
Timer 0
Interrup
Reques
C/T0#
TMOD.2
INT0#
GATE0
TMOD.3
FTx
CLOCK
÷ 6
See section “Clock”
TR0
TCON.4
TR1
TCON.6
TH0
(8 bits)
Overflow
TF1
TCON.7
Timer 1
Interrup
Reques
Timer 1Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. Follow-
ing comments help to understand the differences:
•Timer 1 functions as either a Timer or event Counter in three modes of operati on.
Figure 24 to Figure 26 show the logical configuration for modes 0, 1, and 2. Timer
1’s mode 3 is a hold-count mode.
•Timer 1 is controlled by the four high-order bits of TMOD register (See Figure 39)
and bits 2, 3, 6 and 7 of TCON register (See Figure 38). TMOD register selects the
method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of
operation (M11 and M01). TCON register provides Timer 1 control functions:
overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type
control bit (IT1).
•Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best
suited for this purpose.
4126L–CAN–01/08
59
AT/T89C51CC02
•For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented
by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control
Timer operation.
•Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating
an interrupt request.
•When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit
(TR1). For this situation, use Timer 1 only for applications that do not require an
interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in
and out of mode 3 to turn it off and on.
•It is important to stop Timer/Counter before changing mode.
Mode 0 (13-bit Timer)Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-
ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register
(See Figure 24). The upper 3 bi ts of TL1 r egister are ignore d. Pr escale r over flow increments TH1 register.
Mode 1 (16-bit Timer)Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in
cascade (See Figure 25). The selected input increments TL1 register.
Mode 2 (8-bit Timer with AutoReload)
Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from
TH1 register on ove rflo w (Se e Figur e 26). TL1 over flow set s TF 1 fl ag in TC ON regi ster
and reloads TL1 with the contents of TH1, which is preset by software. The reload
leaves TH1 unchanged.
Mode 3 (Halt)Placing Timer 1 in mode 3 causes it to halt and ho ld its coun t. This can be used to halt
Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
InterruptEach Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This
flag is set every time an overfl ow oc c urs. Fla gs are cl eared when v ec tor in g to the Timer
interrupt routine. Interrupts are enabled by setting
interrupts are globally enabled by setting EA bit in IEN0 register.
Figure 28. Timer Interrupt System
TF0
TCON.5
ET0
IEN0.1
TF1
TCON.7
ET1
IEN0.3
ETx bit in IEN0 register. This assumes
Timer 0
Interrupt Request
Timer 1
Interrupt Request
60
4126L–CAN–01/08
RegistersTable 38. TCON Register
TCON (S:88h)
Timer/Counter Control Register
76543210
TF1TR1TF0TR0 IE1IT1IE0 IT0
AT/T89C51CC02
Bit
Number
7TF1
6TR1
5TF0
4TR0
3IE1
2IT1
1IE0
Bit
Mnemonic Description
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Ti mer 1 register overflows.
Timer 1 Run Control bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Ti mer 0 register overflows.
Timer 0 Run Control bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (See IT1).
Set by hardware when external interrupt is detected on INT1# pin.
Interrupt 1 Type Control bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1#).
Set to select falling edge active (edge triggered) for external interrupt 1.
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (See IT0).
Set by hardware when external interrupt is detected on INT0# pin.
4126L–CAN–01/08
0IT0
Interrupt 0 Type Control bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0#).
Set to select falling edge active (edge triggered) for external interrupt 0.
Reset Value = 0000 0000b
61
AT/T89C51CC02
Table 39. TMOD Register
TMOD (S:89h)
Timer/Counter Mode Control Register
76543210
GATE1C/T1# M11M01GATE0C/T0#M10 M00
Bit
Number
7GATE1
6C/T1#
5M11Timer 1 Mode Select bits
4M01
3GATE0
2C/T0#
1M10
0
Bit
Mnemonic Description
Timer 1 Gating Control bit
Clear to enable Timer 1 whenever TR1 bit is set.
Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.
Timer 1 Counter/Timer Select bit
Clear for Timer operation: Timer 1 counts the divided-down system clock.
Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
Clear to enable Timer 0 whenever TR0 bit is set.
Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.
Timer 0 Counter/Timer Select bit
Clear for Timer operation: Timer 0 counts the divided-down system clock.
Set for Counter operation: Timer 0 counts negative transitions on external pin T0.
Timer 2The T89C51CC02 Timer 2 is compatible with Timer 2 in the 80C52.
See section “Clock”
It is a 16-bit timer/counter: the count is maintained by two eightbit timer registers, TH2
and TL2 that are cascade-co nnecte d. It is con trolled by T2CON reg ister (See Table 45)
and T2MOD register (See Table 46). Timer 2 operation is similar to Timer 0 and Timer
1. C/T2
timer clock. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 includes the following enhancements:
•Auto-reload mode (up or down counter)
•Programmable clock-output
Auto-Reload ModeThe auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto-
matic reload. This feature is controlled by the DCEN bit in T2MOD register (See Table
45). Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 29. In
this mode the T2EX pin controls the counting direction.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and gene rates an inter rupt requ est. The overfl ow a lso cau ses th e 16 -bit v alu e
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflow or underflow, depending on the direction of
the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit
resolution.
selects F
/6 (timer operation) or external pin T2 (counter operation) as
T2 clock
Figure 29. Auto-Reload Mode Up/Down Counter
FT2
CLOCK
T2
:6
0
1
CT/2
T2CON.1
(DOWN COUNTING RELOAD VALUE)
FFh
(8-bit)
TL2
8-bit)
(
RCAP2L
(8-bit)
(UP COUNTING RELOAD VALUE)
FFh
(8-bit)
TH2
(8-bit)
RCAP2H
(8-bit)
TR2
T2CON.2
T2EX:
1=UP
2=DOWN
TOGGLE
TF2
T2CON Reg
T2CON Reg
EXF2
TIMER 2
INTERRUPT
64
4126L–CAN–01/08
AT/T89C51CC02
Programmable ClockOutput
In clock-out mode , Tim er 2 ope rates as a 50 %-duty - cycle, programmable clock ge ner ator (Figure 30). The input clock increments TL2 at frequency f
/2. The timer
OSC
repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H
and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do
not generate interrupts. The formula gives the clock-out frequency depending on the
system oscillator frequenc y and the val ue in the RCAP2H and RCAP2L registers:
Clock OutFrequency–
For a 16 MHz system clock in x1 mode, Timer 2 has a programmable frequency range
of 61 Hz (f
/4). The generated clock signal is brought out to T2 pin
FT2clock
(P1.0).
Timer 2 is programmed for the clock-out mode as follows:
•Set T2OE bit in T2MOD register.
•Clear C/T2
bit in T2CON register.
•Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or different depending on the application.
•To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
Figure 30. Clock-Out Mode
FT2
CLOCK
T2
T2EX
Toggle
Q
QD
TR2
T2CON.2
EXEN2
T2CON reg
TL2
(8-bit)
RCAP2L
(8-bit)
T2OE
T2MOD reg
EXF2
T2CON reg
TH2
(8-bit)
RCAP2H
(8-bit)
OVERFLOW
TIMER 2
INTERRUPT
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AT/T89C51CC02
RegistersTable 44. T2CON Register
T2CON (S:C8h)
Timer 2 Control Register
76543210
TF2EXF2RCLKTCLKEXEN2TR2C/T2#C P/RL2#
Bit
Number
7TF2
6EXF2
5RCLK
4TCLK
3EXEN2
2TR2
Bit
Mnemonic Description
Timer 2 Overflow Flag
TF2 is not set if RCLK=1 or TCLK = 1.
Must be cleared by software.
Set by hardware on Timer 2 overflow.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software.
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
Timer 2 Run Control bit
Clear to tur n off Timer 2.
Set to turn on Timer 2.
66
1C/T2#
0C P/RL2#
Timer/Counter 2 Select bit
Clear for timer operation (input from internal clock system: f
Set for counter operation (input from T2 input pin).
Timer 2 Captur e /Reload bi t
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
Timer 2 overflow.
Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
bit addressable
).
OSC
4126L–CAN–01/08
AT/T89C51CC02
Table 45. T2MOD Register
T2MOD (S:C9h)
Timer 2 Mode Control Register
76543210
------T2OEDCEN
Bit
Number
7-
6-
5-
4-
3-
2-
1T2OE
0DCEN
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 Output Enable bit
Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
Down Counter Enable bit
Clear to disable Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
Watchdog TimerT89C51CC02 contains a powerful programmable hardware Watchdog Timer (WDT) that
automatically resets the chip if it software fails to reset the WDT before the selected time
Figure 31. Watchdog Timer
interval has elapsed. It permits large Timeout ranging from 16ms to 2s @f
in X1 mode.
This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog
Timer reset regist er (WDTRS T ) a nd a Wa tch dog T imer pr ogram min g ( WD T PRG) r egister. When exiting reset, the WDT is -by default- disable.
To enable the WDT, the user has to wr ite the sequenc e 1EH and E1H into WDTR ST
register with no instr uction between the two wri tes. When the Watchdog Timer is
enabled, it will increment every machine cycle while the oscillator is running and there is
no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will gener ate an output RESET pulse at th e RST
pin. The RESET pulse duration is 96xT
, where T
OSC
OSC
=1/f
. To make the best use of
OSC
the WDT, it should be se rviced in th ose sectio ns of code that will per iodically be executed within the time required to prevent a WDT reset
Note:When the watchdog is enable it is impossible to change its period.
= 12 MHz
OSC
Fwd Clock
RESET
WDTPRG
-
-
WDTRST
-
Enable
14-bit Counter
-
-
Decoder
WR
0
1
2
Control
7-bit Counter
Outputs
RESET
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AT/T89C51CC02
Watchdog ProgrammingThe three lower bits (S0, S1, S2) located into WDTPRG register permit to program the
WDT duration.
Table 50. Machine Cycle Count
S2S1S0Machine Cycle Count
0002
0012
0102
0112
1002
1012
1102
1112
To compute WD Timeout, the following formula is applied:
Note:Svalue represents the decimal value of (S2 S1 S0)
osc
2142
Svalue
×()
14
- 1
15
- 1
16
- 1
17
- 1
18
- 1
19
- 1
20
- 1
21
- 1
Find Hereafter computed Timeout values for f
XTAL = 12 MHz in X1 mode
OSC
Table 51. Time out Comp utat ion
S2S1S0 f
00016.38 ms12.28 ms9.82 ms
00132.77 ms24.57 ms19.66 ms
01065.54 ms49.14 ms39.32 ms
011131.07 ms98.28 ms78.64 ms
100262.14 ms196.56 ms157.28 ms
101524.29 ms393.12 ms314.56 ms
1101.05 s786.24 ms629.12 ms
1112.10 s1.57 s1.25 s
=12 MHzf
OSC
=16MHzf
OSC
=20 MHz
OSC
70
4126L–CAN–01/08
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Watchdog Timer
During Power-down
Mode and Idle
In Power-down mode the oscill ator stops, whi ch means the W DT also stops . While in
Power-down mode, the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabl ed p rio r to e nter ing Po wer-do wn mo de. W hen Powe r-down is e xite d wit h
hardware reset, the watchdog is disabled. Exiting Power-down with an interrupt is significantly different. The interrupt shall be held low long enough for the oscillator to stabilize.
When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service
for the interrupt used to exit Power-down.
To ensure that the WDT does not overflow within a few states of exiting powerdown, it is
best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting
T89C51CC02 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
Note:The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in
sequence without instruction between these two sequences.
72
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CAN ControllerThe CAN Cont ro ller prov id es al l th e fe atu re s re qui red to implement the ser ial c om mun i-
cation protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to
by ISO/11898 (2.0A & 2.0B) for high speed and ISO/11519-2 for low speed. The CAN
Controller is able to handle al l typ es of fram es (D ata, Remo te, Erro r and Ov erlo ad) and
achieves a bitrate of 1-Mbit/s at 8 MHz
Note:1. At BRP = 1 sampling point will be fixed.
CAN ProtocolThe CAN pr otocol is an inter nationa l stand ard defi ned in the ISO 1189 8 for high sp eed
and ISO 11519-2 for low speed.
PrinciplesCAN is based on a broadcast communication mechanism. This broadcast communica-
tion is achieved by using a message oriented transmission protocol. These messages
are identified by using a message identifier. Such a message identifier has to be unique
within the whole network and it defines not only the content but also the priority of the
message.
The priority at which a message is transmitted compared to another less urgent message is spe cifie d by the i dent ifier of eac h message. The priorities are laid down during
system design in the form of corresponding binary values and cannot be changed
dynamically. The identifier with the lowest binary number has the highest priority.
Bus access confl icts are r esolved by bit-wis e arbitrati on on the i dentifiers involved by
each node observing the bus level bit for bit. This happens in accordance with the "wired
and" mechanism, b y w hic h t he d omi nan t state overwrites the r ece ss i ve sta te. T h e c ompetition for bus all ocation is lost by a ll n odes with r ecessi ve tr ansm ission and domi nant
observation. All the "los ers" a utomati cally become recei vers of the messag e with the
highest priority and do not re-attempt transmission until the bus is available again.
1
Crystal frequency in X2 Mode.
Message FormatsThe CAN proto col supports two me ssage frame formats, the only essential difference
being in the length of the identifier. The CAN standard frame, also known as CAN 2.0 A,
supports a length of 11 b its for the identi fier , and the C AN exte nded frame , als o know n
as CAN 2.0 B, supports a length of 29 bits for the identifier.
Can Standard Frame
Figure 32. CAN Standard Frames
Data Frame
Bus IdleBus Idle
Interframe
Space
SOF
SOF
11-bit identifier
ID10..0
Arbitration
Field
RTR
4-bit DLC
IDE r0ACK
DLC4..0
Control
Field
0 - 8 bytes
Data
Field
15-bit CRC
CRC
Field
CRC
del.
ACK
Field
ACK
del.
7 bits
End of
Frame
Intermission
3 bits
Interframe
(Indefinite)
Space
Remote Frame
Bus IdleBus Idle
Interframe
Space
SOF
SOF
11-bit identifier
ID10..0
Arbitration
Field
RTR
A message in the CAN standard frame format begins with the "Start Of Frame (SOF)",
this is followed by the "Arbitration field" which consist of the identifier and the "Remote
Transmission Request (RTR)" bit used to distinguish between the data frame and the
data request frame called remote frame. The following "Control field" contains the "IDentifier Extension (IDE)" bit and the "Da ta Length Code (DLC)" used to indicate the
4-bit DLC
IDE r0ACK
DLC4..0
Control
Field
15-bit CRC
CRC
Field
CRC
del.
ACK
ACK
Field
del.
7 bits
End of
Frame
Intermission
3 bits
Interframe
(Indefinite)
Space
4126L–CAN–01/08
73
AT/T89C51CC02
number of followin g data byte s in the "D ata field". In a remote frame, the DLC contains
)
the number of request ed data bytes . The "Data field" that foll ows can hol d up to 8 data
bytes. The fra me integri ty is gua ranteed by the fol lowing "Cy clic Redund ant Check
(CRC)" sum . The "A CKnow ledge ( ACK) field" comp romise s the A CK slot and th e ACK
delimiter. The bit in t he A C K slot i s se nt as a re ce ss iv e bit and is ov erwr itt en a s a dom inant bit by the receivers which have at this time received the data correctly. Correct
messages are acknowledged by the receivers regardless of the result of the acceptance
test. The end of the messa ge is in dicat ed by "End Of Fram e (EOF) ". The "In termi ssion
Frame Space (IFS)" is the minimum number of bits separating consecutive messages. If
there is no following bus access by any node, the bus remains idle.
CAN Extended Frame
Figure 33. CAN Extended Frames
Data Frame
Bus IdleBus Idle
11-bit base identifier
SOF
SOF
IDT28..18
SRR
18-bit identifier extension
IDEACK
ID17..0
RTR
r0r1
4-bit DLC
DLC4..0
0 - 8 bytes
15-bit CRC
CRC
del.
ACK
del.
7 bits
Intermission
3 bits
(Indefinite
Interframe
Space
Arbitration
Field
Control
Field
Data
Field
CRC
Field
ACK
Field
End of
Frame
Interframe
Space
Remote Frame
Bus IdleBus Idle
Interframe
Space
11-bit base identifier
SOF
SOF
IDT28..18
SRR
Format Co-existenceAs the two form ats have to co- exist on one bus, it is lai d down which mes sage has
18-bit identifier extension
IDEr0
Arbitration
Field
ID17..0
RTR
4-bit DLC
r1ACK
DLC4..0
Control
Field
15-bit CRC
CRC
Field
CRC
del.
ACK
Field
ACK
del.
7 bits
End of
Frame
Intermission
3 bits
Interframe
Space
(Indefinite)
A message in th e CAN extended frame form at is li kely the same as a message in CA N
standard frame format. The difference is the length of the identifier used. The identifier is
made up of the existing 11-bit identi fier (base id entifier) and an 18-bit extens ion (identifier extension). The d istin ction between CAN stan dard fra me forma t and CAN extended
frame format is made by using the IDE bit which is trans mi tted as d omi nan t in cas e o f a
frame in CAN standard frame format, and transmitted as recessive in the other case.
higher priority on the bus in the case of bus access collision with different formats and
the same identifier / base identifier: The message in CAN standard frame format always
has priority over the message in extended format.
There are three different types of CAN modules available:
–2.0A - Considers 29 bit ID as an error
–2.0B Passive - Ignores 29 bit ID messages
–2.0B Active - Handles both 11 and 29 bit ID Messages
Bit TimingTo ensure co rrect sampling up to the la st bit, a CAN node needs to re-sync hronize
Bit ConstructionOne CAN bit time is specified as four non- overl apping time segments . Each s egment is
74
throughout the entire frame. This is done at the beginning of each message with the falling edge SOF and on each recessive to dominant edge.
constructed from an in teger multiple of the T ime Q uan tum. T he Ti me Q u antu m or TQ is
the smallest discrete timing resolution used by a CAN node.
4126L–CAN–01/08
AT/T89C51CC02
Figure 34. CAN Bit Construction
CAN Frame
(producer)
Transmission Point
(producer)
Nominal CAN Bit Time
Time Quantum
(producer)
Segments
(producer)
Segments
(consumer)
SYNC_SEG
propagation
delay
Synchronization SegmentThe first segment is used to synchronize the various bus nodes.
On transmission, at the start of thi s segment, the curren t bit level is output. If th ere is a
bit state change betwe en th e prev io us bit and t he c ur rent b it, th en t he bu s s tat e ch ange
is expected to occur within this segment by the receiving nodes.
PROP_SEGPHASE_SEG_1PHASE_SEG_2
SYNC_SEG
PROP_SEGPHASE_SEG_1PHASE_SEG_2
Sample Point
Propagation Time SegmentThis segment is used to compensate for signal delays across the network.
This is neces sary to c ompensate for signa l propag ation d elays on the bus l ine and
through the transceivers of the bus nodes.
Phase Segment 1Phase Segment 1 is used to compensate for edge phase errors.
This segment may be lengthened during resynchronization.
Sample PointThe sample point is the point of time at which the bus level is read and interpreted as the
value of the respective bit. Its location is at the end of Phase Segment 1 (between the
two Phase Segments).
Phase Segment 2This segment is also used to compensate for edge phase errors.
This segment may be shortened during resynchronization, but the length has to be at
least as long as the information processing time and may not be more than the length of
Phase Segment 1.
Information Processing TimeIt is the time required for the logic to determine the bit level of a sampled bit.
The Information pr ocessin g Time begin s at the sam ple point, is measured i n TQ and is
fixed at 2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample
point and is t he las t segm ent in the bi t time, Phase Segme nt 2 m inimum shall not be
less than the Information processing Time.
Bit LengtheningAs a result of resynchronization, Phase Segment 1 may be lengthened or Phase Seg-
ment 2 may be shortened to compensa te for osc illator tolerances. If, for ex ample, the
transmitter oscillator is slower tha n the re ceiver oscillator , the nex t falling e dge use d for
resynchronization may be delayed. So Phase Segment 1 is lengthened in order to
adjust the sample point and the end of the bit time.
4126L–CAN–01/08
75
AT/T89C51CC02
Bit ShorteningIf, on the other hand, the transmitter oscillator is faster than the receiver one, the next
-
falling edge use d for resync hroni zation ma y be too earl y. So Phas e Segment 2 in bit N
is shortened in order to adjust the sample point for bit N+1 and the end of the bit time
Synchronization Jump WidthThe limit to the amount of lengthening or shortening of the Phase Segments is set by the
Resynchronization Jump Width.
This segment may not be longer than Phase Segment 2.
Programming the Sample PointProgramming of the sample point allows "tuning" of the characteristics to suit the bus.
Early sampling allo ws more Tim e Quanta in the Phase Se gment 2 so the Synchron ization Jump Width can be programmed to its maximum. This maximum capacity to
shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances,
so that lower cost oscillators such as ceramic resonators may be used.
Late sampling allows more Time Quanta in the Propagation Time Segment which allows
a poorer bus topology and maximum bus length.
Arbitration
Figure 35. Bus Arbitration
Arbitration lost
node A
TXCAN
node B
TXCAN
CAN bus
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
SOF
SOF
Node A loses the bus
Node B wins the bus
RTR IDE
- - - - - - - -
The CAN protocol handles bus accesses according to the concept called “Carrier Sense
Multiple Access with Arbitration on Message Priority”.
During transmission, arbitra tion on the CAN bus can be lost to a com peting device with
a higher priority CAN Identifier. This arbitration concept avoids collisions of messages
whose transmission was started by more than one node simultaneously and makes sure
the most important message is sent first without time loss.
The bus access conflic t is res olved du ring the a rbitra tion fi eld mostl y over the iden tifier
value. If a data frame and a remote frame wi th the same ident ifier are initi ated at the
same time, the data frame prevails over the remote frame (c.f. RTR bit).
ErrorsThe CAN protocol signals any errors immediately as they occur. Three error detection
mechanisms are implemented at the message level and two at the bit level:
Error at Message Level•Cyclic Redundancy Check (CRC)
The CRC safeguards the information in the frame by adding redundant check bits at
the transmission end. At the receiver these bits are re-computed and tested against
the received bits. If they do not agree there has been a CRC error.
76
•Frame Check
This mechanism verifies the structure of the transmitted frame by checking the bit
4126L–CAN–01/08
AT/T89C51CC02
fields against the fixed format and the frame size. Errors detected by frame checks
are designated "format errors".
•ACK Errors
As already mentioned frames received are acknowledged by all receivers through
positive acknowledgement. If no acknowledgement is received by the transmitter of
the message an ACK error is indicated.
Error at Bit Level•Monitoring
The ability of the transmitter to detect errors is based on the monitoring of bus
signals. Each node which transmits also observes the bus level and thus detects
differences between the bit sent and the bit received. This permits reliable detection
of global errors and errors local to the transmitter.
•Bit Stuffing
The coding of the individual bits is tested at bit level. The bit representation used by
CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency
in bit coding. The synchronization edges are generated by means of bit stuffing.
Error SignallingIf one or more errors are discovered by at least one node using the above mechanisms,
the current transmission is aborted by sending an "error flag". This prevents other nodes
accepting the messa ge and thus ensures the cons istency of data thro ughout the network. After transmission of an erroneou s message that has been aborted, the sender
automatically re-attempts transmission.
CAN Controller
Description
The CAN controller accesses are made through SFR.
Several operations are possible by SFR:
•arithmetic and logic operations, transfers and program control (SFR is accessible by
direct addressing).
•4 independent message objects are implemented, a pagination system manages
their accesses.
Any message o bj ec t c an be programmed in a r ec ept ion b u ffe r bl oc k ( ev en non -con secutive buffers ). For the r eceptio n of def ined mes sages on e or seve ral rec eiver me ssage
objects can be masked without participating in the buffer feature. An IT is generated
when the buffer is full. The frames foll owing the buffer-full interrupt will not be take n in to
account until at least one of the buffer message objects is re-enabled in reception.
Higher priority of a message object for reception or transmiss ion is given to the lower
message object number.
The programmable 16-b it Time r (CANT IMER ) is used to st amp e ach r eceive d and sent
message in the CANSTMP register. This timer starts counting as soon as the CAN controller is enabled by the ENA bit in the CANGCON register.
The Time Trigger Communication (TTC) protocol is supported by the T89C51CC02.
4126L–CAN–01/08
77
AT/T89C51CC02
Figure 36. CAN Controller Block Diagram
TxDC
RxDC
bit
Timing
Logic
Error
Counter
Rec/Tec
bit
Stuffing /Destuffing
Cyclic
Redundancy Check
ReceiveTransmit
CAN Controller Mailbox
and Registers
Organization
Page
Register
The pagination allows management of the 91 registers including 80(4 x 20) Bytes of
mailbox via 32 SFRs.
All actions on the message object window SFRs apply to the corresponding message
object registers pointed by the message object number find in the Page message object
register (CANPAGE) as illustrate in Figure 37.
DPR(Mailbox + Registers)
µC-Core Interface
Interface
Bus
Core
Control
Priority
Encoder
78
4126L–CAN–01/08
Figure 37. CAN Controller Memory Organization
SFRsOn-chip CAN Controller Registers
General Control
General Status
General Interrupt
bit Timing - 1
bit Timing - 2
bit Timing - 3
Enable message object
Enable Interrupt
Enable Interrupt message object
Status Interrupt message object
Timer Control
CANTimer High
CANTimer Low
TimTTC High
TimTTC Low
TEC counter
REC counter
Page message object
(message object number)(Data offset)
AT/T89C51CC02
4 Message Objects
message object Status
message object Control & DLC
Message Data
ID Tag - 1
ID Tag - 2
ID Tag - 3
ID Tag - 4
ID Mask - 1
ID Mask - 2
ID Mask - 3
ID Mask - 4
TimStmp High
TimStmp Low
message object Window SFRs
message object 0 - Status
message object 0 - Control & DLC
Ch.0 - Message Data - byte 0
8 Bytes
Ch.0 - ID Tag - 1
Ch.0 - ID Tag - 2
Ch.0 - ID Tag - 3
Ch.0 - ID Tag - 4
Ch.0 - ID Mask- 1
Ch.0 - ID Mask- 2
Ch.0 - ID Mask- 3
Ch.0 - ID Mask - 4
Ch.0 TimStmp High
Ch.0 TimStmp Low
message object 3 - Status
message object 3 - Control & DLC
Ch.3 - Message Data - byte 0
Ch.3 - ID Tag - 1
Ch.3 - ID Tag - 2
Ch.3 - ID Tag - 3
Ch.3 - ID Tag - 4
Ch.3 - ID Mask - 1
Ch.3 - ID Mask - 2
Ch.3 - ID Mask - 3
Ch.3 - ID Mask - 4
Ch.3 TimStmp High
Ch.3 TimStmp Low
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AT/T89C51CC02
Working on Message ObjectsThe Page message object regi ster ( CANPA GE) is used t o sele ct one o f the 4 me ssag e
objects. Then, message object Control (CANCONCH) and message object Status
(CANSTCH) are available for this selected message object number in the corresponding
SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is
managed by the Page message object register with an auto-incrementation at the end of
each access. The range of this counter is 8.
Note that the maibox is a pure RAM, ded ic ate d to one mes sa ge ob je ct, wi tho ut over la p.
In most cases, i t is n ot neces sary to transfe r the rec eived me ssage i nto t he stand ard
memory. The message to be transmitted can be built directly in the maibox. Most calculations or tests can be executed in the mailbox area which provide quicker access.
CAN Controller
Management
In order to enable the CAN Controller correctly the following registers have to be
initialized:
•General Control (CANGCON),
•bit Timing (CANBT 1, 2 & 3),
•And for each page of 15 message objects:
–Message object Control (CANCONCH),
–Message object Status (CANSTCH).
During operation, the CAN Enable message object registers (CANEN) gives a fast overview of the message objects availability.
The CAN messages can be handled by interrupt or polling modes.
A message object can be configured as follows:
•Transmit message object
•Receive message object
•Receive buffer message object
•Disable
This configuration is made in the CONCH field of the CANCONCH register (See
Table 54).
When a message object is configured, the corresponding ENCH bit of CANEN register
is set.
When a Tran smitter or Recei ver act ion of a mes sage o bject is complet ed, the c orresponding ENCH bit of the CANEN register is cleared. In order to re-enable the message
object, it is necessary to re-write the configuration in CANCONCH register.
Non-consecutive message objects can be used for all three types of message objects
(Transmitter, Receiver and Receiver buffer).
4126L–CAN–01/08
AT/T89C51CC02
Buffer ModeAny messag e objec t can be u sed to de fine on e buffer , includ ing non -cons ecutiv e mes-
sage objects, and with no limitation in number of message objects used up to 4.
Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1;
The same acceptance filter must be defined for each message objects of the buffer.
When there is no mask on the identifier or the IDE, all messages are accepted.
A received frame will always be stored in the lowest free message object.
When the flag RxOk is set on one of the buffer message objects, this message object
can then be read by t he a ppl ic ation. This flag must then be cl ear ed by th e software and
the message object re-enabled in buffer reception in order to free the message object.
buffer 0
The OVRBUF flag in the CANGIT register is set when the buffer is full. This flag can
generate an interrupt.
The frames following the buffer-full interrupt will not be stored and no status will be overwritten in the CANSTCH registers involved in the buffer until at least one of the buffer
message objects is re-enabled in reception.
This flag must be cleared by the software in order to ack nowledge the interrupt.
IT CAN ManagementThe different interrupts are:
•Transmission interrupt
•Reception int erru pt
•Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error)
•Interrupt when Buffer receive is full
•Interrupt on overrun of CAN Timer
4126L–CAN–01/08
81
AT/T89C51CC02
Figure 39. CAN Controller Interrupt Structure
IT
CANGIE.5
ENRX
CANGIE.4
ENTX
CANGIE.3
ENERCH
RXOK i
CANSTCH.5
TXOK i
CANSTCH.6
BERR i
CANSTCH.4
SERR i
CANSTCH.3
CERR i
CANSTCH.2
FERR i
CANSTCH.1
AERR i
CANSTCH.0
OVRBUF
CANGIT.4
SERG
CANGIT.3
CERG
CANGIT.2
FERG
CANGIT.1
AERG
CANGIT.0
CANSIT
SIT i
SIT i
CANIE
EICH i
CANGIE.2
ENBUF
CANGIE.1
ENERG
i=0
i=4
CANGIT.7
CANIT
IEN1.0
ECAN
CAN
IEN1.2
ETIM
OVRTIM
CANGIT.5
To enable a transmission interrupt:
•Enable General CAN IT in the interrupt system register
•Enable interrupt by message object, EICHi
•Enable transmission interrupt, ENTX
To enable a reception interrupt:
•Enable General CAN IT in the interrupt system register
•Enable interrupt by message object, EICHi
•Enable reception interrupt, ENRX
To enable an interrupt on message object error:
•Enable General CAN IT in the interrupt system register
•Enable interrupt by message object, EICHi
•Enable interrupt on error, ENERCH
To enable an interrupt on general error:
•Enable General CAN IT in the interrupt system register
•Enable interrupt on error, ENERG
OVRIT
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4126L–CAN–01/08
AT/T89C51CC02
To enable an interrupt on Buffer-full condition:
•Enable General CAN IT in the interrupt system register
•Enable interrupt on Buffer full, ENBUF
To enable an interrupt when Timer overruns:
•Enable Overrun IT in the interrupt system register
When an interrupt occurs, the corresponding message obj ect bit is set in the SIT
register.
To acknowledge an interrupt, the corr esponding CANSTCH bi ts (RXOK, TXOK,...) or
CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application.
When the CAN node is in transm is si on an d dete ct s a For m Er ror in its fr ame , a bit Er ror
will also be rai se d. Cons eq uen tly , two co nse cu tiv e in ter rupts c an oc cur , b oth du e to the
same error.
When a message object error occu rs and is set in CANSTCH regi ster, no general error
are set in CANGIE register.
4126L–CAN–01/08
83
AT/T89C51CC02
Bit Timing and Baud
t
Rate
FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time
quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s.
Field and segment abbrevia tio ns :
•BRP: Baud Rate Prescaler.
•TQ: Time Quantum (output of Baud Rate Prescaler).
•SYNS: SYNchronization Segment is 1 TQ long.
•PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.
•PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.
•PHS2: PHase Segment 2 is programmable to be superior or eual to the Information
Processing Time and inferior or equal to TPHS1
•INFORMATION PROCESSING TIME is 2 TQ.
•SJW: (Re) Synchronization Jump Width is programmable to be minimum of PHS1
and 4.
The total number of TQ in a bit time has to be programmed at least from 8 to 25.
The total number of Tscl (Time Quanta) in a bit time must be comprised between 8 to
25.
84
4126L–CAN–01/08
Figure 41. General Structure of a bit Period
nt
(
(
(
(
1/ Fcan
Oscillator
AT/T89C51CC02
System Clock
Data
1) Phase error ≤ 0
2) Phase error ≥ 0
3) Phase error > 0
4) Phase error < 0
Tscl
bit Rate Prescaler
One Nominal bit
Tsyns (*)
(*) Synchronization Segment: SYNS
Tsyns = 1xTscl (fixed)
example of bit timing determination for CAN baudrate of 500 kbit/s:
F
= 12 MHz in X1 mode => FCAN = 6MHz
OSC
Verify that the CAN baud rate you want is an integer division of FCAN clock.
FCAN/CANbaudrate = 6 MHz/500 kHz = 12
The time quanta TQ must be comprised between 8 and 25: TQ = 12 and BRP = 0
Tprs
Tbit calculation:
Tphs1 (1)
Tphs1 + Tsjw (3)
Tbit
TbitTsyns Tprs Tphs 1Tphs2++ +=
Tphs2 - Tsjw (4)
Sample Point
Tphs2 (2)
Transmission Poi
Define the various timing parameters: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 =
12TQ
Tsyns = 1TQ and Tsjw =1TQ => SJW = 0
If we chose a sample point at 66.6% => Tphs2 = 4TQ => PHS2 = 3
Tbit = 12 = 4 + 1 + Tphs1 + Tprs, let us choose Tprs = 3 Tphs1 = 4
PHS1 = 3 and PRS = 2
BRP = 0 so CANBT1 = 00h
SJW = 0 and PRS = 2 so CANBT2 = 04h
PHS2 = 3 and PHS1 = 3 so CANBT3 = 36h
4126L–CAN–01/08
85
AT/T89C51CC02
Fault ConfinementWith respect to fault confinement, a unit may be in one of the three following status:
•Error active
•Error passive
•Bus off
An error active unit takes part in bus communication and can send an active error frame
when the CAN macro detects an error.
An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a
transmission, an error passive unit will wait before initiating further transmission.
A bus off unit is not allowed to have any influence on the bus.
For fault confinement, two error counters (TEC and REC) are implemented.
See CAN Specification for details on Fault confinement.
Figure 42. Line Error Mode
ERRP = 0
BOFF = 0
Init.
TEC: Transmit Error Counter
REC: Receive Error Counter
TEC>127
or
REC>127
ERRP = 1
BOFF = 0
Error
Passive
Error
Active
TEC<127
and
REC<127
TEC>255
128 Occurrences
of
11 Consecutive
Recessive
bit
Bus
Off
ERRP = 0
BOFF = 1
86
4126L–CAN–01/08
AT/T89C51CC02
Acceptance FilterUpon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received
and an ID+RTR+RB+IDE sp ecified while taking the c omparison mask into acc ount) the
ID+RTR+RB+IDE received are written over the ID TAG Registers.
ID => IDT0-29
RTR => RTRTAG
RB => RB0-1TAG
IDE => IDE in CANCONCH register
Figure 43. Acceptance Filter Block Diagram
RxDC
Rx Shift Register (internal)
ID & RBRTR IDE
13/32
=
Write
Enable
13/32
13/32
ID TAG Registers (Ch i) & CanConch
ID & RBRTR
example:
To accept only ID = 318h in part A.
ID MSK = 111 1111 1111 b
ID TAG = 011 0001 1000 b
IDE
13/32
1
13/32
ID MSK Registers (Ch i)
ID & RBRTR IDE
Hit
(Ch i)
4126L–CAN–01/08
87
AT/T89C51CC02
Data and Remote FrameDescription of the different steps for:
r
•Data frame
Node ANode B
K
K
V
O
L
O
X
P
X
R
T
R
D
u uuuu
c ucuu
A
T
A
F
R
A
M
E
message object in tran sm iss i on
message object disabled
•Remote frame, with automatic reply
H
C
R
T
N
R
E
0 1x 0 0
0 0x 1 0
H
V
L
C
R
P
T
N
T
R
R
E
0 1x 0 0
0 0x 0 1
u uuuu
u ccuu
K
K
O
O
X
X
R
message object in reception
message object disabled
H
C
R
T
N
R
E
message object in transmission
message object in reception
by CAN controllerby CAN controller
message object disabled
1 1x 0 0
0 1x 1 0
0 0x 0 1
cuu
K
K
V
O
L
O
X
P
X
R
T
R
R
E
M
u uuuu
c uuuc
c
u
O
T
E
F
R
A
M
E
E
M
A
R
F
)
e
A
t
a
T
i
A
d
D
e
m
m
i
(
H
C
R
T
N
R
E
1 11 0 0
0 10 0 0
0 00 1 0
K
K
V
O
L
O
X
P
X
R
T
R
u uuuu
u uucc
c uccu
message object in reception
message object in transmission
message object disabled
•Remote frame
K
K
V
O
L
O
X
P
X
R
R
T
u uuuu
u ccuu
u uuuu
c ucuu
message object in rece ption
message object disabled
message obj ect in transmission by use
message object disabled
message object in transmission
message object disabled
message object in reception
by user
H
V
C
L
R
P
T
N
T
E
R
R
1 1x 0 0
0 1x 1 0
0 0x 0 1
u uuuu
c uuuc
u ccuc
K
K
O
O
X
X
R
R
E
M
O
T
E
F
R
A
M
E
E
M
A
R
F
)
d
A
e
T
r
r
A
e
f
D
e
d
(
H
C
R
T
N
R
E
1 10 0 0
1 00 0 1
0 1x 0 0
0 0x 1 0
88
i
: modified by user
u
i
: modified by CAN
c
4126L–CAN–01/08
AT/T89C51CC02
Time Trigger
Communication (TTC)
and Message Stamping
The T89C51CC02 has a progr ammable 1 6-bit Timer ( CANTIMH&CA NTIML) for message stamp and TTC.
This CAN Timer starts after th e CAN contr oller is enabl ed by th e ENA bit i n the CANGCON register.
Two modes in the timer are implemented:
•Time Trigger Communication:
–Capture of this timer value in the CANTTCH & CANTTCL registers on Start
Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC bit in
the CANGCON register, when the network is configured in TTC by the TTC
bit in the CANGCON register.
Note:In this mode, CAN only sends the frame once, even if an error occurs.
•Message Stamping
–Capture of this timer value in the CANSTMPH & CANSTMPL registers of the
message object which received or sent the frame.
–All messages can be stamps.
–The stamping of a received frame occurs when the RxOk flag is set.
–The stamping of a sent frame occurs when the TxOk flag is set.
The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base.
When the timer roll-over from FFFFh to 0000h, an interrupt is generated if the ETIM bit
in the interrupt enable register IEN1 is set.
Figure 44. Block Diagram of CAN Timer
Fcan
CLOCK
TXOK i
CANSTCH.4
RXOK i
CANSTCH.5
CANSTMPH & CANSTMPL
÷ 6
CANTCON
CANTIMH & CANTIML
CANGCON.1
ENA
CANTTCH & CANTTCL
When 0xFFFF to 0x0000
CANGCON.5
TTC
OVRTIM
CANGIT.5
CANGCON.4
SYNCTTC
SOF on CAN frame
EOF on CAN frame
4126L–CAN–01/08
89
AT/T89C51CC02
CAN Autobaud and
Listening Mode
To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must
be set. In this mode, the CAN controll er is only listening to the line wi thout ackno wledging the received messages. It cannot send any message. The error flags are updated.
The bit timing can be adjusted until no error occurs (good configuration find).
In this mode, the error counters are frozen.
To go back to the standard mode, the AUTOBAUD bit must be cleared.
Figure 45. Autobaud Mode
TxDC
TxDC
AUTOBAUD
CANGCON.3
RxDC
Routine Examples1. Init of CAN macro
// Reset the CAN macro
CANGCON = 01h;
// Disable CAN interrupts
ECAN = 0;
ETIM = 0;
// Init the Mailbox
for num_page =0; num_page <4; num_page++
{
CANPAGE = num_channel << 4;
CANCONCH = 00h
CANSTCH = 00h;
CANIDT1 = 00h;
CANIDT2 = 00h;
CANIDT3 = 00h;
CANIDT4 = 00h;
CANIDM1 = 00h;
CANIDM2 = 00h;
CANIDM3 = 00h;
CANIDM4 = 00h;
for num_data =0; num_data <8; num_data++)
{
CANMSG = 00h;
}
}
// Configure the bit timing
CANBT1 = xxh
CANBT2 = xxh
CANBT3 = xxh
RxDC
1
0
90
4126L–CAN–01/08
AT/T89C51CC02
// Enable the CAN macro
CANGCON = 02h
2. Configure message object 3 in reception to receive only standard (11bit
identifier) message 100h
// Select the message object 3
CANPAGE = 30h
// Enable the interrupt on this message object
CANIE = 08h
// Clear the status and control register
CANSTCH = 00h
CANCONCH= 00h
// Init the acceptance filter to accept only message 100h in standard mode
CANIDT1 = 20h
CANIDT2 = 00h
CANIDT3 = 00h
CANIDT4 = 00h
CANIDM1 = FFh
CANIDM2 = FFh
CANIDM3 = FFh
CANIDM4 = FFh
// Enable channel in reception
CANCONCH = 88h // enable reception
Note: to enable the CAN interrupt in reception:
EA = 1
ECAN = 1
CANGIE = 20h
3. Send a message on the message object 0
// Select the message object 0
CANPAGE = 00h
// Enable the interrupt on this message object
CANIE = 01h
// Clear the Status register
CANSTCH = 00h;
// load the identifier to send (ex: 555h)
CANIDT1 = AAh;
CANIDT2 = A0h;
// load data to send
CANMSG = 00h
CANMSG = 01h
CANMSG = 02h
CANMSG = 03h
CANMSG = 04h
CANMSG = 05h
CANMSG = 06h
CANMSG = 07h
// configure the control register
CANCONCH = 18h
4. Interrupt routine
// Save the current CANPAGE
4126L–CAN–01/08
91
AT/T89C51CC02
// Find the first message object which generate an interrupt in CANSIT
// Select the corresponding message object
// Analyse the CANSTCH register to identify which kind of interrupt is
generated
// Manage the interrupt
// Clear the status register CANSTCH = 00h;
// if it is not a channel interrupt but a general interrupt
// Manage the general interrupt and clear CANGIT register
// restore the old CANPAGE
92
4126L–CAN–01/08
CAN SFRs
Table 55. SFR Mapping
(1)
0/8
AT/T89C51CC02
1/92/A3/B4/C5/D6/E7/F
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
IPL1
xxxx x000CH0000 0000
B
0000 0000
IEN1
xxxx x000CL0000 0000
ACC
0000 0000
CCON
0000 0000
PSW
0000 0000
T2CON
0000 0000
P4
xxxx xx11
IPL0
x000 0000
P3
1111 1111
IEN0
0000 0000
P2
xxxx xx11
CMOD
0xxx x000
FCON
0000 0000
T2MOD
xxxx xx00
CANGIE
1100 0000
SADEN
0000 0000
CANPAGE
1100 0000
SADDR
0000 0000
CANTCON
0000 0000
CCAP0H
0000 0000
ADCLK
xxx0 0000
CCAP0L
0000 0000
CCAPM0
x000 0000
EECON
xxxx xx00
RCAP2L
0000 0000
CANSTCH
xxxx xxxx
CANGSTA
1010 0000
(2)
AUXR1
xxxx 00x0
CCAP1H
0000 0000
ADCON
x000 0000
CCAP1L
0000 0000
CCAPM1
x000 0000
RCAP2H
0000 0000
CANIE
1111 0000
CANSIT
xxxx 0000
CANCONCH
xxxx xxxx
CANGCON
0000 0000
CANMSG
xxxx xxxx
ADDL
0000 0000
TL2
0000 0000
CANIDM1
xxxx xxxx
CANIDT1
xxxx xxxx
CANBT1
xxxx xxxx
CANTIML
0000 0000
CANTTCL
0000 0000
ADDH
0000 0000
TH2
0000 0000
CANIDM2
xxxx xxxx
CANIDT2
xxxx xxxx
CANBT2
xxxx xxxx
CANTIMH
0000 0000
CANTTCH
0000 0000
ADCF
0000 0000
CANIDM3
xxxx xxxx
CANIDT3
xxxx xxxx
CANBT3
xxxx xxxx
CANSTMPL
xxxx xxxx
WDTRST
1111 1111
IPH1
xxxx x000
CANEN
xxxx 0000
CANIDM4
xxxx xxxx
CANIDT4
xxxx xxxx
IPH0
x000 0000
CANSTMPH
xxxx xxxx
WDTPRG
xxxx x000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
98h
90h
88h
80h
4126L–CAN–01/08
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
(1)
0/8
SBUF
0000 0000
TMOD
0000 0000
SP
0000 0111
1/92/A3/B4/C5/D6/E7/F
TL0
0000 0000
DPL
0000 0000
CANGIT
0x00 0000
TL1
0000 0000
DPH
0000 0000
CANTEC
0000 0000
TH0
0000 0000
CANREC
0000 0000
TH1
0000 0000
CKCON
0000 0000
PCON
00x1 0000
9Fh
97h
8Fh
87h
93
AT/T89C51CC02
RegistersTable 56. CANGCON Register
CANGCON (S:ABh)
CAN General Control Register
7654 3210
ABRQOVRQTTCSYNCTTC AUTOBAUDTESTENAGRES
Bit NumberBit MnemonicDescription
7ABRQ
6OVRQ
5TTC
4SYNCTTC
Abort Request
Not an auto-resetable bit. A reset of the ENCH bi t (message object
control & DLC register) is done for each message object. The
pending transmission communications are immediately aborted but
the on-going communication will be terminated normally, setting
the appropriate status flags, TxOk or RxOk.
Overload Frame Request (Initiator).
Auto-resetable bit.
Set to send an overload frame after the next received message.
Cleared by the hardware at the beginning of transmission of the
overload frame.
Network in Timer Trigger Communication
set to select node in TTC.
clear to disable TTC features.
Synchronization of TTC
When this bit is set the TTC timer is caught on the last bit of the
End Of Frame.
When this bit is clear the TTC timer is caught on the Start Of
Frame.
This bit is only used in the TTC mode.
3AUTOBAUD
2TEST
1ENA/STB
0GRES
Reset Value = 0000 0000b
AUTOBAUD
set to active listening mode.
Clear to disable listening mode
Test mode. The test mode is intended for factory testing and not for
customer use.
Enable/Standby CAN Controller
When this bit is set, it enables the CAN controller and its input
clock.
When this bit is clear, the on-going communication is terminated
normally and the CAN controller state of the machine is frozen (the
ENCH bit of each message object does not change).
In the standby mode, the transmitter constantly provides a
recessive level; the receiver is not activated and the input clock is
stopped in the CAN controller. During the disable mode, the
registers and the mailbox remain accessible.
Note that two clock periods are needed to start the CAN controller
state of the machine.
General Reset (Software Reset).
Auto-resetable bit. This reset command is ‘ORed’ with the
hardware reset in order to reset the controller. After a reset, the
controller is disabled.
94
4126L–CAN–01/08
AT/T89C51CC02
Table 57. CANGSTA Register
CANGST A (S:AAh Read Only)
CAN General Status Register
76543210
-OVFG-TBSYRBSYENFGBOFFERRP
Bit NumberBit MnemonicDescription
7-
6OVFG
5-
4TBSY
3RBSY
2ENFG
1BOFF
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Overload frame flag
This status bit is set by the hardware as long as the produced
overload frame is sent.
This flag does not generate an interrupt
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Transmitter busy
This status bit is set by the hardware as long as the CAN
transmitter generates a frame (remote, data, overload or error
frame) or an ack field. This bit is also active during an InterFrame
Spacing if a frame must be sent.
This flag does not generate an interrupt.
Receiver busy
This status bit is set by the hardware as long as the CAN receiver
acquires or monitors a frame.
This flag does not generate an interrupt.
Enable on-chip CAN controller flag
Because an enable/disable command is not effective immediately,
this status bit gives the true state of a chosen mode.
This flag does not generate an interrupt.
Bus off mode
See Figure 42
4126L–CAN–01/08
0ERRP
Reset Value = x0x0 0000b
Error passive mode
See Figure 42
95
AT/T89C51CC02
Table 58. CANGIT Register
CANGIT (S:9Bh)
CAN General Interrupt
76543210
CANIT-OVRTIMOVRBUFSERGCERGFERGAERG
Bit NumberBit MnemonicDescription
General interrupt flag
7CANIT
This status bit is the image of all the CAN controller interrupts sent
to the interrupt controller.
It can be used in the case of the polling method.
(1)
6-
5OVRTIM
4OVRBUF
3SERG
2CERG
1FERG
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Overrun CAN Timer
This status bit is set when the CAN timer switches 0xFFFF to
0x0000.
If the bit ETIM in the IE1 register is set, an interrupt is generated.
Clear this bit in order to reset the interrupt.
Overrun BU FFER
0 - no interrupt.
1 - IT turned on
This bit is set when the buffer is full.
bit resetable by user.
See Figure 39.
Stuff Error General
Detection of more than five consecutive bits with the same polarity.
This flag can generate an interrupt. resetable by user.
CRC Error General
The receiver performs a CRC check on each destuffed received
message from the start of frame up to the data field.
If this checking does not match with the destuffed CRC field, a
CRC error is set.
This flag can generate an interrupt. resetable by user.
Form Error General
The form error results from one or more violations of the fixed form
in the following bit fields:
CRC delimiter
acknowledgment delimiter
end_of_frame
This flag can generate an interrupt. resetable by user.
96
0AERG
Note:1. This field is Read Only.
Reset Value = 0x00 0000b
Acknowledgment Error G en e r a l
No detection of the dominant bit in the acknowledge slot.
This flag can generate an interrupt. resetable by user.
4126L–CAN–01/08
AT/T89C51CC02
Table 59. CANTEC Register
CANTEC (S:9Ch Read Only) – CAN Transmit Error Counter
The values read from these bits are indeterminate. Do not set these
bits.
5ENRX
4ENTX
3ENERCH
2ENBUF
1E NERG
0-
Reset Value = xx00 000xb
Enable Receive Interrupt
0 - Disable
1 - Enable
Enable Transmit Interrupt
0 - Disable
1 - Enable
Enable Message Object Error Interrupt
0 - Disable
1 - Enable
Enable BUF Interrupt
0 - Disable
1 - Enable
Enable General Error Interrupt
0 - Disable
1 - Enable
Reserved
The value read from this bit is indeterminate. Do not set this bit.
See Figure 39.
98
4126L–CAN–01/08
AT/T89C51CC02
Table 62. CANEN Register
CANEN (S:CFh Read Only)
CAN Enable Message Object Registers
76543210
----ENCH3ENCH2ENCH1ENCH0
Bit NumberBit MnemonicDescription
Reserved
7 - 4-
3 - 0ENCH3:0
Reset Value = xxxx 0000b
Table 63. CANSIT Register
CANSIT (S:BBh Read Only) – CAN Status Interrupt Message Object Registers
The values read from these bits are indeterminate. Do not set these
bits.
Enable Message Object
0 - message object is disabled => the message object is free for a
new emission or reception.
1 - message object is enabled.
This bit is resetable by re-writing the CANCONCH of the
corresponding message object.
76543210
----SIT3SIT2SIT1SIT0
Bit NumberBit MnemonicDescription
Reserved
7 - 4-
3 - 0SIT3:0
The values read from these bits are indeterminate. Do not set these
bits.
Status of Interrupt by Message Object
0 - no interrupt.
1 - IT turned on. Reset when interrupt condition is cleared by user.
SIT3:0 = 0b 0000 1001 -> IT’s on message objects 3 & 0.
See Figure 39.
Reset Value = xxxx0000b
4126L–CAN–01/08
99
AT/T89C51CC02
Table 64. CANIE Register
CANIE (S:C3h) – CAN Enable Interrupt message object Registers
76543210
----IECH 3IECH 2IECH 1IECH 0
Bit NumberBit MnemonicDescription
Reserved
7 - 4-
3 - 0IECH3:0
The values read from these bits are indeterminate. Do not set these
bits.
Enable Interrupt by Message Object
0 - disable IT.
1 - enable IT.
IECH3:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2.
Reset Value = xxxx 0000b
Table 65. CANBT1 Register
CANBT1 (S:B4h) – CAN bit Timing Registers 1
76543210
-BRP 5BRP 4BRP 3BRP 2BRP 1BRP 0-
Bit NumberBit MnemonicDescription
7-
6 - 1BRP5:0
0-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Prescaler
The period of the CAN controller system clock Tscl is
programmable and determines the individual bit timing.
Tscl =
Reserved
The value read from this bit is indeterminate. Do not set this bit.
BRP[5..0] + 1
F
CAN
(1)
Note:1. The CAN controller bi t tim ing r egi ste rs m us t be ac ce ss ed only if th e C AN con trol ler is
disabled with the ENA bit of the CANGCON register set to 0.
See Figure 41.
No default value after reset.
100
4126L–CAN–01/08
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