ATMEL AT89C51CC02 User Manual

BDTIC www.bdtic.com/ATMEL

Features

80C51 Core Architecture
256 Bytes of On-chip RAM
256 Bytes of On-chip XRAM
16K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C – Erase/Write Cycle: 100K
2K Bytes of On-chip Flash for Bootloader
In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
2K Bytes of On-chip EEPROM
– Erase/Write Cycle: 100K
14-sources 4-level Interrupts
Three 16-bit Timers/Coun ter s
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)
Three or Four Ports: 16 or 20 Digital I/O Lines
Two-channel 16-bit PCA
– PWM (8-bit) – High-speed Output – Timer and Edge Capture
Double Data Pointer
21-bit Watchdog Timer (7 Programmable bits)
A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs
Full CAN Controller
– Fully Compliant with CAN rev.# 2.0A and 2.0B – Optimized Structure for Communication Management (Via SFR) – 4 Independent Message Objects
-Each Message Object Programmable on Transmission or Reception
-Individual Tag and Mask Filters up to 29-bit Identifier/Channel
-8-byte Cyclic Data Regis ter (FIFO)/Message Object
-16-bit Status and Control Register/Message Object
-16-bit Time-Stamping Register/Message Object
-CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object
-Access to Message Object Control and D ata Registers Via SFR
-Programmable Reception Buffer Length up to 4 Message Objects
-Priority Management of Reception of Hits on Several Message Objects Simultaneously (Basic CAN Feature)
-Priority Management for Transmission
-Message Object Overrun Interrupt
– Supports
-Time Triggered Communication
-Autobaud and Listening Mode
-Programmable Automatic Reply Mode
1-Mbit/s Maximum Transfer Rate at 8 MHz
Readable Error Counters
Programmable Link to On-chip Timer for Time Stamping and Network Synchronization
Independent Baud Rate Prescaler
Data, Remote, Error and Overload Frame Handling
Power-saving Modes
–Idle Mode – Power-down Mode
Power Supply: 3 Volts to 5.5 Volts
Temperature Range: Industrial (-40° to +85°C)
Packages: SOIC28, SOIC24, PLCC28, VQFP32
(1)
Crystal Frequency In X2 Mode
Enhanced 8-bit Microcontroller with CAN Controller and Flash
T89C51CC02 AT89C51CC02
Note: 1. At BRP = 1 sampling point will be fixed.
Rev. 4126L–CAN–01/08
AT/T89C51CC02

Description Part of the CANary

tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller. In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CA N controll er T89C51CC02 p rovides 16K Bytes of Fl ash memory
including In-Sy stem Programm ing (ISP), 2K Byt es Boot Flash Mem ory, 2K Bytes EEPROM and 512 Bytes RAM.
Special attention is payed to the reduction of the electro-magnetic emission of T89C51CC02.

Block Diagram

RxD
TxD
TM
family of 8-bit microcon troll er s dedi ca ted to C AN ne twork appl ica-
TxDC
PCA
Vss
Vcc
ECI
T2EX
T2
RxDC
XTAL1 XTAL2
CPU
C51
CORE
T1
RAM
256x8
INT
Ctrl
INT0
UART
Timer 0 Timer 1
T0
RESET
INT1
IB-bus
Flash 16K x
8
loader 2K x 8
Port 1
Note: 1. 8 analog Inputs/8 Digital I/O.
2. 2-bit I/O Port.
Boot
EE PROM 2K x 8
Parallel I/O Ports
Port 3
Port 2
P2(2)
P1(1)
P3
XRAM
256 x 8
Port 4
P4(2)
Watch
Dog
PCA
Timer 2
CAN
CONTROLLER
10-bit
ADC
VAREF
VAGND
VAVCC
2
4126L–CAN–01/08

Pin Configurations

AT/T89C51CC02
VAREF
VAGND
VAVCC
P4.1/RxDC
P4.0/TxDC
P2.1
P3.7
P3.6 P3.5/T1 P3.4/T0
P3.3/INT1 P3.2/INT0
P3.1/TxD
P3.0/RxD
VAREF
VAGND
VAVCC
P4.1/RxDC P4.0/TxDC
P3.5/T1 P3.4/T0
P3.3/INT1
P3.2/INT0
P3.1/TxD
P3.0/RxD
XTAL2
1
2
3 4
5
6 7
SO28
8
9
10
11
12 13 14
1
2
3 4
5
6 7
SO24
8
9
10
11
12
28
P1.0/
27
P1.1/AN1/T2EX
26
P1.2/AN2/ECI
P1.3/AN3/CEX0
25
P1.4/AN4/CEX1
24
P1.5/AN5
23
P1.6/AN6
22
P1.7/AN7
21
P2.0
20
RESE
19 18
VSS VCC
17
XTAL1
16
XTAL2
15
24
P1.0/
23
P1.1/AN1/T2EX
22
P1.2/AN2/ECI
P1.3/AN3/CEX0
21
P1.4/AN4/CEX1
20
P1.5/AN5
19
P1.6/AN6
18
P1.7/AN7
17
RESE
16
VSS
15 14
VCC XTAL1
13
AN0/T2
T
AN0/T2
T
4126L–CAN–01/08
P4.0/TxDC
P2.1 P3.7
P3.6 P3.5/T1 P3.4/T0
P3.3/INT1
VAGND
VAVCC
P4.1/RxDC
432
5 6 7
PLCC-28
8 9 10 11
12131415161718
P3.1/TxD
P3.0/RxD
P3.2/INT0
VAREF
1
XTAL2
P1.1/AN1/T2EX
P1.0/AN 0/T2
282726
VCC
XTAL1
P1.2/AN2/ECI
25 24 23 22 21 20 19
VSS
P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P2.0 RESET
3
AT/T89C51CC02
P4.1/RxDC
NC
VAREF
VAGND
VAVCC
P1.0/AN 0/T2
P1.2/AN2/ECI
P1.1/AN1/T2EX
P4.0/TxDC
P2.1 P3.7
P3.6 P3.5/T1 P3.4/T0
NC
P3.3/INT1
1 2 3
4 5 6 7 8
32
9
P3.2/INT0
30
31
QFP-32
101112
NC
P3.1/TxD
P3.0/RxD
28
29
131415
XTAL2
27
25
26
24
P1.3/AN3/CEX0
23
P1.4/AN4/CEX1
22
P1.5/AN5
21
P1.6/AN6
20
P1.7/AN7
19
P2.0
18
NC
17
RESET
16
VSS
VCC
XTAL1
4
4126L–CAN–01/08

Pin Description

Pin Name Type Description
VSS GND Circuit ground
VCC Supply Voltage VAREF Reference Voltage for ADC (input) VAVCC Supply Voltage for ADC
VAGND Reference Ground for ADC (internaly connected with the VSS)
P1.0:7 I/O Port 1:
Is an 8-bit bi-directional I/O port w ith internal pull -ups. Port 1 pins can be used for digit al input/o utput or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of curren t (I because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register (in this case the internal pull-ups are disconnected). As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O.
P1.0/AN0/T2 Analog input channel 0, External clock input for Timer/counter2.
P1.1/AN1/T2EX Analog input channel 1, Trigger input for Timer/counter2.
P1.2/AN2/ECI Analog input channel 2, PCA external clock inpu t.
P1.3/AN3/CEX0 Analog input channel 3, PCA module 0 Entry of input/PWM output.
P1.4/AN4/CEX1 Analog input channel 4, PCA module 1 Entry of input/PWM output.
P1.5/AN5 Analog input channel 5, P1.6/AN6 Analog input channel 6, P1.7/AN7 Analog input channel 7,
It can drive CMOS inputs without external pull-ups.
AT/T89C51CC02
, See section ’Electrical C haracteristic’)
IL
P2.0:1 I/O Port 2:
4126L–CAN–01/08
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. In the T89C51CC02 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.
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AT/T89C51CC02
Pin Name Type Description
P3.0:7 I/O Port 3:
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pu lled low externally will be a source of current (I because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for TxD and WR P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface
P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface P3.2/INT0 P3.3/INT1 P3.4/T0: Timer 0 counter input P3.5/T1: Timer 1 counter input P3.6: Regular I/O port pin P3.7: Regular I/O port pin
P4.0:1 I/O Port 4:
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up transistor. The output latch corresponding to a secondary function RxDC must be programmed to one for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows: P4.0/TxDC: Transmitter output of CAN controller
P4.1/RxDC: Receiver input of CAN controller. It can drive CMOS inputs without external pull-ups.
IL
). The secondary functions are assigned to the pins of port 3 as follows:
: External interrupt 0 input/timer 0 gate control input : External interrupt 1 input/timer 1 gate control input
, See section ’Electrical Characteristic’)
RESET I/O Reset:
A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC.
XTAL1 I XTAL1:
Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock sourc e, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained.
XTAL2 O XTAL2:
Output from the inverting oscillator amplifier.
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4126L–CAN–01/08
AT/T89C51CC02

I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A

CPU ’write to latch’ signal initiates transfer of internal bus data into the type-D latch. A CPU ’read latch’ signal transf ers the latched Q out put onto the intern al bus. Similarl y, a ’read pin’ signal transfers the logical level of the Port pin. Some Port data instructions activate the ’read latch’ signal while others activate the ’read pin’ signal. Latch instruc­tions are referred to as Read-Modify-Write instructions. Each I/O line may be independently programmed as input or output.

Port Structure Figure 1 shows the structure of Ports, which have internal pull-ups. An external source

can pull the pin low. Each Port pin can be configured either for general-purpose I/O or for its alternate input output function.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg­ister (x = 1 to 4). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive.
To configure a pin for its al ter nat e fun ction, set the bit in the Px register . W hen the l atch is set, the ’alterna te outpu t funct ion’ sig nal c ontrols the out put lev el (See Figur e 1) . The operation of Ports is discussed further in ’Quasi-Bi-directional Port Operation’ paragraph.
Figure 1. Ports Structure
VCC
READ LATCH
ALTERNATE OUTPUT FUNCTION
INTERNAL PULL-UP (1)
P1.x P2.x
INTERNAL BUS
WRITE TO LATCH
READ PIN
D
LATCH
CL
Q
ALTERNATE INPUT FUNCTION
P3.x P4.x
Note: 1. The internal pull-up can be disabled on P1 when analog function is selected.
(1)
4126L–CAN–01/08
7
AT/T89C51CC02

Read-Modify-Write Instructions

Some instructions rea d the l atch data rath er th an the pin da ta. T he latch based inst ruc­tions read the data, m odify the data an d then r ewrit e the latc h. T hese are called ’Read­Modify-Write’ instructions. Below is a complete list of these special instructions (See Table 1). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin:
Table 1. Read/Modify/Write Instructions
Instruction Description Example
ANL Logical AND ANL P1, A ORL Logical OR ORL P2, A XRL Logical EX-OR XRL P3, A JBC Jump if bit = 1 and clear bit JBC P1.1, LABEL CPL Complement bit CPL P3.0
INC Increment INC P2
DEC Decrement DEC P2
DJNZ Decrement and jump if not zero DJNZ P3, LABEL
MOV Px.y, C Move carry bit to bit y of Port x MOV P1.5, C
CLR Px.y Clear bit y of Port x CLR P2.4
SET Px.y Set bit y of Port x SET P3.3

Quasi Bi-directional Port Operation

It is not obvious t hat t he l as t thr ee in str uc ti ons in thi s lis t a re Rea d -Modify-Write inst ru c­tions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These Read-Modify-Write instr uctions are directed to the latc h rather than the p in in or der to av oid poss ible mi sinterpret ation of voltage (and there fore, logic) levels at th e pin. For e xampl e, a P ort b it used to dri ve the base of an external bipolar transistor cannot rise above the transistor’s base-emitter junction voltage (a v al ue l owe r than VIL). With a logic one wr itt en t o th e bi t, a ttem pts by the CPU to read the P ort a t the p in are misi nterpret ed as logi c ze ro. A r ead of the l atch rather than the pins returns the correct logic one value.
Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as ’quasi-bidi­rectional’ Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Resets write logic one to all Port latch es. If log ical zer o is subs equently w ritten to a P ort latch , it can b e returned to input conditions by a logic one written to the latch.
Note: Port latch values change near the end of Read-Modify-Write insruction cycles. Output
buffers (and therefore the pin state) are updated early in the instruction after Read-Mod­ify-Write instruction cycle.
Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1) to aid this logic tran siti on S ee Fi gure 2. T his in cre ases s witc h s peed. Thi s ext ra p ull-u p sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist of three p-channel FET (pFE T) devi ces. A pFE T is on when th e gate sen ses logic zero and off when the gate senses log ic one. p FET # 1 is tur ned o n for two osc illator pe riods immediately after a zero- to-one transition in the Port latc h. A logic one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logic one. pFET #2 is a very weak pull-up switched on whenever the
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4126L–CAN–01/08
AT/T89C51CC02
associated nFET is switched off. This is tradition al CMOS switch conventio n. Current strengths are 1/10 that of pFET #3.
Note: During Reset, pFET#1 is not avtivated. During Reset, only the weak pFET#3 pull up the
pin.
Figure 2. Internal Pull-up Configurations
2 Osc. PERIODS
VCCVCCVCC
OUTPUT DATA
INPUT DATA READ PIN
p1(1)
n
p2
p3
P1.x P2.x P3.x P4.x
4126L–CAN–01/08
9
AT/T89C51CC02

SFR Mapping Tables 3 through Table 11 show the Special Function Registers (SFRs) of the

T89C51CC02.
Table 2. C51 Core SFRs
MnemonicAddName 76543210
ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P SP 81h Stack Pointer
Data Pointer Low
DPL 82h
DPH 83h
Table 3. I/O Port SFRs
MnemonicAddName 76543210
P1 90h Port 1
byte LSB of DPTR
Data Pointer High byte
MSB of DPTR
P2 A0h Port 2 (x2) P3 B0h Port 3 P4 C0h Port 4 (x2)
Table 4. Timers SFRs
MnemonicAddName 76543210
TH0 8Ch
TL0 8Ah
TH1 8Dh
TL1 8Bh
TH2 CDh
TL2 CCh
TCON 88h
Timer/Counter 0 High byte
Timer/Counter 0 Low byte
Timer/Counter 1 High byte
Timer/Counter 1 Low byte
Timer/Counter 2 High byte
Timer/Counter 2 Low byte
Timer/Counter 0 and 1 control
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h
Timer/Counter 0 and 1 Modes
10
GATE1 C/T1# M11 M 01 GATE0 C/T0# M10 M00
4126L–CAN–01/08
AT/T89C51CC02
Table 4. Timers SFRs (Continued)
MnemonicAddName 76543210
T2CON C8h
T2MOD C9h
RCAP2H CBh
RCAP2L CAh
WDTRST A6h
WDTPRG A7h
Timer/Counter 2 control
Timer/Counter 2 Mode
Timer/Counter 2 Reload/Capture High byte
Timer/Counter 2 Reload/Capture Low byte
WatchDog Timer Reset
WatchDog Timer Program
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2OE DCEN
S2 S1 S0
Table 5. Serial I/O Port SFRs
MnemonicAddName 76543210
SCON 98h Serial Cont rol FE/SM0 SM1 SM2 REN TB8 RB8 TI R I SBUF 99h Serial Data Buffer SADEN B 9h Slave Address Mask SADDR A9h Slave Address
Table 6. PCA SFRs
MnemonicAddName 76543210
CCON D8h
CMOD D9h
CL E9h
CH F9h
CCAPM0 CCAPM1
CCAP0H CCAP1H
DAh DBh
FAh
FBh
PCA Timer/Counter Control
PCA Timer/Counter Mode
PCA Timer/Counter Low byte
PCA Timer/Counter High byte
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Compare Capture Module 0 H
PCA Compare Capture Module 1 H
CF CR CCF4 CCF3 CCF2 CCF1 CCF0
CIDL CPS1 CPS0 ECF
CCAP0H7 CCAP1H7
ECOM0 ECOM1
CCAP0H6 CCAP1H6
CAPP0 CAPP1
CCAP0H5 CCAP1H5
CAPN0 CAPN1
CCAP0H4 CCAP1H4
MAT0 MAT1
CCAP0H3 CCAP1H3
TOG0 TOG1
CCAP0H2 CCAP1H2
PWM0 PWM1
CCAP0H1 CCAP1H1
CCAP0H0 CCAP1H0
ECCF0 ECCF1
4126L–CAN–01/08
11
AT/T89C51CC02
Table 6. PCA SFRs (Continued)
MnemonicAddName 76543210
CCAP0L CCAP1L
PCA Compare
EAh
Capture Module 0 L
EBh
PCA Compare Capture Module 1 L
CCAP0L7 CCAP1L7
CCAP0L6 CCAP1L6
CCAP0L5 CCAP1L5
CCAP0L4 CCAP1L4
CCAP0L3 CCAP1L3
CCAP0L2 CCAP1L2
CCAP0L1 CCAP1L1
CCAP0L0 CCAP1L0
Table 7. Interrupt SFRs
MnemonicAddName 76543210
IEN0 A8h
IEN1 E8h
IPL0 B8h
IPH0 B7h
IPL1 F8h
IPH1 F7h
Interrupt Enable Control 0
Interrupt Enable Control 1
Interrupt Priorit y Control Low 0
Interrupt Priorit y Control High 0
Interrupt Priorit y Control Low 1
Interrupt Priorit y Control High1
EA EC ET2 ES ET1 EX1 ET0 EX0
ETIM EADC ECAN
PPC PT2 PS PT1 PX1 PT0 PX0
PPCH PT2H PSH PT1H PX1H PT0H PX0H
POVRL PADCL PCANL
POVRH PADCH PCANH
Table 8. ADC SFRs
MnemonicAddName 76543210
ADCON F3h ADC Control PSIDLE ADEN ADEOC ADSST SCH2 S CH1 SCH0 ADCF F6h ADC Configuration CH7 CH6 CH5 C H4 CH3 CH2 CH 1 CH0 ADCLK F2h ADC Clock PRS4 PRS3 PRS2 PRS1 PRS0 ADDH F5h ADC Data High byte ADAT9 A DAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 ADDL F4h ADC Data Low byte ADAT1 ADAT0
Table 9. CAN SFRs
MnemonicAddName 76543210
CANGCON ABh
CANGSTA AAh
CANGIT 9Bh
CANBT1 B4h CAN bit Timing 1 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CANBT2 B5h CAN bit Timing 2 SJW1 SJW0 PRS2 PRS1 PRS0 CANBT3 B6h CAN bit Timing 3 PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP
CAN General Control
CAN General Status
CAN General Interrupt
ABRQ OVRQ TTC SYNCTTC AUT-BAUD TEST ENA GRES
OVFG TBSY RBSY ENFG BOFF ERRP
CANIT OVRTIM OVRBUF SERG CERG FERG AERG
12
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Table 9. CAN SFRs (Continued)
MnemonicAddName 76543210
CANEN CFh
CANGIE C1h
CANIE C3h
CANSIT BBh
CANTCON A1h CAN Timer Control TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0 CANTIMH ADh CAN Timer high CANTIM 15 CANTIM 14 CANTIM 13 CANTIM 12 CANTIM 11 CANTIM 10 CANTIM 9 CANTIM 8 CANTIML ACh CAN Timer low CANTIM 7 CANTIM 6 CANTIM 5 CANTIM 4 CANTIM 3 CANTIM 2 CANTIM 1 CANTIM 0
CANSTMPH AFh
CANSTMPL AEh
CANTTCH A5h
CANTTCL A4h CAN Timer TTC low
CANTEC 9Ch
CANREC 9Dh
CAN Enable Channel byte
CAN General Interrupt Enable
CAN Interrupt Enable Channel byte
CAN Status Interrupt Channel byte
CAN Timer Stamp high
CAN Timer Stamp low
CAN Timer TTC high
CAN Transmit Error Counter
CAN Receive Error Counter
ENCH3 ENCH2 ENCH1 ENCH0
ENRX ENTX ENERCH ENBUF ENERG
IECH3 IE CH2 IECH1 IECH0
SIT3 SIT2 SIT1 SIT0
TIMSTMP 15TIMSTMP 14TIMSTMP 13TIMSTMP
TIMSTMP7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0
TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10
TIMTTC
7
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
TIMTTC
6
TIMTTC
5
12
TIMTTC
4
TIMSTMP 11
TIMTTC
3
TIMSTMP
10
TIMTTC
2
TIMSTMP 9 TIMSTMP 8
TIMTTC
9
TIMTTC
1
TIMTTC
8
TIMTTC
0
CANPAGE B1h CAN Page - - CHNB1 CHNB0 AINC INDX2 INDX1 INDX0 CANSTCH B2h CAN Stat us Channel DLCW TXOK RXOK BERR SERR CERR FERR AERR
CANCONCH B3h
CANMSG A3h CAN Message Data MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0
CANIDT1 BCh
CANIDT2 BDh
CANIDT3 BE h
CANIDT4 BFh
CANIDM1 C4h
CAN Control Channel
CAN Identifier Tag byte 1(Part A) CAN Identifier Tag byte 1(PartB)
CAN Identifier Tag byte 2 (PartA) CAN Identifier Tag byte 2 (PartB)
CAN Identifier Tag byte 3(PartA)
CAN Identifier Tag byte 3(PartB)
CAN Identifier Tag byte 4(PartA)
CAN Identifier Tag byte 4(PartB)
CAN Identifier Mask byte 1(PartA)
CAN Identifier Mask byte 1(PartB)
CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0
IDT10 IDT28
IDT2
IDT20
-
IDT12
-
IDT4
IDMSK10
IDMSK28
IDT9
IDT27
IDT1
IDT19
-
IDT11
-
IDT3
IDMSK9
IDMSK27
IDT8
IDT26
IDT0
IDT18
-
IDT10
-
IDT2
IDMSK8
IDMSK26
IDT7
IDT25
-
IDT17
-
IDT9
-
IDT1
IDMSK7
IDMSK25
IDT6
IDT24
-
IDT16
-
IDT8
-
IDT0
IDMSK6
IDMSK24
IDT5
IDT23
-
IDT15
-
IDT7
RTRTAG
IDMSK5
IDMSK23
IDT4
IDT22
-
IDT14
-
IDT6
-
RB1TAG
IDMSK4
IDMSK22
IDT3
IDT21
-
IDT13
-
IDT5
RB0TAG
IDMSK3
IDMSK21
4126L–CAN–01/08
13
AT/T89C51CC02
Table 9. CAN SFRs (Continued)
MnemonicAddName 76543210
CANIDM2 C5h
CANIDM3 C6h
CANIDM4 C7h
CAN Identifier Mask byte 2(PartA) CAN Identifier Mask byte 2(PartB)
CAN Identifier Mask byte 3(PartA) CAN Identifier Mask byte 3(PartB)
CAN Identifier Mask byte 4(PartA) CAN Identifier Mask byte 4(PartB)
IDMSK2
IDMSK20
-
IDMSK12
-
IDMSK4
IDMSK1
IDMSK19
-
IDMSK11-IDMSK10
-
IDMSK3
IDMSK0
IDMSK18
-
IDMSK2
-
IDMSK17-IDMSK16-IDMSK15-IDMSK14-IDMSK13
-
IDMSK9
-
IDMSK1
-
IDMSK8
-
IDMSK0
-
IDMSK7
RTRMSK - IDEMSK
-
IDMSK6
-
IDMSK5
Table 10. Other SFRs
MnemonicAddName 76543210
PCON 87h Power Cont rol SMOD1 SMOD0 POF GF1 GF0 PD IDL AUXR1 A2h Auxiliary Register 1 ENBOOT GF3 0 DPS CKCON 8Fh Clock Control CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 EEE EEBUSY
14
4126L–CAN–01/08
Table 11. SFR Mapping
(1)
0/8
AT/T89C51CC02
1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
IPL1
xxxx x000
B
0000 0000
IEN1
xxxx x000
ACC
0000 0000
CCON
0000 0000
PSW
0000 0000
T2CON
0000 0000
P4
xxxx xx11
IPL0
x000 0000
P3
1111 1111
IEN0
0000 0000
P2
xxxx xx11
CH
0000 0000
CL
0000 0000
CMOD
0xxx x000
FCON
0000 0000
T2MOD
xxxx xx00
CANGIE
1100 0000
SADEN
0000 0000 CANPAGE
1100 0000
SADDR
0000 0000
CANTCON
0000 0000
CCAP0H
0000 0000
ADCLK
xxx0 0000
CCAP0L
0000 0000
CCAPM0
x000 0000
EECON
xxxx xx00
RCAP2L
0000 0000
CANSTCH
xxxx xxxx
CANGSTA 1010 0000
(2)
AUXR1 xxxx 00x0
CCAP1H
0000 0000
ADCON
x000 0000
CCAP1L
0000 0000
CCAPM1
x000 0000
RCAP2H
0000 0000
CANIE
1111 0000
CANSIT
xxxx 0000
CANCONCH
xxxx xxxx
CANGCON
0000 0000
CANMSG xxxx xxxx
ADDL
0000 0000
TL2
0000 0000
CANIDM1
xxxx xxxx CANIDT1
xxxx xxxx
CANBT1
xxxx xxxx
CANTIML
0000 0000 CANTTCL
0000 0000
ADDH
0000 0000
TH2
0000 0000
CANIDM2
xxxx xxxx CANIDT2
xxxx xxxx
CANBT2
xxxx xxxx
CANTIMH
0000 0000 CANTTCH
0000 0000
ADCF
0000 0000
CANIDM3
xxxx xxxx CANIDT3
xxxx xxxx
CANBT3
xxxx xxxx
CANSTMPL
xxxx xxxx WDTRST
1111 1111
IPH1
xxxx x000
CANEN
xxxx 0000 CANIDM4
xxxx xxxx CANIDT4
xxxx xxxx
IPH0
x000 0000
CANSTMPH
xxxx xxxx WDTPRG
xxxx x000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
98h
90h
88h
80h
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
(1)
0/8
SBUF
0000 0000
TMOD
0000 0000
SP
0000 0111
1/9 2/A 3/B 4/C 5/D 6/E 7/F
TL0
0000 0000
DPL
0000 0000
Reserved
Notes: 1. These registers are bit-addressable.
Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFRs are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.
2. AUXR1 bit ENBOOT is initialized with the content of the BLJB bit inverted.
4126L–CAN–01/08
CANGIT
0x00 0000
TL1
0000 0000
DPH
0000 0000
CANTEC
0000 0000
TH0
0000 0000
CANREC
0000 0000
TH1
0000 0000
CKCON
0000 0000
PCON
00x1 0000
9Fh
97h
8Fh
87h
15
AT/T89C51CC02

Clock The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature,

called “X2”, provides the following advantages:
Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.
Saves power consumption while keeping the same CPU power (oscillator power saving).
Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.
Increases CPU power by 2 while keeping the same crystal frequency.
In order to keep the ori ginal C51 com patibil ity, a divider -by-2 is in serted betwe en the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software.
An extra feature is available to start after Reset in the X2 Mode. This feature can be enabled by a bit X2B in the Hardware Sec urity Byte. Thi s bit is described in the section ’In-System Programming’.

Description The X2 bit in the CKCON regi ster (See T able 12) allows switching from 12 clock cycles

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode).
Setting this bit activates the X2 feature (X2 Mode) for the CPU Clock only (See Figure
3).
The Timers 0, 1 and 2, Uart, PCA, watchdog or CAN switch in X2 Mode only if the corre­sponding bit is cleared in the CKCON register.
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 Mode, as thi s divid er is bypas s ed, t he s ig nal s o n XTA L1 m us t hav e a cy clic ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2 bit is validat ed on th e XTAL1 ÷ 2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 4 shows the mode switching waveforms.
16
4126L–CAN–01/08
Figure 3. Clock CPU Generation Diagram
X
X
AT/T89C51CC02
X2B
Hardware Byte
On RESET
PCON.0
IDL
X2
CKCON.0
TAL1
÷ 2
0 1
CPU Core Clock
TAL2
CPU
CLOCK
PD
PCON.1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
1 0
÷ 2
1 0
1 0
1 0
1 0
1 0
CPU Core Clock Symbol
and ADC
1 0
FT0 Clock
FT1 Clock
FT2 Clock
FUart Clock
FPca Cloc k
FWd Clock
FCan Clock
4126L–CAN–01/08
X2
CKCON.0
CANX2
CKCON.7
WDX2
CKCON.6
PCAX2
CKCON.5
SIX2
CKCON.4
T2X2
CKCON.3
T1X2
CKCON.2
PERIPH
CLOCK
Peripheral Clock Symbol
T0X2
CKCON.1
17
AT/T89C51CC02
Figure 4. Mode Switching Waveforms
XTAL1
XTAL2
X2 bit
CPU clock
STD Mode
(1)
X2 Mode
STD Mode
Note: 1. In order to prevent any incorrect operation while operating in the X2 Mode, users must be aware that all peripherals using
the clock frequency a s a time ref erence (UAR T, timers...) will have their time referen ce div ided b y 2. Fo r example , a free ru n­ning timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.
18
4126L–CAN–01/08

Register Table 12. CKCON Register

CKCON (S:8Fh) Clock Control Register
76543210
CANX2 WDX2 PCAX2 SIX2 T 2X2 T1X2 T0X2 X2
AT/T89C51CC02
Bit
Number
7CANX2
6WDX2
5PCAX2
4SIX2
3T2X2
2T1X2
1T0X2
Bit
Mnemonic Description
CAN Clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Watchdog Clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Cloc k
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (MODE 0 and 2)
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Timer 2 Clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Timer 1 Clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Timer 0 Clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
(1)
(1)
(1)
(1)
(1)
(1)
(1)
4126L–CAN–01/08
CPU Clock
0X2
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the individual peripherals ’X2’ bits.
Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
has no effect.
Reset Value = 0000 0000b
19
AT/T89C51CC02

Power Management Two power reduction modes are implemented in the A/T89C51CC02: the Idle mode and

0
the Power-do wn mode . These modes ar e detai led in th e follo wing se ction s. In ad dition to these power redu cti on mo des , t he cl oc ks o f th e c ore and peripherals can be dy nam i­cally divided by 2 using the X2 Mode detailed in Section “Clock”.

Reset Pin In order to start- up (c old re se t) or to res tart (warm rese t) pro perly the m icroc ontroll er, a

high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of the internal registers like S F Rs, P C, etc . and to unp re dicta ble behavior of the microcon­troller. A warm reset ca n be applied either dir ectly o n the RST pin or indire ctly by an internal reset source such as a watchdog, PCA, timer, etc.

At Power-up (cold reset) Two conditions are required before enabling a CPU start-up:

VDD must reach the specified VDD range,
The level on xtal1 input must be outside the specification (VIH, VIL).
If one of these two conditions are not met, the microcontroller d oes not start cor rectly and can execute an instruct ion fetch fro m anywhe re in the progr am spac e. An active level applied on the RST pin must be mainta ined unti l both of th e above c onditi ons are met. A reset is active wh en the lev el VIH1 is reached an d when the pu lse wid th covers the period of time where VDD and the oscillator are not stabilized. Two parameters have to be taken into account to determine the reset pulse width:
VDD rise time (vddrst),
Oscillator startup time (oscrst).
To determine the capacitor the highest value of these two parameters has to be chosen. The reset circuitry is shown in Figure 5.
Figure 5. Reset Circuitry
VDD
Crst
RST pin
Rrst
Reset input circuitry
Internal reset
Table 13 and Table 14 give some typical examples for three values of VDD rise times, two values of oscillator start-up time and two pull-down resistor values.
Table 13. Minimum Reset Capacitor for a 50K Pull-down Resistor
oscrst/vddrst 1ms 10ms 100ms
5ms 820nF 1.2µF 12µF
20
20ms 2.7µF 3.9µF 12µF
4126L–CAN–01/08
AT/T89C51CC02
Table 14. Minimum Reset Capacitor for a 15k Pull-down Resistor
oscrst/vddrst 1ms 10ms 100ms
5ms 2.7µF 4.7µF 47µF
20ms 10µF 15µF 47µF
Note: These values assume VDD starts from 0v to the nominal value. If the time between two
on/off sequences is too fast, the power-supply decoupling capacitors may not be fully discharged, leading to a bad reset sequence.

During a Normal Operation (Warm Reset)

Reset pin must be maintained for at l ea st 2 m achi ne cy cl es (24 os c illat or c lock pe r iod s) to apply a reset s equence duri ng normal o peration. The number of cl ock periods is mode independent (X2 or X1).

Watchdog Reset A 1K resistor must be added in series with the capacitor to allow the use of watchdog

reset pulse output on the RST pin or when an external power-supply supervisor is used. Figure 6 shows the reset circuitry when a capacitor is used.
Figure 6. Reset Circuitry for a Watchdog Configuration
VDD
Crst
1k RST pin
Rrst
Reset input circuitry
To other on-board circuitry
Figure 7 shows the reset circuitry when an external reset circuit is used.
watchdog
Internal reset
4126L–CAN–01/08
Figure 7. Reset Circuitry Example Using an External Reset Circuit
VDD
External reset circuit
RST
1k RST pin
Rrst
Reset input circuitry
To other on-board circuitry
watchdog
Internal reset
21
AT/T89C51CC02

Reset Recommendation to Prevent Flash Corruption

When a Flash program memory is embedded on-chip, it is strongly recommended to use an external reset chip (brown out device) to apply a reset (Figure 7). It prevents sys­tem malfunction during periods of insufficient power-supply voltage (power-supply failure, power supply switched off, etc.).

Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode,

program execution halts. Idle mode freezes the cl ock to the CPU at known sta tes while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 15.
Entering Idle Mode To enter Idle mode, set the IDL bi t in PCON register (See Table 16). The
A/T89C51CC02 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed.
Note: If IDL bit and PD bit are set simultaneously, the A/T89C51CC02 enters Power-down
mode. Then it does not go in Idle mode when exiting Power-down mode.
Exiting Idle Mode There are two ways to exit Idle mode:
1. Generate an enabled interrupt. Hardware clears IDL bit in PCON register which restores the clock to the CPU. Exe-
cution resumes with the interrupt service routine. Upon completion of the interrupt service routine, pr o gr am exec uti on r e su mes with the instruction im med iat ely follow­ing the instruction that activated Idle mode. The general purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred dur­ing normal operati on o r dur i ng I dle mo de. Wh en Idle mode is exite d b y a n i nte rrup t, the interrupt service routine may examine GF1 and GF0.
2. Generate a reset. A logic high on the RST pin clears IDL bit in PCON register directly and asynchro-
nously. This restores the c lock to the CPU. Program execu tion momentarily resumes with the inst ructio n immedia tely follow ing the in structi on that activ ated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the A/T89C51CC02 and vectors the CPU to address C:0000h.

Power-down Mode The Power-down mode places the A/T89C51 CC02 in a v ery low po wer state. Powe r-

Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The A/T89C51CC02 enters
22
Notes: 1. Dur i ng the t im e th at ex e cuti o n re su me s, th e i nte r na l R AM ca n no t be ac ce ss ed ; ho w -
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM.
2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle.
down mode stops t he osci ll ator , freez es a ll c lock at k nown s tate s. The CPU st atus p rior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM content s a re pres erv ed. T h e s tatu s of the Po rt pins dur in g P ower -do w n mode is detailed in Table 15.
the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed.
4126L–CAN–01/08
AT/T89C51CC02
Exiting Power-down Mode Note: If V
was reduced during the Power-down mode, do not exit Power-down mode until
DD
V
is restored to the normal operating level.
DD
There are two ways to exit the Power-down mode:
1. Generate an enabled external interrupt. – The A/T89C51CC02 provides capability to exit from Power-down using
INT0#, INT1#. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTx# input, execution resumes when the input is released (See Figure 8). Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-down mode.
Notes: 1. The external interrupt used to exit Power-down mode must be configured as level
sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted.
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.
Figure 8. Power-down Exit Waveform Using INT1:0#
INT1:0#
OSC
Power-down phase Oscillator restart phase Active phaseActive phase
2. Generate a reset. – A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the A/T89C51CC02 and vectors the CPU to address 0000h.
Notes: 1. Dur i ng the t im e th at ex e cuti o n re su me s, th e i nte r na l R AM ca n no t be ac ce ss ed ; ho w -
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated the Power-down mode should not write to a Port pin or to the external RAM.
2. Exit from power-down by res et r edefines all the SFRs, b ut do es not af fect the internal RAM content.
4126L–CAN–01/08
23
AT/T89C51CC02
Table 15. Pin Conditions in Special Operating Modes
Mode Port 1 Port 2 Port 3 Port 4
Reset High High High High
Idle
(internal
code)
Idle
(external
code)
Power-
Down(inter
nal code)
Power-
Down
(external
code)
Data Data Data Data
Data Data Data Data
Data Data Data Data
Data Data Data Data
24
4126L–CAN–01/08

Registers Table 16. PCON Register

PCON (S:87h) Power Control Register
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
AT/T89C51CC02
Bit
Number
7SMOD1
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
Bit
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Clear to recognize next reset type. Set by hardware when V software.
General purpose Flag
Cleared by user for general purpose usage. Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage. Set by user for general purpose usage.
Power-down Mode bit
Cleared by hardware when reset occurs. Set to enter power-down mode.
Idle Mode bit
Clear by hardware when interrupt or reset occurs. Set to enter idle mode.
rises from 0 to its nominal voltage. Can also be set by
CC
4126L–CAN–01/08
Reset Value = 00X1 0000b Not bit addressable
25
AT/T89C51CC02

Data Memory The T89C51CC02 provides data memory access in two different spaces:

The internal space mapped in three separate segments:
The lower 128 Bytes RAM segment.
The upper 128 Bytes RAM segment.
The expanded 256 Bytes RAM segment (XRAM). A fourth internal segment is available but dedicated to Special Function Registers,
SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 9 shows the internal data memory spaces organization.
Figure 9. Internal memory - RAM
FFh
00h
256 Bytes
Internal XRAM
FFh
80h 80h
7Fh
00h
Upper
128 Bytes
Internal RAM
Indirect Addressing
Lower
128 Bytes
Internal RAM
Direct or Indirect
Addressing
FFh
Direct Addressing
Special
Function
Registers

Internal Space

Lower 128 Bytes RAM The lower 128 Bytes of RAM (See Figure 10) are accessible from address 00h to 7Fh
using direct or indirect address ing modes. T he lowest 32 Bytes are grouped in to 4 banks of 8 registers (R0 to R7 ). Two bits RS0 and RS 1 in PSW re giste r (See Tabl e 18) select which bank is in use according to Table 17. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct address­ing, and can be used for context switching in interrupt service routines.
Table 17. Register Bank Selection
RS1 RS0 Description
0 0 Register bank 0 from 00h to 07h
26
0 1 Register bank 0 from 08h to 0Fh 1 0 Register bank 0 from 10h to 17h 1 1 Register bank 0 from 18h to 1Fh
The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 ins truction set i ncludes a wide s election o f singlebit instruct ions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh.
4126L–CAN–01/08
Figure 10. Lower 128 Bytes Internal RAM Organization
7Fh
AT/T89C51CC02
30h
20h 18h 10h 08h 00h
2Fh
bit-Addressable Space
(bit Addresses 0-7Fh) 1Fh 17h
4 Banks of
8 Registers
0Fh
R0-R7 07h
Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
addressing mode.
Expanded RAM The on-chip 256 Bytes of expanded RAM (XRAM) are accessible from address 0000h to
00FFh using i ndirect ad dressing mode thro ugh MOVX in structio ns. In this a ddress range.
Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile
memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.
4126L–CAN–01/08
27
AT/T89C51CC02

Dual Data Pointer

Description The T89C51CC02 imp lements a second data pointer for speeding up code exe cution
and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are Seen by the CPU as DPT R and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (See Figure 19) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (See Figure 11).
Figure 11. Dual Data Pointer Implementation
DPL0 DPL1
DPTR0
DPTR1
DPH0 DPH1
0 1
DPS
0 1
DPL
AUXR1.0
DPH
DPTR
Application Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare…) are well served by using one data pointer as a “source” pointer and the other one as a “destination” pointer. Hereafter is an example of block move implementation using the two pointers and coded in assembler. The latest C compiler takes als o advantag e of this feature b y providin g enhanced algorithm libraries. The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the DPS bit in the AUXR 1 reg ister. H owever , note that th e INC i nstruc tion do es no t direc tly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move exa mple, o nly the f act that DP S is tog gled i n the pr oper s equenc e mat­ters, not its actual value. In other words, the block move routine works the same whether DPS is 0 or 1 on entry.
; ASCII block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; Ends when encountering NULL character ; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is added
28
AUXR1EQU0A2h
move:movDPTR,#SOURCE ; address of SOURCE
incAUXR1 ; switch data pointers movDPTR,#DEST ; address of DEST
mv_loop:incAUXR1; switch data pointers
movxA,@DPTR; get a byte from SOURCE incDPTR; increment SOURCE address incAUXR1; switch data pointers movx@DPTR,A; write the byte to DEST incDPTR; increment DEST address jnzmv_loop; check for NULL terminator
end_move:
4126L–CAN–01/08

Registers Table 18. PSW Register

PSW (S:D0h) Program Status Word Register
76543210
CY AC F0 RS1 RS0 OV F1 P
AT/T89C51CC02
Bit
Number
7CY
6AC
5F0User Definable Flag 0
4 - 3 RS1:0
2OV
1F1User Definable Flag 1
0P
Bit
Mnemonic Description
Carry Flag
Carry out from bit 1 of ALU operands.
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
Register Bank Select bits
Refer to Table 17 for bits description.
Overflow Flag
Overflow set by arithmetic operations.
Parity bit
Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.
Reset Value = 0000 0000b
4126L–CAN–01/08
29
AT/T89C51CC02
Table 19. AUXR1 Register
AUXR1 (S:A2h) Auxiliary Control Register 1
76543210
- - ENBOOT - GF3 0 - DPS
Bit
Number
7 - 6 -
5 ENBOOT
4-
3GF3General Purpose Flag 3
20
1-Reserved for Data Pointer Extension
0DPS
Bit
Mnemonic Description
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Enable Boot Flash
(1)
Set this bit to map the boot Flash between F800h -FFFFh Clear this bit to disable boot Flash.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag.
Data Pointe r Select bit
Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.
Reset Value = XXXX 00X0b
Note: 1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming
section.
30
4126L–CAN–01/08
AT/T89C51CC02

EEPROM Data Memory

Write Dat a i n the Column Latches

The 2K bytes on-chi p EEPRO M memo ry bloc k is l ocated at addres ses 0000h to 07FF h of the XRAM/XRAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction.
A physical write i n the E EPRO M memo ry is d one in two step s: write data in the co lumn latches and transfer of all data latches into an EEPROM memory row (programming).
The number of data written on the page may vary from 1 up to 128 Bytes (the page size). When programm ing, onl y the dat a writte n in the col umn latc h is pro grammed an d a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth bit is set when the writing th e corresponding b yte in a row and all these n inth bits are reset after the writing of the complete EEPROM row.
Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of t he d ata poi nter, the 4 MSBs are used fo r pag e s ele ct ion ( row ) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column lat ches mus t stay on the sa me p age, mea ning tha t the 4 MSB must no be changed.
The following procedure is used to write to the column latches:
Save and disable int er ru pt
Set bit EEE of EECON register
Load DPTR with the address to write
Store A register with the data to be written
Execute a MOVX @DPTR, A
If needed loop the three last instructions until the end of a 128 Bytes page
Restore interrupt
Note: The last page address used when loading the column latch is the one used to select the
page programming address.

Programming The EEPROM programming consists of the following actions:

Write one or more Bytes of one page in the column latches. Normally, all Bytes must belong to the same page; if not, the last page address will be latched and the others discarded.
Launch programming by writing the control sequence (50h followed by A0h) to the EECON register.
EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading.
The end of programming is indicated by a hardware clear of the EEBUSY flag.
Note: The sequence 5xh and Axh must be executed without instructions between then other-
wise the programming is aborted.

Read Data The following procedure is used to read the data stored in the EEPROM memory:

Save and disable int er ru pt
Set bit EEE of EECON register
Load DPTR with the address to read
Execute a MOVX A, @DPTR
Restore interrupt
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AT/T89C51CC02

Examples ;*F*************************************************************************

;* NAME: api_rd_eeprom_byte
;* DPTR contain address to read.
;* Acc contain the reading value
;* NOTE: before execute this function, be sure the EEPROM is not BUSY
;***************************************************************************
api_rd_eeprom_byte:
; Save and clear EA
MOV EECON, #02h; map EEPROM in XRAM space
MOVX A, @DPTR
MOV EECON, #00h; unmap EEPROM
; Restore EA
ret
;*F*************************************************************************
;* NAME: api_ld_eeprom_cl
;* DPTR contain address to load
;* Acc contain value to load
;* NOTE: in this example we load only 1 byte, but it is possible upto
;* 128 Bytes.
;* before execute this function, be sure the EEPROM is not BUSY
;***************************************************************************
api_ld_eeprom_cl:
; Save and clear EA
MOV EECON, #02h ; map EEPROM in XRAM space
MOVX @DPTR, A
MOVEECON, #00h; unmap EEPROM
; Restore EA
ret
32
;*F*************************************************************************
;* NAME: api_wr_eeprom
;* NOTE: before execute this function, be sure the EEPROM is not BUSY
;***************************************************************************
api_wr_eeprom:
; Save and clear EA
MOV EECON, #050h
MOV EECON, #0A0h
; Restore EA
ret
4126L–CAN–01/08

Registers Table 20. EECON Register

EECON (S:0D2h) EEPROM Control Register
76543210
EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY
Bit
Bit Number
Mnemonic Description
AT/T89C51CC02
7 - 4 EEPL3-0
3-
2-
1EEE
0EEBUSY
Programming Launch Command bits
Write 5Xh followed by AXh to EEPL to launch the programming.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable EEPROM Space bit
Set to map the EEPROM space during MOVX instructions (Write in the column latches) Clear to map the XRAM space during MOVX.
Programming Busy Flag
Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.
Reset Value = XXXX XX00b Not bit addressable
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AT/T89C51CC02

Program/Code Memory

The T89C51CC02 implement 16K Bytes of on-chip program/code memory. The Flash memory increa ses EP ROM and ROM func tional ity by in-cir cui t electric al era-
sure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash ce lls is gene rated on-chip usi ng the standard V
DD
volt­age. Thus, the Flash memory can be programmed using only one voltage and allows In­System Progr ammi ng (IS P). Har dwar e prog rammin g mode is also availab le usi ng spe­cific programming tool.
Figure 12. Program/Code Memory Organization
3FFFh
16K Bytes
Internal Flash
0000h

Flash Memory Architecture

T89C51CC02 features two on-chip Flash memories:
•Flash memory FM0:
•Flash memory FM1:
The FM0 can be program by both parallel programming and Serial ISP whereas FM1 supports only parallel programming by pr ogrammers. The ISP mod e is detailed in the ’In-System Programming’ section.
All Read/Write access operations on Flash memory by user application are managed by a set of API described in the ’In-System Programming’ section.
Figure 13. Flash Memory Architecture
Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes)
3FFFh
containing 16K Bytes of program memory (user space) organized into 128 bytes pages,
2K Bytes for boot loader and Application Programming Interfaces (API).
FFFFh
F800h
16K Bytes
Flash Memory
User Space
FM0
2K Bytes
Flash Memory
Boot Space
FM1
FM1 mapped between F800h and FFFFh when bit ENBOOT is set in AUXR1 register
34
0000h
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FM0 Memory Architecture The Flash memory is made up of 4 blocks (See Figure 13):
1. The memory array (user space) 16K Bytes
2. The Extra Row
3. The Hardware security bits
4. The column latch registers
User Space This space is composed of a 16K Bytes Flash memory organized in 128 pages of 128
Bytes. It contains the user’s application code.
Extra Row (XRow) This row is a pa rt of FM0 and has a size of 12 8 B yt es. T he ex tra r ow may con t ain i nfo r-
mation for boot loader usage.
Hardware Security Byte The Hardware security Byte space is a part of FM0 and has a size of 1 byte.
The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode.
Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes).
The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte).
Cross Flash Memory Access Description
The FM0 memory can be programmed as describe on Table 21. Programming FM0 from FM0 is impossible.
The FM1 memory can be program only by parallel programming. Table 21 show all software Flash access allowed.
Table 21. Cross Flash Memory Access
Code executing from
FM0
(user Flash)
FM1
(boot Flash)
Action
Read ok -
Load column latch ok -
Write - -
Read ok ok
Load column latch ok -
Write ok -
FM0
(user Flash)
FM1
(boot Flash)
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AT/T89C51CC02

Overview of FM0 Operations

The CPU interfaces the Flash memory through the FCON register and AUXR1 register. These registers are used to:
Map the memory spaces in the adressable space
Launch the programming of the memory spaces
Get the status of the Flash memory (busy/not busy)
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EEE bit in EECON register.
The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor­dance with Table 22. A MOVC instruction is then used for reading these spaces.
Table 22. FM0 blocks Select bits
FMOD1 FMOD0 FM0 Adressable Space
0 0 User (0000h-3FFFh) 0 1 Extra Row(FF80h-FFFFh) 1 0 Hardware Security Byte (0000h) 11Reserved
Launching Programming FPL3:0 bits i n FCON regist er are us ed to s ecure th e launc h of pr ogrammi ng. A s pecific
sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5xh followed by Axh. Table 23 summarizes the memory spaces to program according to FMOD1:0 bits.
Table 23. Programming Spaces
Write to FCON
OperationFPL3:0 FPS FMOD1 FMOD0
5 x 0 0 No action
User
Extra Row
Hardware
Security
Byte
Reserved
Note: The sequence 5xh and Axh must be executing without instructions between them other-
wise the programming is aborted. Interrupts that may occur during programming time must be disabled to avoid any spuri­ous exit of the programming mode.
Ax00
5 x 0 1 No action
Ax01
5 x 1 0 No action
A x 1 0 Write the fuse bits space
5 x 1 1 No action
A x 1 1 No action
Write the column latches in user space
Write the column latches in extra row space
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Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Loading the Column Latches Any num ber of data fr om 1 byte to 128 Bytes can be lo ade d i n the column latches. T his
provides the capability to program the whole memory by byte, by page or by any number of Bytes in a page.
When progra mmin g is laun ched, a n aut omati c erase of the loc atio ns load ed in th e col ­umn latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page.
The following procedure is used to load the column latches and is summarized in Figure 14:
Save then disable interrupt and map the column latch space by setting FPS bit.
Load the DPTR with the address to load.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
If needed loop the three last instructions until the page is completely loaded.
unmap the column latch and Restore Interrupt
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AT/T89C51CC02
Figure 14. Column Latches Loading Procedure
Column Latches
Loading
Save & Disable IT
EA = 0
Column Latches Mapping
FCON = 08h (FPS = 1)
Data Load
DPTR = Address
ACC = Data
Exec: MOVX @DPTR, A
Last Byte
to load?
Data Memory Mapping
FCON = 00h (FPS = 0)
(1)
Restore IT
Note: 1. The last page address used when loading the column latch is the one used to select
the page programming address.
Programming the Flash Spaces
User The following procedure is used to program the User space and is summarized in
Figure 15:
Load up to one page of data in the column latches from address 0000h to 3FFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 50h followed by A0h in
FCON register.This step must be executed from FM1. The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
Extra Row The following procedure is used to pr ogra m the Extra Row space a nd is summ arized i n
Figure 15:
Load data in the column latches from address FF80h to FFFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 52h followed by A2h in
FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
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Figure 15. Flash and Extra row Programming Procedure
Flash Spaces Programming
Column Latches Load i n g
See Figure 14
Save & Disable IT
EA = 0
Launch Programming
FCON = 5xh FCON = Axh
FBusy
Cleared?
AT/T89C51CC02
Hardware Security Byte
Clear Mode
FCON = 00h
End Programming
Restore IT
The following procedure is used to program the Hardware Security Byte space and is summarized in Figure 16:
Set FPS and map Hardware byte (FCON = 0x0C)
Save then disable the interrupts.
Load DPTR at address 0000h.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
Launch the programming by writing the data sequence 54h followed by A4h in
FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBusy flag cleared.
Restore the interrupts
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AT/T89C51CC02
Figure 16. Hardware Programming Procedure
Flash Spaces
Programming
Save & Disable IT
EA = 0
FCON = 0Ch
Save & Disable IT
EA = 0
Launch Programming
FCON = 54h
FCON = A4h
Data Load
DPTR = 00h ACC = Data
Exec: MOVX @DPTR, A
End Loading
Restore IT
FBusy
Cleared?
Clear Mode
FCON = 00h
End Programming
RestoreIT
Reading the Flash Spaces
User The following procedure is used to read the User space:
Read one byte in Accumulator by executing MOVC A,@A+DPTR with A+DPTR is
the address of the code byte to read.
Note: FCON must be cleared (00h) when not used.
Extra Row The following procedure is used to read the Extra Row space and is summarized in
Figure 17:
Map the Extra Row space by writing 02h in FCON register.
Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &
DPTR= FF80h to FFFFh.
Clear FCON to unmap the Extra Row.
Hardware Security Byte
40
The following procedure is used to read the Hardware Security Byte and is sum­marized in Figure 17:
Map the Hardware Security space by writing 04h in FCON register.
Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &
DPTR= 0000h.
Clear FCON to unmap the Hardware Security Byte.
4126L–CAN–01/08
Figure 17. Reading Procedure
Flash Spaces Reading
Flash Spaces Mapping
FCON = 00000aa0b
Data Read
DPTR = Address
Exec: MOVC A, @A+DPTR
Note: aa = 10 for the Hardware Security Byte.
ACC= 0
Clear Mode
FCON = 00h
AT/T89C51CC02
Flash Protection from Parallel Programming
The three lock bits in Hardware Security Byte ( See ’In-System Prog ramming’ section) are programmed according to Table 24 provide different level of protection for the on­chip code and data located in FM0 and FM1.
The only way to write this bits are the parallel mode. They are set by default to level 3.
Table 24. Program Lock bit
Program Lock bits
Security
Level
1 U U U No program lock features enabled. 2 P U U Parallel programming of the Flash is disabled.
3UPU
4UUPSame as 3
LB0 LB1 LB2
Protection Description
Same as 2, also verify through parallel programming interface is disabled. This is the factory defaul programming.
Note: 1. Program Lock bits
U: unprogrammed P: programmed
WARNING: Security level 2, 3 and 4 should only be programmed after Flash and Core verification.
Preventing Flash Corruption See Section “Power Management”.
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AT/T89C51CC02

Registers Table 25. FCON Register

FCON Register FCON (S:D1h) Flash Control Register
76543210
FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY
Bit
Number
7 - 4 FPL3:0
3FPS
2 - 1 FMOD1:0
0FBUSY
Bit
Mnemonic Description
Programming Launch Command bits
Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (See Table 23.)
Flash Map Program Space
Set to map the column latch space in the data memory space. Clear to re-map the data memory space.
Flash Mode
See Table 22 or Table 23.
Flash Busy
Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.
Reset Value = 0000 0000b
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AT/T89C51CC02

Operation Cross Memory Access

Table 26. Cross Memory Access
Action RAM ERAM Boot FLASH FM0 E² Data
Space addressable in read and write are:
•RAM
ERAM (Expanded RAM access by movx)
EEPROM DATA
FM0 ( user flash )
Hardware byte
•XROW
•Boot Flash
Flash Column latch The table below prov ides the differen t kin d of m emory wh ich can be acce ssed f rom d if-
ferent code location.
Hardware
Byte XROW
boot FLASH
Read OK OK OK OK ­Write - OK Read OK OK OK -OK -
FM0
Write - OK (idle) OK
Note: 1. RWW: Read While Write
(1)
OK
(1)
(1)
(1)
OK
--OK
OK
(1)
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Sharing Instructions Table 27. Ins tr uctions shared

AT/T89C51CC02
Action RAM ERAM
Read MOV MOVX MOVX MOVC MOVC MOVC M OVC Write MOV MOVX MOVX - by cl by cl by cl
EEPROM
DATA
Boot
FLASH FM0
Hardware
Byte XROW
Note: by cl : using Column Latch
Table 28. Read MOVX A, @DPTR
EEE bit in
EECON
Register
00XOK 01XOK 10X OK 11XOK
FPS in
FCON Register ENBOOT ERAM
EEPROM
DATA
Flash
Column
Latch
Table 29. Write MOVX @DPTR,A
EEE bit in
EECON
Register
FPS bit in
FCON Register ENBOOT ERAM
EEPROM
Data
Flash
Column
Latch
00XOK 01X OK 10X OK 11X OK
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AT/T89C51CC02
Table 30. Read MOVC A, @DPTR
Code Execution
From FM0
From FM1
(ENBOOT =1
FCON Register
ENBOOT DPTR FM1 FM0 XROW
0 0000h to 3FFFh OK
00X
01X X
10X X X OK
11X
0
00
1
01X
1
0 000h to 3FFFh OK
1
1
0X NA 1X OK 0X NA 1 0NA
0000h to 3FFFh OK
F800h to FFFFh Do not use this configuration
0000 to 007Fh
(1)
See
0000h to 3FFFh OK
F800h to FFFFh Do not use this configuration
0000h to 3FFF OK
F800h to FFFFh OK
0000h to 007h
(2)
See
OK
OK
Hardware
ByteFMOD1 FMOD0 FPS
10X
11X
1 0NA 1 0NA
X
OK
000h to 3FFFh
OK
1. For DPTR higher than 007Fh o nly lo west 7 b its are dec oded, t hus th e behav ior is the sa me as for addre sses from 0000h to 007Fh
2. For DPTR higher than 007Fh o nly lo west 7 b its are dec oded, t hus th e behav ior is the sa me as for addre sses from 0000h to 007Fh
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AT/T89C51CC02
h

In-System Programming (ISP)

Flash Programming and Erasure

With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the T89C51CC02 allows the system engineer the development of applica­tions with a very high l evel of flex ibility . Th is fle xibili ty is based on the p ossibi lity t o alter the customer program at any stages of a product’s life:
Before mounting the chip on the PCB, FM0 flash can be programmed with the application code. FM1 is always preprogrammed by Atmel with a bootloader (chip can be ordered with CAN bootloader or UART bootloader).
Once the chip is mounted on the PCB, it can be programmed by serial mode via the CAN bus or UART.
Note: 1. The user can also program his own bootloader in FM1.
This ISP allows code modification over the total lifetime of the product. Besides the default Bootloa ders Atmel prov ide customers all the needed Applic ation-
Programming-Interfaces (API) which are nee ded for the ISP . The AP I a re loc at ed i n th e Boot memory.
This allow the customer to have a full use of the 16-Kbyte user memory.
There are three methods for programming the Flash memory:
The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1)will be used to program FM0. The interface used for serial downloading to FM0 is the UART or the CAN. API can be called also by user’s bootloader located in FM0 at [SBV]00h.
A further method exist in activating the Atmel boot loader by hardware activation. See the Section “Hardware Security Byte”.
The FM0 can be programmed also by the parallel mode using a programmer.
(1)
Figure 18. Flash Memory Mapping
3FFFh
Custom Bootloader
[SBV]00h
16K Bytes
Flash Memory
FM0
0000h
F800h
FFFFh
2K Bytes IAP
Bootloader
FM1
FM1 Mapped between F800h and FFFF when API Called
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AT/T89C51CC02

Boot Process

Software Boot Proc ess Example
Figure 19. Hardware Boot Process Algorithm
Hardware
Many algorithms can be used for the software boot process. Below are descriptions of the different flags and Bytes.
Boot Loader Jump bit (BLJB):
- This bit indicate s if on RESET the us er wants to jum p to this applic ation at addr ess
@0000h on FM0 or execute the boot loader at address @F800h on FM1.
- BLJB = 0 (i.e. boo tloader FM 1 execut ed after a res et) is t he d efault Atm el fac tory pr o-
gramming.
-To read or modify this bit, the APIs are used.
Boot Vector Address (SBV):
- This byte contains the MSB of the user boot loader address in FM0.
- The default value of SBV is FCh (no user boot loader in FM0).
- To read or modify this byte, the APIs are used.
Extra Byte (EB) & Boot Status Byte (BSB):
- These Bytes are reserved for customer use.
- To read or modify these Bytes, the APIs are used.
ENBOOT = 0 PC = 0000h
RESET
BLJB == 0
?
bit ENBOOT in AUXR1 Register Is Initialized with BLJB Inverted.
Example, if BLJB=0, ENBOOT
is set (=1) during reset, thus the bootloader is executed after the
reset.
Application
Software
in FM0
Application­Programming-Interface
48
ENBOOT = 1 PC = F800h
Bootloader in FM1
Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions.
All these APIs are described in detail in the following documents on the Atmel web site.
Datasheet Bootloader CAN T89C51CC02. – Datasheet Bootloader UART T89C51CC02.
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AT/T89C51CC02

XROW Bytes The EXTRA ROW (XROW) incl udes 128 bytes. Some of these bytes are us ed for spe-

cific purpose in conjonction with the bootloader.
Table 31. XROW Mapping
Description Default Value Address
Copy of the Manufacturer Code 58h 30h Copy of the Device ID#1: Family code D7h 31h Copy of the Device ID#2: Memories size and type BBh 60h Copy of the Device ID#3: Name and Revision FFh 61h

Hardware Conditions It is possible to force the controller to ex ecute the bootl oader after a Res et with hard-

ware conditions. During the first programming, the user can define a configuration on Port1 that will be
recognized by the chip as the hardware conditions during a Reset. If this condition is met, the chip will start executing the bootloader at the end of the Reset.
See a detailed description in the applicable Document.
Datasheet Bootloader CAN T89C51CC02. – Datasheet Bootloader UART T89C51CC02.
4126L–CAN–01/08
49
AT/T89C51CC02

Hardware Security Byte Table 32. Hardware Security byte

76543210
X2B BLJB - - - LB2 LB1 LB0
Bit
Number
7X2B
6BLJB
5 - 3 -
2 - 0 L B 2:0 Lock bits (see Table 22)
Bit
Mnemonic Description
X2 bit
Set this bit to start in standard mode Clear this bit to start in X2 Mode.
Boot Loader Jump bit
- 1: To start the user ’s application on next RESET (@0000h) located in FM0,
- 0: To start the boot loader(@F800h) located in FM1.
Reserved
The value read from these bits are indeterminate.
After erasing the chip in parallel mode, the default value is : FFh The erasing in ISP mode (from bootloader) does not modify this byte.
Notes: 1. O nly the 4 MSB bi ts can be access ed by software .
2. The 4 LSB bits can only be accessed by parallel mode.
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Serial I/O Port The T89C51CC02 I/O serial port is compatible with the I/O serial port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-dup lex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates
Serial I/O port includes the following enhancements:

Framing error detection

Automatic address recognition
Figure 20. Serial I/O Port Block Diagram
IB Bus
TXD
RXD
SBUF
Transmitter
Write SBUF
Mode 0 Transmit
RI
TI
SBUF
Receiver
Receive
Shift register
Read SBUF
Load SBUF
Serial Port Interrupt Request
Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register. Figure 21. Framing Error Block Diagram
SM0/FE
Set FE bit if Stop bit is 0 (Framing Error)
RITIRB8TB8RENSM2SM1
4126L–CAN–01/08
SM0 to UART Mode Control
SMOD1
To UART Framing Error Control
IDLPDGF0GF1POF-SMOD0
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register bit is set.
The software may examine the FE bit after ea ch reception to ch eck for data errors. Once set, only softwa r e o r a r es et clea rs t he FE b it. Subsequently received fr am es wi th valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 22 and Figure 23).
51
AT/T89C51CC02
Figure 22. UART Timing in Mode 1

Automatic Address Recognition

RXD
RI
SMOD0 = x
FE
SMOD0 = 1
Start
bit
Data Byte
D7D6D5D4D3D2D1D0
Stop
bit
Figure 23. UART Timing in Modes 2 and 3
RXD
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
Start
bit
Data Byte Ninth
D8D7D6D5D4D3D2D1D0
Stop
bit
bit
The automatic addr es s rec ogn iti on feat ur e i s en abl ed when the multiprocess or c om mu­nication feature is enabled (SM2 bit in SCON register is set).
Implemented in the hardware, automatic address recognition enhances the multiproces­sor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address will the receiver set the RI bit in the SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If necessary, the user can enab le the automati c address re cognition feat ure in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. bit RI is set only when the received comma nd frame address matches the dev ice’s addr e ss and is term i­nated by a valid stop bit.

Given Address Each device has an individual address that is specified in the SADDR register; the

52
To support automatic a ddr ess re co gni tio n, a dev ic e i s identified by a given add re ss an d a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:
SADDR0101 0110b
1111 1100b
SADEN
Given0101 01XXb
4126L–CAN–01/08
AT/T89C51CC02
Here is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN
1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
Slave C:SADDR1111 0011b
1111 1001b
SADEN
Given1111 0XX1b
1111 1101b
SADEN
Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com­municate with sl ave A onl y, the ma ster mus t send an ad dres s where bi t 0 is clea r (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e.g.:
SADDR 0101 0110b SADEN 1111 1100b
SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b
SADEN
1111 1010b
Given1111 1X11b,
4126L–CAN–01/08
Slave B:SADDR1111 0011b
Slave C:SADDR=1111 0010b
1111 1001b
SADEN
Given1111 1X11B,
1111 1101b
SADEN
Given1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the ma ster must se nd an add ress F Fh. To c ommun icate with sl aves A and B, but not slave C, the master can send and address FBh.
53
AT/T89C51CC02

Registers Table 33. SCON Register

SCON (S:98h) Serial Control Register
76543210
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number
7
6SM1
5SM2
4REN
3TB8
2RB8
Bit
Mnemonic Description
FE
SM0
Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected.
Serial port Mode bit 0 (SMOD0 = 0)
Refer to SM1 for serial port mode selection.
Serial port Mode bit 1
SM0
SM1 Mode Baud Rate 0 0 Shift Register F 0 1 8-bit UART Variable 1 0 9bit UART F 1 1 9bit UART Variable
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3.
Reception Enable bit
Clear to disable serial reception. Set to enable serial reception.
Transmitter bit 8/Ninth bit to Transmit in Modes 2 and 3
Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.
Receiver bit 8/Ninth bit Received in Modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.
XTAL
XTAL
/12 (or F
/64 or F
/6 in mode X2)
XTAL
/32
XTAL
54
Transmit Interrupt Flag
1TI
0RI
Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes.
Receive Interrupt Flag
Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, See Figure 22. and Figure 23. in the other modes.
Reset Value = 0000 0000b bit addressable
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AT/T89C51CC02
Table 34. SADEN Regi ster
SADEN (S:B9h) Slave Address Mask Register
76543210
Bit
Number
7 - 0 Mask Data for Slave Individual Address
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
Table 35. SADDR Register SADDR (S:A9h) Slave Address Register
76543210
Bit
Number
7 - 0 S lave Individual Address
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
Table 36. SBUF Register SBUF (S:99h) Serial Data Buffer
4126L–CAN–01/08
76543210
Bit
Number
7 - 0 Data sent/received by Serial I/O Port
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
55
AT/T89C51CC02
Table 37. PCON Register
PCON (S:87h) Power Control Register
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
7SMOD1
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
Bit
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Clear to recognize next reset type. Set by hardware when V software.
General purpose Flag
Cleared by user for general purpose usage. Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage. Set by user for general purpose usage.
Power-down Mode bit
Cleared by hardware when reset occurs. Set to enter power-down mode.
Idle Mode bit
Clear by hardware when interrupt or reset occurs. Set to enter idle mode.
rises from 0 to its nominal voltage. Can also be set by
CC
56
Reset Value = 00X1 0000b Not bit addressable
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AT/T89C51CC02

Timers/Counters The T89C51CC02 implements two general-purpose, 16-bit Timers/Counters. Such are

identified as Timer 0 and Timer 1, and can be indepen dently configure d to operat e in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Tim er/Counter counts n egative transit ions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various o perating modes o f each Ti mer/Count er are de scribed in the fo llowing sections.

Timer/Counter Operations

A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (See Figure 38) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when T Hx overflows it sets the T imer overflow f lag (TFx) in T CON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer regis­ters can be accessed to obtain the cur rent co unt or to enter pr eset value s. They ca n be read at any time but TRx bit must be cleared to preset their values, otherwise the behav­ior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin T x as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer op erat ion (C/Tx # = 0 ), t he T ime r reg ist er co unts the div ided-d own peri phera l clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is f
PER
/6, i.e. f
/12 in standard m ode or f
OSC
OSC
/6 in X2
Mode. For Counter operation (C/Tx # = 1), the T im er reg ister cou nts the neg ati ve tran si ti ons on
the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is f
/12, i.e. f
PER
/24 in standard mode or f
OSC
/12 in X2 Mode.
OSC
There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampl ed at least onc e before it changes, i t should be hel d for at leas t one full peripheral cycle.

Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation.

Figure 24 through Figure 27 show the logical configuration of each mode. Timer 0 is controlled by the four l ower bi ts of TMO D r egis ter (See F igure 39) and bits 0,
1, 4 and 5 of TCON register (See Figure 38). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON r egister pr ovides Ti mer 0 cont rol func tions: ove rflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer ope ratio n (GAT E0 = 0) , se tting TR 0 allows TL 0 to be increme nted by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter­rupt request.
It is important to stop Timer/Counter before changing mode.
57
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AT/T89C51CC02
Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Time r which is s et up as an 8-bit Timer (TH0
See section “C lock”
register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (See Figure 24). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register.
Figure 24. Timer/Counter x (x= 0 or 1) in Mode 0
See section “Clock”
FTx
CLOCK
÷ 6
0 1
THx
(8 bits)
TLx
(5 bits)
Overflow
TFx
TCON Reg
Timer x Interrupt Request
Tx
C/Tx#
TMOD Reg
INTx#
GATEx
TMOD Reg
TRx
TCON Reg
Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in
cascade (See Figure 25). The selected input increments TL0 register.
Figure 25. Timer/Counter x (x= 0 or 1) in Mode 1
FTx
CLOCK
Tx
INTx#
÷ 6
0 1
C/Tx#
TMOD Reg
THx
(8 bits)
TLx
(8 bits)
Overflow
TFx
TCON Reg
Timer x Interrupt Request
GATEx
TMOD Reg
Mode 2 (8-bit Timer with Auto­Reload)
58
TRx
TCON Reg
Mode 2 configures Timer 0 as an 8-b it Timer (TL0 register) tha t automatically reloads from TH0 register (See Figure 26). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is servic ed, ha rdware clears TF0. The reload leaves TH0 unch anged. The next reload value may be changed at any time by writing it to TH0 register.
4126L–CAN–01/08
Figure 26. Timer/Counter x (x= 0 or 1) in Mode 2
t t
t t
t t
See section “Clock”
AT/T89C51CC02
FTx
CLOCK
÷ 6
0 1
TLx
(8 bits)
Overflow
TFx
TCON Reg
Timer x Interrup Reques
Tx
C/Tx#
TMOD Reg
INTx#
GATEx
TMOD Reg
TRx
TCON Reg
THx
(8 bits)
Mode 3 (Two 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (See Figure 27). This mode is provided for applications requiring an additional 8­bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg­ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting F
/6) and takes over use of the Timer 1 in terrupt (TF1) and
PER
run control (TR1) bits. Thus , operation of Tim er 1 is restricted when Timer 0 is in mod e
3.
Figure 27. Timer/Counter 0 in Mode 3: Two 8-bit Counters
FTx
CLOCK
T0
÷ 6
0 1
TL0
(8 bits)
Overflow
TF0
TCON.5
Timer 0 Interrup Reques
C/T0#
TMOD.2
INT0#
GATE0
TMOD.3
FTx
CLOCK
÷ 6
See section “Clock”
TR0
TCON.4
TR1
TCON.6
TH0
(8 bits)
Overflow
TF1
TCON.7
Timer 1 Interrup Reques

Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. Follow-

ing comments help to understand the differences:
Timer 1 functions as either a Timer or event Counter in three modes of operati on. Figure 24 to Figure 26 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode.
Timer 1 is controlled by the four high-order bits of TMOD register (See Figure 39) and bits 2, 3, 6 and 7 of TCON register (See Figure 38). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1).
Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose.
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59
AT/T89C51CC02
For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation.
Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request.
When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on.
It is important to stop Timer/Counter before changing mode.
Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-
ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (See Figure 24). The upper 3 bi ts of TL1 r egister are ignore d. Pr escale r over flow incre­ments TH1 register.
Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in
cascade (See Figure 25). The selected input increments TL1 register.
Mode 2 (8-bit Timer with Auto­Reload)
Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on ove rflo w (Se e Figur e 26). TL1 over flow set s TF 1 fl ag in TC ON regi ster and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.
Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and ho ld its coun t. This can be used to halt
Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This

flag is set every time an overfl ow oc c urs. Fla gs are cl eared when v ec tor in g to the Timer interrupt routine. Interrupts are enabled by setting interrupts are globally enabled by setting EA bit in IEN0 register.
Figure 28. Timer Interrupt System
TF0
TCON.5
ET0
IEN0.1
TF1
TCON.7
ET1
IEN0.3
ETx bit in IEN0 register. This assumes
Timer 0 Interrupt Request
Timer 1 Interrupt Request
60
4126L–CAN–01/08

Registers Table 38. TCON Register

TCON (S:88h) Timer/Counter Control Register
76543210
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
AT/T89C51CC02
Bit
Number
7TF1
6TR1
5TF0
4TR0
3IE1
2IT1
1IE0
Bit
Mnemonic Description
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Ti mer 1 register overflows.
Timer 1 Run Control bit
Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Ti mer 0 register overflows.
Timer 0 Run Control bit
Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0.
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (See IT1). Set by hardware when external interrupt is detected on INT1# pin.
Interrupt 1 Type Control bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1.
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (See IT0). Set by hardware when external interrupt is detected on INT0# pin.
4126L–CAN–01/08
0IT0
Interrupt 0 Type Control bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.
Reset Value = 0000 0000b
61
AT/T89C51CC02
Table 39. TMOD Register
TMOD (S:89h) Timer/Counter Mode Control Register
76543210
GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
Bit
Number
7GATE1
6C/T1#
5M11Timer 1 Mode Select bits
4M01
3GATE0
2C/T0#
1M10
0
Bit
Mnemonic Description
Timer 1 Gating Control bit
Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.
Timer 1 Counter/Timer Select bit
Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
M01 Operating mode
M11
0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter.
1 1 Mode 3: Timer 1 halted. Retains count.
1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1).
Timer 0 Gating Control bit
Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.
Timer 0 Counter/Timer Select bit
Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0.
Timer 0 Mode Select bit
M10
M00 Operating mode 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter.
M00
1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0). 1 1 Mode 3: TL0 is an 8-bit Timer/Counter.
TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.
(1)
(2)
62
Reset Value = 0000 0000b
Notes: 1. Reload ed from TH1 at overflo w.
2. Reloaded from TH0 at overflow.
Table 40. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register
76543210
Bit
Number
7:0 High Byte of Timer 0
Bit
Mnemonic Description
Reset Value = 0000 0000b
4126L–CAN–01/08
AT/T89C51CC02
Table 41. TL0 Register
TL0 (S:8Ah) Timer 0 Low Byte Register
76543210
Bit
Number
7:0 Low Byte of Timer 0
Bit
Mnemonic Description
Reset Value = 0000 0000b
Table 42. TH1 Register TH1 (S:8Dh) Timer 1 High Byte Register
76543210
Bit
Number
7:0 High Byte of Timer 1
Bit
Mnemonic Description
Reset Value = 0000 0000b
Table 43. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register
76543210
Bit
Number
7:0 Low Byte of Timer 1
Bit
Mnemonic Description
Reset Value = 0000 0000b
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63
AT/T89C51CC02
Timer 2 The T89C51CC02 Timer 2 is compatible with Timer 2 in the 80C52.
See section “Clock”
It is a 16-bit timer/counter: the count is maintained by two eightbit timer registers, TH2 and TL2 that are cascade-co nnecte d. It is con trolled by T2CON reg ister (See Table 45) and T2MOD register (See Table 46). Timer 2 operation is similar to Timer 0 and Timer
1. C/T2 timer clock. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 includes the following enhancements:
Auto-reload mode (up or down counter)
Programmable clock-output

Auto-Reload Mode The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto-

matic reload. This feature is controlled by the DCEN bit in T2MOD register (See Table
45). Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 29. In this mode the T2EX pin controls the counting direction.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and gene rates an inter rupt requ est. The overfl ow a lso cau ses th e 16 -bit v alu e in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflow or underflow, depending on the direction of the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit resolution.
selects F
/6 (timer operation) or external pin T2 (counter operation) as
T2 clock
Figure 29. Auto-Reload Mode Up/Down Counter
FT2
CLOCK
T2
:6
0 1
CT/2
T2CON.1
(DOWN COUNTING RELOAD VALUE)
FFh
(8-bit)
TL2
8-bit)
(
RCAP2L
(8-bit)
(UP COUNTING RELOAD VALUE)
FFh
(8-bit)
TH2
(8-bit)
RCAP2H
(8-bit)
TR2
T2CON.2
T2EX: 1=UP 2=DOWN
TOGGLE
TF2
T2CON Reg
T2CON Reg
EXF2

TIMER 2

INTERRUPT
64
4126L–CAN–01/08
AT/T89C51CC02
Programmable Clock­Output
In clock-out mode , Tim er 2 ope rates as a 50 %-duty - cycle, programmable clock ge ner a­tor (Figure 30). The input clock increments TL2 at frequency f
/2. The timer
OSC
repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency depending on the system oscillator frequenc y and the val ue in the RCAP2H and RCAP2L registers:
Clock OutFrequency
For a 16 MHz system clock in x1 mode, Timer 2 has a programmable frequency range of 61 Hz (f
OSC
16)
/2
to 4 MHz (f
OSC
---------------------------------------------------------------------------------------- -
=
4 65536 RCAP2H RCAP2L()×
/4). The generated clock signal is brought out to T2 pin
FT2clock
(P1.0). Timer 2 is programmed for the clock-out mode as follows:
Set T2OE bit in T2MOD register.
•Clear C/T2
bit in T2CON register.
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or different depending on the application.
To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simulta­neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.
Figure 30. Clock-Out Mode
FT2
CLOCK
T2
T2EX
Toggle
Q
Q D
TR2
T2CON.2
EXEN2
T2CON reg
TL2
(8-bit)
RCAP2L
(8-bit)
T2OE
T2MOD reg
EXF2
T2CON reg
TH2
(8-bit)
RCAP2H
(8-bit)
OVERFLOW
TIMER 2
INTERRUPT
4126L–CAN–01/08
65
AT/T89C51CC02

Registers Table 44. T2CON Register

T2CON (S:C8h) Timer 2 Control Register
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# C P/RL2#
Bit
Number
7TF2
6EXF2
5 RCLK
4TCLK
3EXEN2
2TR2
Bit
Mnemonic Description
Timer 2 Overflow Flag
TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on Timer 2 overflow.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software.
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port.
Timer 2 Run Control bit
Clear to tur n off Timer 2. Set to turn on Timer 2.
66
1C/T2#
0 C P/RL2#
Timer/Counter 2 Select bit
Clear for timer operation (input from internal clock system: f Set for counter operation (input from T2 input pin).
Timer 2 Captur e /Reload bi t
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b bit addressable
).
OSC
4126L–CAN–01/08
AT/T89C51CC02
Table 45. T2MOD Register
T2MOD (S:C9h) Timer 2 Mode Control Register
76543210
------T2OEDCEN
Bit
Number
7-
6-
5-
4-
3-
2-
1T2OE
0 DCEN
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 Output Enable bit
Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.
Down Counter Enable bit
Clear to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter.
Reset Value = XXXX XX00b Not bit addressable
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Table 46. TH2 Register TH2 (S:CDh) Timer 2 High Byte Register
76543210
--------
Bit
Number
7 - 0 High Byt e of Timer 2
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
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AT/T89C51CC02
Table 47. TL2 Register
TL2 (S:CCh) Timer 2 Low Byte Register
76543210
--------
Bit
Number
7 - 0 Low By te of Timer 2
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
Table 48. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register
76543210
--------
Bit
Number
7 - 0 High Byte of Timer 2 Reload/Capture.
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
Table 49. RCAP2L Register RCAP2L (S:CAh) Timer 2 Reload/Capture Low Byte Register
68
76543210
--------
Bit
Number
7 - 0 Low By te of Timer 2 Reload/Capture.
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
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Watchdog Timer T89C51CC02 contains a powerful programmable hardware Watchdog Timer (WDT) that
automatically resets the chip if it software fails to reset the WDT before the selected time

Figure 31. Watchdog Timer

interval has elapsed. It permits large Timeout ranging from 16ms to 2s @f in X1 mode.
This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset regist er (WDTRS T ) a nd a Wa tch dog T imer pr ogram min g ( WD T PRG) r egis­ter. When exiting reset, the WDT is -by default- disable.
To enable the WDT, the user has to wr ite the sequenc e 1EH and E1H into WDTR ST register with no instr uction between the two wri tes. When the Watchdog Timer is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT over­flow reset). When WDT overflows, it will gener ate an output RESET pulse at th e RST pin. The RESET pulse duration is 96xT
, where T
OSC
OSC
=1/f
. To make the best use of
OSC
the WDT, it should be se rviced in th ose sectio ns of code that will per iodically be exe­cuted within the time required to prevent a WDT reset
Note: When the watchdog is enable it is impossible to change its period.
= 12 MHz
OSC
Fwd Clock
RESET
WDTPRG
-
-
WDTRST
-
Enable
14-bit Counter
-
-
Decoder
WR
0
1
2
Control
7-bit Counter
Outputs
RESET
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Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the

WDT duration.
Table 50. Machine Cycle Count
S2 S1 S0 Machine Cycle Count
000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2
To compute WD Timeout, the following formula is applied:
F
---------------------------------------------------------------------------- -
FTime Out
=
62×
WDX2 X2
Note: Svalue represents the decimal value of (S2 S1 S0)
osc
2142
Svalue
×()
14
- 1
15
- 1
16
- 1
17
- 1
18
- 1
19
- 1
20
- 1
21
- 1
Find Hereafter computed Timeout values for f
XTAL = 12 MHz in X1 mode
OSC
Table 51. Time out Comp utat ion
S2 S1 S0 f
0 0 0 16.38 ms 12.28 ms 9.82 ms 0 0 1 32.77 ms 24.57 ms 19.66 ms 0 1 0 65.54 ms 49.14 ms 39.32 ms 0 1 1 131.07 ms 98.28 ms 78.64 ms 1 0 0 262.14 ms 196.56 ms 157.28 ms 1 0 1 524.29 ms 393.12 ms 314.56 ms 1 1 0 1.05 s 786.24 ms 629.12 ms 1 1 1 2.10 s 1.57 s 1.25 s
=12 MHz f
OSC
=16MHz f
OSC
=20 MHz
OSC
70
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Watchdog Timer During Power-down Mode and Idle

In Power-down mode the oscill ator stops, whi ch means the W DT also stops . While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabl ed p rio r to e nter ing Po wer-do wn mo de. W hen Powe r-down is e xite d wit h hardware reset, the watchdog is disabled. Exiting Power-down with an interrupt is signif­icantly different. The interrupt shall be held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down.
To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C51CC02 while in Idle mode, the user should always set up a timer that will periodi­cally exit Idle, service the WDT, and re-enter Idle mode.

Register Table 52. WDTPRG Register

WDTPRG (S:A7h) – Watchdog Timer Duration Programming register
76543210
-----S2S1S0
Bit
Number
7-
6-
5-
4-
3-
2S2
1S1
0S0
Reset Value = XXXX X000b
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Watchdog Timer Duration selection bit 2
Work in conjunction with bit 1 and bit 0.
Watchdog Timer Duration selection bit 1
Work in conjunction with bit 2 and bit 0.
Watchdog Timer Duration selection bit 0
Work in conjunction with bit 1 and bit 2.
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Table 53. WDTRST Register
WDTRST (S:A6h Write Only) – Watchdog Timer Enable register
76543210
--------
Bit
Number
7 - Watchdog Control Value
Bit
Mnemonic Description
Reset Value = 1111 1111b
Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in
sequence without instruction between these two sequences.
72
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CAN Controller The CAN Cont ro ller prov id es al l th e fe atu re s re qui red to implement the ser ial c om mun i-

cation protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to by ISO/11898 (2.0A & 2.0B) for high speed and ISO/11519-2 for low speed. The CAN Controller is able to handle al l typ es of fram es (D ata, Remo te, Erro r and Ov erlo ad) and achieves a bitrate of 1-Mbit/s at 8 MHz
Note: 1. At BRP = 1 sampling point will be fixed.

CAN Protocol The CAN pr otocol is an inter nationa l stand ard defi ned in the ISO 1189 8 for high sp eed

and ISO 11519-2 for low speed.
Principles CAN is based on a broadcast communication mechanism. This broadcast communica-
tion is achieved by using a message oriented transmission protocol. These messages are identified by using a message identifier. Such a message identifier has to be unique within the whole network and it defines not only the content but also the priority of the message.
The priority at which a message is transmitted compared to another less urgent mes­sage is spe cifie d by the i dent ifier of eac h message. The priorities are laid down during system design in the form of corresponding binary values and cannot be changed dynamically. The identifier with the lowest binary number has the highest priority.
Bus access confl icts are r esolved by bit-wis e arbitrati on on the i dentifiers involved by each node observing the bus level bit for bit. This happens in accordance with the "wired and" mechanism, b y w hic h t he d omi nan t state overwrites the r ece ss i ve sta te. T h e c om­petition for bus all ocation is lost by a ll n odes with r ecessi ve tr ansm ission and domi nant observation. All the "los ers" a utomati cally become recei vers of the messag e with the highest priority and do not re-attempt transmission until the bus is available again.
1
Crystal frequency in X2 Mode.
Message Formats The CAN proto col supports two me ssage frame formats, the only essential difference
being in the length of the identifier. The CAN standard frame, also known as CAN 2.0 A, supports a length of 11 b its for the identi fier , and the C AN exte nded frame , als o know n as CAN 2.0 B, supports a length of 29 bits for the identifier.
Can Standard Frame
Figure 32. CAN Standard Frames
Data Frame
Bus Idle Bus Idle
Interframe
Space
SOF
SOF
11-bit identifier
ID10..0
Arbitration
Field
RTR
4-bit DLC
IDE r0 ACK
DLC4..0
Control
Field
0 - 8 bytes
Data Field
15-bit CRC
CRC Field
CRC
del.
ACK Field
ACK
del.
7 bits
End of
Frame
Intermission
3 bits
Interframe
(Indefinite)
Space
Remote Frame
Bus Idle Bus Idle
Interframe
Space
SOF
SOF
11-bit identifier
ID10..0
Arbitration
Field
RTR
A message in the CAN standard frame format begins with the "Start Of Frame (SOF)", this is followed by the "Arbitration field" which consist of the identifier and the "Remote Transmission Request (RTR)" bit used to distinguish between the data frame and the data request frame called remote frame. The following "Control field" contains the "IDen­tifier Extension (IDE)" bit and the "Da ta Length Code (DLC)" used to indicate the
4-bit DLC
IDE r0 ACK
DLC4..0
Control
Field
15-bit CRC
CRC Field
CRC
del.
ACK
ACK Field
del.
7 bits
End of Frame
Intermission
3 bits
Interframe
(Indefinite)
Space
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AT/T89C51CC02
number of followin g data byte s in the "D ata field". In a remote frame, the DLC contains
)
the number of request ed data bytes . The "Data field" that foll ows can hol d up to 8 data bytes. The fra me integri ty is gua ranteed by the fol lowing "Cy clic Redund ant Check (CRC)" sum . The "A CKnow ledge ( ACK) field" comp romise s the A CK slot and th e ACK delimiter. The bit in t he A C K slot i s se nt as a re ce ss iv e bit and is ov erwr itt en a s a dom i­nant bit by the receivers which have at this time received the data correctly. Correct messages are acknowledged by the receivers regardless of the result of the acceptance test. The end of the messa ge is in dicat ed by "End Of Fram e (EOF) ". The "In termi ssion Frame Space (IFS)" is the minimum number of bits separating consecutive messages. If there is no following bus access by any node, the bus remains idle.
CAN Extended Frame
Figure 33. CAN Extended Frames
Data Frame
Bus Idle Bus Idle
11-bit base identifier
SOF
SOF
IDT28..18
SRR
18-bit identifier extension
IDE ACK
ID17..0
RTR
r0r1
4-bit DLC
DLC4..0
0 - 8 bytes
15-bit CRC
CRC
del.
ACK
del.
7 bits
Intermission
3 bits
(Indefinite
Interframe
Space
Arbitration
Field
Control
Field
Data
Field
CRC Field
ACK Field
End of Frame
Interframe
Space
Remote Frame
Bus Idle Bus Idle
Interframe
Space
11-bit base identifier
SOF
SOF
IDT28..18
SRR
Format Co-existence As the two form ats have to co- exist on one bus, it is lai d down which mes sage has
18-bit identifier extension
IDE r0
Arbitration
Field
ID17..0
RTR
4-bit DLC
r1 ACK
DLC4..0
Control
Field
15-bit CRC
CRC Field
CRC
del.
ACK Field
ACK
del.
7 bits
End of Frame
Intermission
3 bits
Interframe
Space
(Indefinite)
A message in th e CAN extended frame form at is li kely the same as a message in CA N standard frame format. The difference is the length of the identifier used. The identifier is made up of the existing 11-bit identi fier (base id entifier) and an 18-bit extens ion (identi­fier extension). The d istin ction between CAN stan dard fra me forma t and CAN extended frame format is made by using the IDE bit which is trans mi tted as d omi nan t in cas e o f a frame in CAN standard frame format, and transmitted as recessive in the other case.
higher priority on the bus in the case of bus access collision with different formats and the same identifier / base identifier: The message in CAN standard frame format always has priority over the message in extended format.
There are three different types of CAN modules available:
2.0A - Considers 29 bit ID as an error – 2.0B Passive - Ignores 29 bit ID messages – 2.0B Active - Handles both 11 and 29 bit ID Messages
Bit Timing To ensure co rrect sampling up to the la st bit, a CAN node needs to re-sync hronize
Bit Construction One CAN bit time is specified as four non- overl apping time segments . Each s egment is
74
throughout the entire frame. This is done at the beginning of each message with the fall­ing edge SOF and on each recessive to dominant edge.
constructed from an in teger multiple of the T ime Q uan tum. T he Ti me Q u antu m or TQ is the smallest discrete timing resolution used by a CAN node.
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Figure 34. CAN Bit Construction
CAN Frame
(producer)
Transmission Point
(producer)
Nominal CAN Bit Time
Time Quantum
(producer)
Segments (producer)
Segments
(consumer)
SYNC_SEG
propagation
delay
Synchronization Segment The first segment is used to synchronize the various bus nodes.
On transmission, at the start of thi s segment, the curren t bit level is output. If th ere is a bit state change betwe en th e prev io us bit and t he c ur rent b it, th en t he bu s s tat e ch ange is expected to occur within this segment by the receiving nodes.
PROP_SEG PHASE_SEG_1 PHASE_SEG_2
SYNC_SEG
PROP_SEG PHASE_SEG_1 PHASE_SEG_2
Sample Point
Propagation Time Segment This segment is used to compensate for signal delays across the network.
This is neces sary to c ompensate for signa l propag ation d elays on the bus l ine and through the transceivers of the bus nodes.
Phase Segment 1 Phase Segment 1 is used to compensate for edge phase errors.
This segment may be lengthened during resynchronization.
Sample Point The sample point is the point of time at which the bus level is read and interpreted as the
value of the respective bit. Its location is at the end of Phase Segment 1 (between the two Phase Segments).
Phase Segment 2 This segment is also used to compensate for edge phase errors.
This segment may be shortened during resynchronization, but the length has to be at least as long as the information processing time and may not be more than the length of Phase Segment 1.
Information Processing Time It is the time required for the logic to determine the bit level of a sampled bit.
The Information pr ocessin g Time begin s at the sam ple point, is measured i n TQ and is fixed at 2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is t he las t segm ent in the bi t time, Phase Segme nt 2 m inimum shall not be less than the Information processing Time.
Bit Lengthening As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Seg-
ment 2 may be shortened to compensa te for osc illator tolerances. If, for ex ample, the transmitter oscillator is slower tha n the re ceiver oscillator , the nex t falling e dge use d for resynchronization may be delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and the end of the bit time.
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Bit Shortening If, on the other hand, the transmitter oscillator is faster than the receiver one, the next
-
falling edge use d for resync hroni zation ma y be too earl y. So Phas e Segment 2 in bit N is shortened in order to adjust the sample point for bit N+1 and the end of the bit time
Synchronization Jump Width The limit to the amount of lengthening or shortening of the Phase Segments is set by the
Resynchronization Jump Width. This segment may not be longer than Phase Segment 2.
Programming the Sample Point Programming of the sample point allows "tuning" of the characteristics to suit the bus.
Early sampling allo ws more Tim e Quanta in the Phase Se gment 2 so the Synchron iza­tion Jump Width can be programmed to its maximum. This maximum capacity to shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances, so that lower cost oscillators such as ceramic resonators may be used.
Late sampling allows more Time Quanta in the Propagation Time Segment which allows a poorer bus topology and maximum bus length.
Arbitration
Figure 35. Bus Arbitration
Arbitration lost
node A
TXCAN
node B
TXCAN
CAN bus
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
SOF
SOF
Node A loses the bus Node B wins the bus
RTR IDE
- - - - - - - -
The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple Access with Arbitration on Message Priority”.
During transmission, arbitra tion on the CAN bus can be lost to a com peting device with a higher priority CAN Identifier. This arbitration concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss.
The bus access conflic t is res olved du ring the a rbitra tion fi eld mostl y over the iden tifier value. If a data frame and a remote frame wi th the same ident ifier are initi ated at the same time, the data frame prevails over the remote frame (c.f. RTR bit).
Errors The CAN protocol signals any errors immediately as they occur. Three error detection
mechanisms are implemented at the message level and two at the bit level:
Error at Message Level Cyclic Redundancy Check (CRC)
The CRC safeguards the information in the frame by adding redundant check bits at the transmission end. At the receiver these bits are re-computed and tested against the received bits. If they do not agree there has been a CRC error.
76
•Frame Check This mechanism verifies the structure of the transmitted frame by checking the bit
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fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors".
ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If no acknowledgement is received by the transmitter of the message an ACK error is indicated.
Error at Bit Level Monitoring
The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received. This permits reliable detection of global errors and errors local to the transmitter.
Bit Stuffing The coding of the individual bits is tested at bit level. The bit representation used by CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding. The synchronization edges are generated by means of bit stuffing.
Error Signalling If one or more errors are discovered by at least one node using the above mechanisms,
the current transmission is aborted by sending an "error flag". This prevents other nodes accepting the messa ge and thus ensures the cons istency of data thro ughout the net­work. After transmission of an erroneou s message that has been aborted, the sender automatically re-attempts transmission.

CAN Controller Description

The CAN controller accesses are made through SFR. Several operations are possible by SFR:
arithmetic and logic operations, transfers and program control (SFR is accessible by direct addressing).
4 independent message objects are implemented, a pagination system manages their accesses.
Any message o bj ec t c an be programmed in a r ec ept ion b u ffe r bl oc k ( ev en non -con sec­utive buffers ). For the r eceptio n of def ined mes sages on e or seve ral rec eiver me ssage objects can be masked without participating in the buffer feature. An IT is generated when the buffer is full. The frames foll owing the buffer-full interrupt will not be take n in to account until at least one of the buffer message objects is re-enabled in reception. Higher priority of a message object for reception or transmiss ion is given to the lower message object number.
The programmable 16-b it Time r (CANT IMER ) is used to st amp e ach r eceive d and sent message in the CANSTMP register. This timer starts counting as soon as the CAN con­troller is enabled by the ENA bit in the CANGCON register.
The Time Trigger Communication (TTC) protocol is supported by the T89C51CC02.
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AT/T89C51CC02
Figure 36. CAN Controller Block Diagram
TxDC RxDC
bit
Timing
Logic
Error Counter Rec/Tec
bit
Stuffing /Destuffing
Cyclic
Redundancy Check
Receive Transmit

CAN Controller Mailbox and Registers Organization

Page
Register
The pagination allows management of the 91 registers including 80(4 x 20) Bytes of mailbox via 32 SFRs. All actions on the message object window SFRs apply to the corresponding message object registers pointed by the message object number find in the Page message object register (CANPAGE) as illustrate in Figure 37.
DPR(Mailbox + Registers)
µC-Core Interface
Interface
Bus
Core
Control
Priority
Encoder
78
4126L–CAN–01/08
Figure 37. CAN Controller Memory Organization
SFRs On-chip CAN Controller Registers
General Control
General Status
General Interrupt
bit Timing - 1 bit Timing - 2 bit Timing - 3
Enable message object
Enable Interrupt
Enable Interrupt message object
Status Interrupt message object
Timer Control
CANTimer High
CANTimer Low
TimTTC High
TimTTC Low
TEC counter
REC counter
Page message object
(message object number)(Data offset)
AT/T89C51CC02
4 Message Objects
message object Status
message object Control & DLC
Message Data
ID Tag - 1 ID Tag - 2 ID Tag - 3 ID Tag - 4
ID Mask - 1 ID Mask - 2 ID Mask - 3 ID Mask - 4
TimStmp High TimStmp Low
message object Window SFRs
message object 0 - Status
message object 0 - Control & DLC
Ch.0 - Message Data - byte 0
8 Bytes
Ch.0 - ID Tag - 1 Ch.0 - ID Tag - 2 Ch.0 - ID Tag - 3 Ch.0 - ID Tag - 4
Ch.0 - ID Mask- 1 Ch.0 - ID Mask- 2 Ch.0 - ID Mask- 3
Ch.0 - ID Mask - 4
Ch.0 TimStmp High
Ch.0 TimStmp Low
message object 3 - Status
message object 3 - Control & DLC
Ch.3 - Message Data - byte 0
Ch.3 - ID Tag - 1 Ch.3 - ID Tag - 2 Ch.3 - ID Tag - 3
Ch.3 - ID Tag - 4
Ch.3 - ID Mask - 1 Ch.3 - ID Mask - 2 Ch.3 - ID Mask - 3 Ch.3 - ID Mask - 4
Ch.3 TimStmp High Ch.3 TimStmp Low
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Working on Message Objects The Page message object regi ster ( CANPA GE) is used t o sele ct one o f the 4 me ssag e
objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected message object number in the corresponding SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is managed by the Page message object register with an auto-incrementation at the end of each access. The range of this counter is 8. Note that the maibox is a pure RAM, ded ic ate d to one mes sa ge ob je ct, wi tho ut over la p. In most cases, i t is n ot neces sary to transfe r the rec eived me ssage i nto t he stand ard memory. The message to be transmitted can be built directly in the maibox. Most calcu­lations or tests can be executed in the mailbox area which provide quicker access.

CAN Controller Management

In order to enable the CAN Controller correctly the following registers have to be initialized:
General Control (CANGCON),
bit Timing (CANBT 1, 2 & 3),
And for each page of 15 message objects: – Message object Control (CANCONCH), – Message object Status (CANSTCH).
During operation, the CAN Enable message object registers (CANEN) gives a fast over­view of the message objects availability.
The CAN messages can be handled by interrupt or polling modes. A message object can be configured as follows:
Transmit message object
Receive message object
Receive buffer message object
Disable
This configuration is made in the CONCH field of the CANCONCH register (See Table 54).
When a message object is configured, the corresponding ENCH bit of CANEN register is set.
80
Table 54. Configuration for CONCH1:2
CONCH 1 CONCH 2 Type of Message Object
0 0 Disable 0 1 Transmitter 10Receiver 1 1 Receiver buffer
When a Tran smitter or Recei ver act ion of a mes sage o bject is complet ed, the c orre­sponding ENCH bit of the CANEN register is cleared. In order to re-enable the message object, it is necessary to re-write the configuration in CANCONCH register.
Non-consecutive message objects can be used for all three types of message objects (Transmitter, Receiver and Receiver buffer).
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Buffer Mode Any messag e objec t can be u sed to de fine on e buffer , includ ing non -cons ecutiv e mes-
sage objects, and with no limitation in number of message objects used up to 4. Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1;
Figure 38. Buffer Mode
Block buffer
buffer 1
message object 3 message object 2 message object 1 message object 0
The same acceptance filter must be defined for each message objects of the buffer. When there is no mask on the identifier or the IDE, all messages are accepted.
A received frame will always be stored in the lowest free message object. When the flag RxOk is set on one of the buffer message objects, this message object
can then be read by t he a ppl ic ation. This flag must then be cl ear ed by th e software and the message object re-enabled in buffer reception in order to free the message object.
buffer 0
The OVRBUF flag in the CANGIT register is set when the buffer is full. This flag can generate an interrupt.
The frames following the buffer-full interrupt will not be stored and no status will be over­written in the CANSTCH registers involved in the buffer until at least one of the buffer message objects is re-enabled in reception.
This flag must be cleared by the software in order to ack nowledge the interrupt.

IT CAN Management The different interrupts are:

Transmission interrupt
Reception int erru pt
Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error)
Interrupt when Buffer receive is full
Interrupt on overrun of CAN Timer
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Figure 39. CAN Controller Interrupt Structure
IT
CANGIE.5
ENRX
CANGIE.4
ENTX
CANGIE.3
ENERCH
RXOK i
CANSTCH.5
TXOK i
CANSTCH.6
BERR i
CANSTCH.4
SERR i
CANSTCH.3
CERR i
CANSTCH.2
FERR i
CANSTCH.1
AERR i
CANSTCH.0
OVRBUF
CANGIT.4
SERG
CANGIT.3
CERG
CANGIT.2
FERG
CANGIT.1
AERG
CANGIT.0
CANSIT
SIT i
SIT i
CANIE
EICH i
CANGIE.2
ENBUF
CANGIE.1
ENERG
i=0
i=4
CANGIT.7
CANIT
IEN1.0
ECAN
CAN
IEN1.2
ETIM
OVRTIM
CANGIT.5
To enable a transmission interrupt:
Enable General CAN IT in the interrupt system register
Enable interrupt by message object, EICHi
Enable transmission interrupt, ENTX
To enable a reception interrupt:
Enable General CAN IT in the interrupt system register
Enable interrupt by message object, EICHi
Enable reception interrupt, ENRX
To enable an interrupt on message object error:
Enable General CAN IT in the interrupt system register
Enable interrupt by message object, EICHi
Enable interrupt on error, ENERCH
To enable an interrupt on general error:
Enable General CAN IT in the interrupt system register
Enable interrupt on error, ENERG
OVRIT
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AT/T89C51CC02
To enable an interrupt on Buffer-full condition:
Enable General CAN IT in the interrupt system register
Enable interrupt on Buffer full, ENBUF
To enable an interrupt when Timer overruns:
Enable Overrun IT in the interrupt system register
When an interrupt occurs, the corresponding message obj ect bit is set in the SIT register.
To acknowledge an interrupt, the corr esponding CANSTCH bi ts (RXOK, TXOK,...) or CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application.
When the CAN node is in transm is si on an d dete ct s a For m Er ror in its fr ame , a bit Er ror will also be rai se d. Cons eq uen tly , two co nse cu tiv e in ter rupts c an oc cur , b oth du e to the same error.
When a message object error occu rs and is set in CANSTCH regi ster, no general error are set in CANGIE register.
4126L–CAN–01/08
83
AT/T89C51CC02
Bit Timing and Baud
t
Rate
FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s.
Field and segment abbrevia tio ns :
BRP: Baud Rate Prescaler.
TQ: Time Quantum (output of Baud Rate Prescaler).
SYNS: SYNchronization Segment is 1 TQ long.
PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.
PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.
PHS2: PHase Segment 2 is programmable to be superior or eual to the Information Processing Time and inferior or equal to TPHS1
INFORMATION PROCESSING TIME is 2 TQ.
SJW: (Re) Synchronization Jump Width is programmable to be minimum of PHS1 and 4.
The total number of TQ in a bit time has to be programmed at least from 8 to 25.
Figure 40. Sample and Transmission Point
FCAN
CLOCK
Prescaler BR P
System Clock Tscl
Time Quantum
bit Timing
PRS 3bit length PHS1 3bit length PHS2 3bit length SJW 2-bit length
Sample Point
Transmission Poin
The baud rate selection is made by Tbit calculation: Tbit = Tsyns + Tprs + Tphs1 + Tphs2
1. Tsyns = Tscl = (BRP[5..0]+ 1)/Fcan = 1TQ
2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl
3. Tphs1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl
4. Tphs2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl
Tphs2 = Max of (Tphs1 and 2TQ)
5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl
The total number of Tscl (Time Quanta) in a bit time must be comprised between 8 to
25.
84
4126L–CAN–01/08
Figure 41. General Structure of a bit Period
nt
( ( ( (
1/ Fcan
Oscillator
AT/T89C51CC02
System Clock
Data
1) Phase error ≤ 0
2) Phase error ≥ 0
3) Phase error > 0
4) Phase error < 0
Tscl
bit Rate Prescaler
One Nominal bit
Tsyns (*)
(*) Synchronization Segment: SYNS
Tsyns = 1xTscl (fixed)
example of bit timing determination for CAN baudrate of 500 kbit/s:
F
= 12 MHz in X1 mode => FCAN = 6MHz
OSC
Verify that the CAN baud rate you want is an integer division of FCAN clock.
FCAN/CANbaudrate = 6 MHz/500 kHz = 12
The time quanta TQ must be comprised between 8 and 25: TQ = 12 and BRP = 0
Tprs
Tbit calculation:
Tphs1 (1)
Tphs1 + Tsjw (3)
Tbit
Tbit Tsyns Tprs Tphs 1 Tphs2++ +=
Tphs2 - Tsjw (4)
Sample Point
Tphs2 (2)
Transmission Poi
Define the various timing parameters: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 = 12TQ
Tsyns = 1TQ and Tsjw =1TQ => SJW = 0
If we chose a sample point at 66.6% => Tphs2 = 4TQ => PHS2 = 3
Tbit = 12 = 4 + 1 + Tphs1 + Tprs, let us choose Tprs = 3 Tphs1 = 4
PHS1 = 3 and PRS = 2
BRP = 0 so CANBT1 = 00h
SJW = 0 and PRS = 2 so CANBT2 = 04h
PHS2 = 3 and PHS1 = 3 so CANBT3 = 36h
4126L–CAN–01/08
85
AT/T89C51CC02

Fault Confinement With respect to fault confinement, a unit may be in one of the three following status:

Error active
Error passive
Bus off
An error active unit takes part in bus communication and can send an active error frame when the CAN macro detects an error.
An error passive unit cannot send an active error frame. It takes part in bus communica­tion, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit will wait before initiating further transmission.
A bus off unit is not allowed to have any influence on the bus. For fault confinement, two error counters (TEC and REC) are implemented. See CAN Specification for details on Fault confinement.
Figure 42. Line Error Mode
ERRP = 0 BOFF = 0
Init.
TEC: Transmit Error Counter
REC: Receive Error Counter
TEC>127
or
REC>127
ERRP = 1 BOFF = 0
Error
Passive
Error
Active
TEC<127
and
REC<127
TEC>255
128 Occurrences
of
11 Consecutive
Recessive
bit
Bus
Off
ERRP = 0 BOFF = 1
86
4126L–CAN–01/08
AT/T89C51CC02

Acceptance Filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received

and an ID+RTR+RB+IDE sp ecified while taking the c omparison mask into acc ount) the ID+RTR+RB+IDE received are written over the ID TAG Registers.
ID => IDT0-29 RTR => RTRTAG RB => RB0-1TAG IDE => IDE in CANCONCH register
Figure 43. Acceptance Filter Block Diagram
RxDC
Rx Shift Register (internal)
ID & RB RTR IDE
13/32
=
Write Enable
13/32
13/32
ID TAG Registers (Ch i) & CanConch
ID & RB RTR
example: To accept only ID = 318h in part A. ID MSK = 111 1111 1111 b ID TAG = 011 0001 1000 b
IDE
13/32
1
13/32
ID MSK Registers (Ch i)
ID & RB RTR IDE
Hit
(Ch i)
4126L–CAN–01/08
87
AT/T89C51CC02

Data and Remote Frame Description of the different steps for:

r
Data frame
Node A Node B
K
K
V
O
L
O
X
P
X
R
T
R
D
u uu uu
c uc uu
A
T
A
F
R
A
M
E
message object in tran sm iss i on
message object disabled
Remote frame, with automatic reply
H
C
R
T
N
R
E
0 1 x 0 0
0 0 x 1 0
H
V
L
C
R
P
T
N
T
R
R
E
0 1 x 0 0
0 0 x 0 1
u uu uu
u cc uu
K
K
O
O
X
X
R
message object in reception
message object disabled
H
C
R
T
N
R
E
message object in transmission
message object in reception by CAN controller by CAN controller
message object disabled
1 1 x 0 0
0 1 x 1 0
0 0 x 0 1
c uu
K
K
V
O
L
O
X
P
X
R
T
R
R
E
M
u uu uu
c uu uc
c
u
O
T
E
F
R
A
M
E
E
M
A
R
F
)
e
A
t
a
T
i
A
d
D
e
m
m
i
(
H
C
R
T
N
R
E
1 1 1 0 0
0 1 0 0 0
0 0 0 1 0
K
K
V
O
L
O
X
P
X
R
T
R
u uu uu
u uu cc
c uc cu
message object in reception
message object in transmission
message object disabled
Remote frame
K
K
V
O
L
O
X
P
X
R
R
T
u uu uu
u cc uu
u uu uu
c uc uu
message object in rece ption
message object disabled
message obj ect in transmission by use
message object disabled
message object in transmission
message object disabled
message object in reception by user
H
V
C
L
R
P
T
N
T
E
R
R
1 1 x 0 0
0 1 x 1 0
0 0 x 0 1
u uu uu
c uu uc
u cc uc
K
K
O
O
X
X
R
R
E
M
O
T
E
F
R
A
M
E
E
M
A
R
F
)
d
A
e
T
r
r
A
e
f
D
e
d
(
H
C
R
T
N
R
E
1 1 0 0 0
1 0 0 0 1
0 1 x 0 0
0 0 x 1 0
88
i
: modified by user
u
i
: modified by CAN
c
4126L–CAN–01/08
AT/T89C51CC02

Time Trigger Communication (TTC) and Message Stamping

The T89C51CC02 has a progr ammable 1 6-bit Timer ( CANTIMH&CA NTIML) for mes­sage stamp and TTC.
This CAN Timer starts after th e CAN contr oller is enabl ed by th e ENA bit i n the CANG­CON register.
Two modes in the timer are implemented:
Time Trigger Communication: – Capture of this timer value in the CANTTCH & CANTTCL registers on Start
Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC bit in the CANGCON register, when the network is configured in TTC by the TTC bit in the CANGCON register.
Note: In this mode, CAN only sends the frame once, even if an error occurs.
Message Stamping – Capture of this timer value in the CANSTMPH & CANSTMPL registers of the
message object which received or sent the frame. – All messages can be stamps. – The stamping of a received frame occurs when the RxOk flag is set. – The stamping of a sent frame occurs when the TxOk flag is set.
The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base. When the timer roll-over from FFFFh to 0000h, an interrupt is generated if the ETIM bit
in the interrupt enable register IEN1 is set.
Figure 44. Block Diagram of CAN Timer
Fcan
CLOCK
TXOK i
CANSTCH.4
RXOK i
CANSTCH.5
CANSTMPH & CANSTMPL
÷ 6
CANTCON
CANTIMH & CANTIML
CANGCON.1
ENA
CANTTCH & CANTTCL
When 0xFFFF to 0x0000
CANGCON.5
TTC
OVRTIM
CANGIT.5
CANGCON.4
SYNCTTC
SOF on CAN frame EOF on CAN frame
4126L–CAN–01/08
89
AT/T89C51CC02

CAN Autobaud and Listening Mode

To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controll er is only listening to the line wi thout ackno wledg­ing the received messages. It cannot send any message. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find).
In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared.
Figure 45. Autobaud Mode
TxDC
TxDC
AUTOBAUD
CANGCON.3
RxDC

Routine Examples 1. Init of CAN macro

// Reset the CAN macro
CANGCON = 01h;
// Disable CAN interrupts
ECAN = 0;
ETIM = 0;
// Init the Mailbox
for num_page =0; num_page <4; num_page++
{
CANPAGE = num_channel << 4;
CANCONCH = 00h
CANSTCH = 00h;
CANIDT1 = 00h;
CANIDT2 = 00h;
CANIDT3 = 00h;
CANIDT4 = 00h;
CANIDM1 = 00h;
CANIDM2 = 00h;
CANIDM3 = 00h;
CANIDM4 = 00h;
for num_data =0; num_data <8; num_data++)
{
CANMSG = 00h;
}
}
// Configure the bit timing
CANBT1 = xxh
CANBT2 = xxh
CANBT3 = xxh
RxDC
1 0
90
4126L–CAN–01/08
AT/T89C51CC02
// Enable the CAN macro
CANGCON = 02h
2. Configure message object 3 in reception to receive only standard (11bit identifier) message 100h
// Select the message object 3
CANPAGE = 30h
// Enable the interrupt on this message object
CANIE = 08h
// Clear the status and control register
CANSTCH = 00h
CANCONCH= 00h
// Init the acceptance filter to accept only message 100h in standard mode
CANIDT1 = 20h
CANIDT2 = 00h
CANIDT3 = 00h
CANIDT4 = 00h
CANIDM1 = FFh
CANIDM2 = FFh
CANIDM3 = FFh
CANIDM4 = FFh
// Enable channel in reception
CANCONCH = 88h // enable reception
Note: to enable the CAN interrupt in reception:
EA = 1
ECAN = 1
CANGIE = 20h
3. Send a message on the message object 0
// Select the message object 0
CANPAGE = 00h
// Enable the interrupt on this message object
CANIE = 01h
// Clear the Status register
CANSTCH = 00h;
// load the identifier to send (ex: 555h)
CANIDT1 = AAh;
CANIDT2 = A0h;
// load data to send
CANMSG = 00h
CANMSG = 01h
CANMSG = 02h
CANMSG = 03h
CANMSG = 04h
CANMSG = 05h
CANMSG = 06h
CANMSG = 07h
// configure the control register
CANCONCH = 18h
4. Interrupt routine
// Save the current CANPAGE
4126L–CAN–01/08
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AT/T89C51CC02
// Find the first message object which generate an interrupt in CANSIT
// Select the corresponding message object
// Analyse the CANSTCH register to identify which kind of interrupt is generated
// Manage the interrupt
// Clear the status register CANSTCH = 00h;
// if it is not a channel interrupt but a general interrupt
// Manage the general interrupt and clear CANGIT register
// restore the old CANPAGE
92
4126L–CAN–01/08

CAN SFRs

Table 55. SFR Mapping
(1)
0/8
AT/T89C51CC02
1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
IPL1
xxxx x000CH0000 0000
B
0000 0000
IEN1
xxxx x000CL0000 0000
ACC
0000 0000
CCON
0000 0000
PSW
0000 0000
T2CON
0000 0000
P4
xxxx xx11
IPL0
x000 0000
P3
1111 1111
IEN0
0000 0000
P2
xxxx xx11
CMOD
0xxx x000
FCON
0000 0000
T2MOD
xxxx xx00
CANGIE
1100 0000
SADEN
0000 0000 CANPAGE
1100 0000
SADDR
0000 0000
CANTCON
0000 0000
CCAP0H
0000 0000
ADCLK
xxx0 0000
CCAP0L
0000 0000
CCAPM0
x000 0000
EECON
xxxx xx00
RCAP2L
0000 0000
CANSTCH
xxxx xxxx
CANGSTA 1010 0000
(2)
AUXR1
xxxx 00x0
CCAP1H
0000 0000
ADCON
x000 0000
CCAP1L
0000 0000
CCAPM1
x000 0000
RCAP2H
0000 0000
CANIE
1111 0000
CANSIT
xxxx 0000
CANCONCH
xxxx xxxx
CANGCON
0000 0000
CANMSG xxxx xxxx
ADDL
0000 0000
TL2
0000 0000
CANIDM1
xxxx xxxx CANIDT1
xxxx xxxx
CANBT1
xxxx xxxx
CANTIML
0000 0000
CANTTCL
0000 0000
ADDH
0000 0000
TH2
0000 0000 CANIDM2
xxxx xxxx CANIDT2
xxxx xxxx
CANBT2
xxxx xxxx
CANTIMH 0000 0000
CANTTCH 0000 0000
ADCF
0000 0000
CANIDM3
xxxx xxxx CANIDT3
xxxx xxxx
CANBT3
xxxx xxxx
CANSTMPL
xxxx xxxx WDTRST
1111 1111
IPH1
xxxx x000
CANEN
xxxx 0000 CANIDM4
xxxx xxxx CANIDT4
xxxx xxxx
IPH0
x000 0000
CANSTMPH
xxxx xxxx
WDTPRG xxxx x000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
98h
90h
88h
80h
4126L–CAN–01/08
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
(1)
0/8
SBUF
0000 0000
TMOD
0000 0000
SP
0000 0111
1/9 2/A 3/B 4/C 5/D 6/E 7/F
TL0
0000 0000
DPL
0000 0000
CANGIT
0x00 0000
TL1
0000 0000
DPH
0000 0000
CANTEC
0000 0000
TH0
0000 0000
CANREC
0000 0000
TH1
0000 0000
CKCON
0000 0000
PCON
00x1 0000
9Fh
97h
8Fh
87h
93
AT/T89C51CC02

Registers Table 56. CANGCON Register

CANGCON (S:ABh) CAN General Control Register
7654 3210
ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES
Bit Number Bit Mnemonic Description
7ABRQ
6OVRQ
5TTC
4 SYNCTTC
Abort Request
Not an auto-resetable bit. A reset of the ENCH bi t (message object control & DLC register) is done for each message object. The pending transmission communications are immediately aborted but the on-going communication will be terminated normally, setting the appropriate status flags, TxOk or RxOk.
Overload Frame Request (Initiator). Auto-resetable bit. Set to send an overload frame after the next received message. Cleared by the hardware at the beginning of transmission of the overload frame.
Network in Timer Trigger Communication
set to select node in TTC. clear to disable TTC features.
Synchronization of TTC
When this bit is set the TTC timer is caught on the last bit of the End Of Frame. When this bit is clear the TTC timer is caught on the Start Of Frame. This bit is only used in the TTC mode.
3AUTOBAUD
2TEST
1ENA/STB
0GRES
Reset Value = 0000 0000b
AUTOBAUD
set to active listening mode. Clear to disable listening mode
Test mode. The test mode is intended for factory testing and not for customer use.
Enable/Standby CAN Controller
When this bit is set, it enables the CAN controller and its input clock. When this bit is clear, the on-going communication is terminated normally and the CAN controller state of the machine is frozen (the ENCH bit of each message object does not change). In the standby mode, the transmitter constantly provides a recessive level; the receiver is not activated and the input clock is stopped in the CAN controller. During the disable mode, the registers and the mailbox remain accessible. Note that two clock periods are needed to start the CAN controller state of the machine.
General Reset (Software Reset).
Auto-resetable bit. This reset command is ‘ORed’ with the hardware reset in order to reset the controller. After a reset, the controller is disabled.
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AT/T89C51CC02
Table 57. CANGSTA Register
CANGST A (S:AAh Read Only) CAN General Status Register
76543210
- OVFG - TBSY RBSY ENFG BOFF ERRP
Bit Number Bit Mnemonic Description
7-
6OVFG
5-
4TBSY
3RBSY
2ENFG
1BOFF
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Overload frame flag
This status bit is set by the hardware as long as the produced overload frame is sent. This flag does not generate an interrupt
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Transmitter busy
This status bit is set by the hardware as long as the CAN transmitter generates a frame (remote, data, overload or error frame) or an ack field. This bit is also active during an InterFrame Spacing if a frame must be sent. This flag does not generate an interrupt.
Receiver busy
This status bit is set by the hardware as long as the CAN receiver acquires or monitors a frame. This flag does not generate an interrupt.
Enable on-chip CAN controller flag
Because an enable/disable command is not effective immediately, this status bit gives the true state of a chosen mode. This flag does not generate an interrupt.
Bus off mode
See Figure 42
4126L–CAN–01/08
0 ERRP
Reset Value = x0x0 0000b
Error passive mode
See Figure 42
95
AT/T89C51CC02
Table 58. CANGIT Register
CANGIT (S:9Bh) CAN General Interrupt
76543210
CANIT - OVRTIM OVRBUF SERG CERG FERG AERG
Bit Number Bit Mnemonic Description
General interrupt flag
7CANIT
This status bit is the image of all the CAN controller interrupts sent to the interrupt controller. It can be used in the case of the polling method.
(1)
6-
5OVRTIM
4OVRBUF
3SERG
2CERG
1FERG
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Overrun CAN Timer
This status bit is set when the CAN timer switches 0xFFFF to 0x0000. If the bit ETIM in the IE1 register is set, an interrupt is generated. Clear this bit in order to reset the interrupt.
Overrun BU FFER
0 - no interrupt. 1 - IT turned on This bit is set when the buffer is full. bit resetable by user. See Figure 39.
Stuff Error General
Detection of more than five consecutive bits with the same polarity. This flag can generate an interrupt. resetable by user.
CRC Error General
The receiver performs a CRC check on each destuffed received message from the start of frame up to the data field. If this checking does not match with the destuffed CRC field, a CRC error is set. This flag can generate an interrupt. resetable by user.
Form Error General
The form error results from one or more violations of the fixed form in the following bit fields: CRC delimiter acknowledgment delimiter end_of_frame This flag can generate an interrupt. resetable by user.
96
0AERG
Note: 1. This field is Read Only.
Reset Value = 0x00 0000b
Acknowledgment Error G en e r a l
No detection of the dominant bit in the acknowledge slot. This flag can generate an interrupt. resetable by user.
4126L–CAN–01/08
AT/T89C51CC02
Table 59. CANTEC Register
CANTEC (S:9Ch Read Only) – CAN Transmit Error Counter
76543210
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
Bit Number Bit Mnemonic Description
7 - 0 TEC7:0
Transmit Error Counter See Figure 42
Reset Value = 00h
Table 60. CANREC Register CANREC (S:9Dh Read Only) – CAN Reception Error Counter
76543210
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
Bit Number Bit Mnemonic Description
7 - 0 REC7:0
Reception Error Counter
See Figure 42
Reset Value = 00h
4126L–CAN–01/08
97
AT/T89C51CC02
Table 61. CANGIE Register
CANGIE (S:C1h) – CAN
76543210
- - ENRX ENTX ENERCH ENBUF ENERG -
Bit Number Bit Mnemonic Description
Reserved
7 - 6 -
The values read from these bits are indeterminate. Do not set these bits.
5 ENRX
4ENTX
3 ENERCH
2 ENBUF
1 E NERG
0-
Reset Value = xx00 000xb
Enable Receive Interrupt
0 - Disable 1 - Enable
Enable Transmit Interrupt
0 - Disable 1 - Enable
Enable Message Object Error Interrupt
0 - Disable 1 - Enable
Enable BUF Interrupt
0 - Disable 1 - Enable
Enable General Error Interrupt
0 - Disable 1 - Enable
Reserved
The value read from this bit is indeterminate. Do not set this bit. See Figure 39.
98
4126L–CAN–01/08
AT/T89C51CC02
Table 62. CANEN Register
CANEN (S:CFh Read Only) CAN Enable Message Object Registers
76543210
----ENCH3 ENCH2 ENCH1 ENCH0
Bit Number Bit Mnemonic Description
Reserved
7 - 4 -
3 - 0 ENCH3:0
Reset Value = xxxx 0000b
Table 63. CANSIT Register CANSIT (S:BBh Read Only) – CAN Status Interrupt Message Object Registers
The values read from these bits are indeterminate. Do not set these bits.
Enable Message Object
0 - message object is disabled => the message object is free for a new emission or reception. 1 - message object is enabled. This bit is resetable by re-writing the CANCONCH of the corresponding message object.
76543210
----SIT3SIT2SIT1SIT0
Bit Number Bit Mnemonic Description
Reserved
7 - 4 -
3 - 0 SIT3:0
The values read from these bits are indeterminate. Do not set these bits.
Status of Interrupt by Message Object
0 - no interrupt. 1 - IT turned on. Reset when interrupt condition is cleared by user. SIT3:0 = 0b 0000 1001 -> IT’s on message objects 3 & 0. See Figure 39.
Reset Value = xxxx0000b
4126L–CAN–01/08
99
AT/T89C51CC02
Table 64. CANIE Register
CANIE (S:C3h) – CAN Enable Interrupt message object Registers
76543210
----IECH 3IECH 2IECH 1IECH 0
Bit Number Bit Mnemonic Description
Reserved
7 - 4 -
3 - 0 IECH3:0
The values read from these bits are indeterminate. Do not set these bits.
Enable Interrupt by Message Object
0 - disable IT. 1 - enable IT. IECH3:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2.
Reset Value = xxxx 0000b
Table 65. CANBT1 Register CANBT1 (S:B4h) – CAN bit Timing Registers 1
76543210
- BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 -
Bit Number Bit Mnemonic Description
7-
6 - 1 BRP5:0
0-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Prescaler The period of the CAN controller system clock Tscl is
programmable and determines the individual bit timing.
Tscl =
Reserved
The value read from this bit is indeterminate. Do not set this bit.
BRP[5..0] + 1
F
CAN
(1)
Note: 1. The CAN controller bi t tim ing r egi ste rs m us t be ac ce ss ed only if th e C AN con trol ler is
disabled with the ENA bit of the CANGCON register set to 0. See Figure 41.
No default value after reset.
100
4126L–CAN–01/08
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