ATMEL AT89C51AC2 User Manual

BDTIC www.bdtic.com/ATMEL

Features

80C51 Core Architecture
256 Bytes of On-chip RAM
1 KB of On-chip XRAM
32 KB of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
2 KB of On-chip Flash for Bootloader
2 KB of On-chip EEPROM
Read/Write Cycle: 100K
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)
Five Ports: 32 + 2 Digital I/O Lines
Five-channel 16-bit PCA with:
– PWM (8-bit) – High-speed Output – Timer and Edge Capture
Double Data Pointer
21-bit Watchdog Timer (7 Programmable Bits)
10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
On-chip Emulation Logic (Enhanced Hook System)
Power Saving Modes:
– Idle Mode – Power-down Mode
Power Supply: 3V to 5.5V
Temperature Range: Industrial (-40° to +85°C)
Packages: VQFP44, PLCC44
Enhanced 8-bit Microcontroller with 32 KB Flash Memory
AT89C51AC2 T89C51AC2

Description

The A/T89C51AC2 is a high performance Flash version of the 80C51 single chip 8-bit microcontrollers. It contains a 32 KB Flash memory block for program and data.
The 32 KB Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin.
The A/T89C51AC2 retains all features of the 80C51 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/cou nters. In addition, the A/T89C51AC2 has a 10-bit A/D converter, a 2 KB Boot Flash memory, 2 KB EEPROM for data, a Programmable Counter Array, an XRAM of 1024 bytes, a Hardware Watch­Dog Timer, and a more versatile se rial channel that facilitates multiprocessor communication (EUART). The fully static design of the A/T89C51AC2 reduces system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.
The A/T89C51AC2 has two software-selectable modes of reduced activity and an 8­bit clock prescaler for further reduction in power consumption. In the idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the Power-down mode the RAM is saved and all other functions are inoperative.
The added features of the A/T89C51AC2 make it more powerful for applications that need A/D conversion, pulse width modulation, high speed I/O and counting capabili­ties such as industrial control, consumer goods, alarms, motor control, among others. While remaining fully compatible with the 80C52, the T8C51AC2 offers a superset of this standard microcontroller. In X2 mode, a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
Rev. 4127H–8051–02/08
1
A/T89C51AC2

Block Diagram

Timer 0
INT
RAM
256x8
T0
T1
RxD
TxD
WR
RD
EA
PSEN
ALE
XTAL2
XTAL1
UART
CPU
Timer 1
INT1
Ctrl
INT0
C51
CORE
Port 0P0Port 1
Port 2
Port 3
Parallel I/O Ports and Ext. Bus
P1(1)
P2
P3
XRAM
1kx8
IB-bus
PCA
RESET
Watch
Dog
PCA
ECI
Vss
Vcc
Timer 2
T2EX
T2
Port 4
P4(2)
10 bit
ADC
Flash
32kx
8
Boot
loader
2kx8
EE
PROM
2kx8
VAREF
VAVCC
VAGND
Notes: 1. 8 analog Inputs/8 Digital I/O
2. 2-Bit I/O Port
2
4127H–8051–02/08

Pin Configuration

PLCC44
P1.3/AN3/CEX0
P1.2/AN2/ECI
P1.1/AN1/T2EX
P1.0/AN 0/T2
VAREF
VAGND
RESET
VSS
VCC
XTAL1
XTAL2
P3.7/RD
P4.0
P4.1
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P3.6/WR
39 38 37 36 35 34 33 32
29
30
31
7 8 9 10 11 12 13 14
17
16
15
1819202122232425262728
65432
4443424140
ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.1/AD1 P0.0/AD0 P2.0/A8
P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4
EA
P3.0/RxD
P3.1/TxD P3.2/INT0 P3.3/INT1
P3.4/T0 P3.5/T1
1
43 42 41 40 3944
38 37 36 35 34
12 13 17161514 201918 21 22
33 32
31
30
29
28
27
26 25
24
23
VQFP44
1
2
3
4
5
6
7
8
9
10
11
P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4
EA P3.0/RxD P3.1/TxD
P3.2/INT0 P3.3/INT1
P3.4/T0 P3.5/T1
ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5
P0.2 /AD2
P0.3 /AD3
P0.4 /AD4
P0.1 /AD1 P0.0 /AD0 P2.0/A8
P1.3/AN3/CEX0
P1.2/AN2/ECI
P1.1/AN1/T2EX
P1.0/AN 0/T2
VAREF
VAGND
RESET
VSS
VCC
XTAL1
XTAL2
P3.7/RD
P4.0
P4.1
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P3.6/WR
A/T89C51AC2
4127H–8051–02/08
3
A/T89C51AC2
Table 1. Pin Description
Pin Name Type Description
VSS GND Circuit ground
VCC Supply Voltage
VAREF Reference Voltage for ADC
VAGND Reference Ground for ADC
P0.0:7 I/O Port 0:
P1.0:7 I/O Port 1:
Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pull-ups when emitting 1’s. Port 0 also outputs the code Bytes during program validation. External pull-ups are required during program verification.
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register (in this case the internal pull-ups are disconnected). As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O.
P1.0/AN0/T2 Analog input channel 0, External clock input for Timer/counter2.
P1.1/AN1/T2EX Analog input channel 1, Trigger input for Timer/counter2.
P1.2/AN2/ECI Analog input channel 2, PCA external clock input.
P1.3/AN3/CEX0 Analog input channel 3, PCA module 0 Entry of input/PWM output.
P1.4/AN4/CEX1 Analog input channel 4, PCA module 1 Entry of input/PWM output.
P1.5/AN5/CEX2 Analog input channel 5, PCA module 2 Entry of input/PWM output.
P1.6/AN6/CEX3 Analog input channel 6, PCA module 3 Entry of input/PWM output.
P1.7/AN7/CEX4 Analog input channel 7, PCA module 4 Entry ot input/PWM output. Port 1 receives the low-order address byte during EPROM programming and program verification. It can drive CMOS inputs without external pull-ups.
P2.0:7 I/O Port 2:
4
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byte during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register. It also receives high-order addresses and control signals during program validation. It can drive CMOS inputs without external pull-ups.
4127H–8051–02/08
Table 1. Pin Description (Continued)
Pin Name Type Description
A/T89C51AC2
P3.0:7 I/O Port 3:
P4.0:1 I/O Port 4:
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:
P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface
P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface
P3.2/INT0: External interrupt 0 input/timer 0 gate control input
P3.3/INT1: External interrupt 1 input/timer 1 gate control input
P3.4/T0: Timer 0 counter input
P3.5/T1: Timer 1 counter input
P3.6/WR: External Data Memory write strobe; latches the data byte from port 0 into the external data memory
P3.7/RD: External Data Memory read strobe; Enables the external data memory. It can drive CMOS inputs without external pull-ups.
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up transistor. P4.0
P4.1: It can drive CMOS inputs without external pull-ups.
RESET I/O
ALE O
PSEN O
EA I
XTAL1 I
XTAL2 O
Reset:
A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC.
ALE:
An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are executed from an internal Flash (EA = 1), ALE generation can be disabled by the software.
PSEN:
The Program Store Enable output is a control signal that enables the external program memory of the bus during external fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when executing from of the external program memory two activations of PSEN are skipped during each access to the external Data memory. The PSEN is not activated for internal fetches.
EA:
When External Access is held at the high level, instructions are fetched from the internal Flash when the program counter is less then 8000H. When held at the low level,A/T89C51AC2 fetches all instructions from the external program memory
XTAL1:
Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained.
XTAL2:
Output from the inverting oscillator amplifier.
.
4127H–8051–02/08
5
A/T89C51AC2

I/O Configurations

D
CL
QP1.X
LATCH
INTERNAL
WRITE TO LATCH
READ PIN
READ LATCH
P1.x
P3.X P4.X
ALTERNATE OUTPUT FUNCTION
VCC
INTERNAL PULL-UP (1)
ALTERNATE INPUT FUNCTION
P3.x P4.x
BUS
Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instruc­ti ons a re referred to as R e a d-Modify-Wri t e instructions. Ea c h I/O l in e may b e independently programmed as input or output.

Port 1, Port 3 and Port 4

Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either for general-purpose I/O or for its alternate input output function.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg­ister (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive.
To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed further in the "quasi-Bidirectional Port Opera­tion" section.
Figure 1. Port 1, Port 3 and Port 4 Structure

Port 0 and Port 2

6
Note: The internal pull-up can be disabled on P1 when analog function is selected.
Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3 shows the structure of Port 2. An external source can pull a Port 2 pin low.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg­ister (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to turn off the output driver FET.
4127H–8051–02/08
A/T89C51AC2
D
Q
P0.X
LATCH
INTERNAL
WRITE TO LATCH
READ PIN
READ LATCH
0
1
P0.x (1)
ADDRESS LOW/ DATA
CONTROL
VDD
BUS
(2)
D
Q
P2.X
LATCH
INTERNAL
WRITE TO LATCH
READ PIN
READ LATCH
0
1
P2.x (1)
ADDRESS HIGH/
CONTROL
BUS
VDD
INTERNAL PULL-UP (2)
Figure 2. Port 0 Structure
Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as
address/data bus drivers.
2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.
Figure 3. Port 2 Structure
Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus
drivers.
2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle.
When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line.

Read-Modify-Write Instructions

4127H–8051–02/08
Some instructions read the latch data rather than the pin data. The latch based instruc­tions read the data, modify the data and then rewrite the latch. These are called "Read­Modify-Write" instructions. Below is a complete list of these special instructions (see Table ). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin:
7
A/T89C51AC2
Table 2. Read-Modify-Write Instructions
Instruction Description Example
ANL logical AND ANL P1, A
ORL logical OR ORL P2, A
XRL logical EX-OR XRL P3, A
JBC jump if bit = 1 and clear bit JBC P1.1, LABEL
CPL complement bit CPL P3.0
INC increment INC P2
DEC decrement DEC P2
DJNZ decrement and jump if not zero DJNZ P3, LABEL
MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C
CLR Px.y clear bit y of Port x CLR P2.4
SET Px.y set bit y of Port x SET P3.3
It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic-one value.

Quasi-Bidirectional Port Operation

Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Port 0 is a "true bidirectional" pin. The pins float when configured as input. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input conditions by a logical one written to the latch.
Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output
buffers (and therefore the pin state) update early in the instruction after Read-Modify­Write instruction cycle.
Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull­up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull­ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch con­vention. Current strengths are 1/10 that of pFET #3.
8
4127H–8051–02/08
A/T89C51AC2
READ PIN
INPUT DATA
P1.x
OUTPUT DATA
2 Osc. PERIODS
n
p1(1)
p2
p3
VCCVCCVCC
P2.x P3.x P4.x
Figure 4. Internal Pull-Up Configurations
Note: Port 2 p1 assists the logic-one output for memory bus cycles.
4127H–8051–02/08
9
A/T89C51AC2

SFR Mapping

The Special Function Registers (SFRs) of the A/T89C51AC2 fall into the following categories:
Table 3. C51 Core SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
ACC E0h Accumulator
B F0h B Register
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stack Pointer
Data Pointer Low
DPL 82h
DPH 83h
byte
LSB of DPTR
Data Pointer High byte
MSB of DPTR
Table 4. I/O Port SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
P0 80h Port 0
P1 90h Port 1
P2 A0h Port 2
P3 B0h Port 3
P4 C0h Port 4 (x2)
Table 5. Timers SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
TH0 8Ch
TL0 8Ah
TH1 8Dh
TL1 8Bh
TH2 CDh
TL2 CCh
Timer/Counter 0 High byte
Timer/Counter 0 Low byte
Timer/Counter 1 High byte
Timer/Counter 1 Low byte
Timer/Counter 2 High byte
Timer/Counter 2 Low byte
TCON 88h
TMOD 89h
10
Timer/Counter 0 and 1 control
Timer/Counter 0 and 1 Modes
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
4127H–8051–02/08
A/T89C51AC2
Table 5. Timers SFRs (Continued)
Mnemonic Add Name 7 6 5 4 3 2 1 0
T2CON C8h
T2MOD C9h
RCAP2H CBh
RCAP2L CAh
WDTRST A6h
WDTPRG A7h
Timer/Counter 2 control
Timer/Counter 2 Mode
Timer/Counter 2 Reload/Capture High byte
Timer/Counter 2 Reload/Capture Low byte
Watchdog Timer Reset
Watchdog Timer Program
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2OE DCEN
S2 S1 S0
Table 6. Serial I/O Port SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADEN B9h Slave Address Mask
SADDR A9h Slave Address
Table 7. PCA SFRs
Mnemonic
CCON D8h PCA Timer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA Timer/Counter Mode CIDL WDTE CPS1 CPS0 ECF
CL E9h PCA Timer/Counter Low byte
CH F9h PCA Timer/Counter High byte
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
Add Name 7 6 5 4 3 2 1 0
DAh
PCA Timer/Counter Mode 0
DBh
PCA Timer/Counter Mode 1
DCh
PCA Timer/Counter Mode 2
DDh
PCA Timer/Counter Mode 3
DEh
PCA Timer/Counter Mode 4
FAh
PCA Compare Capture Module 0 H
FBh
PCA Compare Capture Module 1 H
FCh
PCA Compare Capture Module 2 H
FDh
PCA Compare Capture Module 3 H
FEh
PCA Compare Capture Module 4 H
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
MAT0
MAT1
MAT2
MAT3
MAT4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
TOG0
TOG1
TOG2
TOG3
TOG4
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
PWM0
PWM1
PWM2
PWM3
PWM4
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
4127H–8051–02/08
11
A/T89C51AC2
Table 7. PCA SFRs (Continued)
Mnemonic
Add Name 7 6 5 4 3 2 1 0
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
PCA Compare Capture Module 0 L
EBh
PCA Compare Capture Module 1 L
ECh
PCA Compare Capture Module 2 L
EDh
PCA Compare Capture Module 3 L
EEh
PCA Compare Capture Module 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
Table 8. Interrupt SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
IEN0 A8h
IEN1 E8h
IPL0 B8h
IPH0 B7h
IPL1 F8h
IPH1 F7h
Interrupt Enable Control 0
Interrupt Enable Control 1
Interrupt Priority Control Low 0
Interrupt Priority Control High 0
Interrupt Priority Control Low 1
Interrupt Priority Control High1
EA EC ET2 ES ET1 EX1 ET0 EX0
EADC
PPC PT2 PS PT1 PX1 PT0 PX0
PPCH PT2H PSH PT1H PX1H PT0H PX0H
PADCL
PADCH
Table 9. ADC SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
ADCON F3h ADC Control PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0
ADCF F6h ADC Configuration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
ADCLK F2h ADC Clock PRS4 PRS3 PRS2 PRS1 PRS0
ADDH F5h ADC Data High byte ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2
ADDL F4h ADC Data Low byte ADAT1 ADAT0
Table 10. Other SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
PCON 87h Power Control SMOD1 SMOD0 POF GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 M0 XRS1 XRS2 EXTRAM A0
AUXR1 A2h Auxiliary Register 1 ENBOOT GF3 0 DPS
CKCON 8Fh Clock Control WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY
EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 EEE EEBUSY
12
4127H–8051–02/08
Table 11. SFR Mapping
(1)
0/8
A/T89C51AC2
1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
IPL1
xxxx xx0x
B
0000 0000
IEN1
xxxx xx0x
ACC
0000 0000
CCON
00x0 0000
PSW
0000 0000
T2CON
0000 0000
P4
xxxx xx11
IPL0
x000 0000
P3
1111 1111
IEN0
0000 0000
CH
0000 0000
CL
0000 0000
CMOD
00xx x000
FCON
0000 0000
T2MOD
xxxx xx00
SADEN
0000 0000
SADDR
0000 0000
CCAP0H
0000 0000
ADCLK
xxx0 0000
CCAP0L
0000 0000
CCAPM0
x000 0000
EECON
xxxx xx00
RCAP2L
0000 0000
CCAP1H
0000 0000
ADCON
x000 0000
CCAP1L
0000 0000
CCAPM1
x000 0000
RCAP2H
0000 0000
CCAP2H
0000 0000
ADDL
0000 0000
CCAP2L
0000 0000
CCAPM2
x000 0000
TL2
0000 0000
CCAP3H
0000 0000
ADDH
0000 0000
CCAP3L
0000 0000
CCAPM3
x000 0000
TH2
0000 0000
CCAP4H
0000 0000
ADCF
0000 0000
CCAP4L
0000 0000
CCAPM4
x000 0000
IPH1
xxxx xx0x
IPH0
x000 0000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A0h
98h
90h
88h
80h
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
(1)
0/8
SBUF
0000 0000
TMOD
0000 0000
SP
0000 0111
1/9 2/A 3/B 4/C 5/D 6/E 7/F
AUXR1
xxxx 00x0
TL0
0000 0000
DPL
0000 0000
Reserved
Note: 1. These registers are bit–addressable.
Sixteen addresses in the SFR space are both byte–addressable and bit–addressable. The bit–addressable SFR’s are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.
TL1
0000 0000
DPH
0000 0000
TH0
0000 0000
TH1
0000 0000
WDTRST 1111 1111
AUXR
x00x 1100
WDTPRG xxxx x000
CKCON
0000 0000
PCON
00x1 0000
A7h
9Fh
97h
8Fh
87h
4127H–8051–02/08
13
A/T89C51AC2

Clock

The A/T89C51AC2 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages:
Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.
Saves power consumption while keeping the same CPU power (oscillator power saving).
Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.
Increases CPU power by 2 while keeping the same crystal frequency.
In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software.
An extra feature is available to start after Reset in the X2 mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section "In-System-Programming".

Description

The X2 bit in the CKCON register (see Table 12) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode).
Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure
5.).
The Timers 0, 1 and 2, Uart, PCA, or Watchdog switch in X2 mode only if the corre­sponding bit is cleared in the CKCON register.
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2 bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 6 shows the mode switching waveforms.
14
4127H–8051–02/08
Figure 5. Clock CPU Generation Diagram
XTAL1
XTAL2
PD
PCON.1
CPU Core
1
0
÷
2
PERIPH
CLOCK
Clock
Peripheral Clock Symbol
CPU
CLOCK
CPU Core Clock Symbol
X2
CKCON.0
X2B
Hardware byte
WDX2
CKCON.6
PCAX2
CKCON.5
SIX2
CKCON.4
T2X2
CKCON.3
T1X2
CKCON.2
T0X2
CKCON.1
IDL
PCON.0
1
0
÷
2
1
0
÷
2
1
0
÷
2
1
0
÷
2
1
0
÷
2
1
0
÷
2
X2
CKCON.0
FWd Clock
FPca Clock
FUart Clock
FT2 Clock
FT1 Clock
FT0 Clock
and ADC
On RESET
A/T89C51AC2
4127H–8051–02/08
15
A/T89C51AC2
Figure 6. Mode Switching Waveforms
XTAL1/2
XTAL1
CPU clock
X2 bit
X2 ModeSTD Mode STD Mode
Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the
clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.
16
4127H–8051–02/08
A/T89C51AC2

Register

Table 12. CKCON Register
CKCON (S:8Fh) Clock Control Register
7 6 5 4 3 2 1 0
- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number
- -
6 WDX2
5 PCAX2
4 SIX2
3 T2X2
2 T1X2
1 T0X2
Bit
Mnemonic Description
Reserved
Do not set this bit.
Watchdog clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (MODE 0 and 2)
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Timer 2 clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Timer 1 clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Timer 0 clock
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
(1)
(1)
(1)
(1)
(1)
(1)
CPU clock
0 X2
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits.
Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
has no effect.
Reset Value = x000 0000b
4127H–8051–02/08
17
A/T89C51AC2

Power Management

0
VDD
Rrst
Crst
RST pin
Internal reset
Reset input circuitry
Two power reduction modes are implemented in the A/T89C51AC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynami­cally divided by 2 using the X2 Mode detailed in Section “Clock”.

Reset Pin

At Power-up (Cold Reset)

In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of the internal registers like SFRs, PC, etc. and to unpredictable behavior of the microcon­troller. A warm reset can be applied either directly on the RST pin or indirectly by an internal reset source such as a watchdog, PCA, timer, etc.
Two conditions are required before enabling a CPU start-up:
VDD must reach the specified VDD range,
The level on xtal1 input must be outside the specification (VIH, VIL).
If one of these two conditions are not met, the microcontroller does not start correctly and can execute an instruction fetch from anywhere in the program space. An active level applied on the RST pin must be maintained until both of the above conditions are met. A reset is active when the level VIH1 is reached and when the pulse width covers the period of time where VDD and the oscillator are not stabilized. Two parameters have to be taken into account to determine the reset pulse width:
VDD rise time (vddrst),
Oscillator startup time (oscrst).
To determine the capacitor the highest value of these two parameters has to be chosen. The reset circuitry is shown in Figure 7.
Figure 7. Reset Circuitry
18
Table 13 and Table 15 give some typical examples for three values of VDD rise times, two values of oscillator start-up time and two pull-down resistor values.
Table 13. Minimum Reset Capacitor for a 15k Pull-down Resistor
oscrst/vddrst 1ms 10ms 100ms
5 ms 2.7 µF 4.7 µF 47 µF
20 ms 10 µF 15 µF 47 µF
Note: These values assume VDD starts from 0v to the nominal value. If the time between two
on/off sequences is too fast, the power-supply de coupling capacitors may not be fully discharged, leading to a bad reset sequence.
4127H–8051–02/08
A/T89C51AC2
R
RST
RST
VSS
To CPU core and peripherals
VDD
+
VSS
VDD
RST
1K
To other on-board
circuitry
Warm Reset To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock periods is mode independent (X2 or X1).
Watchdog Reset As detailed in Section “PCA Watchdog Timer”, page 80, the WDT generates a 96-clock
period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1K resis­tor must be added as shown Figure 8.
Figure 8. Reset Circuitry for WDT reset out usage

Reset Recommendation to Prevent Flash Corruption

An example of bad initialization situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program Counter is accidently in the range of the boot memory addresses then a flash access (write or erase) may corrupt the Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to prevent system malfunction during periods of insufficient power supply voltage (power supply failure, power supply switched off).

Idle Mode

Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 14.
Entering Idle Mode To enter Idle mode, you must set the IDL bit in PCON register (see Table 15). The
T89C51CC02 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed.
Note: If IDL bit and PD bit are set simultaneously, the T89C51CC02 enters Power-down mode.
Then it does not go in Idle mode when exiting Power-down mode.
Exiting Idle Mode There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
4127H–8051–02/08
Hardware clears IDL bit in PCON register which restores the clock to the
CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode.
19
A/T89C51AC2
The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0.
2. Generate a reset.
A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C51CC02 and vectors the CPU to address C:0000h.
Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM.
2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle.

Power-down Mode

The Power-down mode places the T89C51CC02 in a very low power state. Power-down mode stops the oscillator and freezes all clocks at known states. The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 14.
Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The T89C51CC02 enters the
Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed.
Exiting Power-down Mode If VDD was reduced during the Power-down mode, do not exit Power-down mode until
VDD is restored to the normal operating level.
There are two ways to exit the Power-down mode:
1. Generate an enabled external interrupt.
The T89C51CC02 provides capability to exit from Power-down using INT0#,
INT1#. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTx# input, execution resumes when the input is released (see Figure 9) while using KINx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see Figure 8). Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-down mode.
20
Note: 1. The external interrupt used to exit Power-down mode must be configured as level
sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted.
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.
4127H–8051–02/08
Figure 9. Power-down Exit Waveform Using INT1:0#
INT1:0#
OSC
Power-down phase Oscillator restart phase Active phaseActive phase
2. Generate a reset.
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C51CC02 and vectors the CPU to address 0000h.
Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated the Power-down mode should not write to a Port pin or to the external RAM.
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM content.
A/T89C51AC2
Table 14. Pin Conditions in Special Operating Modes
Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PSEN#
Reset Floating High High High High High High
Idle
(internal
code)
Idle
(external
code)
Power-
Down(inter
nal code)
Power-
Down
(external
code)
Data Data Data Data Data High High
Floating Data Data Data Data High High
Data Data Data Data Data Low Low
Floating Data Data Data Data Low Low
4127H–8051–02/08
21
A/T89C51AC2

Registers

Table 15. PCON Register
PCON (S:87h) – Power configuration Register
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
7 SMOD1
6 SMOD0
5 -
4 POF
3 GF1
2 GF0
1 PD
Bit
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3
Serial port Mode bit 0
Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Clear to recognize next reset type. Set by hardware when Vcc rises from 0 to its nominal voltage. Can also be set by software.
General-purpose flag 1
One use is to indicate whether an interrupt occurred during normal operation or during Idle mode.
General-purpose flag 0
One use is to indicate whether an interrupt occurred during normal operation or during Idle mode.
Power-down Mode bit
Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence.
Idle Mode bit
0 IDL
Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.
Reset Value = 00X1 0000b
22
4127H–8051–02/08
A/T89C51AC2
Upper
128 Bytes
Internal RAM
Lower
128 Bytes
Internal RAM
Special
Function
Registers
80h
80h
00h
FFh
FFh
direct addressing
addressing
7Fh
direct or indirect
indirect addressing
256 up to 1024 Bytes
00h
64 KB
External XRAM
0000h
FFFFh
Internal XRAM
EXTRAM = 0
EXTRAM = 1
FFh or 3FFh
Internal
External

Data Memory

The A/T89C51AC2 provides data memory access in two different spaces:
1. The internal space mapped in three separate segments:
the lower 128 Bytes RAM segment.
the upper 128 Bytes RAM segment.
the expanded 1024 Bytes RAM segment (XRAM).
2. The external space.
A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode.
Figure 11 shows the internal and external data memory spaces organization.
Figure 10. Internal Memory - RAM
Figure 11. Internal and External Data Memory Organization XRAM-XRAM
4127H–8051–02/08
23
A/T89C51AC2

Internal Space

Bit-Addressable Space
4 Banks of 8 Registers R0-R7
30h
7Fh
(Bit Addresses 0-7Fh)
20h
2Fh
18h
1Fh
10h
17h
08h
0Fh
00h
07h
Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 11) are accessible from address 00h to 7Fh
using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 18) select which bank is in use according to Table 16. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct address­ing, and can be used for context switching in interrupt service routines.
Table 16. Register Bank Selection
RS1 RS0 Description
0 0 Register bank 0 from 00h to 07h
0 1 Register bank 0 from 08h to 0Fh
1 0 Register bank 0 from 10h to 17h
1 1 Register bank 0 from 18h to 1Fh
The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh.
Figure 12. Lower 128 Bytes Internal RAM Organization
Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
Expanded RAM The on-chip 1024 Bytes of expanded RAM (XRAM) are accessible from address 0000h
24
addressing mode.
to 03FFh using indirect addressing mode through MOVX instructions. In this address range, the bit EXTRAM in AUXR register is used to select the XRAM (default) or the XRAM. As shown in Figure 11 when EXTRAM = 0, the XRAM is selected and when EXTRAM = 1, the XRAM is selected.
The size of XRAM can be configured by XRS1-0 bit in AUXR register (default size is 1024 Bytes).
Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile
memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.
4127H–8051–02/08
A/T89C51AC2
RAM
PERIPHERAL
A/T89C51AC2
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
WR
OERD
WR
Latch

External Space

Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (RD, WR, and ALE).
Figure 13 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 17 describes the external memory interface signals.
Figure 13. External Data Memory Interface Structure
Table 17. External Data Memory Interface Signals
Signal
Name Type Description
A15:8 O
AD7:0 I/O
ALE O
RD O
WR O
Address Lines
Upper address lines for the external bus.
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE signals indicates that valid address information are available on lines AD7:0.
Read
Read signal output to external data memory.
Write
Write signal output to external memory.
Alternative
Function
P2.7:0
P0.7:0
-
P3.7
P3.6
External Bus Cycles This section descri bes the bus cycles the A/T89C51AC2 executes to read (see
Figure 14), and write data (see Figure 15) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor­mation on X2 mode.
Slow peripherals can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR signals from 3 to 15 CPU clock periods.
4127H–8051–02/08
For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycle timing parameters refer to the Section “AC Characteristics”.
25
A/T89C51AC2
Figure 14. External Data Read Waveforms
ALE
P0
P2
RD 1
DPL or Ri D7:0
DPH or P22
P2
CPU Clock
ALE
P0
P2
WR
1
DPL or Ri D7:0
P2
CPU Clock
DPH or P22
Notes: 1.
RD
signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
Figure 15. External Data Write Waveforms
Notes: 1.WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
26
4127H–8051–02/08
A/T89C51AC2
0
1
DPH0
DPH1
DPL0
0
1
DPS
AUXR1.0
DPH
DPL
DPL1
DPTR
DPTR0
DPTR1

Dual Data Pointer

Description The A/T89C51AC2 implements a second data pointer for speeding up code execution
and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 20) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 16).
Figure 16. Dual Data Pointer Implementation
Application Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare…) are well served by using one data pointer as a “source” pointer and the other one as a “destination” pointer. Hereafter is an example of block move implementation using the two pointers and coded in assembler. The latest C compiler takes also advantage of this feature by providing enhanced algorithm libraries.
The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence mat­ters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.
; ASCII block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; Ends when encountering NULL character ; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is added
AUXR1EQU0A2h
move:movDPTR,#SOURCE ; address of SOURCE
incAUXR1 ; switch data pointers movDPTR,#DEST ; address of DEST
mv_loop:incAUXR1; switch data pointers
movxA,@DPTR; get a byte from SOURCE incDPTR; increment SOURCE address incAUXR1; switch data pointers movx@DPTR,A; write the byte to DEST incDPTR; increment DEST address
4127H–8051–02/08
jnzmv_loop; check for NULL terminator
end_move:
27
A/T89C51AC2

Registers

Table 18. PSW Register
PSW (S:D0h) Program Status Word Register
7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV F1 P
Bit
Number
7 CY
6 AC
5 F0
4-3 RS1:0
2 OV
1 F1
0 P
Bit
Mnemonic Description
Carry Flag
Carry out from bit 1 of ALU operands.
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
User Definable Flag 0.
Register Bank Select Bits
Refer to Table 16 for bits description.
Overflow Flag
Overflow set by arithmetic operations.
User Definable Flag 1
Parity Bit
Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.
Reset Value = 0000 0000b
Table 19. AUXR Register
AUXR (S:8Eh) Auxiliary Register
28
7 6 5 4 3 2 1 0
- - M0 - XRS1 XRS0 EXTRAM A0
Bit
Number
7-6 -
5 M0
4 -
3-2 XRS1-0
Bit
Mnemonic Description
Reserved
The value read from these bits are indeterminate. Do not set this bit.
Stretch MOVX control:
the RD/ and the WR/ pulse length is increased according to the value of M0.
M0 Pulse length in clock period
0 6 1 30
Reserved
The value read from this bit is indeterminate. Do not set this bit.
XRAM size:
Accessible size of the XRAM
XRS 1:0 XRAM size
0 0 256 Bytes 0 1 512 Bytes 1 0 768 Bytes 1 1 1024 Bytes (default)
4127H–8051–02/08
A/T89C51AC2
Bit
Number
1 EXTRAM
0 A0
Bit
Mnemonic Description
Internal/External RAM (00h - FFh)
access using MOVX @ Ri/@ DPTR 0 - Internal XRAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access.
Disable/Enable ALE)
0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) 1 - ALE is active only during a MOVX or MOVC instruction.
Reset Value = X00X 1100b Not bit addressable
Table 20. AUXR1 Register
AUXR1 (S:A2h) Auxiliary Control Register 1
7 6 5 4 3 2 1 0
- - ENBOOT - GF3 0 - DPS
Bit
Number
7-6 -
Bit
Mnemonic Description
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Enable Boot Flash
5 ENBOOT
4 -
3 GF3
2 0
1 -
0 DPS
(1)
Set this bit for map the boot Flash between F800h -FFFFh Clear this bit for disable boot Flash.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
General-purpose Flag 3
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag.
Reserved for Data Pointer Extension.
Data Pointer Select Bit
Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.
Reset Value = XXXX 00X0b
Note: 1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming
section.
4127H–8051–02/08
29
A/T89C51AC2

EEPROM Data Memory

The 2 KB on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction.
A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming).
The number of data written on the page may vary from 1 up to 128 Bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row.

Write Data in the Column Latches

Programming

Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed.
The following procedure is used to write to the column latches:
Save and disable interrupt.
Set bit EEE of EECON register
Load DPTR with the address to write
Store A register with the data to be written
Execute a MOVX @DPTR, A
If needed loop the three last instructions until the end of a 128 Bytes page
Restore interrupt.
Note: The last page address used when loading the column latch is the one used to select the
page programming address.
The EEPROM programming consists of the following actions:
writing one or more Bytes of one page in the column latches. Normally, all Bytes must belong to the same page; if not, the last page address will be latched and the others discarded.
launching programming by writing the control sequence (50h followed by A0h) to the EECON register.
EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading.
The end of programming is indicated by a hardware clear of the EEBUSY flag.
Note: The sequence 5xh and Axh must be executed without instructions between then other-
wise the programming is aborted.

Read Data

30
The following procedure is used to read the data stored in the EEPROM memory:
Save and disable interrupt
Set bit EEE of EECON register
Load DPTR with the address to read
Execute a MOVX A, @DPTR
Restore interrupt
4127H–8051–02/08
A/T89C51AC2

Examples

;*F*************************************************************************
;* NAME: api_rd_eeprom_byte
;* DPTR contain address to read.
;* Acc contain the reading value
;* NOTE: before execute this function, be sure the EEPROM is not BUSY
;***************************************************************************
api_rd_eeprom_byte:
; Save and clear EA
MOV EECON, #02h; map EEPROM in XRAM space
MOVX A, @DPTR
MOV EECON, #00h; unmap EEPROM
; Restore EA
ret
;*F*************************************************************************
;* NAME: api_ld_eeprom_cl
;* DPTR contain address to load
;* Acc contain value to load
;* NOTE: in this example we load only 1 byte, but it is possible upto
;* 128 Bytes.
;* before execute this function, be sure the EEPROM is not BUSY
;***************************************************************************
api_ld_eeprom_cl:
; Save and clear EA
MOV EECON, #02h ; map EEPROM in XRAM space
MOVX @DPTR, A
MOVEECON, #00h; unmap EEPROM
; Restore EA
ret
4127H–8051–02/08
;*F*************************************************************************
;* NAME: api_wr_eeprom
;* NOTE: before execute this function, be sure the EEPROM is not BUSY
;***************************************************************************
api_wr_eeprom:
; Save and clear EA
MOV EECON, #050h
MOV EECON, #0A0h
; Restore EA
ret
31
A/T89C51AC2

Registers

Table 21. EECON Register
EECON (S:0D2h) EEPROM Control Register
7 6 5 4 3 2 1 0
EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY
Bit
Bit Number
Mnemonic Description
7-4 EEPL3-0
3 -
2 -
1 EEE
0 EEBUSY
Programming Launch command bits
Write 5Xh followed by AXh to EEPL to launch the programming.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable EEPROM Space bit
Set to map the EEPROM space during MOVX instructions (Write in the column latches) Clear to map the XRAM space during MOVX.
Programming Busy flag
Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.
Reset Value = XXXX XX00b Not bit addressable
32
4127H–8051–02/08
A/T89C51AC2
0000h
32 KB
7FFFh
internal
0000h
7FFFh
FFFFh
8000h
Flash
32 KB
external memory
32 KB
external memory
EA = 0
EA = 1

Program/Code Memory

The A/T89C51AC2 implement 32 KB of on-chip program/code memory. Figure 17 shows the partitioning of internal and external program/code memory spaces depending on the product.
The Flash memory increases EPROM and ROM functionality by in-circuit electrical era­sure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD volt­age. Thus, the Flash Memory can be programmed using only one voltage and allows In­System-Programming commonly known as ISP. Hardware programming mode is also available using specific programming tool.
Figure 17. Program/Code Memory Organization
Notes: 1. If the program executes exclusively from on-chip code memory (not from external
memory), beware of executing code from the upper byte of on-chip memory (7FFFh) and thereby disrupt I/O Ports 0 and 2 due to external prefetch. Fetching code con­stant from this location does not affect Ports 0 and 2.
2. Default factory programmed parts come with maximum hardware protection. Execu­tion from external memory is not possible unless the Hardware Security Byte is reprogrammed. See Table 26.
4127H–8051–02/08
33
A/T89C51AC2

External Code Memory Access

Flash
EPROM
A/T89C51AC2
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
Latch
OEPSEN#
Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (PSEN#, and ALE).
Figure 18 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 18 describes the external memory interface signals.
Figure 18. External Code Memory Interface Structure
Table 22. External Code Memory Interface Signals
Signal
Name Type Description
Alternate Function
A15:8 O
AD7:0 I/O
ALE O
PSEN# O
Address Lines
Upper address lines for the external bus.
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE signals indicates that valid address information are available on lines AD7:0.
Program Store Enable Output
This signal is active low during external code fetch or external code read (MOVC instruction).
P2.7:0
P0.7:0
-
-
External Bus Cycles This section describes the bus cycles the A/T89C51AC2 executes to fetch code (see
Figure 19) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor­mation on X2 mode see section “Clock “.
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information.
For bus cycling parameters refer to the ‘AC-DC parameters’ section.
34
4127H–8051–02/08
Figure 19. External Code Fetch Waveforms
ALE
P0
P2
PSEN#
PCL
PCHPCH
PCLD7:0 D7:0
PCH
D7:0
CPU Clock
7FFFh
32 KB
Flash memory
FM0
0000h
Hardware Security (1 byte)
Column Latches (128 Bytes)
user space
Extra Row (128 Bytes)
2 KB
Flash memory
FM1
boot space
FFFFh
F800h
FM1 mapped between F800h and FFFFh when bit ENBOOT is set in AUXR1 register
A/T89C51AC2

Flash Memory Architecture

A/T89C51AC2 features two on-chip Flash memories:
Flash memory FM0:
Flash memory FM1:
The FM0 can be program by both parallel programming and Serial In-System-Program­ming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the "In-System-Programming" section.
All Read/Write access operations on Flash Memory by user application are managed by a set of API described in the "In-System-Programming" section.
Figure 20. Flash Memory Architecture
containing 32 KB of program memory (user space) organized into 128 byte pages,
2 KB for boot loader and Application Programming Interfaces (API).
4127H–8051–02/08
35
A/T89C51AC2
FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 20):
The memory array (user space) 32 KB
The Extra Row
The Hardware security bits
The column latch registers
User Space This space is composed of a 32 KB Flash memory organized in 256 pages of 128 Bytes.
It contains the user’s application code.
Extra Row (XRow) This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain infor-
mation for boot loader usage.
Hardware Security Byte The Hardware security Byte space is a part of FM0 and has a size of 1 byte.
The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode.
Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes).
The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte).
Cross Flash Memory Access Description
The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from external memory is impossible.
The FM1 memory can be program only by parallel programming.
The Table 23 show all software Flash access allowed.
Table 23. Cross Flash Memory Access
(user Flash)
(boot Flash)
Code executing from
FM0
FM1
External memory
EA = 0
FM0
Action
Read ok -
Load column latch ok -
Write - -
Read ok ok
Load column latch ok -
Write ok -
Read - -
Load column latch - -
Write - -
(user Flash)
FM1
(boot Flash)
36
4127H–8051–02/08
A/T89C51AC2

Overview of FM0 Operations

The CPU interfaces to the Flash memory through the FCON register and AUXR1 register.
These registers are used to:
Map the memory spaces in the adressable space
Launch the programming of the memory spaces
Get the status of the Flash memory (busy/not busy)
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.
The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor­dance with Table 24. A MOVC instruction is then used for reading these spaces.
Table 24. FM0 Blocks Select Bits
FMOD1 FMOD0 FM0 Adressable space
0 0 User (0000h-7FFFh)
0 1 Extra Row(FF80h-FFFFh)
1 0 Hardware Security Byte (0000h)
1 1 Reserved
Launching Programming FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5xh followed by Axh. Table 25 summarizes the memory spaces to program according to FMOD1:0 bits.
4127H–8051–02/08
37
A/T89C51AC2
Table 25. Programming Spaces
Write to FCON
5 X 0 0 No action
OperationFPL3:0 FPS FMOD1 FMOD0
User
Extra Row
Hardware
Security
Byte
Reserved
Notes: 1. The sequence 5xh and Axh must be executing without instructions between them
2. Interrupts that may occur during programming time must be disabled to avoid any
A X 0 0
5 X 0 1 No action
A X 0 1
5 X 1 0 No action
A X 1 0 Write the fuse bits space
5 X 1 1 No action
A X 1 1 No action
otherwise the programming is aborted.
spurious exit of the programming mode.
Write the column latches in user space
Write the column latches in extra row space
Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.
Loading the Column Latches Any number of data from 1 Byte to 128 Bytes can be loaded in the column latches. This
provides the capability to program the whole memory by byte, by page or by any number of Bytes in a page. When programming is launched, an automatic erase of the locations loaded in the col­umn latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page.
38
The following procedure is used to load the column latches and is summarized in Figure 21:
Save then disable interrupt and map the column latch space by setting FPS bit.
Load the DPTR with the address to load.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
If needed loop the three last instructions until the page is completely loaded.
Unmap the column latch and Restore Interrupt
4127H–8051–02/08
Figure 21. Column Latches Loading Procedure
Column Latches
Loading
Data Load
DPTR = Address
ACC = Data
Exec: MOVX @DPTR, A
Last Byte
to load?
Column Latches Mapping
FCON = 08h (FPS=1)
Data memory Mapping
FCON = 00h (FPS = 0)
Save and Disable IT
EA = 0
Restore IT
A/T89C51AC2
Note: The last page address used when loading the column latch is the one used to select the
page programming address.
Programming the Flash Spaces
User The following procedure is used to program the User space and is summarized in
Figure 22:
Load up to one page of data in the column latches from address 0000h to 7FFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 50h followed by A0h in FCON register (only from FM1). The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
Extra Row The following procedure is used to program the Extra Row space and is summarized in
Figure 22:
Load data in the column latches from address FF80h to FFFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 52h followed by A2h in FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBUSY flag cleared. The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
4127H–8051–02/08
39
A/T89C51AC2
Figure 22. Flash and Extra Row Programming Procedure
Flash Spaces
Programming
Save and Disable IT
EA = 0
Launch Programming
FCON = 5xh FCON = Axh
End Programming
Restore IT
Column Latches Loading
see Figure 21
FBusy
Cleared?
Clear Mode
FCON = 00h
Hardware Security Byte The following procedure is used to program the Hardware
summarized in Figure 23:
Set FPS and map Hardware byte (FCON = 0x0C)
Save and disable the interrupts.
Load DPTR at address 0000h.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
Launch the programming by writing the data sequence 54h followed by A4h in FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBUSY flag cleared. The end of the programming indicated by the FBusy flag cleared.
Restore the interrupts.
Security
Byte space and is
40
4127H–8051–02/08
Figure 23. Hardware Programming Procedure
Flash Spaces
Programming
Save and Disable IT
EA = 0
Launch Programming
FCON = 54h
FCON = A4h
End Programming
RestoreIT
FBusy
Cleared?
Clear Mode
FCON = 00h
Data Load
DPTR = 00h
ACC = Data
Exec: MOVX @DPTR, A
FCON = 0Ch
Save and Disable IT
EA = 0
End Loading
Restore IT
A/T89C51AC2
Reading the Flash Spaces
User The following procedure is used to read the User space:
Read one byte in Accumulator by executing MOVC A,@A+DPTR where A+DPTR is the address of the code byte to read.
Note: FCON is supposed to be reset when not needed.
Extra Row The following procedure is used to read the Extra Row space and is summarized in
Hardware Security Byte The following procedure is used to read the Hardware
Figure 24:
Map the Extra Row space by writing 02h in FCON register.
Read one byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and DPTR = FF80h to FFFFh.
Clear FCON to unmap the Extra Row.
in Figure 24:
Security
space and is summarized
Map the Hardware Security space by writing 04h in FCON register.
Read the byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and DPTR = 0000h.
Clear FCON to unmap the Hardware Security Byte.
4127H–8051–02/08
41
A/T89C51AC2
Figure 24. Reading Procedure
Flash Spaces Reading
Flash Spaces Mapping
FCON = 0000aa0b
(1)
Data Read
DPTR = Address
ACC = 0
Exec: MOVC A, @A+DPTR
Clear Mode
FCON = 00h
Note: 1. aa = 10 for the Hardware Security Byte.
Flash Protection from Parallel Programming
The three lock bits in Hardware Security Byte (see "In-System-Programming" section) are programmed according to Table 26 provide different level of protection for the on­chip code and data located in FM0 and FM1.
The only way to write these bits are the parallel mode. They are set by default to level 4
Table 26. Program Lock bit
Program Lock Bits
Security
Level
1 U U U
2 P U U
3 U P U
4 U U P
LB0 LB1 LB2
Protection Description
No program lock features enabled. MOVC instruction executed from external program memory returns non coded data.
MOVC instructions executed from external program memory are barred to return code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled.
Same as 2, also verify through parallel programming interface is disabled.
Same as 3, also external execution is disabled if code roll over beyond 7FFFh
Program Lock bits
U: unprogrammed
Preventing Flash Corruption See the “Power Management” section.
42
P: programmed
WARNING: Security level 2 and 3 should only be programmed after Flash and Core verification.
4127H–8051–02/08
A/T89C51AC2

Registers

FCON RegisterFCON (S:D1h)
Flash Control Register
7 6 5 4 3 2 1 0
FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY
Bit
Number
7-4 FPL3:0
3 FPS
2-1 FMOD1:0
0 FBUSY
Bit
Mnemonic Description
Programming Launch Command Bits
Write 5Xh followed by AXh to launch the programming according to FMOD1:0 (see Table 25)
Flash Map Program Space
Set to map the column latch space in the data memory space. Clear to re-map the data memory space.
Flash Mode
See Table 24 or Table 25.
Flash Busy
Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.
Reset Value = 0000 0000b
4127H–8051–02/08
43
A/T89C51AC2

Operation Cross Memory Access

Space addressable in read and write are:
RAM
ERAM (Expanded RAM access by movx)
XRAM (eXternal RAM)
EEPROM DATA
FM0 (user flash)
Hardware byte
XROW
Boot Flash
Flash Column latch
The table below provide the different kind of memory which can be accessed from differ­ent code location.
Table 27. Cross Memory Access
Action RAM
boot FLASH
FM0
External memory
EA = 0
or Code Roll
Over
Read OK OK OK OK -
Write - OK
Read OK OK OK OK -
Write - OK (idle) OK
Read - - OK - -
Write - - OK
Note: 1. RWW: Read While Write
XRAM
ERAM Boot FLASH FM0 E² Data
(1)
OK
(1)
(1)
(1)
Hardware
Byte XROW
(1)
OK
- OK
- -
OK
(1)
44
4127H–8051–02/08
A/T89C51AC2

Sharing Instructions

Table 28. Instructions shared
XRAM
Action RAM
Read MOV MOVX MOVX MOVC MOVC MOVC MOVC
Write MOV MOVX MOVX - by cl by cl by cl
ERAM
Note: by cl: using Column Latch
EEPROM
DATA
Boot
FLASH FM0
Hardware
Byte XROW
Table 29. Read MOVX A, @DPTR
EEE bit in
EECON
Register
0 0 X X OK
0 1 X X OK
1 0 X X OK
1 1 X X OK
FPS in
FCON Register ENBOOT EA
XRAM
ERAM
EEPROM
DATA
Table 30. Write MOVX @DPTR,A
EEE bit in
EECON
Register
FPS bit in
FCON Register ENBOOT EA
XRAM
ERAM
EEPROM
Data
Flash
Column
Latch
Flash
Column
Latch
0 0 X X OK
0 1 X
1 0 X X OK
1 1 X
1 OK
0 OK
1 OK
0 OK
4127H–8051–02/08
45
A/T89C51AC2
Table 31. Read MOVC A, @DPTR
Code Execution
From FM0
From FM1
(ENBOOT =1
FCON Register
ENBOOT DPTR FM1 FM0 XROW
0 0000h to 7FFFh OK
0 0 X
0 1 X X
1 0 X X X OK
1 1 X
0
0 0
1
0 1 X
1
0 000h to 7FFFh OK
1
1
0 X NA
1 X OK
0 X NA
1
0 NA
0000h to 7FFFh OK
F800h to FFFFh Do not use this configuration
0000 to 007Fh
(1)
See
0000h to 7FFFh OK
F800h to FFFFh Do not use this configuration
0000h to 7FFF OK
F800h to FFFFh OK
0000h to 007h
(2)
See
OK
OK
Hardware
Byte
External
CodeFMOD1 FMOD0 FPS
External code :
EA=0 or Code
Roll Over
1 0 X
1 1 X
X 0 X X X OK
1
0 NA
1
0 NA
X
OK
000h to 7FFFh
OK
1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh
2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh
46
4127H–8051–02/08
A/T89C51AC2
F800h
7FFFh
32 KB
Flash memory
2 KB IAP
bootloader
FM0
FM1
Custom Boot Loader
[SBV]00h
FFFFh
FM1 mapped between F800h and FFFFh when API called
0000h

In-System Programming (ISP)

Flash Programming and Erasure

With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the A/T89C51AC2 allows the system engineer the development of applica­tions with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life:
Before mounting the chip on the PCB, FM0 Flash can be programmed with the application code. FM1 is always preprogrammed by Atmel with a bootloader (UART bootloader).
Once the chip is mounted on the PCB, it can be programmed by serial mode via the UART.
Note: 1. The user can also program his own bootloader in FM1.
This In-System-Programming (ISP) allows code modification over the total lifetime of the product.
Besides the default Boot loader Atmel provide to the customer also all the needed Appli­cation-Programming-Interfaces (API) which are needed for the ISP. The API are located also in the Boot memory.
This allow the customer to have a full use of the 32 KB user memory.
There are three methods of programming the Flash memory:
The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1) will be used to program FM0. The interface used for serial downloading to FM0 is the UART. API can be called also by the user’s bootloader located in FM0 at [SBV]00h.
A further method exists in activating the Atmel boot loader by hardware activation. See Section “Hardware Security Byte”.
The FM0 can be programmed also by the parallel mode using a programmer.
(1)
Figure 25. Flash Memory Mapping
4127H–8051–02/08
47
A/T89C51AC2

Boot Process

Software Boot Process Example
Many algorithms can be used for the software boot process. Below are descriptions of the different flags and Bytes.
Boot Loader Jump Bit (BLJB):
- This bit indicates if on RESET the user wants to jump to this application at address
@0000h on FM0 or execute the boot loader at address @F800h on FM1.
- BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory pro-
gramming.
- To read or modify this bit, the APIs are used.
Boot Vector Address (SBV):
- This byte contains the MSB of the user boot loader address in FM0.
- The default value of SBV is FCh (no user boot loader in FM0).
- To read or modify this byte, the APIs are used.
Extra Byte (EB) and Boot Status Byte (BSB):
- These Bytes are reserved for customer use.
- To read or modify these Bytes, the APIs are used.
Hardware Boot Process At the falling edge of RESET, the bit ENBOOT in AUXR1 register is initialized with the
value of Boot Loader Jump Bit (BLJB).
Further at the falling edge of RESET if the following conditions (called Hardware condi­tion) are detected. The FCON register is initialized with the value 00h and the PC is initialized with F800h (FM1 lower byte = Bootloader entry point).
Harware Conditions:
PSEN low
(1)
EA high,
ALE high (or not connected).
The Hardware condition forces the bootloader to be executed, whatever BLJB value is. Then BLBJ will be checked.
If no hardware condition is detected, the FCON register is initialized with the value F0h. Then BLJB value will be checked.
Conditions are:
If bit BLJB = 1: User application in FM0 will be started at @0000h (standard reset).
If bit BLJB = 0: Boot loader will be started at @F800h in FM1.
Note: 1. As PSEN is an output port in normal operating mode (running user applications or
bootloader applications) after reset it is recommended to release PSEN after the fall­ing edge of Reset is signaled. The hardware conditions are sampled at reset signal Falling Edge, thus they can be released at any time when reset input is low.
2. To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during power-on.
48
4127H–8051–02/08
Figure 26. Hardware Boot Process Algorithm
RESET
Hardware
condition?
BLJB = = 0
?
bit ENBOOT in AUXR1 register is initialized with BLJB inverted.
Hardware
Software
ENBOOT = 1 PC = F800h
ENBOOT = 1 PC = F800h
FCON = 00h
FCON = F0h
Boot Loader in FM1
ENBOOT = 0 PC = 0000h
Yes
Yes
No
No
Application in FM0
(Example, if BLJB=0, ENBOOT is set (=1) during reset, thus the bootloader is executed after the reset)
A/T89C51AC2

Application Programming Interface

XROW Bytes

Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions.
All of these APIs are described in detail in the following documents on the Atmel web site.
Datasheet Bootloader UART A/T89C51AC2
Table 32. XROW Mapping
Description Default Value Address
Copy of the Manufacturer Code 58h 30h
Copy of the Device ID#1: Family code D7h 31h
Copy of the Device ID#2: Memories size and type F7h 60h
Copy of the Device ID#3: Name and Revision FFh 61h
4127H–8051–02/08
49
A/T89C51AC2

Hardware Security Byte

Table 33. Hardware Security Byte
7 6 5 4 3 2 1 0
X2B BLJB - - - LB2 LB1 LB0
Bit
Number
7 X2B
6 BLJB
5-3 -
2-0 LB2:0
Bit
Mnemonic Description
X2 Bit
Set this bit to start in standard mode. Clear this bit to start in X2 mode.
Boot Loader JumpBit
- 1: To start the user’s application on next RESET (@0000h) located in FM0,
- 0: To start the boot loader(@F800h) located in FM1.
Reserved
The value read from these bits are indeterminate.
Lock Bits
After erasing the chip in parallel mode, the default value is : FFh
The erasing in ISP mode (from bootloader) does not modify this byte.
Notes: 1. Only the 4 MSB bits can be accessed by software.
2. The 4 LSB bits can only be accessed by parallel mode.
50
4127H–8051–02/08
A/T89C51AC2
Write SBUF
RI
TI
SBUF
Transmitter
SBUF
Receiver
IB Bus
Mode 0 Transmit
Receive
Shift register
Load SBUF
Read SBUF
Interrupt Request
Serial Port
TXD
RXD
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART framing error control
SM0 to UART mode control
Set FE bit if stop bit is 0 (framing error)

Serial I/O Port

The A/T89C51AC2 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates
Serial I/O port includes the following enhancements:
Framing error detection
Automatic address recognition
Figure 27. Serial I/O Port Block Diagram

Framing Error Detection

Figure 28. Framing Error Block Diagram
4127H–8051–02/08
Framing bit error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register.
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register bit is set.
The software may examine the FE bit after each reception to check for data errors. Once set, only software or a reset clears the FE bit. Subsequently received frames with valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 29. and Figure 30.).
51
A/T89C51AC2
Figure 29. UART Timing in Mode 1
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD
D7D6D5D4D3D2D1D0
FE
SMOD0=1
RI
SMOD0=0
Data byte Ninth
bit
Stop
bit
Start
bit
RXD
D8D7D6D5D4D3D2D1D0
RI
SMOD0=1
FE
SMOD0=1
Figure 30. UART Timing in Modes 2 and 3

Automatic Address Recognition

The automatic address recognition feature is enabled when the multiprocessor commu­nication feature is enabled (SM2 bit in SCON register is set).
Implemented in the hardware, automatic address recognition enhances the multiproces­sor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address will the receiver set the RI bit in the SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices.
If necessary, you can enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
52
4127H–8051–02/08
A/T89C51AC2

Given Address

Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:
SADDR0101 0110b SADEN1111 1100b
Given0101 01XXb
Here is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0011b
SADEN1111 1101b
Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com­municate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

Broadcast Address

4127H–8051–02/08
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.:
SADDR 0101 0110b SADEN 1111 1100b
SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 1X11B,
Slave C:SADDR=1111 0010b
SADEN1111 1101b
Given1111 1111b
53
A/T89C51AC2
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.

Registers

Table 34. SCON Register
SCON (S:98h) Serial Control Register
7 6 5 4 3 2 1 0
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number
7
6 SM1
5 SM2
Bit
Mnemonic Description
FE
SM0
Framing Error bit (SMOD0=1
Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected.
Serial port Mode bit 0 (SMOD0=0)
Refer to SM1 for serial port mode selection.
Serial port Mode bit 1
SM0 SM1 Mode Baud Rate 0 0 Shift Register F 0 1 8-bit UART Variable 1 0 9-bit UART F 1 1 9-bit UART Variable
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3.
)
XTAL
XTAL
/12 (or F
/64 or F
/6 in mode X2)
XTAL
/32
XTAL
4 REN
3 TB8
2 RB8
1 TI
0 RI
Reception Enable bit
Clear to disable serial reception. Set to enable serial reception.
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.
Transmit Interrupt flag
Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 29. and Figure 30. in the other modes.
Reset Value = 0000 0000b Bit addressable
54
4127H–8051–02/08
A/T89C51AC2
Table 35. SADEN Register
SADEN (S:B9h) Slave Address Mask Register
7 6 5 4 3 2 1 0
Bit
Number
7-0
Bit
Mnemonic Description
Mask Data for Slave Individual Address
Reset Value = 0000 0000b Not bit addressable
Table 36. SADDR Register
SADDR (S:A9h) Slave Address Register
7 6 5 4 3 2 1 0
Bit
Number
7-0
Bit
Mnemonic Description
Slave Individual Address
Reset Value = 0000 0000b Not bit addressable
Table 37. SBUF Register
4127H–8051–02/08
SBUF (S:99h) Serial Data Buffer
7 6 5 4 3 2 1 0
Bit
Number
7-0
Bit
Mnemonic Description
Data sent/received by Serial I/O Port
Reset Value = 0000 0000b Not bit addressable
55
A/T89C51AC2
Table 38. PCON Register
PCON (S:87h) Power Control Register
7 6 5 4 3 2 1 0
SMOD1 SMOD0 POF GF1 GF0 PD IDL
Bit
Number
7 SMOD1
6 SMOD0
5 -
4 POF
3 GF1
2 GF0
1 PD
0 IDL
Bit
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
General-purpose Flag
Cleared by user for general-purpose usage. Set by user for general-purpose usage.
General-purpose Flag
Cleared by user for general-purpose usage. Set by user for general-purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs. Set to enter power-down mode.
Idle mode bit
Clear by hardware when interrupt or reset occurs. Set to enter idle mode.
56
Reset Value = 00X1 0000b Not bit addressable
4127H–8051–02/08
A/T89C51AC2

Timers/Counters

Timer/Counter Operations

The A/T89C51AC2 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections.
A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 39) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer regis­ters can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behav­ior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable.
For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is F
PER
/6, i.e. F
/12 in standard mode or F
OSC
OSC
/6 in X2
mode.

Timer 0

For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is F
/12, i.e. F
PER
/24 in standard mode or F
OSC
/12 in X2
OSC
mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle.
Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 31 to Figure 34 show the logical configuration of each mode.
Timer 0 is controlled by the four lower bits of TMOD register (see Figure 40) and bits 0, 1, 4 and 5 of TCON register (see Figure 39). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter­rupt request.
It is important to stop Timer/Counter before changing mode.
4127H–8051–02/08
57
A/T89C51AC2
Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0
FTx
CLOCK
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
÷
6
Overflow
Timer x Interrupt Request
C/Tx#
TMOD reg
TLx
(5 bits)
THx
(8 bits)
INTx#
Tx
See the “Clock” section
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow
Timer x Interrupt Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FTx
CLOCK
÷
6
See the “Clock” section
register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 31). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register.
Figure 31. Timer/Counter x (x = 0 or 1) in Mode 0
Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in
cascade (see Figure 32). The selected input increments TL0 register.
Figure 32. Timer/Counter x (x = 0 or 1) in Mode 1
58
4127H–8051–02/08
A/T89C51AC2
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow
Timer x Interrupt Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FTx
CLOCK
÷
6
See the “Clock” section
TR0
TCON.4
TF0
TCON.5
INT0#
0
1
GATE0
TMOD.3
Overflow
Timer 0 Interrupt Request
C/T0#
TMOD.2
TL0
(8 bits)
TR1
TCON.6
TH0
(8 bits)
TF1
TCON.7
Overflow
Timer 1 Interrupt Request
T0
FTx
CLOCK
÷
6
FTx
CLOCK
÷
6
See the “Clock” section
Mode 2 (8-bit Timer with Auto­Reload)
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 33). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register.
Figure 33. Timer/Counter x (x = 0 or 1) in Mode 2
Mode 3 (Two 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (see Figure 34). This mode is provided for applications requiring an additional 8­bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg­ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting F
/6) and takes over use of the Timer 1 interrupt (TF1) and
PER
run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode
3.
Figure 34. Timer/Counter 0 in Mode 3: Two 8-bit Counters
4127H–8051–02/08
59
A/T89C51AC2

Timer 1

Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The fol­lowing comments help to understand the differences:
Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 31 to Figure 33 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode.
Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 40) and bits 2, 3, 6 and 7 of TCON register (see Figure 39). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1).
Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose.
For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation.
Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request.
When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on.
It is important to stop Timer/Counter before changing mode.
Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-
ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 31). The upper 3 bits of TL1 register are ignored. Prescaler overflow incre­ments TH1 register.
Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in
cascade (see Figure 32). The selected input increments TL1 register.
Mode 2 (8-bit Timer with Auto­Reload)
Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt

Interrupt

Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (see Figure 33). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.
Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting interrupts are globally enabled by setting EA bit in IEN0 register.
ETx
bit in IEN0 register. This assumes
60
4127H–8051–02/08
Figure 35. Timer Interrupt System
TF0
TCON.5
ET0
IEN0.1
Timer 0 Interrupt Request
TF1
TCON.7
ET1
IEN0.3
Timer 1 Interrupt Request
A/T89C51AC2
4127H–8051–02/08
61
A/T89C51AC2

Registers

Table 39. TCON Register
TCON (S:88h) Timer/Counter Control Register
7 6 5 4 3 2 1 0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit
Number
7 TF1
6 TR1
5 TF0
4 TR0
3 IE1
2 IT1
1 IE0
Bit
Mnemonic Description
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.
Timer 1 Run Control Bit
Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.
Timer 0 Run Control Bit
Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0.
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin.
Interrupt 1 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1.
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin.
62
0 IT0
Interrupt 0 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.
Reset Value = 0000 0000b
4127H–8051–02/08
A/T89C51AC2
Table 40. TMOD Register
TMOD (S:89h) Timer/Counter Mode Control Register
7 6 5 4 3 2 1 0
GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
Bit
Number
7 GATE1
6 C/T1#
5 M11
4 M01
3 GATE0
2 C/T0#
1 M10
0
Bit
Mnemonic Description
Timer 1 Gating Control Bit
Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.
Timer 1 Counter/Timer Select Bit
Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
Timer 1 Mode Select Bits
M11 M01 Operating mode
0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter.
1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1) 1 1 Mode 3: Timer 1 halted. Retains count
Timer 0 Gating Control Bit
Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.
Timer 0 Counter/Timer Select Bit
Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0.
Timer 0 Mode Select Bit
M10 M00 Operating mode
0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter.
M00
1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0) 1 1 Mode 3: TL0 is an 8-bit Timer/Counter
TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.
Notes: 1. Reloaded from TH1 at overflow.
2. Reloaded from TH0 at overflow.
(1)
(2)
4127H–8051–02/08
Reset Value = 0000 0000b
63
A/T89C51AC2
Table 41. TH0 Register
TH0 (S:8Ch) Timer 0 High Byte Register
7 6 5 4 3 2 1 0
Bit
Number
7:0
Bit
Mnemonic Description
High Byte of Timer 0.
Reset Value = 0000 0000b
Table 42. TL0 Register
TL0 (S:8Ah) Timer 0 Low Byte Register
7 6 5 4 3 2 1 0
Bit
Number
7:0
Bit
Mnemonic Description
Low Byte of Timer 0.
Reset Value = 0000 0000b
Table 43. TH1 Register
TH1 (S:8Dh) Timer 1 High Byte Register
64
7 6 5 4 3 2 1 0
Bit
Number
7:0
Bit
Mnemonic Description
High Byte of Timer 1.
Reset Value = 0000 0000b
4127H–8051–02/08
A/T89C51AC2
Table 44. TL1 Register
TL1 (S:8Bh) Timer 1 Low Byte Register
7 6 5 4 3 2 1 0
Bit
Number
7:0
Bit
Mnemonic Description
Low Byte of Timer 1.
Reset Value = 0000 0000b
4127H–8051–02/08
65
A/T89C51AC2

Timer 2

(DOWN COUNTING RELOAD VALUE)
TF2
T2
EXF2
TH2
(8-bit)
TL2
(
8-bit)
RCAP2H
(8-bit)
RCAP2L
(8-bit)
FFh
(8-bit)
FFh
(
8-bit)
TOGGLE
(UP COUNTING RELOAD VALUE)
TIMER 2
INTERRUPT
:6
T2CONreg
T2CONreg
T2EX:
1=UP
2=DOWN
0
1
CT/2
T2CON.1
TR2
T2CON.2
FT2
CLOCK
see section “Clock”
The A/T89C51AC2 timer 2 is compatible with timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected. It is controlled by T2CON register (See Table ) and T2MOD register (See Table 47). Timer 2 operation is similar to Timer 0 and Timer
1. C/T2 selects F
/6 (timer operation) or external pin T2 (counter operation) as
T2 clock
timer clock. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 includes the following enhancements:
Auto-reload mode (up or down counter)
Programmable clock-output

Auto-Reload Mode

The auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto­matic reload. This feature is controlled by the DCEN bit in T2MOD register (See Table 47). Setting the DCEN bit enables timer 2 to count up or down as shown in Figure 36. In this mode the T2EX pin controls the counting direction.
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when timer 2 overflow or underflow, depending on the direction of the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit resolution.
Figure 36. Auto-Reload Mode Up/Down Counter
66
4127H–8051–02/08
A/T89C51AC2
Clo c k OutFreque n c y
FT 2clock
4 65536 RCAP2H RCAP 2 L( )×
-----------------------------------------------------------------------------------------
=
EXEN2
EXF2
OVERFLOW
T2EX
TH2
(8-bit)
TL2
(8-bit)
TIMER 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2CON reg
T2CON reg
T2MOD reg
INTERRUPT
TR2
T2CON.2
FT2
CLOCK
T2
Q D
Toggle
Q
Programmable Clock­Output
In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera­tor (See Figure 37). The input clock increments TL2 at frequency F
/2. The timer
OSC
repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency depending on the system oscillator frequency and the value in the RCAP2H and RCAP2L registers:
For a 16 MHz system clock in x1 mode, timer 2 has a programmable frequency range of 61 Hz (F
OSC
16)
/2
to 4 MHz (F
/4). The generated clock signal is brought out to T2 pin
OSC
(P1.0).
Timer 2 is programmed for the clock-out mode as follows:
Set T2OE bit in T2MOD register.
Clear C/T2 bit in T2CON register.
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or different depending on the application.
To start the timer, set TR2 run control bit in T2CON register.
Figure 37. Clock-Out Mode
It is possible to use timer 2 as a baud rate generator and a clock generator simulta­ne o usly. F o r thi s conf igu ration, t h e ba u d rat e s an d clo c k fr e que ncies a r e not independent since both functions use the values in the RCAP2H and RCAP2L registers.
4127H–8051–02/08
67
A/T89C51AC2

Registers

Table 45. T2CON Register
T2CON (S:C8h) Timer 2 Control Register
7 6 5 4 3 2 1 0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number
7 TF2
6 EXF2
5 RCLK
4 TCLK
3 EXEN2
2 TR2
Bit
Mnemonic Description
Timer 2 Overflow Flag
TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software.
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port.
Timer 2 Run Control bit
Clear to turn off timer 2. Set to turn on timer 2.
68
1 C/T2#
0 CP/RL2#
Timer/Counter 2 Select bit
Clear for timer operation (input from internal clock system: F Set for counter operation (input from T2 input pin).
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b Bit addressable
).
OSC
4127H–8051–02/08
A/T89C51AC2
Table 46. T2MOD Register
T2MOD (S:C9h) Timer 2 Mode Control Register
7 6 5 4 3 2 1 0
- - - - - - T2OE DCEN
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 -
1 T2OE
0 DCEN
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 Output Enable bit
Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.
Down Counter Enable bit
Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.
Reset Value = XXXX XX00b Not bit addressable
4127H–8051–02/08
Table 47. TH2 Register
TH2 (S:CDh) Timer 2 High Byte Register
7 6 5 4 3 2 1 0
- - - - - - - -
Bit
Number
7-0 High Byte of Timer 2.
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
69
A/T89C51AC2
Table 48. TL2 Register
TL2 (S:CCh) Timer 2 Low Byte Register
7 6 5 4 3 2 1 0
- - - - - - - -
Bit
Number
7-0 Low Byte of Timer 2.
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
Table 49. RCAP2H Register
RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register
7 6 5 4 3 2 1 0
- - - - - - - -
Bit
Number
7-0 High Byte of Timer 2 Reload/Capture.
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
Table 50. RCAP2L Register
70
RCAP2L (S:CAH) T
IMER
2 REload/Capture Low Byte Register
7 6 5 4 3 2 1 0
- - - - - - - -
Bit
Number
7-0 Low Byte of Timer 2 Reload/Capture.
Bit
Mnemonic Description
Reset Value = 0000 0000b Not bit addressable
4127H–8051–02/08
A/T89C51AC2
WDTPRG

Watchdog Timer

Figure 38. Watchdog Timer
A/T89C51AC2 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz in X1 mode.
This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) regis­ter. When exiting reset, the WDT is -by default- disable.
To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST register no instruction in between. When the Watchdog Timer is enabled, it will incre­ment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xT
, where T
OSC
OSC
=1/F
. To make the best use of the WDT, it
OSC
should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset
Note: When the Watchdog is enable it is impossible to change its period.
Fwd Clock
RESET
-
Decoder
WR
WDTRST
Enable
14-bit COUNTER
-
-
-
-
2
0
1
Control
7-bit COUNTER
Outputs
RESET
4127H–8051–02/08
71
A/T89C51AC2

Watchdog Programming

FT i me O ut
F
osc
6 2×
WD X2X2∧
2142
Sv a lue
×( )
-----------------------------------------------------------------------------
=
The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration.
Table 51. Machine Cycle Count
S2 S1 S0 Machine Cycle Count
0 0 0 214 - 1
0 0 1 215 - 1
0 1 0 2
0 1 1 217 - 1
1 0 0 218 - 1
1 0 1 219 - 1
1 1 0 220 - 1
1 1 1 221 - 1
16
- 1
To compute WD Time-Out, the following formula is applied:
Note: Svalue represents the decimal value of (S2 S1 S0)
The following table outlines the time-out value for Fosc
= 12 MHz in X1 mode
XTAL
Table 52. Time-Out Computation
S2 S1 S0 Fosc = 12 MHz Fosc = 16 MHz Fosc = 20 MHz
0 0 0 16.38 ms 12.28 ms 9.82 ms
0 0 1 32.77 ms 24.57 ms 19.66 ms
0 1 0 65.54 ms 49.14 ms 39.32 ms
0 1 1 131.07 ms 98.28 ms 78.64 ms
1 0 0 262.14 ms 196.56 ms 157.28 ms
1 0 1 524.29 ms 393.12 ms 314.56 ms
1 1 0 1.05 s 786.24 ms 629.12 ms
1 1 1 2.10 s 1.57 s 1.25 s
72
4127H–8051–02/08
A/T89C51AC2

Watchdog Timer During Power-down Mode and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is sig­nificantly different. The interrupt shall be held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the inter­rupt service for the interrupt used to exit Power-down.
To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting A/T89C51AC2 while in Idle mode, the user should always set up a timer that will period­ically exit Idle, service the WDT, and re-enter Idle mode.
Register Table 53. WDTPRG Register
WDTPRG (S:A7h) Watchdog Timer Duration Programming Register
7 6 5 4 3 2 1 0
S2 S1 S0
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 S2
1 S1
0 S0
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Watchdog Timer Duration selection bit 2
Work in conjunction with bit 1 and bit 0.
Watchdog Timer Duration selection bit 1
Work in conjunction with bit 2 and bit 0.
Watchdog Timer Duration selection bit 0
Work in conjunction with bit 1 and bit 2.
Reset Value = XXXX X000b
4127H–8051–02/08
73
A/T89C51AC2
Table 54. WDTRST Register
WDTRST (S:A6h Write only) Watchdog Timer Enable Register
7 6 5 4 3 2 1 0
Bit
Number
7 - Watchdog Control Value
Bit
Mnemonic Description
Reset Value = 1111 1111b
Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in
sequence without instruction between these two sequences.
74
4127H–8051–02/08
A/T89C51AC2

Programmable Counter Array (PCA)

The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu­racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any of the following signals:
PCA clock frequency/6 (see “clock” section)
PCA clock frequency/2
Timer 0 overflow
External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
rising and/or falling edge capture,
software timer,
high-speed output,
pulse width modulator.
Module 4 can also be programmed as a Watchdog timer. see the "PCA Watchdog Timer" section.
When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/Os. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O.

PCA Timer

PCA Component External I/O Pin
16-bit Counter P1.2/ECI
16-bit Module 0 P1.3/CEX0
16-bit Module 1 P1.4/CEX1
16-bit Module 2 P1.5/CEX2
16-bit Module 3 P1.6/CEX3
16-bit Module 4 P1.7/CEX4
The PCA timer is a common time base for all five modules (see Figure 39). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table
8) and can be programmed to run at:
1/6 the PCA clock frequency.
1/2 the PCA clock frequency.
the Timer 0 overflow.
the input on the ECI pin (P1.2).
4127H–8051–02/08
75
A/T89C51AC2
Figure 39. PCA Timer/Counter
CIDL CPS1 CPS0 ECF
It
CH CL
16 bit up counter
To PCA modules
FPca/6
FPca/2
T0 OVF
P1.2
Idle
CMOD 0xD9
WDTE
CF CR
CCON 0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
overflow
The CMOD register includes three additional bits associated with the PCA.
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the Watchdog function on module 4.
The ECF bit which when set causes an interrupt and the PCA overflow flag CF in CCON register to be set when the PCA timer overflows.

PCA Modules

76
The CCON register contains the run control bit for the PCA and the flags for the PCA timer and each module.
The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit.
The CF bit is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.
The CCF0:4 bits are the flags for the modules (CCF0 for module0...) and are set by hardware when either a match or a capture occurs. These flags also can be cleared by software.
Each one of the five compare/capture modules has six possible functions. It can perform:
16-bit Capture, positive-edge triggered
16-bit Capture, negative-edge triggered
16-bit Capture, both positive and negative-edge triggered
16-bit Software Timer
16-bit High Speed Output
8-bit Pulse Width Modulator.
In addition module 4 can be used as a Watchdog Timer.
4127H–8051–02/08

PCA Interrupt

CF CR
CCON
CCF4 CCF3 CCF2 CCF1 CCF0
Module 4
Module 3
Module 2
Module 1
Module 0
PCA Timer/Counter
ECCFn
CCAPMn.0
To Interrupt
EA
IEN0.7
EC
IEN0.6
ECF
CMOD.0
A/T89C51AC2
Each module in the PCA has a special function register associated with it (CCAPM0 for module 0...). The CCAPM0:4 registers contain the bits that control the mode that each module will operate in.
The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module.
The PWM bit enables the pulse width modulation mode.
The TOG bit when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register.
The match bit MAT when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register.
The two bits CAPN and CAPP in CCAPMn register determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled.
The bit ECOM in CCAPM register when set enables the comparator function.
Figure 40. PCA Interrupt System

PCA Capture Mode

To use one of the PCA modules in capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture reg­isters (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.
4127H–8051–02/08
77
A/T89C51AC2
Figure 41. PCA Capture Mode
CEXn n = 0, 4
PCA Counter
CH
(8bits)
CL
(8bits)
CCAPnH
CCAPnL
CCFn
CCON
PCA Interrupt Request
-
0CAPPn CAPNn 000 ECCFn
7
CCAPMn Register (n = 0, 4)
0
CCAPnL
(8 bits)
CCAPnH
(8 bits)
-
ECOMn0 0 MATn TOGn0 ECCFn
7 0
CCAPMn Register
(n = 0, 4)
CH
(8 bits)CL(8 bits)
16-Bit Comparator
Match
Enable
CCFn
CCON reg
PCA Interrupt Request
CEXn
Compare/Capture Module
PCA Counter
“0”
“1”
Reset
Write to
CCAPnL
Write to CCAPnH
For software Timer mode, set ECOMn and MATn. For high speed output mode, set ECOMn, MATn and TOGn.
Toggle

16-bit Software Timer Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.
Figure 42. PCA 16-bit Software Timer and High Speed Output Mode
78
4127H–8051–02/08
A/T89C51AC2
CH CL
CCAPnH CCAPnL
ECOMn
CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16-bit comparator
Match
CF CR
CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
Enable
CEXn
PCA counter/timer
“1”“0”
Write to
CCAPnL
Reset
Write to
CCAPnH

High Speed Output Mode

In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set.
Figure 43. PCA High Speed Output Mode

Pulse Width Modulator Mode

All the PCA modules can be used as PWM outputs. The output frequency depends on the source for the PCA timer. All the modules will have the same output frequency because they all share the PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module’s CCAPLn SFR the output will be low, when it is equal to or greater than it, the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated with­out glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode.
4127H–8051–02/08
79
A/T89C51AC2
Figure 44. PCA PWM Mode
CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL
CCAPnL
CCAPnH
8-Bit Comparator
CL (8 bits)
“0”
“1”
CL < CCAPnL
CL > = CCAPnL
CEX
PWMn
CCAPMn.1
ECOMn
CCAPMn.6

PCA Watchdog Timer

An on-board Watchdog timer is available with the PCA to improve system reliability with­out increasing chip count. Watchdog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a Watchdog. However, this module can still be used for other modes if the Watchdog is not needed. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high.
To hold off the reset, the user has three options:
periodically change the compare value so it will never match the PCA timer,
periodically change the PCA timer value so it will never match the compare values, or
disable the Watchdog by clearing the WDTE bit before a match occurs and then re­enable it.
The first two options are more reliable because the Watchdog timer is never disabled as in the third option. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. If other PCA modules are being used the second option not recommended either. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most appli­cations the first solution is the best option.
80
4127H–8051–02/08
A/T89C51AC2

PCA Registers

Table 55. CMOD Register
CMOD (S:D9h) PCA Counter Mode Register
7 6 5 4 3 2 1 0
CIDL WDTE - - - CPS1 CPS0 ECF
Bit
Number
7 CIDL
6 WDTE
5 -
4 -
3 -
2-1 CPS1:0
Bit
Mnemonic Description
PCA Counter Idle Control bit
Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked.
Watchdog Timer Enable
Clear to disable Watchdog Timer function on PCA Module 4, Set to enable it.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
EWC Count Pulse Select bits
CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4)
0 ECF
Enable PCA Counter Overflow Interrupt bit
Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt.
Reset Value = 00XX X000b
4127H–8051–02/08
81
A/T89C51AC2
Table 56. CCON Register
CCON (S:D8h) PCA Counter Control Register
7 6 5 4 3 2 1 0
CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
Bit
Number
7 CF
6 CR
5 -
4 CCF4
3 CCF3
2 CCF2
1 CCF1
Bit
Mnemonic Description
PCA Timer/Counter Overflow flag
Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software.
PCA Timer/Counter Run Control bit
Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Module 4 Compare/Capture flag
Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 4 bit in CCAPM 4 register is set. Must be cleared by software.
PCA Module 3 Compare/Capture flag
Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 3 bit in CCAPM 3 register is set. Must be cleared by software.
PCA Module 2 Compare/Capture flag
Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 2 bit in CCAPM 2 register is set. Must be cleared by software.
PCA Module 1 Compare/Capture flag
Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software.
82
PCA Module 0 Compare/Capture flag
0 CCF0
Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software.
Reset Value = 00X0 0000b
4127H–8051–02/08
A/T89C51AC2
Table 57. CCAPnH Registers
CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0..4)
7 6 5 4 3 2 1 0
CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0
Bit
Number
7:0
Bit
Mnemonic Description
CCAPnH
7:0
High byte of EWC-PCA comparison or capture values
Reset Value = 0000 0000b
Table 58. CCAPnL Registers
CCAP0L (S:EAh) CCAP1L (S:EBh) CCAP2L (S:ECh) CCAP3L (S:EDh) CCAP4L (S:EEh) PCA Low Byte Compare/Capture Module n Register (n=0..4)
7 6 5 4 3 2 1 0
CCAPnL 7 CCAPnL 6 CCAPnL 5 CCAPnL 4 CCAPnL 3 CCAPnL 2 CCAPnL 1 CCAPnL 0
Bit
Number
7:0
Bit
Mnemonic Description
CCAPnL
7:0
Low byte of EWC-PCA comparison or capture values
Reset Value = 0000 0000b
4127H–8051–02/08
83
A/T89C51AC2
Table 59. CCAPMn Registers
CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0..4)
7 6 5 4 3 2 1 0
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Bit
Number
7 -
6 ECOMn
5 CAPPn
4 CAPNn
3 MATn
2 TOGn
1 PWMn
Bit
Mnemonic Description
Reserved
The Value read from this bit is indeterminate. Do not set this bit.
Enable Compare Mode Module x bit
Clear to disable the Compare function. Set to enable the Compare function. The Compare function is used to implement the software Timer, the high-speed output, the Pulse Width Modulator (PWM) and the Watchdog Timer (WDT).
Capture Mode (Positive) Module x bit
Clear to disable the Capture function triggered by a positive edge on CEXx pin. Set to enable the Capture function triggered by a positive edge on CEXx pin
Capture Mode (Negative) Module x bit
Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin.
Match Module x bit
Set when a match of the PCA Counter with the Compare/Capture register sets CCFx bit in CCON register, flagging an interrupt.
Toggle Module x bit
The toggle mode is configured by setting ECOMx, MATx and TOGx bits. Set when a match of the PCA Counter with the Compare/Capture register toggles the CEXx pin.
Pulse Width Modulation Module x Mode bit
Set to configure the module x as an 8-bit Pulse Width Modulator with output waveform on CEXx pin.
84
0 ECCFn
Enable CCFx Interrupt bit
Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request.
Reset Value = X000 0000b
4127H–8051–02/08
A/T89C51AC2
Table 60. CH Register
CH (S:F9h) PCA Counter Register High Value
7 6 5 4 3 2 1 0
CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0
Bit
Number
7:0 CH 7:0 High byte of Timer/Counter
Bit
Mnemonic Description
Reset Value = 0000 00000b
Table 61. CL Register
CL (S:E9h) PCA counter Register Low Value
7 6 5 4 3 2 1 0
CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1 CL 0
Bit
Number
7:0 CL0 7:0 Low byte of Timer/Counter
Bit
Mnemonic Description
Reset Value = 0000 00000b
4127H–8051–02/08
85
A/T89C51AC2

Analog-to-Digital Converter (ADC)

This sec t ion des c ri bes the on- c hip 10 bit anal o g-to - digit al c onver ter of t he A/T89C51AC2. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit cascaded potentiometric ADC.
Two modes of conversion are available:
- Standard conversion (8 bits).
- Precision conversion (10 bits).
For the precision conversion, set bit PSIDLE in ADCON register and start conversion. The device is in a pseudo-idle mode, the CPU does not run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion.
For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up.
If another interrupt occurs during the precision conversion, it will be served only after this conversion is completed.

Features

ADC Port 1 I/O Functions

VAREF

8 channels with multiplexed inputs
10-bit cascaded potentiometric ADC
Conversion time 16 micro-seconds (typ.)
Zero Error (offset) ± 2 LSB max
Positive External Reference Voltage Range (VAREF) 2.4 to 3.0 Volt (typ.)
ADCIN Range 0 to 3Volt
Integral non-linearity typical 1 LSB, max. 2 LSB
Differential non-linearity typical 0.5 LSB, max. 1 LSB
Conversion Complete Flag or Conversion Complete Interrupt
Selectable ADC Clock
Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general-purpose I/O or as the alter­nate function that is available.
A conversion launched on a channel which are not selected on ADCF register will not have any effect.
VAREF should be connected to a low impedance point and must remain in the range specified in Table 77. If the ADC is not used, it is recommended to connect VAREF to VAGND.
86
4127H–8051–02/08
Figure 45. ADC Description
Rai
AN0/P1.0
AN1/P1.1
AN2/P1.2
AN3/P1.3
AN4/P1.4
AN5/P1.5
AN6/P1.6
AN7/P1.7
000
001
010
011
100
101
110
111
SCH2
ADCON.2
SCH0
ADCON.0
SCH1
ADCON.1
ADC
CLOCK
ADEN
ADCON.5
ADSST
ADCON.3
ADEOC
ADCON.4
ADC Interrupt Request
EADC
IEN1.1
CONTROL
AVSS
Sample and Hold
ADDH
VAREF
R/2R DAC
VAGND
8
10
+
-
ADDL
2
SAR
ADCIN
Cai
ADEN
ADSST
ADEOC
T
SETUP
(1)
T
CONV
(2)
CLK
A/T89C51AC2
Figure 46 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the Section “AC Characteristics” of the A/T89C51AC2 datasheet.
Figure 46. Timing Diagram
Notes: 1. Tsetup min, see the AC Parameter for A/D conversion.
2. Tconv = 11 clock ADC = 1sample and hold + 10 bit conversion The user must ensure that Tsetup time between setting ADEN and the start of the first conversion.
4127H–8051–02/08
87
A/T89C51AC2

ADC Converter Operation

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
After completion of the A/D conversion, the ADSST bit is cleared by hardware.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set (see Figure 48). Clear this flag for re­arming the interrupt.

Voltage Conversion

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection.
Note: 1. Always leave Tsetup time before starting a conversion unless ADEN is permanently
(1)
high. In this case one should wait Tsetup only before the first conversion.
Table 62. Selected Analog input
SCH2 SCH1 SCH0 Selected Analog input
0 0 0 AN0
0 0 1 AN1
0 1 0 AN2
0 1 1 AN3
1 0 0 AN4
1 0 1 AN5
1 1 0 AN6
1 1 1 AN7
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND.
Note: ADCIN should not exceed VAREF absolute maximum range (see “Absolute Maximum
Ratings” on page 141)

Clock Selection

88
The ADC clock is the same as CPU.
The maximum clock frequency is defined in the DC parmeter for A/D converter. A pres­caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.
if PRS > 0 then f
if PRS = 0 then f
ADC
ADC
= F
= F
periph
periph
/ 2 x PRS
/ 64
4127H–8051–02/08
Figure 47. A/D Converter clock
Prescaler ADCLK
A/D
Converter
ADC Clock
CPU
CLOCK
CPU Core Clock Symbol
÷
2
ADEOC
ADCON.2
EADC
IEN1.1
ADCI
A/T89C51AC2

ADC Standby Mode

IT ADC Management

Routines examples

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is reduced.
An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.
Figure 48. ADC Interrupt Structure
1. Configure P1.2 and P1.3 in ADC channels
// configure channel P1.2 and P1.3 for ADC
ADCF = 0Ch
// Enable the ADC
ADCON = 20h
2. Start a standard conversion
// The variable "channel" contains the channel to convert
// The variable "value_converted" is an unsigned int
// Clear the field SCH[2:0]
ADCON and = F8h
// Select channel
ADCON | = channel
// Start conversion in standard mode
ADCON | = 08h
// Wait flag End of conversion
while((ADCON and 01h)! = 01h)
// Clear the End of conversion flag
ADCON and = EFh
// read the value
value_converted = (ADDH << 2)+(ADDL)
4127H–8051–02/08
3. Start a precision conversion (need interrupt ADC)
// The variable "channel" contains the channel to convert
// Enable ADC
EADC = 1
89
A/T89C51AC2
// clear the field SCH[2:0]
ADCON and = F8h
// Select the channel
ADCON | = channel
// Start conversion in precision mode
ADCON | = 48h
Note: to enable the ADC interrupt:
EA = 1
90
4127H–8051–02/08
A/T89C51AC2

Registers

Table 63. ADCF Register
ADCF (S:F6h) ADC Configuration
7 6 5 4 3 2 1 0
CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0
Bit
Number
7-0 CH 0:7
Bit
Mnemonic Description
Channel Configuration
Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port.
Reset Value = 0000 0000b
Table 64. ADCON Register
ADCON (S:F3h) ADC Control Register
7 6 5 4 3 2 1 0
- PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0
Bit
Number
Bit
Mnemonic Description
7 -
6 PSIDLE
5 ADEN
4 ADEOC
3 ADSST
2-0 SCH2:0
Pseudo Idle Mode (Best Precision)
Set to put in idle mode during conversion Clear to convert without idle mode.
Enable/Standby Mode
Set to enable ADC Clear for Standby mode (power dissipation 1 uW).
End Of Conversion
Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software.
Start and Status
Set to start an A/D conversion. Cleared by hardware after completion of the conversion
Selection of Channel to Convert
see Table 62
Reset Value = X000 0000b
4127H–8051–02/08
91
A/T89C51AC2
Table 65. ADCLK Register
ADCLK (S:F2h) ADC Clock Prescaler
7 6 5 4 3 2 1 0
- - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0
Bit
Number
7-5 -
4-0 PRS4:0
Bit
Mnemonic Description
Reserved
The value read from these bits are indeterminate. Do not set these bits.
Clock Prescaler
f
=
fcpu clock/ (4 (or 2 in X2 mode)* PRS )
ADC
Reset Value = XXX0 0000b
Table 66. ADDH Register
ADDH (S:F5h Read Only) ADC Data High Byte Register
7 6 5 4 3 2 1 0
ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2
Bit
Number
7-0 ADAT9:2
Bit
Mnemonic Description
ADC result
bits 9-2
Reset Value = 00h
92
Table 67. ADDL Register
ADDL (S:F4h Read Only) ADC Data Low Byte Register
7 6 5 4 3 2 1 0
- - - - - - ADAT 1 ADAT 0
Bit
Number
7-2 -
1-0 ADAT1:0
Bit
Mnemonic Description
Reserved
The value read from these bits are indeterminate. Do not set these bits.
ADC result
bits 1-0
Reset Value = 00h
4127H–8051–02/08

Interrupt System

EX0
IEN0.0
00 01 10 11
External
Interrupt 0
INT0#
EX1
IEN0.2
External
Interrupt 1
INT1#
ET0
IEN0.1
Timer 0
EC
IEN0.6
PCA
ET1
IEN0.3
Timer 1
ES
IEN0.4
UART
EADC
IEN1.1
A to D
Converter
Interrupt Enable Lowest Priority Interrupts
Highest
Priority Enable
00 01 10 11
00 01 10 11
00 01 10 11
00 01 10 11
00 01 10 11
00 01 10 11
Priority
Interrupts
AIN1:0
Timer 2
00 01 10 11
ET2
IEN0.5
TxD
RxD
CEX0:5
A/T89C51AC2

Introduction

The controller has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1 and 2), a serial port interrupt, a PCA, a timer overrun interrupt and an ADC. These interrupts are shown below.
Figure 49. Interrupt Control System
4127H–8051–02/08
93
A/T89C51AC2
Each of the interrupt sources can be individually enabled or disabled by setting or clear­ing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time.
Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination.
Table 68. Priority Level Bit Values
IPH.x IPL.x Interrupt Level Priority
0 0 0 (Lowest)
0 1 1
1 0 2
1 1 3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of the higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, see Table 69.
Table 69. Interrupt Priority Within level
Interrupt Name Interrupt Address Vector Priority Number
external interrupt (INT0) 0003h 1
Timer 0 (TF0) 000Bh 2
external interrupt (INT1) 0013h 3
Timer 1 (TF1) 001Bh 4
PCA (CF or CCFn) 0033h 5
UART (RI or TI) 0023h 6
Timer 2 (TF2) 002Bh 7
ADC (ADCI) 0043h 9
94
4127H–8051–02/08
A/T89C51AC2

Registers

Table 70. IEN0 Register
IEN0 (S:A8h) Interrupt Enable Register
7 6 5 4 3 2 1 0
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit
Number
7 EA
6 EC
5 ET2
4 ES
Bit
Mnemonic Description
Enable All Interrupt bit
Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit.
PCA Interrupt Enable
Clear to disable the PCA interrupt. Set to enable the PCA interrupt.
Timer 2 Overflow Interrupt Enable bit
Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt.
Serial Port Enable bit
Clear to disable serial port interrupt. Set to enable serial port interrupt.
Timer 1 Overflow Interrupt Enable bit
3 ET1
2 EX1
1 ET0
0 EX0
Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt.
External Interrupt 1 Enable bit
Clear to disable external interrupt 1. Set to enable external interrupt 1.
Timer 0 Overflow Interrupt Enable bit
Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.
External Interrupt 0 Enable bit
Clear to disable external interrupt 0. Set to enable external interrupt 0.
Reset Value = 0000 0000b bit addressable
4127H–8051–02/08
95
A/T89C51AC2
Table 71. IEN1 Register
IEN1 (S:E8h) Interrupt Enable Register
7 6 5 4 3 2 1 0
- - - - - - EADC -
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 -
1 EADC
0 -
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
ADC Interrupt Enable bit
Clear to disable the ADC interrupt. Set to enable the ADC interrupt.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = xxxx xx00b bit addressable
96
4127H–8051–02/08
A/T89C51AC2
Table 72. IPL0 Register
IPL0 (S:B8h) Interrupt Enable Register
7 6 5 4 3 2 1 0
- PPC PT2 PS PT1 PX1 PT0 PX0
Bit
Number
7 -
6 PPC
5 PT2
4 PS
3 PT1
2 PX1
1 PT0
0 PX0
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Interrupt Priority bit
Refer to PPCH for priority level
Timer 2 Overflow Interrupt Priority bit
Refer to PT2H for priority level.
Serial Port Priority bit
Refer to PSH for priority level.
Timer 1 Overflow Interrupt Priority bit
Refer to PT1H for priority level.
External Interrupt 1 Priority bit
Refer to PX1H for priority level.
Timer 0 Overflow Interrupt Priority bit
Refer to PT0H for priority level.
External Interrupt 0 Priority bit
Refer to PX0H for priority level.
Reset Value = X000 0000b bit addressable
4127H–8051–02/08
97
A/T89C51AC2
Table 73. IPL1 Register
IPL1 (S:F8h) Interrupt Priority Low Register 1
7 6 5 4 3 2 1 0
- - - - - - PADCL -
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 -
1 PADCL
0 -
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
ADC Interrupt Priority Level Less Significant Bit
Refer to PSPIH for priority level.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = XXXX XX0Xb bit addressable
98
4127H–8051–02/08
A/T89C51AC2
Table 74. IPH0 Register
IPH0 (B7h) Interrupt High Priority Register
7 6 5 4 3 2 1 0
- PPCH PT2H PSH PT1H PX1H PT0H PX0H
Bit
Number
7 -
6 PPCH
5 PT2H
4 PSH
3 PT1H
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Interrupt Priority Level Most Significant bit
PPCH PPC Priority level 0 0 Lowest 0 1 1 0 1 1 Highest priority
Timer 2 Overflow Interrupt High Priority bit
PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest
Serial Port High Priority bit
PSH PS Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest
Timer 1 Overflow Interrupt High Priority bit
PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest
4127H–8051–02/08
External Interrupt 1 High Priority bit
PX1H PX1 Priority Level
2 PX1H
1 PT0H
0 PX0H
0 0 Lowest 0 1 1 0 1 1 Highest
Timer 0 Overflow Interrupt High Priority bit
PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest
External Interrupt 0 high priority bit
PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest
Reset Value = X000 0000b
99
A/T89C51AC2
Table 75. IPH1 Register
IPH1 (S:F7h) Interrupt High Priority Register 1
7 6 5 4 3 2 1 0
- - - - - - PADCH -
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 -
1 PADCH
0 -
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
ADC Interrupt Priority Level Most Significant bit
PADCH PADCL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest
Reserved
The value read from this bit is indeterminate. Do not set this bit.
100
Reset Value = XXXX X000b
4127H–8051–02/08
Loading...