ATMEL AT89C5131A-M User Manual

BDTIC www.bdtic.com/ATMEL

Features

80C52X2 Core (6 Clocks per Instruction)
– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART) – Three 16-bit Timer/Counters: T0, T1 and T2 – 256 Bytes of Scratchpad RAM
16/32-Kbyte On-chip Flash EEPROM In-System Programmi
– Byte and Page (128 bytes) Erase and Write – 100k Write Cycles
3-KbyteFlash EEPROM for Bootloader
– Byte and Page (128 bytes) Erase and Write – 100k Write Cycles
1-Kbyte EEPROM Data (
– Byte and Page (128 bytes) Erase and Write – 100k Write Cycles
On-chip Expanded RAM (ERAM): 1024 Bytes
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers: 32-byte FIFO – 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
• Endpoint 1, 2, 3: 32-byte FIFO
• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)
• Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode) – Suspend/Resume Interrupts – 48 MHz PLL for Full-speed Bus Operation – Bus Disconnection on Microcontroller Request
5 Channels Programmable Counter Array (PCA) with 16-
Output, Compare/Capture, PWM and Watchdog Timer Capabilities
Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 100 ms
to 3s at 8 MHz
Keyboard Interrupt Interface on Port P1 (8 Bits)
TWI (Two Wire Interface) 400Kbit/s
SPI Interface (Master/Slave Mode)
34 I/O Pins
4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical
4-level Priority Interrupt System (11 sources)
Idle and Power-down Modes
0 to 24 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis
Industrial Temperature Range
Extended Range Power Supply: 2.7V to 5.5V (3.3V to 5.5V required for USB)
Packages: PLCC52, VQFP64, QFN32
bit Counter, High-speed
8-bit Flash Microcontroller with Full Speed USB Device
AT89C5130A-M AT89C5131A-M
AT89C5130A/31A-M

1. Description

AT89C5130A/31A-M is a high-performance Flash version of the 80C51 single-chip 8-bit micro­controllers with full speed USB functions.
AT89C5130A/31A-M features a full-speed USB module compatible with the USB specifications Version 1.1 and 2.0. This module integrates the USB transceivers with a 3.3V voltage regulator and the Serial Interface Engine (SIE) with Digital Phase Locked Loop and 48 MHz clock recov­ery. USB Event detection logic (Reset and Suspend/Resume) and FIFO buffers supporting the m a n d a to ry c o n tr ol E nd po in t ( E P0 ) a n d u p t o 6 v er sa ti le E nd po i n t s (EP1/EP2/EP3/EP4/EP5/EP6) with minimum software overhead are also part of the USB module.
AT89C5130A/31A-M retains the features of the Atmel 80C52 with extended Flash capacity (16/32-Kbytes), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full duplex enhanced UART (EUART) and an on-chip oscillator.
In addition, AT89C5130A/31A-M has an on-chip expanded RAM of 1024 bytes (ERAM), a dual data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA), up to 4 pro­grammable LED current sources, a programmable hardware watchdog and a power-on reset.
AT89C5130A/31A-M has two software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial ports and the interrupt system are still operating. In the power-down mode the RAM is saved, the periph­eral clock is frozen, but the device has full wake-up capability through USB events or external interrupts.
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2. Block Diagram

Timer 0
INT
RAM
256x8
T0
T1
RxD
TxD
WR
RD
EA
PSEN
ALE
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0P0Port 1
Port 2
Port 3
Parallel I/O Ports & Ext. Bus
P1
P2
P3
ERAM
1Kx8
PCA
RST
Watch
Dog
CEX
ECI
VSS
VDD
(2)(2)
(1)(1)
Timer2
T2EX
T2
(1) (1)
Port 4
P4
16/32Kx8Flash
+
BRG
USB
D -
D +
VREF
Regu-
Key
Board
KIN [0..7]
lator
AVSS
EEPROM
4Kx8
SPI
MISO
MOSI
SCK
(1) (1) (1)
SS
(1)
AVDD
TWI
SCL
SDA
(3) (3)
AT89C5130A/31A-M
Notes: 1. Alternate function of Port 1
2. Alternate function of Port 3
3. Alternate function of Port 4
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AT89C5130A/31A-M

3. Pinout Description

21 22 26252423 292827 30 31
5 4 3 2 1 6
52 51 50 49 48
8
9
10
11
12
13
14
15
16
17
18
46
45
44
43
42
41
40 39
38
37
36
PLCC52
7 47
19
20
32 33
34
35
P1.1/T2EX/KIN1/SS
P1.0/T2/KIN0
P0.6/AD6
ALE
P0.7/AD7
EA
PSEN
P1.7/CEX4/KIN7/MOSI
P1.3/CEX0/KIN3
P1.5/CEX2/KIN5/MISO
P1.6/CEX3/KIN6/SCK
PLLF
P3.0/RxD
AVSS
P2.6/A14
XTAL1
P2.5/A13
P0.3/AD3
P0.5/AD5
P0.4/AD4
VREF
P0.2/AD2
P0.0/AD0
P0.1/AD1
AVDD
UCAP
P3.2/INT0
P3.6/WR/LED2
XTAL2
RST
P3.1/TxD
P3.3/INT1/LED0
P3.7/RD/LED3
D-
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
VSS
P2.4/A12
P4.1/SDA
D+
P4.0/SCL
P1.2/ECI/KIN2
P1.4/CEX1/KIN4
P3.4/T0
P3.5/T1/LED1
NC
NC
VDD
UVSS
P2.7/A15

3.1 Pinout

Figure 3-1. AT89C5130A/31A-M 52-pin PLCC Pinout
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Figure 3-2. AT89C5130A/31A-M 64-pin VQFP Pinout
17 18 22212019 252423 26 27
62 61 60 59 58 63
57 56 55 54 53
1 2
3
4
5
6
7
8
9
10
11
48 47
46
45
44
43
42
41 40
39
38
VQFP64
64
52
12 13
28
29
36
37
51 50
49
35
33
34
14
15 16
30
31 32
P1.1/T2EX/KIN1/SS
ALE
EA
PSEN
P1.7/CEX4/KIN7/MOSI
P1.3/CEX0/KIN3
P1.5/CEX2/KIN5/MISO
P1.6/CEX3/KIN6/SCK
P2.7/A15
P2.6/A14
P4.1/SDA
P1.2/ECI/KIN2
P1.4/CEX1/KIN4
P1.0/T2/KIN0
PLLF
UCAP
XTAL2
RST
P3.7/RD/LED3
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
NC
NC
P3.0/RxD
NC
VREF
P0.0/AD0
AVSS
P3.2/INT0
P3.6/WR/LED2
P3.1/TxD
P3.3/INT1/LED0
VSS
P3.4/T0
P3.5/T1/LED1
NC
P0.6/AD6 P0.7/AD7
P2.5/A13
P0.3/AD3
P0.5/AD5
P0.4/AD4
P0.2/AD2
P0.1/AD1
D-
D+
P4.0/SCL
XTAL1
AVDD
NC
NC
NC
NC
UVSS
NC
NC
NC
NC
NC
NC
VDD
AT89C5130A/31A-M
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5
AT89C5130A/31A-M
Figure 3-3. AT89C5130A/31A-M 32-pin QFN Pinout
1
2
3
4
5
6
QFN32
7
P1.1/T2EX/KIN1/SS
P1.7/CEX4/KIN7/MOSI
P1.3/CEX0/KIN3
P1.5/CEX2/KIN5/MISO
P1.6/CEX3/KIN6/SCK
P3.0/RxD
AVSS
XTAL1
VREF
UCAP
P3.2/INT0
P3.5/T1/LED1
XTAL2
RST
P3.1/TxD
P3.3/INT1/LED0
P3.7/RD/LED3
D-
VSS
P4.1/SDA
D+
P4.0/SCL
P1.2/ECI/KIN2
P1.4/CEX1/KIN4
P3.4/T0
P1.0/T2/KIN0
VDD
8
PLLF
P3.6/WR/LED2
UVSS
NC
NC
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
Note : The metal plate can be connected to Vss

3.2 Signals

6
All the AT89C5130A/31A-M signals are detailed by functionality on Table 3-1 through Table 3-
12.
Table 3-1. Keypad Interface Signal Description
Signal
Name Type Description
Table 3-2. Programmable Counter Array Signal Description
KIN[7:0) I
Signal
Name Type Description
ECI I External Clock Input P1.2
Keypad Input Lines
Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt if enabled. Held line is reported in the KBCON register.
Alternate Function
P1[7:0]
Alternate Function
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AT89C5130A/31A-M
Signal
Name Type Description
Capture External Input
CEX[4:0] I/O
Compare External Output
Table 3-3. Serial I/O Signal Description
Signal
Name Type Description
RxD I Serial Input Port P3.0
TxD O Serial Output Port P3.1
Table 3-4. Timer 0, Timer 1 and Timer 2 Signal Description
Signal
Name Type Description
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register.
INT0 I
External Interrupt 0
INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits IE0 are set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by a low level on INT0.
Alternate Function
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Function
Alternate Function
P3.2
Timer 1 Gate Input
serves as external run control for Timer 1, when selected by GATE1
INT1 bit in TCON register.
INT1 I
T0 I
T1 I
T2
T2EX I Timer/Counter 2 Reload/Capture/Direction Control Input P1.1
External Interrupt 1
INT1 input set IE1 in the TCON register. If bit IT1 in this register is set, bits IE1 are set by a falling edge on INT1. If bit IT1 is cleared, bits IE1 is set by a low level on INT1.
Timer Counter 0 External Clock Input
When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count.
Timer/Counter 1 External Clock Input
When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count.
IOTimer/Counter 2 External Clock Input
Timer/Counter 2 Clock Output
P3.3
P3.4
P3.5
P1.0
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AT89C5130A/31A-M
Table 3-5. LED Signal Description
Signal
Name Type Description
Direct Drive LED Output
LED[3:0] O
These pins can be directly connected to the Cathode of standard LEDs without external current limiting resistors. The typical current of each output can be programmed by software to 2, 6 or 10 mA. Several outputs can be connected together to get higher drive capabilities.
Table 3-6. TWI Signal Description
Signal
Name Type Description
SCL I/O
SDA I/O
SCL: TWI Serial Clock
SCL output the serial clock to slave peripherals. SCL input the serial clock from master.
SDA: TWI Serial Data
SCL is the bidirectional TWI data line.
Table 3-7. SPI Signal Description
Signal
Name Type Description
SS I/O SS
: SPI Slave Select P1.1
Alternate Function
P3.3
P3.5
P3.6
P3.7
Alternate Function
P4.0
P4.1
Alternate Function
MISO I/O
SCK I/O
MOSI
I/O
MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller.
SCK: SPI Serial Clock
SCK outputs clock to the slave peripheral or receive clock from the master
MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller
P1.5
P1.6
P1.7
8
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Table 3-8. Ports Signal Description
Signal
Name Type Description Alternate Function
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0
P0[7:0] I/O
P1[7:0] I/O
pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, Floating P0 inputs must be pulled to V
.
V
SS
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
AT89C5130A/31A-M
AD[7:0]
or
DD
KIN[7:0]
T2
T2EX
ECI
CEX[4:0]
P2[7:0] I/O
P3[7:0] I/O
P4[1:0] I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 4
P4 is an 2-bit open drain port.
Table 3-9. Clock Signal Description
Signal
Name Type Description
XTAL1 I
XTAL2 O
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin.
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected.
A[15:8]
LED[3:0]
RxD
TxD
INT0 INT1
T0 T1
WR
RD
SCL
SDA
Alternate Function
-
-
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PLLF I
PLL Low Pass Filter input
Receive the RC network of the PLL low pass filter.
-
9
AT89C5130A/31A-M
Table 3-10. USB Signal Description
Signal
Name Type Description
D+ I/O
D- I/O
VREF O
USB Data + signal
Set to high level under reset.
USB Data - signal
Set to low level under reset.
USB Reference Voltage
Connect this pin to D+ using a 1.5 k resistor to use the Detach function.
Table 3-11. System Signal Description
Signal
Name Type Description
AD[7:0] I/O
A[15:8] I/O Address Bus MSB for external access P2[7:0]
RD
WR I/O
Multiplexed Address/Data LSB for external access
Data LSB for Slave port access (used for 8-bit and 16-bit modes)
Read Signal
Read signal asserted during external data memory read operation.
I/O
Control input for slave port read access cycles.
Write Signal
Write signal asserted during external data memory write operation.
Control input for slave write access cycles.
Alternate Function
-
-
-
Alternate Function
P0[7:0]
P3.7
P3.6
Reset Input
Holding this pin low for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than V
RST O
ALE O
PSEN I/O
EA I
This pin has an internal pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and VSS. Asserting RST when the chip is in Idle mode or Power-down mode returns the chip to normal operation. This pin is tied to 0 for at least 12 oscillator periods when an internal reset occurs ( hardware watchdog or power monitor).
Address Latch Enable Output
The falling edge of ALE strobes the address into external latch. This signal is active only when reading or writing external memory using MOVX instructions.
Program Strobe Enable / Hardware conditions Input for ISP
Used as input under reset to detect external hardware conditions of ISP mode.
External Access Enable
This pin must be held low to force the device to fetch code from external program memory starting at address 0000h.
Table 3-12. Power Signal Description
Signal
Name Type Description
is applied, whether or not the oscillator is running.
IL
-
-
-
-
Alternate Function
10
AVSS GND
Analog Ground
AVSS is used to supply the on-chip PLL and the USB PAD.
-
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Table 3-12. Power Signal Description (Continued)
Signal
Name Type Description
AT89C5130A/31A-M
Alternate Function
AVDD PWR
VSS GND
UVSS GND
UCAP PWR
VDD PWR
VREF O
Analog Supply Voltage
AVDD is used to supply the on-chip PLL and the USB PAD.
Digital Ground
VSS is used to supply the buffer ring and the digital core.
USB Digital Ground
UVSS is used to supply the USB pads.
USB Pad Power Capacitor
UCAP must be connect to an external capacitor for USB pad power supply (for typical application see
Digital Supply Voltage
VDD is used to supply the buffer ring on all versions of the device.
It is also used to power the on-chip voltage regulator of the Standard versions or the digital core of the Low Power versions.
USB pull-up Controlled Output
VREF is used to control the USB D+ 1.5 k pull up.
The Vref output is in high impedance when the bit DETACH is set in the USBCON register.
Figure 4-1 on page 12)
-
-
-
-
-
-
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11
AT89C5130A/31A-M

4. Typical Application

VSS
XTAL1
XTAL2
Q
22pF
22pF
VSS
PLLF
100R
10nF
2.2nF
VSS
VSS
AVSS
VSS
D-
UCAP
1µF
VSS
D+
27R
27R
VRef
1.5K
USB
D+
D-
VBUS
GND
VSS
VDD
AVDD
VDD
VDD
4.7µF
VSS
100nF
VSS
100nF
VSS
UVSS
AT89C5130A/31A-M
+20%

4.1 Recommended External components

All the external components described in the figure below must be implemented as close as pos­sible from the microcontroller package.
The following figure represents the typical wiring schematic.
Figure 4-1. Typical Application
12
4337K–USB–04/08

4.2 PCB Recommandations

D+
VRef
D-
USB Connector
Wires must be routed in Parallel and
Components must be
If possible, isolate D+ and D- signals from other signals with ground wires
must be as short as possible
close to the microcontroller
PLLFAVss
Components must be
Isolate filter components
with a ground wire
microcontroller
close to the
C2
C1
R
Figure 4-2. USB Pads
Figure 4-3. USB PLL
AT89C5130A/31A-M
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13
AT89C5130A/31A-M

5. Clock Controller

X1
X2
PD
PCON.1
IDL
PCON.0
Peripheral
CPU Core
0
1
X2
CKCON.0
÷
2
Clock
Clock
EXT48
PLLCON.2
0
1
PLL
USB Clock

5.1 Introduction

The AT89C5130A/31A-M clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller.
The AT89C5130A/31A-M X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 5-1) that can be configured with off-chip components as a Pierce oscillator (see Figure 5-2). Value of capacitors and crystal characteristics are detailed in the section “DC Characteristics”.
The X1 pin can also be used as input for an external 48 MHz clock.
The clock controller outputs three different clocks as shown in Figure 5-1:
• a clock for the CPU core
• a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port sampling clocks
• a clock for the USB controller
These clocks are enabled or disabled depending on the power reduction mode as detailed in Section “Power Management”, page 155.
Figure 5-1. Oscillator Block Diagram

5.2 Oscillator

Two types of clock sources can be used for CPU:
• Crystal oscillator on X1 and X2 pins: Up to 32 MHz (Amplifier Bandwidth)
• External clock on X1 pin: Up to 48MHz
14
4337K–USB–04/08

5.3 PLL

VSS
X1
X2
Q
C1
C2
PLLEN
PLLCON.1
N3:0
N divider
R divider
VCO USB Clock
US B clk
OSC clk R 1+( )×
N 1+
-----------------------------------------------=
PFLD
PLOCK
PLLCON.0
PLLF
CHP
Vref
Up
Down
R3:0
USB
CLOCK
USB Clock Symbol

5.3.1 PLL Description

AT89C5130A/31A-M
In order to optimize the power consumption, the oscillator inverter is inactive when the PLL out­put is not selected for the USB device.
Figure 5-2. Crystal Connection
The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to generate the USB interface clock. Figure 5-3 shows the internal structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the comparison between the reference clock coming from the N divider and the reverse clock com­ing from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Figure 5-3) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by inject­ing or extracting charges from the external filter connected on PLLF pin (see Figure 5-4). Value of the filter components are detailed in the Section “DC Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V the charge pump. It generates a square wave signal: the PLL clock.
Figure 5-3. PLL Block Diagram and Symbol
produced by
REF
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15
AT89C5130A/31A-M
Figure 5-4. PLL Filter Connection
VSS
PLLF
R
C1
C2
VSS
PLL
Programming
Configure Dividers
N3:0 = xxxxb R3:0 = xxxxb
Enable PLL
PLLEN = 1
PLL Locked?
LOCK = 1?
The typical values are: R = 100 , C1 = 10 nf, C2 = 2.2 nF.

5.3.2 PLL Programming

The PLL is programmed using the flow shown in Figure 5-5. As soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable.
Figure 5-5. PLL Programming Flow

5.3.3 Divider Values

To generate a 48 MHz clock using the PLL, the divider values have to be configured following the oscillator frequency. The typical divider values are shown in
Table 5-1. Typical Divider Values
16
Table 5-1.
Oscillator Frequency R+1 N+1 PLLDIV
3 MHz 16 1 F0h
6 MHz 8 1 70h
8 MHz 6 1 50h
12 MHz 4 1 30h
16 MHz 3 1 20h
18 MHz 8 3 72h
20 MHz 12 5 B4h
24 MHz 2 1 10h
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5.4 Registers

AT89C5130A/31A-M
Oscillator Frequency R+1 N+1 PLLDIV
32 MHz 3 2 21h
40 MHz 12 10 B9h
Table 5-2. CKCON0 (S:8Fh)
Clock Control Register 0
7 6 5 4 3 2 1 0
TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit Number
7 TWIX2
6 WDX2
5 PCAX2
4 SIX2
3 T2X2
Bit
Mnemonic Description
TWI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Watchdog Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2) This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Timer2 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
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2 T1X2
1 T0X2
0 X2
Timer1 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Timer0 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
System Clock Control bit
Clear to select 12 clock periods per machine cycle (STD mode, F F
/
2).
OSC
Set to select 6 clock periods per machine cycle (X2 mode, F
= F
CPU
PER =
CPU = FPER = FOSC
).
17
AT89C5130A/31A-M
Reset Value = 0000 0000b
Table 5-3. CKCON1 (S:AFh)
Clock Control Register 1
7 6 5 4 3 2 1 0
- - - - - - - SPIX2
Bit Number
7-1 -
0 SPIX2
Bit
Mnemonic Description
Reset Value = 0000 0000b
Table 5-4. PLLCON (S:A3h)
PLL Control Register
7 6 5 4 3 2 1 0
- - - - - EXT48 PLLEN PLOCK
Bit Number
7-3 -
2 EXT48
Bit
Mnemonic Description
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Reserved
The value read from this bit is always 0. Do not set this bit.
External 48 MHz Enable Bit
Set this bit to bypass the PLL and disable the crystal oscillator. Clear this bit to select the PLL output as USB clock and to enable the crystal oscillator.
Reset Value = 0000 0000b
Table 5-5. PLLDIV (S:A4h)
18
PLL Enable Bit
1 PLLEN
0 PLOCK
Set to enable the PLL. Clear to disable the PLL.
PLL Lock Indicator
Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked.
PLL Divider Register
7 6 5 4 3 2 1 0
R3 R2 R1 R0 N3 N2 N1 N0
4337K–USB–04/08
AT89C5130A/31A-M
Bit Number
7-4 R3:0 PLL R Divider Bits
3-0 N3:0 PLL N Divider Bits
Bit
Mnemonic Description
Reset Value = 0000 0000
4337K–USB–04/08
19
AT89C5130A/31A-M

6. SFR Mapping

The Special Function Registers (SFRs) of the AT89C5130A/31A-M fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP
• I/O port registers: P0, P1, P2, P3, P4
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• PCA (Programmable Counter Array) registers: CCON, CMOD, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4)
• Power and clock control registers: PCON
• Hardware Watchdog Timer registers: WDTRST, WDTPRG
• Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• LED register: LEDCON
• Two Wire Interface (TWI) registers: SSCON, SSCS, SSDAT, SSADR
• Serial Port Interface (SPI) registers: SPCON, SPSTA, SPDAT
• USB registers: Uxxx (17 registers)
• PLL registers: PLLCON, PLLDIV
• BRG (Baud Rate Generator) registers: BRL, BDRCON
• Flash register: FCON (FCON access is reserved for the Flash API and ISP software)
• EEPROM register: EECON
• Others: AUXR, AUXR1, CKCON0, CKCON1
20
4337K–USB–04/08
The table below shows all SFRs with their address and their reset value.
Reserved
Table 6-1. SFR Descriptions
Bit
Addressable Non-Bit Addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
AT89C5130A/31A-M
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
UEPINT
0000 0000
B
0000 0000
ACC
0000 0000
CCON
00X0 0000
PSW
0000 0000
T2CON
0000 0000
P4
XXXX 1111
IPL0
X000 000
P3
1111 1111
CH
0000 0000
LEDCON
0000 0000
CL
0000 0000
CMOD
00XX X000
FCON (1)
XXXX 0000
T2MOD
XXXX XX00
SADEN
0000 0000
IEN1
X0XX X000
CCAP0H
XXXX XXXX
CCAP0L
XXXX XXXX
UBYCTLX 0000 0000
CCAPM0
X000 0000
EECON
XXXX XX00
RCAP2L
0000 0000
UEPIEN
0000 0000
UFNUML
0000 0000
IPL1
X0XX X000
CCAP1H
XXXX XXXX
CCAP1L
XXXX XXXX
UBYCTHX 0000 0000
CCAPM1
X000 0000
RCAP2H
0000 0000
SPCON
0001 0100
UFNUMH
0000 0000
IPH1
X0XX X000
CCAP2H
XXXX XXXX
CCAP2L
XXXX XXXX
CCAPM2
X000 0000
UEPCONX 1000 0000
TL2
0000 0000
SPSTA
0000 0000
USBCON
0000 0000
CCAP3H
XXXX XXXX
CCAP3L
XXXX XXXX
CCAPM3
X000 0000
UEPRST
0000 0000
TH2
0000 0000
SPDAT
XXXX XXXX
USBINT
0000 0000
CCAP4H
XXXX XXXX
CCAP4L
XXXX XXXX
CCAPM4
X000 0000
UEPSTAX
0000 0000
USBADDR 1000 0000
USBIEN
0000 0000
UEPDATX 0000 0000
UEPNUM
0000 0000
IPH0
X000 0000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
A8h
A0h
98h
90h
88h
80h
IEN0
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
SADDR
0000 0000
SBUF
XXXX XXXX
TMOD
0000 0000
SP
0000 0111
AUXR1
XXXX X0X0
BRL
0000 0000
TL0
0000 0000
DPL
0000 0000
PLLCON
XXXX XX00
BDRCON
XXX0 0000
SSCON
0000 0000
TL1
0000 0000
DPH
0000 0000
PLLDIV
0000 0000
0000 0000
1111 1000
0000 0000
Note: 1. FCON access is reserved for the Flash API and ISP software.
4337K–USB–04/08
KBLS
SSCS
TH0
KBE
0000 0000
SSDAT
1111 1111
TH1
0000 0000
WDTRST
XXXX XXXX
KBF
0000 0000
SSADR
1111 1110
AUXR
XX0X 0000
CKCON1
0000 0000
WDTPRG
XXXX X000
CKCON0
0000 0000
PCON
00X1 0000
AFh
A7h
9Fh
97h
8Fh
87h
21
AT89C5130A/31A-M
The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories:
Table 6-2. C51 Core SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
ACC E0h Accumulator
B F0h B Register
PSW D0h
SP 81h
DPL 82h
DPH 83h
Table 6-3. I/O Port SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
P0 80h Port 0
P1 90h Port 1
P2 A0h Port 2
P3 B0h Port 3
P4 C0h Port 4 (2bits)
Program Status Word
Stack Pointer
LSB of SPX
Data Pointer Low byte
LSB of DPTR
Data Pointer High byte
MSB of DPTR
Table 6-4. Timer SFR’s
Mnemonic Add Name 7 6 5 4 3 2 1 0
TH0 8Ch Timer/Counter 0 High byte
TL0 8Ah Timer/Counter 0 Low byte
TH1 8Dh Timer/Counter 1 High byte
TL1 8Bh Timer/Counter 1 Low byte
TH2 CDh Timer/Counter 2 High byte
TL2 CCh Timer/Counter 2 Low byte
TCON 88h
TMOD 89h
T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MOD C9h Timer/Counter 2 Mode T2OE DCEN
Timer/Counter 0 and 1 control
Timer/Counter 0 and 1 Modes
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
22
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AT89C5130A/31A-M
Table 6-4. Timer SFR’s (Continued)
Mnemonic Add Name 7 6 5 4 3 2 1 0
RCAP2H CBh
RCAP2L CAh
WDTRST A6h WatchDog Timer Reset
WDTPRG A7h WatchDog Timer Program S2 S1 S0
Timer/Counter 2 Reload/Capture High byte
Timer/Counter 2 Reload/Capture Low byte
Table 6-5. Serial I/O Port SFR’s
Mnemonic Add Name 7 6 5 4 3 2 1 0
SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADEN B9h Slave Address Mask
SADDR A9h Slave Address
Table 6-6. Baud Rate Generator SFR’s
Mnemonic Add Name 7 6 5 4 3 2 1 0
BRL 9Ah Baud Rate Reload
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC
Table 6-7. PCA SFR’s
Mnemo­nic Add Name 7 6 5 4 3 2 1 0
CCON D8h PCA Timer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA Timer/Counter Mode CIDL WDTE CPS1 CPS0 ECF
CL E9h PCA Timer/Counter Low byte
CH F9h PCA Timer/Counter High byte
CCAPM 0
CCAPM 1
CCAPM 2
CCAPM 3
CCAPM 4
DAh
PCA Timer/Counter Mode 0
DBh
PCA Timer/Counter Mode 1
DCh
PCA Timer/Counter Mode 2
DDh
PCA Timer/Counter Mode 3
DEh
PCA Timer/Counter Mode 4
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
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23
AT89C5130A/31A-M
Table 6-7. PCA SFR’s
Mnemo­nic Add Name 7 6 5 4 3 2 1 0
CCAP0 H
CCAP1 H
CCAP2 H
CCAP3 H
CCAP4 H
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
PCA Compare Capture Module 0 H
PCA Compare Capture Module 1
FAh
H
FBh
PCA Compare Capture Module 2
FCh
H
FDh
PCA Compare Capture Module 3
FEh
H
PCA Compare Capture Module 4 H
PCA Compare Capture Module 0 L
PCA Compare Capture Module 1
EAh
L
EBh
PCA Compare Capture Module 2
ECh
L
EDh
PCA Compare Capture Module 3
EEh
L
PCA Compare Capture Module 4 L
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
Table 6-8. Interrupt SFR’s
Mnemo­nic Add Name 7 6 5 4 3 2 1 0
IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1 B1h Interrupt Enable Control 1 EUSB ESPI ETWI EKB
IPL0 B8h Interrupt Priority Control Low 0 PPCL PT2L PSL PT1L PX1L PT0L PX0L
IPH0 B7h Interrupt Priority Control High 0 PPCH PT2H PSH PT1H PX1H PT0H PX0H
IPL1 B2h Interrupt Priority Control Low 1 PUSBL PSPIL PTWIL PKBL
IPH1 B3h Interrupt Priority Control High 1 PUSBH PSPIH PTWIH PKBH
Table 6-9. PLL SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
PLLCON A3h PLL Control EXT48 PLLEN PLOCK
PLLDIV A4h PLL Divider R3 R2 R1 R0 N3 N2 N1 N0
Table 6-10. Keyboard SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
KBF 9Eh
KBE 9Dh
Keyboard Flag Register
Keyboard Input Enable Register
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
24
4337K–USB–04/08
AT89C5130A/31A-M
Table 6-10. Keyboard SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
KBLS 9Ch
Keyboard Level Selector Register
KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
Table 6-11. TWI SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
SSCON 93h
SSCS 94h
SSDAT 95h
SSADR 96h
Synchronous Serial Control
Synchronous Serial Control-Status
Synchronous Serial Data
Synchronous Serial Address
CR2 SSIE STA STO SI AA CR1 CR0
SC4 SC3 SC2 SC1 SC0 - - -
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
A7 A6 A5 A4 A3 A2 A1 A0
Table 6-12. SPI SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
SPCON C3h
SPSTA C4h
Serial Peripheral Control
Serial Peripheral Status-Control
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPIF WCOL SSERR MODF - - - -
SPDAT C5h Serial Peripheral Data R7 R6 R5 R4 R3 R2 R1 R0
Table 6-13. USB SFR’s
Mnemonic Add Name 7 6 5 4 3 2 1 0
USBCON BCh USB Global Control USBE SUSPCLK
USBADDR C6h USB Address FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
USBINT BDh USB Global Interrupt - - WUPCPU EORINT SOFINT - - SPINT
USBIEN BEh
UEPNUM C7h USB Endpoint Number - - - - EPNUM3 EPNUM2 EPNUM1 EPNUM0
UEPCONX D4h USB Endpoint X Control EPEN - - - DTGL EPDIR EPTYPE1 EPTYPE0
UEPSTAX CEh USB Endpoint X Status DIR RXOUTB1 STALLRQ TXRDY STLCRC RXSETUP RXOUTB0 TXCMP
UEPRST D5h USB Endpoint Reset - EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST
UEPINT F8h USB Endpoint Interrupt - EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
UEPIEN C2h
UEPDATX CFh
USB Global Interrupt Enable
USB Endpoint Interrupt Enable
USB Endpoint X FIFO Data
- -
- EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE
FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0
SDRMWU
P
EWUPCP
U
DETACH UPRSM RMWUPE CONFG FADDEN
EEORINT ESOFINT - - ESPINT
4337K–USB–04/08
25
AT89C5130A/31A-M
Table 6-13. USB SFR’s
Mnemonic Add Name 7 6 5 4 3 2 1 0
UBYCTLX E2h
UBYCTHX E3h
UFNUML BAh
UFNUMH BBh
USB Byte Counter Low (EP X)
USB Byte Counter High (EP X)
USB Frame Number Low
USB Frame Number High
BYCT7 BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0
- - - - - BYCT10 BYCT9 BYCT8
FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0
- - CRCOK CRCERR - FNUM10 FNUM9 FNUM8
Table 6-14. Other SFR’s
Mnemonic Add Name 7 6 5 4 3 2 1 0
PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 DPU - M0 - XRS1 XRS2 EXTRAM A0
AUXR1 A2h Auxiliary Register 1 - - ENBOOT - GF3 - - DPS
CKCON0 8Fh Clock Control 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
CKCON1 AFh Clock Control 1 - - - - - - - SPIX2
LEDCON F1h LED Control LED3 LED2 LED1 LED0
FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY
EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY
26
4337K–USB–04/08

7. Dual Data Pointer Register

External Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
The additional data pointer can be used to speed up code execution and reduce code size.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 7-1) that allows the program code to switch between them (see Figure 7-1).
Figure 7-1. Use of Dual Pointer
AT89C5130A/31A-M
Table 7-1. AUXR1 Register
AUXR1- Auxiliary Register 1(0A2h)
7 6 5 4 3 2 1 0
- - ENBOOT - GF3 0 - DPS
Bit
Number
7 -
6 -
5 ENBOOT
4 -
3 GF3 This bit is a general-purpose user flag.
2 0 Always cleared.
1 -
0 DPS
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Boot Flash
Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Cleared to select DPTR0. Set to select DPTR1.
4337K–USB–04/08
Reset Value = XX[BLJB
]X X0X0b
Not bit addressable
a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
27
AT89C5130A/31A-M
ASSEMBLY LANGUAGE
; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc­tion (INC AUXR1), the routine will exit with DPS in the opposite state.
28
4337K–USB–04/08

8. Program/Code Memory

0000h
32 Kbytes
7FFFh
Flash
32 Kbytes
External Code
FFFFh
AT89C5131A
8000h
0000h
16 Kbytes
3FFFh
Flash
48 Kbytes
External Code
FFFFh
AT89C5130A
4000h
The AT89C5130A/31A-M implement 16/ 32 Kbytes of on-chip program/code memory. Figure 8­1 shows the split of internal and external program/code memory spaces depending on the product.
The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard V ory can be progra m m ed u s i ng o n ly o n e vo l t a ge and a l l o ws I n- a p p l i cation Softwa r e Programming commonly known as IAP. Hardware programming mode is also available using specific programming tool.
Figure 8-1. Program/Code Memory Organization
AT89C5130A/31A-M
voltage. Thus, the Flash Mem-
DD
Note: If the program executes exclusively from on-chip code memory (not from external memory),
beware of executing code from the upper byte of on-chip memory (3FFFh/7FFFh) and thereby disrupting I/O Ports 0 and 2 due to external prefetch. Fetching code constant from this location does not affect Ports 0 and 2.

8.1 External Code Memory Access

8.1.1 Memory Interface

The external memory interface comprises the external bus (Port 0 and Port 2) as well as the bus control signals (PSEN, and ALE).
Figure 8-2 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 8-1 describes the exter­nal memory interface signals.
4337K–USB–04/08
29
AT89C5130A/31A-M
Figure 8-2. External Code Memory Interface Structure
Flash
EPROM
AT89C5130A
AT89C5131
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
Latch
OEPSEN
ALE
P0
P2
PSEN
PCL
PCHPCH
PCLD7:0 D7:0
PCH
D7:0
CPU Clock
Table 8-1. External Data Memory Interface Signals

8.1.2 External Bus Cycles

This section describes the bus cycles the AT89C5130A/31A-M executes to fetch code (see Figure 8-3) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock peri­ods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode (see the clock Section).
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information.
Signal
Name Type Description
A15:8 O
AD7:0 I/O
ALE O
PSEN O
Address Lines
Upper address lines for the external bus.
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE signals indicates that valid address information are available on lines AD7:0.
Program Store Enable Output
This signal is active low during external code fetch or external code read (MOVC instruction).
Alternate Function
P2.7:0
P0.7:0
-
-
Figure 8-3. External Code Fetch Waveforms
30
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