– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode
– Dual Data Pointer
– Full-duplex Enhanced UART (EUART)
– Three 16-bit Timer/Counters: T0, T1 and T2
– 256 Bytes of Scratchpad RAM
• 16/32-Kbyte On-chip Flash EEPROM In-System Programming through USB
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
• 3-KbyteFlash EEPROM for Bootloader
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
• 1-Kbyte EEPROM Data (
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
• On-chip Expanded RAM (ERAM): 1024 Bytes
• Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
• USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers: 32-byte FIFO
– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
• Endpoint 1, 2, 3: 32-byte FIFO
• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)
• Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode)
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz DPLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
Output, Compare/Capture, PWM and Watchdog Timer Capabilities
• Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 50 ms to
6s at 4 MHz
• Keyboard Interrupt Interface on Port P1 (8 Bits)
• TWI (Two Wire Interface) 400Kbit/s
• SPI Interface (Master/Slave Mode)
• 34 I/O Pins
• 4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical
• 4-level Priority Interrupt System (11 sources)
• Idle and Power-down Modes
• 0 to 32 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis
• Industrial Temperature Range
• Low Voltage Range Supply: 2.7V to 3.6V (3.0V to 3.6V required for USB)
• Packages: SO28, PLCC52, VQFP64
8-bit Flash
Microcontroller
with Full Speed
USB Device
AT89C5131A-L
Rev. 4338F–USB–08/07
AT89C5131A-L
Description
AT89C5131A-L is a high-performance Flash version of the 80C51 single-chip 8-bit
microcontrollers with full speed USB functions.
AT89C5131A-L features a full-speed USB module compatible with the USB specifications Version 1.1 and 2.0. This module integrates the USB transceivers with a 3.3V
voltage regulator and the Serial Interface Engine (SIE) with Digital Phase Locked Loop
and 48 MHz clock recovery. USB Event detection logic (Reset and Suspend/Resume)
and FIFO buffers supporting the mandatory control Endpoint (EP0) and up to 6 versatile
Endpoints (EP1/EP2/EP3/EP4/EP5/EP6) with minimum software overhead are also part
of the USB module.
AT89C5131A-L retains the features of the Atmel 80C52 with extended Flash capacity
(3 2 -Kbyt e), 256 b ytes of int ernal R AM, a 4-l evel int errup t syste m, two 16 -bit
timer/counters (T0/ T1), a full duplex enhanced U ART (EUART) and an on-chip
oscillator.
In addition, AT89C5131A-L has an on-chip expanded RAM of 1024 bytes (ERAM), a
dual- data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA),
up to 4 programmable LED current sources, a programmable hardware watchdog and a
power-on reset.
AT89C5131A-L has two software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the
serial ports and the interrupt system are still operating. In the power-down mode the
RAM is saved, the peripheral clock is frozen, but the device has full wake-up capability
through USB events or external interrupts.
2
4338F–USB–08/07
Block Diagram
Timer 0
INT
RAM
256x8
T0
T1
RxD
TxD
WR
RD
EA
PSEN
ALE
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2)(2) (2)
Port 0P0Port 1
Port 2
Port 3
Parallel I/O Ports & Ext. Bus
P1
P2
P3
ERAM
1Kx8
PCA
RST
Watch
Dog
CEX
ECI
VSS
VDD
(2)(2)
(1)(1)
Timer2
T2EX
T2
(1)
(1)
Port 4
P4
32Kx8 Flash
+
BRG
USB
D -
D +
VREF
Regu-
Key
Board
KIN
lator
AVSS
EEPROM
4Kx8
SPI
MISO
MOSI
SCK
(1) (1) (1)
SS
(1)
AVDD
TWI
SCL
SDA
AT89C5131A-L
Notes:1. Alternate function of Port 1
2. Alternate function of Port 3
3. Alternate function of Port 4
4338F–USB–08/07
3
AT89C5131A-L
Pinout Description
21 222625242329282730 31
5 4 3 2 1 6
52 51 50 49 48
8
9
10
11
12
13
14
15
16
17
18
46
45
44
43
42
41
40
39
38
37
36
PLCC52
7
47
19
20
32 33
34
35
P1.1/T2EX/KIN1/SS
P1.0/T2/KIN0
P0.6/AD6
ALE
P0.7/AD7
EA
PSEN
P1.7/CEX4/KIN7/MOSI
P1.3/CEX0/KIN3
P1.5/CEX2/KIN5/MISO
P1.6/CEX3/KIN6/SCK
PLLF
P3.0/RxD
AVSS
P2.6/A14
XTAL1
P2.5/A13
P0.3/AD3
P0.5/AD5
P0.4/AD4
VREF
P0.2/AD2
P0.0/AD0
P0.1/AD1
AVDD
NC
P3.2/INT0
P3.6/WR/LED2
XTAL2
RST
P3.1/TxD
P3.3/INT1/LED0
P3.7/RD/LED3
D-
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
VSS
P2.4/A12
P4.1/SDA
D+
P4.0/SCL
P1.2/ECI/KIN2
P1.4/CEX1/KIN4
P3.4/T0
P3.5/T1/LED1
NC
NC
VDD
NC
P2.7/A15
Pinout
Figure 1. AT89C5131A-L 52-pin PLCC Pinout
4
4338F–USB–08/07
Figure 2. AT89C5131A-L 64-pin VQFP Pinout
17 182221201925242326 27
62 61 60 59 58 63
57 56 55 54 53
1
2
3
4
5
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
39
38
VQFP64
64
52
12
13
28
29
36
37
51 50
49
35
33
34
14
15
16
30
31 32
P1.1/T2EX/KIN1/SS
ALE
EA
PSEN
P1.7/CEX4/KIN7/MOSI
P1.3/CEX0/KIN3
P1.5/CEX2/KIN5/MISO
P1.6/CEX3/KIN6/SCK
P2.7/A15
P2.6/A14
P4.1/SDA
P1.2/ECI/KIN2
P1.4/CEX1/KIN4
P1.0/T2/KIN0
PLLF
NC
XTAL2
RST
P3.7/RD/LED3
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
NC
NC
P3.0/RxD
NC
VREF
P0.0/AD0
AVSS
P3.2/INT0
P3.6/WR/LED2
P3.1/TxD
P3.3/INT1/LED0
VSS
P3.4/T0
P3.5/T1/LED1
NC
P0.6/AD6
P0.7/AD7
P2.5/A13
P0.3/AD3
P0.5/AD5
P0.4/AD4
P0.2/AD2
P0.1/AD1
D-
D+
P4.0/SCL
XTAL1
AVDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
P1.1/T2EX/KIN1/SS
PLLF
P3.0/RxD
P1.0/T2/KIN0
AVSS
VDD
XTAL1
XTAL2
P3.2/INT0
P3.5/T1/LED1
P3.6/WR/LED2
P3.7/RD/LED3
D-
P1.4/CEX1/KIN4
VSS
D+
P1.2/ECI/KIN2
P1.3/CEX0/KIN3
P1.5/CEX2/KIN5/MISO
RST
P1.6/CEX3/KIN6/SCK
P1.7/CEX4/KIN7/MOSI
P4.0/SCL
VREFP3.1/TxD
P3.4/T0
1
2
3
4
5
6
7
8
9
10
11
12
28
27
26
25
24
23
22
21
20
19
18
17
SO28
13
14
16
15
P4.1/SDA
P3.3/INT1/LED0
AT89C5131A-L
4338F–USB–08/07
Figure 3. AT89C5131A-L 28-pin SO Pinout
5
AT89C5131A-L
Signals
All the AT89C5131A-L signals are detailed by functionality on Table 1 through Table 12.
Table 1. Keypad Interface Signal Description
Signal
NameType Description
KIN[7:0)I
Keypad Input Lines
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt if enabled. Held line is reported in the KBCON register.
Table 2. Programmable Counter Array Signal Description
Signal
NameType Description
ECIIExternal Clock InputP1.2
Capture External Input
CEX[4:0]I/O
Compare External Output
Table 3. Serial I/O Signal Description
Signal
NameType Description
RxDI
Serial Input
The serial input for Extended UART.
Alternate
Function
P1[7:0]
Alternate
Function
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate
Function
P3.0
TxDO
Serial Output
The serial output for Extended UART.
Table 4. Timer 0, Timer 1 and Timer 2 Signal Description
Signal
NameType Description
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by GATE0
bit in TCON register.
INT0I
INT1I
External Interrupt 0
INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits
IE0 are set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by
a low level on INT0.
Timer 1 Gate Input
INT1 serves as external run control for Timer 1, when selected by GATE1
bit in TCON register.
External Interrupt 1
INT1 input set IE1 in the TCON register. If bit IT1 in this register is set, bits
IE1 are set by a falling edge on INT1. If bit IT1 is cleared, bits IE1 is set by
a low level on INT1.
P3.1
Alternate
Function
P3.2
P3.3
6
4338F–USB–08/07
AT89C5131A-L
Table 4. Timer 0, Timer 1 and Timer 2 Signal Description (Continued)
Signal
NameType Description
Alternate
Function
T0I
T1I
T2
T2EXITimer/Counter 2 Reload/Capture/Direction Control InputP1.1
Timer Counter 0 External Clock Input
When Timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
Timer/Counter 1 External Clock Input
When Timer 1 operates as a counter, a falling edge on the T1 pin
increments the count.
IOTimer/Counter 2 External Clock Input
Timer/Counter 2 Clock Output
Table 5. LED Signal Description
Signal
NameType Description
Direct Drive LED Output
LED[3:0]O
These pins can be directly connected to the Cathode of standard LEDs
without external current limiting resistors. The typical current of each
output can be programmed by software to 2, 6 or 10 mA. Several outputs
can be connected together to get higher drive capabilities.
Table 6. TWI Signal Description
Signal
NameType Description
P3.4
P3.5
P1.0
Alternate
Function
P3.3
P3.5
P3.6
P3.7
Alternate
Function
SCLI/O
SDAI/O
SCL: TWI Serial Clock
SCL output the serial clock to slave peripherals.
SCL input the serial clock from master.
SDA: TWI Serial Data
SCL is the bidirectional TWI data line.
Table 7. SPI Signal Description
Signal
NameType Description
SSI/OSS: SPI Slave SelectP1.1
MISO: SPI Master Input Slave Output line
MISOI/O
SCKI/O
MOSI
When SPI is in master mode, MISO receives data from the slave
peripheral. When SPI is in slave mode, MISO outputs data to the master
controller.
SCK: SPI Serial Clock
SCK outputs clock to the slave peripheral or receive clock from the master
MOSI: SPI Master Output Slave Input line
I/O
When SPI is in master mode, MOSI outputs data to the slave peripheral.
When SPI is in slave mode, MOSI receives data from the master controller
P4.0
P4.1
Alternate
Function
P1.5
P1.6
P1.7
4338F–USB–08/07
7
AT89C5131A-L
Table 8. Ports Signal Description
Signal
NameTypeDescriptionAlternate Function
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0
P0[7:0]I/O
P1[7:0]I/O
pins that have 1s written to them float and can be used
as high impedance inputs. To avoid any parasitic current
consumption, Floating P0 inputs must be pulled to V
VSS.
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
DD
or
AD[7:0]
KIN[7:0]
T2
T2EX
ECI
CEX[4:0]
P2[7:0]I/O
P3[7:0]I/O
P4[1:0]I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 4
P4 is an 2-bit open port.
Table 9. Clock Signal Description
Signal
NameType Description
XTAL1I
XTAL2O
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, its output is connected to this pin.
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, leave XTAL2 unconnected.
A[15:8]
LED[3:0]
RxD
TxD
INT0
INT1
T0
T1
WR
RD
SCL
SDA
Alternate
Function
-
-
8
PLLFI
PLL Low Pass Filter input
Receives the RC network of the PLL low pass filter (See Figure 4 on page
11 ).
4338F–USB–08/07
-
Table 10. USB Signal Description
AT89C5131A-L
Signal
NameType Description
D+I/O
D-I/O
VREFO
USB Data + signal
Set to high level under reset.
USB Data - signal
Set to low level under reset.
USB Reference Voltage
Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function.
Table 11. System Signal Description
Signal
NameType Description
AD[7:0]I/O
A[15:8]I/O
RDI/O
WRI/O
Multiplexed Address/Data LSB for external access
Data LSB for Slave port access (used for 8-bit and 16-bit modes)
Address Bus MSB for external access
Data MSB for Slave port access (used for 16-bit mode only)
Read Signal
Read signal asserted during external data memory read operation.
Control input for slave port read access cycles.
Write Signal
Write signal asserted during external data memory write operation.
Control input for slave write access cycles.
Alternate
Function
-
-
-
Alternate
Function
P0[7:0]
P2[7:0]
P3.7
P3.6
RST I/O
ALEO
PSENO
EAI
Reset
Holding this pin low for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than VIL is applied, whether or not the oscillator is running.
This pin has an internal pull-up resistor which allows the device to be reset
by connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-down mode returns
the chip to normal operation.
This pin is set to 0 for at least 12 oscillator periods when an internal reset
occurs (hardware watchdog or Power monitor).
Address Latch Enable Output
The falling edge of ALE strobes the address into external latch. This signal
is active only when reading or writing external memory using MOVX
instructions.
Program Strobe Enable / Hardware conditions Input for ISP
Used as input under reset to detect external hardware conditions of ISP
mode
External Access Enable
This pin must be held low to force the device to fetch code from external
program memory starting at address 0000h. It is latched during reset and
cannot be dynamically changed during operation.
-
-
-
-
4338F–USB–08/07
9
AT89C5131A-L
Table 12. Power Signal Description
Signal
NameType Description
Alternate
Function
AVSSGND
AVDDPWR
VSSGND
VDDPWR
VREFO
Alternate Ground
AVSS is used to supply the on-chip PLL and the USB PAD.
Alternate Supply Voltage
AVDD is used to supply the on-chip PLL and the USB PAD.
Digital Ground
VSS is used to supply the buffer ring and the digital core.
Digital Supply Voltage
VDD is used to supply the buffer ring on all versions of the device.
It is also used to power the on-chip voltage regulator of the Standard
versions or the digital core of the Low Power versions.
USB pull-up Controlled Output
VREF is used to control the USB D+ 1.5 kΩ pull up.
The Vref output is in high impedance when the bit DETACH is set in the
USBCON register.
-
-
-
-
-
10
4338F–USB–08/07
Typical Application
VSS
XTAL1
XTAL2
Q
22pF
22pF
VSS
PLLF
100R
10nF
2.2nF
VSS
VSS
AVSS
VSS
D-
D+
27R
27R
VRef
1.5K
USB
D+
D-
VBUS
GND
VSS
VDD
AVDD
VDD
4.7µF
VSS
100nF
VSS
100nF
VSS
AT89C5131A-L
Recommended External components
All the external components described in the figure below must be implemented as
close as possible from the microcontroller package.
The following figure represents the typical wiring schematic.
Figure 4. Typical Application
AT89C5131A-L
4338F–USB–08/07
11
AT89C5131A-L
PCB Recommandations
D+
VRef
D-
USB Connector
Wires must be routed in Parallel and
Components must be
If possible, isolate D+ and D- signals from other signals
with ground wires
must be as short as possible
close to the
microcontroller
PLLFAVss
Components must be
Isolate filter components
with a ground wire
microcontroller
close to the
C2
C1
R
Figure 5. USB Pads
Figure 6. USB PLL
12
4338F–USB–08/07
Clock Controller
X1
X2
PD
PCON.1
IDL
PCON.0
Peripheral
CPU Core
0
1
X2
CKCON.0
÷
2
Clock
Clock
EXT48
PLLCON.2
0
1
PLL
USB
Clock
AT89C5131A-L
Introduction
Figure 7. Oscillator Block Diagram
The AT89C5131A-L clock controller is based on an on-chip oscillator feeding an on-chip
Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller.
The AT89C5131A-L X1 and X2 pins are the input and the output of a single-stage onchip inverter (see Figure 7) that can be configured with off-chip components as a Pierce
oscillator (see Figure 8). Value of capacitors and crystal characteristics are detailed in
the section “DC Characteristics”.
The X1 pin can also be used as input for an external 48 MHz clock.
The clock controller outputs three different clocks as shown in Figure 7:
•a clock for the CPU core
•a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port
sampling clocks
•a clock for the USB controller
These clocks are enabled or disabled depending on the power reduction mode as
detailed in Section “Power Management”, page 152.
Oscillator
4338F–USB–08/07
Two clock sources are available for CPU:
•Crystal oscillator on X1 and X2 pins: Up to 32 MHz
•External 48 MHz clock on X1 pin
In order to optimize the power consumption, the oscillator inverter is inactive when the
PLL output is not selected for the USB device.
13
AT89C5131A-L
Figure 8. Crystal Connection
VSS
X1
X2
Q
C1
C2
PLLEN
PLLCON.1
N3:0
N divider
R divider
VCOUSB Clock
US Bclk
OSCclkR1+()×
N1+
-----------------------------------------------=
OSC
CLOCK
PFLD
PLOCK
PLLCON.0
PLLF
CHP
Vref
Up
Down
R3:0
USB
CLOCK
USB Clock Symbol
VSS
PLLF
R
C1
C2
VSS
PLL
PLL DescriptionThe AT89C5131A-L PLL is used to generate internal high frequency clock (the USB
Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL
clock is used to generate the USB interface clock. Figure 9 shows the internal structure
of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register (see Figure 9) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PLLF pin (see
Figure 10 ) . Value o f the fil ter c o m p onents a r e d etailed i n t h e Section “ D C
Characteristics”.
Figure 9. PLL Block Diagram and Symbol
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V
duced by the charge pump. It generates a square wave signal: the PLL clock.
Figure 10. PLL Filter Connection
The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF.
REF
pro-
14
4338F–USB–08/07
AT89C5131A-L
PLL
Programming
Configure Dividers
N3:0 = xxxxb
R3:0 = xxxxb
Enable PLL
PLLEN = 1
PLL Locked?
LOCK = 1?
PLL ProgrammingThe PLL is programmed using the flow shown in Figure 11. As soon as clock generation
is enabled user must wait until the lock indicator is set to ensure the clock output is
stable.
Figure 11. PLL Programming Flow
Divider ValuesTo generate a 48 MHz clock using the PLL, the divider values have to be configured fol-
lowing the oscillator frequency. The typical divider values are shown in Table 13.
Table 13. Typical Divider Values
Oscillator FrequencyR+1N+1PLLDIV
3 MHz161F0h
6 MHz8170h
8 MHz6150h
12 MHz4130h
16 MHz3120h
18 MHz8372h
20 MHz125B4h
24 MHz2110h
32 MHz3221h
40 MHz1210B9h
4338F–USB–08/07
15
AT89C5131A-L
Registers
Table 14. CKCON0 (S:8Fh)
Clock Control Register 0
76543210
TWIX2WDX2PCAX2SIX2T2X2T1X2T0X2X2
Bit Number
7TWIX2
6WDX2
5PCAX2
4SIX2
3T2X2
Bit
Mnemonic Description
TWI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Watchdog Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2)
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer2 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
16
Timer1 Clock
2T1X2
1T0X2
0X2
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer0 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
System Clock Control bit
Clear to select 12 clock periods per machine cycle (STD mode, F
F
OSC
Set to select 6 clock periods per machine cycle (X2 mode, F
Reset Value = 0000 0000b
= F
CPU
/
2).
CPU = FPER = FOSC
PER =
).
4338F–USB–08/07
AT89C5131A-L
Table 15. CKCON1 (S:AFh)
Clock Control Register 1
76543210
-------SPIX2
Bit Number
7-1-
0SPIX2
Bit
Mnemonic Description
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reset Value = 0000 0000b
Table 16. PLLCON (S:A3h)
PLL Control Register
76543210
-----EXT48PLLENPLOCK
Bit Number
7-3-
2EXT48
Bit
Mnemonic Description
Reserved
The value read from this bit is always 0. Do not set this bit.
External 48 MHz Enable Bit
Set this bit to bypass the PLL and disable the crystal oscillator.
Clear this bit to select the PLL output as USB clock and to enable the crystal
oscillator.
4338F–USB–08/07
PLL Enable Bit
1PLLEN
0PLOCK
Set to enable the PLL.
Clear to disable the PLL.
PLL Lock Indicator
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 32) that allows the program
code to switch between them (see Figure 12).
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Boot Flash
Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
Reset Value = XX[BLJB]X X0X0b
Not bit addressable
4338F–USB–08/07
a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
25
AT89C5131A-L
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
26
4338F–USB–08/07
AT89C5131A-L
0000h
32 Kbytes
7FFFh
Flash
32 Kbytes
External Code
FFFFh
AT89C5131A-L
8000h
Flash
EPROM
AT89C5131
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
Latch
OEPSEN
Program/Code
Memory
The AT89C5131A-L implement 32 Kbytes of on-chip program/code memory. Figure 13
shows the split of internal and external program/code memory spaces depending on the
product.
The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for
programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the Flash Memory can be programmed using only one voltage and allows Inapplication Software Programming commonly known as IAP. Hardware programming
mode is also available using specific programming tool.
Figure 13. Program/Code Memory Organization
Note:If the program executes exclusively from on-chip code memory (not from external mem-
ory), beware of executing code from the upper byte of on-chip memory (7FFFh) and
thereby disrupting I/O Ports 0 and 2 due to external prefetch. Fetching code constant
from this location does not affect Ports 0 and 2.
External Code Memory
Access
Memory InterfaceThe external memory interface comprises the external bus (Port 0 and Port 2) as well as
the bus control signals (PSEN, and ALE).
Figure 14 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 33
describes the external memory interface signals.
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
Program Store Enable Output
This signal is active low during external code fetch or external code read
(MOVC instruction).
Alternate
Function
P2.7:0
P0.7:0
-
-
External Bus CyclesThis section describes the bus cycles the AT89C5131A-L executes to fetch code (see
Figure 15) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further
information on X2 mode (see the clock Section).
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized
form and do not provide precise timing information.
Figure 15. External Code Fetch Waveforms
Flash Memory
Architecture
28
AT89C5131A-L features two on-chip Flash memories:
•Flash memory FM0:
containing 32 Kbytes of program memory (user space) organized into 128-byte
pages,
•Flash memory FM1:
3 Kbytes for bootloader and Application Programming Interfaces (API).
The FM0 supports both parallel programming and Serial In-System Programming (ISP)
whereas FM1 supports only parallel programming by programmers. The ISP mode is
detailed in the “In-System Programming” section.
All Read/Write access operations on Flash memory by user application are managed by
a set of API described in the “In-System Programming” section.
4338F–USB–08/07
Figure 16. Flash Memory Architecture
7FFFh
32 Kbytes
Flash Memory
FM0
0000h
Hardware Security (1 Byte)
Column Latches (128 Bytes)
User Space
Extra Row (128 Bytes)
3 Kbytes
Flash Memory
FM1
Boot Space
FFFFh
F400h
FM1 mapped between FFFFh and
F400h when bit ENBOOT is set in
AUXR1 register
FM0 Memory ArchitectureThe Flash memory is made up of 4 blocks (see Figure 16):
1.The memory array (user space) 32 Kbytes
2.The Extra Row
3.The Hardware security bits
4.The column latch registers
AT89C5131A-L
User SpaceThis space is composed of a 32 Kbytes Flash memory organized in 256 pages of 128
bytes. It contains the user’s application code.
Extra Row (XRow)This row is a part of FM0 and has a size of 128 bytes. The extra row contains informa-
tion for bootloader usage. (see Table 39.Software Registers, page 39)
Hardware Security SpaceThe hardware security space is a part of FM0 and has a size of 1 byte.
The 4 MSB can be read/written by software. The 4 LSB can only be read by software
and written by hardware in parallel mode.
Column LatchesThe column latches, also part of FM0, have a size of full page (128 bytes).
The column latches are the entrance buffers of the three previous memory locations
(user array, XRow and Hardware security byte).
Overview of FM0
Operations
The CPU interfaces to the Flash memory through the FCON register and AUXR1
register.
These registers are used to:
•Map the memory spaces in the adressable space
•Launch the programming of the memory spaces
•Get the status of the Flash memory (busy/not busy)
•Select the Flash memory FM0/FM1.
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a
4338F–USB–08/07
page while bits 14 to 7 are used to select the programming address of the page.
Setting this bit takes precedence on the EXTRAM bit in AUXR register.
29
AT89C5131A-L
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 34. A MOVC instruction is then used for reading these spaces.
Table 34. FM0 Blocks Select Bits
FMOD1FMOD0FM0 Adressable Space
00User (0000h-FFFFh)
01Extra Row(FF80h-FFFFh)
10Hardware Security (0000h)
11reserved
Launching ProgrammingFPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5 followed by A. Table 35 summarizes the memory
spaces to program according to FMOD1:0 bits.
Table 35. Programming Spaces
Write to FCON
OperationFPL3:0FPSFMOD1FMOD0
5X00No action
User
Extra Row
Security
Space
Reserved
AX00
5X01No action
AX01
5X10No action
AX10Write the fuse bits space
5X11No action
AX11No action
Write the column latches in user
space
Write the column latches in extra row
space
The Flash memory enters a busy state as soon as programming is launched. In this
state, the memory is not available for fetching code. Thus to avoid any erratic execution
during programming, the CPU enters Idle mode. Exit is automatically performed at the
end of programming.
Note:Interrupts that may occur during programming time must be disabled to avoid any spuri-
ous exit of the idle mode.
Status of the Flash MemoryThe bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
Selecting FM0/FM1The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped
30
up to F800h.
4338F–USB–08/07
AT89C5131A-L
Column Latches
Loading
Data Load
DPTR = Address
ACC = Data
Exec: MOVX @DPTR, A
Last Byte
to load?
Column Latches Mapping
FPS = 1
Data memory Mapping
FPS = 0
Loading the Column LatchesAny number of data from 1 byte to 128 bytes can be loaded in the column latches. This
provides the capability to program the whole memory by byte, by page or by any number
of bytes in a page.
When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus, no page or
block erase is needed and only the loaded data are programmed in the corresponding
page.
The following procedure is used to load the column latches and is summarized in
Figure 17:
•Map the column latch space by setting FPS bit.
•Load the DPTR with the address to load.
•Load Accumulator register with the data to load.
•Execute the MOVX @DPTR, A instruction.
•If needed loop the three last instructions until the page is completely loaded.
Figure 17. Column Latches Loading Procedure
Programming the Flash Spaces
UserThe following procedure is used to program the User space and is summarized in
Figure 18:
•Load data in the column latches from address 0000h to 7FFFh
(1)
.
•Disable the interrupts.
•Launch the programming by writing the data sequence 50h followed by A0h in
FCON register.
The end of the programming indicated by the FBUSY flag cleared.
•Enable the interrupts.
Note:1. The last page address used when loading the column latch is the one used to select
the page programming address.
31
4338F–USB–08/07
AT89C5131A-L
Extra RowThe following procedure is used to program the Extra Row space and is summarized in
Flash Spaces
Programming
Disable IT
EA = 0
Launch Programming
FCON = 5xh
FCON = Axh
End Programming
Enable IT
EA = 1
Column Latches Loading
see Figure 17
FBusy
Cleared?
Erase Mode
FCON = 00h
Figure 18:
•Load data in the column latches from address FF80h to FFFFh.
•Disable the interrupts.
•Launch the programming by writing the data sequence 52h followed by A2h in
FCON register.
The end of the programming indicated by the FBUSY flag cleared.
•Enable the interrupts.
Figure 18. Flash and Extra Row Programming Procedure
32
4338F–USB–08/07
AT89C5131A-L
Flash Spaces
Programming
Disable IT
EA = 0
Launch Programming
FCON = 54h
FCON = A4h
End Programming
Enable IT
EA = 1
FBusy
Cleared?
Erase Mode
FCON = 00h
Data Load
DPTR = 00h
ACC = Data
Exec: MOVX @DPTR, A
FCON = 0Ch
Hardware SecurityThe following procedure is used to program the Hardware Security space and is sum-
marized in Figure 19:
•Set FPS and map Hardware byte (FCON = 0x0C)
•Disable the interrupts.
•Load DPTR at address 0000h.
•Load Accumulator register with the data to load.
•Execute the MOVX @DPTR, A instruction.
•Launch the programming by writing the data sequence 54h followed by A4h in
FCON register.
The end of the programming indicated by the FBusy flag cleared.
•Enable the interrupts.
Figure 19. Hardware Programming Procedure
4338F–USB–08/07
33
AT89C5131A-L
Reading the Flash Spaces
Flash Spaces Reading
Flash Spaces Mapping
FCON = 00000xx0b
Data Read
DPTR = Address
ACC = 0
Exec: MOVC A, @A+DPTR
Erase Mode
FCON = 00h
UserThe following procedure is used to read the User space and is summarized in Figure 20:
•Map the User space by writing 00h in FCON register.
•Read one byte in Accumulator by executing MOVC A, @A+DPTR with A = 0 &
DPTR = 0000h to FFFFh.
Extra RowThe following procedure is used to read the Extra Row space and is summarized in
Figure 20:
•Map the Extra Row space by writing 02h in FCON register.
•Read one byte in Accumulator by executing MOVC A, @A+DPTR with A = 0 &
DPTR = FF80h to FFFFh.
Hardware SecurityThe following procedure is used to read the Hardware Security space and is summa-
rized in Figure 20:
•Map the Hardware Security space by writing 04h in FCON register.
•Read the byte in Accumulator by executing MOVC A, @A+DPTR with A = 0 &
DPTR = 0000h.
Figure 20. Reading Procedure
34
4338F–USB–08/07
AT89C5131A-L
Registers
Table 36. FCON (S:D1h)
Flash Control Register
76543210
FPL3FPL2FPL1FPL0FPSFMOD1FMOD0FBUSY
Bit Number
7-4FPL3:0
3FPS
2-1FMOD1:0
0FBUSY
Bit
Mnemonic Description
Programming Launch Command Bits
Write 5Xh followed by AXh to launch the programming according to FMOD1:0.
(see Table 35.)
Flash Map Program Space
Set to map the column latch space in the data memory space.
Clear to re-map the data memory space.
Flash Mode
See Table 34 or Table 35.
Flash Busy
Set by hardware when programming is in progress.
Clear by hardware when programming is done.
Can not be cleared by software.
Reset Value = 0000 0000b
4338F–USB–08/07
35
AT89C5131A-L
Flash EEPROM Memory
General Description
Features
The Flash memory increases EPROM functionality with in-circuit electrical erasure and
programming. It contains 32 Kbytes of program memory organized in 256 pages of 128
bytes, respectively. This memory is both parallel and serial In-System Programmable
(ISP). ISP allows devices to alter their own program memory in the actual end product
under software control. A default serial loader (bootloader) program allows ISP of the
Flash.
The programming does not require 12V external programming voltage. The necessary
high programming voltage is generated on-chip using the standard VCC pins of the
microcontroller.
•Flash EEPROM internal program memory.
•Boot vector allows user-provided Flash loader code to reside anywhere in the Flash
memory space. This configuration provides flexibility to the user.
•Default loader in Boot EEPROM allows programming via the serial port without the
need of a user provided loader.
•Up to 64K bytes external program memory if the internal program memory is
disabled (EA = 0).
•Programming and erase voltage with standard power supply.
•Read/Program/Erase:
•Byte-wise read (without wait state).
•Byte or page erase and programming (10 ms).
•Typical programming time (32 Kbytes) in 10 sec.
•Parallel programming with 87C51 compatible hardware interface to programmer.
•Programmable security for the code in the Flash.
•100K write cycles
•10 years data retention
Flash Programming and
Erasure
36
The 32 Kbytes Flash is programmed by bytes or by pages of 128 bytes. It is not necessary to erase a byte or a page before programming. The programming of a byte or a
page includes a self erase before programming.
There are three methods of programming the Flash memory:
1.The on-chip ISP bootloader may be invoked which will use low level routines to
program the pages. The interface used for serial downloading of Flash is the
USB.
2.The Flash may be programmed or erased in the end-user application by calling
low-level routines through a common entry point in the Boot Flash.
3.The Flash may be programmed using the parallel method .
The bootloader and the Application Programming Interface (API) routines are located in
the Flash Bootloader.
4338F–USB–08/07
AT89C5131A-L
Flash Registers and
Memory Map
The AT89C5131A-L Flash memory uses several registers:
•Hardware register can be accessed with a parallel programmer.Some bits of the
hardware register can be changed, also, by API (i.e. X2 and BLJB bits of Hardware
security Byte) or ISP.
•Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called “Extra Flash Memory”, is not in the internal Flash program memory
addressing space.
Hardware RegistersThe only hardware register of the AT89C5131A-L is called Hardware Security Byte
(HSB).
Table 37. Hardware Security Byte (HSB)
76543210
X2BLJBOSCON1OSCON0-LB2LB1LB0
Bit
Number
7X2
6BLJB
Bit
Mnemonic Description
X2 Mode
Cleared to force X2 mode (6 clocks per instruction)
Set to force X1 mode, Standard Mode (Default).
Bootloader Jump Bit
Set this bit to start the user’s application on next reset at address 0000h.
Cleared this bit to start the bootloader at address F400h (default).
Oscillator Control Bits
These two bits are used to control the oscillator in order to reduce consumption.
5-4OSCON1-0
3-Reserved
2-0LB2-0
OSCON1 OSCON0 Description
1 1 The oscillator is configured to run from 0 to 32 MHz
1 0 The oscillator is configured to run from 0 to 16 MHz
0 1 The oscillator is configured to run from 0 to 8 MHz
0 0 This configuration shouldn’t be set
User Memory Lock Bits
See Table 38
Bootloader Jump Bit (BLJB)One bit of the HSB, the BLJB bit, is used to force the boot address:
•When this bit is set the boot address is 0000h.
•When this bit is reset the boot address is F400h. By default, this bit is cleared and
the ISP is enabled.
Flash Memory Lock BitsThe three lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 38.
4338F–USB–08/07
37
AT89C5131A-L
Table 38. Program Lock bits
Program Lock Bits
Protection DescriptionSecurity levelLB0LB1LB2
1UUUNo program lock features enabled.
MOVC instruction executed from external
program memory is disabled from fetching code
2PUU
3XPU
4XXPSame as 3, also external execution is disabled.
Notes:1. U: unprogrammed or “one” level.
2. P: programmed or “zero” level.
3. X: don’t care
4. WARNING: Security level 2 and 3 should only be programmed after verification.
bytes from any internal memory, EA is sampled
and latched on reset, and further parallel
programming of the Flash and of the EEPROM
(boot and Xdata) is disabled. ISP and software
programming with API are still allowed.
Same as 2, also verify through parallel
programming interface is disabled and serial
programming ISP is still allowed.
These security bits protect the code access through the parallel programming interface.
They are set by default to level 4. The code access through the ISP is still possible and
is controlled by the “software security bits” which are stored in the extra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must be done first.
This will set the HSB in its inactive state and will erase the Flash memory. The part reference can always be read using Flash parallel programming modes.
Default ValuesThe default value of the HSB provides parts ready to be programmed with ISP:
•BLJB: Cleared to force ISP operation.
•X2: Set to force X1 mode (Standard Mode)
•OSCON1-0: Set to start with 32 MHz oscillator configuration value.
•LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Software RegistersSeveral registers are used, in factory and by parallel programmers, to make copies of
hardware registers contents. These values are used by Atmel ISP (see Section “In-System Programming (ISP)”).
These registers are in the “Extra Flash Memory” part of the Flash memory. This block is
also called ”XAF” or eXtra Array Flash. They are accessed in the following ways:
•Commands issued by the parallel memory programmer.
•Commands issued by the ISP software.
•Calls of API issued by the application software.
Several software registers are described in Table 39.
38
4338F–USB–08/07
AT89C5131A-L
Table 39. Software Registers
AddressMnemonicDescriptionDefault value
01SBVSoftware Boot VectorFFh–
00BSBBoot Status Byte0FFh–
05SSBSoftware Security ByteFFh–
30–
31–
60–
61–
Copy of the Manufacturer
Code
Copy of the Device ID #1:
Family Code
Copy of the Device ID #2:
Memories
Copy of the Device ID #3:
Name
58hAtmel
D7h
F7hAT89C5131A-L 32 Kbyte
DFh
C51 X2, Electrically
Erasable
AT89C5131A-L 32 Kbyte,
revision 0
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 40
and
Table 41.
To assure code protection from a parallel access, the HSB must also be at the required
level.
Table 40. Software Security Byte (SSB)
76543210
------LB1LB0
Bit
Number
7-
Bit
MnemonicDescription
Reserved
Do not clear this bit.
4338F–USB–08/07
6-
5-
4-
3-
2-
1-0LB1-0
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
User Memory Lock Bits
See Table 41
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown to Table 41.
39
AT89C5131A-L
Table 41. Program Lock Bits of the SSB
0000h
Virgin
Default
Virgin
After ISP
After parallel
programming
After parallel
programming
After parallel
programming
ApplicationApplication
After ISP
or
Dedicated
ISP
Dedicated
ISP
7FFFh
AT89C5131A-M
Application
Virgin
or
Application
Virgin
or
Application
Program Lock Bits
Security
LevelLB0LB1
1UUNo program lock features enabled.
2PUISP programming of the Flash is disabled.
3PPSame as 2, also verify through ISP programming interface is disabled.
Notes:1. U: unprogrammed or "one" level.
2. P: programmed or “zero” level.
3. WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
Protection Description
Flash Memory Status
AT89C5131A-L parts are delivered with the ISP boot in the Flash memory. After ISP or
parallel programming, the possible contents of the Flash memory are summarized in
Figure 21:
Figure 21. Flash Memory Possible Contents
Memory Organization
40
In the AT89C5131A-L, the lowest 32K of the 64 Kbyte program memory address space
is filled by internal Flash.
When the EA is pin high, the processor fetches instructions from internal program Flash.
Bus expansion for accessing program memory from 32K upward is automatic since
external instruction fetches occur automatically when the program counter exceeds
7FFFh (32K). If the EA pin is tied low, all program memory fetches are from external
memory. If all storage is on chip, then byte location 7FFFh (32K) should be left vacant to
prevent and undesired pre-fetch from external program memory address 8000h (32K).
4338F–USB–08/07
EEPROM Data Memory
AT89C5131A-L
Description
Write Data in the Column
Latches
The 1-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 03FFh of
the ERAM memory space and is selected by setting control bits in the EECON register.
A read in the EEPROM memory is done with a MOVX instruction.
A physical write in the EEPROM memory is done in two steps: write data in the column
latches and transfer of all data latches into an EEPROM memory row (programming).
The number of data written on the page may vary from 1 to 128 bytes (the page size).
When programming, only the data written in the column latch is programmed and a ninth
bit is used to obtain this feature. This provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page. Indeed, each ninth bit is set
when the writing the corresponding byte in a row and all these ninth bits are reset after
the writing of the complete EEPROM row.
Data is written by byte to the column latches as for an external RAM memory. Out of the
11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7
are used for byte selection. Between two EEPROM programming sessions, all the
addresses in the column latches must stay on the same page, meaning that the 4 MSB
must not be changed.
The following procedure is used to write to the column latches:
•Set bit EEE of EECON register
•Load DPTR with the address to write
•Store A register with the data to be written
•Execute a MOVX @DPTR, A
•If needed, loop the three last instructions until the end of a 128 bytes page
Programming
Read Data
The EEPROM programming consists on the following actions:
•Writing one or more bytes of one page in the column latches. Normally, all bytes
must belong to the same page; if not, the first page address will be latched and the
others discarded.
•Launching programming by writing the control sequence (52h followed by A2h) to
the EECON register.
•EEBUSY flag in EECON is then set by hardware to indicate that programming is in
progress and that the EEPROM segment is not available for reading.
•The end of programming is indicated by a hardware clear of the EEBUSY flag.
The following procedure is used to read the data stored in the EEPROM memory:
•Set bit EEE of EECON register
•Stretch the MOVX to accommodate the slow access time of the column latch (Set bit
M0 of AUXR register)
•Load DPTR with the address to read
•Execute a MOVX A, @DPTR
4338F–USB–08/07
41
AT89C5131A-L
Registers
Table 42. EECON (S:0D2h)
EECON Register
76543210
EEPL3EEPL2EEPL1EEPL0--EEEEEBUSY
Bit
Bit Number
Mnemonic Description
7-4EEPL3-0
3-
2-
1EEE
0EEBUSY
Programming Launch command bits
Write 5Xh followed by AXh to EEPL to launch the programming.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable EEPROM Space bit
Set to map the EEPROM space during MOVX instructions (Write in the column
latches)
Clear to map the ERAM space during MOVX.
Programming Busy flag
Set by hardware when programming is in progress.
Cleared by hardware when programming is done.
Cannot be set or cleared by software.
Reset Value = XXXX XX00b
Not bit addressable
42
4338F–USB–08/07
AT89C5131A-L
F400h
7FFFh
32K Bytes
Flash Memory
3K Bytes IAP
Bootloader
FM0
FM1
Custom
Bootloader
[SBV]00h
FFFFh
FM1 Mapped between F400h and FFFFh
when API Called
0000h
In-System
Programming (ISP)
Flash Programming and
Erasure
With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash
technology the AT89C5131 allows the system engineer the development of applications
with a very high level of flexibility. This flexibility is based on the possibility to alter the
customer program at any stages of a product’s life:
•Before mounting the chip on the PCB, FM0 flash can be programmed with the
application code. FM1 is always preprogrammed by Atmel with a USB bootloader.
•Once the chip is mounted on the PCB, it can be programmed by serial mode via the
USB bus.
Note:1. The user can also program his own bootloader in FM1.
This ISP allows code modification over the total lifetime of the product.
Besides the default Bootloaders Atmel provide customers all the needed ApplicationProgramming-Interfaces (API) which are needed for the ISP. The API are located in the
Boot memory.
This allow the customer to have a full use of the 32-Kbyte user memory.
There are three methods for programming the Flash memory:
•The Atmel bootloader located in FM1 is activated by the application. Low level API
routines (located in FM1)will be used to program FM0. The interface used for serial
downloading to FM0 is the USB. API can be called also by user’s bootloader located
in FM0 at [SBV]00h.
•A further method exist in activating the Atmel boot loader by hardware activation.
See the Section “Hardware Registers”.
•The FM0 can be programmed also by the parallel mode using a programmer.
(1)
Figure 22. Flash Memory Mapping
4338F–USB–08/07
43
AT89C5131A-L
Boot Process
RESET
BLJB == 0
?
Hardware
Software
Bootloader
in FM1
Application
in FM0
bit ENBOOT in AUXR1 Register
Is Initialized with BLJB Inverted.
ENBOOT = 0
PC = 0000h
ENBOOT = 1
PC = F400h
Example, if BLJB=0, ENBOOT
is set (=1) during reset, thus the
bootloader is executed after the
reset.
Software Boot Process
Example
Many algorithms can be used for the software boot process. Below are descriptions of
the different flags and Bytes.
Boot Loader Jump bit (BLJB):
- This bit indicates if on RESET the user wants to jump to this application at address
@0000h on FM0 or execute the boot loader at address @F400h on FM1.
- BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory pro-
gramming.
-To read or modify this bit, the APIs are used.
Boot Vector Address (SBV):
- This byte contains the MSB of the user boot loader address in FM0.
- The default value of SBV is FFh (no user boot loader in FM0).
- To read or modify this byte, the APIs are used.
Extra Byte (EB) & Boot Status Byte (BSB):
- These Bytes are reserved for customer use.
- To read or modify these Bytes, the APIs are used.
Figure 23. Hardware Boot Process Algorithm
44
4338F–USB–08/07
AT89C5131A-L
ALE
EA
VCC
/PSEN
/RST
GND
1K
Unconnected
VCC
VSS
VCC
GND
GND
C1
C2
Crystal
GND
XTAL2
XTAL1
Bootloader
GND
ApplicationProgramming-Interface
XROW Bytes
Hardware Conditions
Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
by functions.
All these APIs are described in detail in the following document on the Atmel web site.
–Datasheet Bootloader USB AT89C5131.
The EXTRA ROW (XROW) includes 128 bytes. Some of these bytes are used for specific purpose in conjonction with the bootloader.
Table 43. XROW Mapping
DescriptionDefault ValueAddress
Copy of the Manufacturer Code58h30h
Copy of the Device ID#1: Family codeD7h31h
Copy of the Device ID#2: Memories size and typeBBh60h
Copy of the Device ID#3: Name and RevisionFFh61h
It is possible to force the controller to execute the bootloader after a Reset with hardware conditions. Depending on the product type (low pin count or high pin count
package), there are two methods to apply the hardware conditions.
High Pin Count Hardware
Conditions (PLCC52, QFP64)
For high pin count packages, the hardware conditons (EA = 1, PSEN = 0) are sampled
during the RESET rising edge to force the on-chip bootloader execution (See Figure 82
on page 172). In this way the bootloader can be carried out regardless of the user Flash
memory content. It is recommended to pull the PSEN pin down to ground though a 1K
resistor to prevent the PSEN pin from being damaged (See Figure 24 below).
Figure 24. ISP Hardware conditions
4338F–USB–08/07
45
AT89C5131A-L
As PSEN is an output port in normal operating mode (running user application or bootloader code) after reset, it is recommended to release PSEN after rising edge of reset
signal.
Low Pin Count Hardware
Conditions (SOIC28)
Low pin count products do not have PSEN signal, thus for these products, the bootloader is always executed after reset thanks to the BLJB bit. The Hardware Conditions
are detected at the begining of the bootloader execution from reset.
The default factory Hardware Condition is assigned to port P1.
•P1 must be equal to FEh
In order to offer the best flexibility, the user can define its own Hardware Condition on
one of the following Ports:
•Port1
•Port3
•Port4 (only bit0 and bit1)
The Hardware Conditions configuration is stored in three bytes called P1_CF, P3_CF,
P4_CF.
These bytes can be modified by the user through a set of API or through an ISP
command.
Note:1. The BLJB must be at 0 (programmed) to be able to restart the bootloader.
2. BLJB can always be changed by the means of API, whether it's a low or high pin
count package.But for a low pin count version, if BLJB=1, no ISP via the Bootloader
is further possible (because the HW conditions are never evaluated, as described in
the USB Bootloader Datasheet). To go back to ISP, BLJB needs to be changed by a
parallel programmer(or by the APIs).
See a detailed description in the applicable Document.
–Datasheet Bootloader USB AT89C5131.
46
4338F–USB–08/07
AT89C5131A-L
ERAM
Upper
128 bytes
Internal
RAM
Lower
128 bytes
Internal
RAM
Special
Function
Register
80h80h
00
0FFh or 3FFh(*)
0FFh
00
0FFh
External
Data
Memory
0000
00FFh up to 03FFh (*)
0FFFFh
indirect accesses
direct accesses
direct or indirect
accesses
7Fh
(*) Depends on XRS1..0
On-chip Expanded
RAM (ERAM)
The AT89C5131A-L provides additional Bytes of random access memory (RAM) space
for increased data parameters handling and high level language usage.
AT89C5131A-L devices have an expanded RAM in the external data space; maximum
size and location are described in Table 44.
Table 44. Description of Expanded RAM
Address
Part NumberERAM Size
AT89C5131A-L102400h3FFh
StartEnd
The AT89C5131A-L has on-chip data memory which is mapped into the following four
separate segments.
1.The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2.The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable
only.
3.The Special Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
4.The expanded RAM bytes are indirectly accessed by MOVX instructions, and
with the EXTRAM bit cleared in the AUXR register (see Table 44)
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. That means they have the same address, but are
physically separate from SFR space.
Figure 25. Internal and External Data Memory Address
4338F–USB–08/07
47
AT89C5131A-L
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
•Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
•Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV atR0, # data where R0 contains 0A0h, accesses the data byte at
address 0A0h, rather than P2 (whose address is 0A0h).
•The ERAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available ERAM as explained in Table 44. This can be
useful if external peripherals are mapped at addresses already used by the internal
ERAM.
•With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to ERAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX atR0, # data where R0 contains 0A0H,
accesses the ERAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the ERAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to ERAM above 0FFH can only be done by the use of
DPTR.
•With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51. MOVX at Ri will provide an eight-bit address multiplexed with data on Port0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port2 outputs the high-order eight address bits (the contents of DPH) while
Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX at Ri and
MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7
(RD).
48
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the ERAM.
The M0 bit allows to stretch the ERAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
4338F–USB–08/07
AT89C5131A-L
Table 45. AUXR Register
AUXR - Auxiliary Register (8Eh)
76543210
DPU-M0-XRS1XRS0EXTRAMAO
Bit
Number
7DPU
6-
5M0
4-
3XRS1
2XRS0
1EXTRAM
MnemonicDescription
Bit
Disable Weak Pull Up
Cleared to enabled weak pull up on standard Ports.
Set to disable weak pull up on standard Ports.
Reserved
The value read from this bit is indeterminate. Do not set this bit
Pulse length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock
periods.
Reserved
The value read from this bit is indeterminate. Do not set this bit
ERAM Size
XRS1XRS0ERAM size
00256 bytes
01512 bytes
10768 bytes
111024 bytes (default)
EXTRAM bit
Cleared to access internal ERAM using MOVX at Ri at DPTR.
Set to access external memory.
4338F–USB–08/07
ALE Output bit
0AO
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or
1/3 if X2 mode is used) (default).
Set, ALE is active only when a MOVX or MOVC instruction is used.
Reset Value = 0X0X 1100b
Not bit addressable
49
AT89C5131A-L
Timer 2
Th e Timer 2 in the AT 89C5131A -L is t he standard C52 Time r 2. It is a 16 -bit
timer/counter: the count is maintained by two cascaded eight-bit timer registers, TH2
and TL2. It is controlled by T2CON (Table 46) and T2MOD (Table 47) registers. Timer 2
operation is similar to Timer 0 and Timer 1. C/T2 selects F
external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to
be incremented by the selected input.
Timer 2 has 3 operating modes: capture, auto reload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
Refer to the Atmel 8-bit microcontroller hardware documentation for the description of
Capture and Baud Rate Generator Modes.
Timer 2 includes the following enhancements:
•Auto-reload mode with up or down counter
•Programmable Clock-output
/12 (timer operation) or
OSC
Auto-reload Mode
The Auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to
the Atmel 8-bit microcontroller hardware description). If DCEN bit is set, Timer 2 acts as
an Up/down timer/counter as shown in Figure 26. In this mode the T2EX pin controls the
direction of count.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of
the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit
resolution.
In the Clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 27). The input clock increments TL2 at frequency F
timer repeatedly counts to overflow from a loaded value. At overflow, the contents of
RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2
overflows do not generate interrupts. The following formula gives the Clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H
and RCAP2L registers
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(F
CLK PERIPH
T2 pin (P1.0).
Timer 2 is programmed for the Clock-out mode as follows:
16)
/2
to 4 MHz (F
•Set T2OE bit in T2MOD register.
•Clear C/T2 bit in T2CON register.
•Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
•To start the timer, set TR2 run control bit in T2CON register.
CLK PERIPH
/4). The generated clock signal is brought out to
CLK PERIPH
/2. The
4338F–USB–08/07
51
AT89C5131A-L
It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-
: 6
EXF2
TR2
OVERFLOW
T2EX
TH2
(8-bit)
TL2
(8-bit)
Timer 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2
F
CLK PERIPH
T2CON
T2CON
T2CON
T2MOD
INTERRUPT
QD
Toggle
EXEN2
ne ously . For t his c onfigurat ion, t he bau d rat es and clock frequ enci es are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
Figure 27. Clock-out Mode C/T2 = 0
52
4338F–USB–08/07
AT89C5131A-L
Table 46. T2CON Register
T2CON - Timer 2 Control Register (C8h)
76543210
TF2EXF2RCLKTCLKEXEN2TR2C/T2#CP/RL2#
Bit
Number
7TF2
6EXF2
5RCLK
4TCLK
3EXEN2
2TR2
Bit
MnemonicDescription
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2 = 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1).
Receive Clock bit
Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
4338F–USB–08/07
Timer/Counter 2 select bit
1C/T2#
0CP/RL2#
Cleared for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to Auto-reload
on Timer 2 overflow.
Cleared to Auto-reload on Timer 2 overflows or negative transitions on T2EX
pin if EXEN2 = 1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
Reset Value = 0000 0000b
Bit addressable
CLK PERIPH
).
53
AT89C5131A-L
Table 47. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
76543210
------T2OEDCEN
Bit
Number
7-
6-
5-
4-
3-
2-
1T2OE
0DCEN
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 Output Enable bit
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
Down Counter Enable bit
Cleared to disable Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
Reset Value = XXXX XX00b
Not bit addressable
54
4338F–USB–08/07
AT89C5131A-L
Programmable
Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/capture modules. Its clock input can be programmed to count
any one of the following signals:
•Peripheral clock frequency (F
•Peripheral clock frequency (F
CLK PERIPH
CLK PERIPH
) ÷ 6
) ÷ 2
•Timer 0 overflow
•External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
•rising and/or falling edge capture,
•software timer
•high-speed output, or
•pulse width modulator
Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog
Timer", page 65).
When the compare/capture modules are programmed in the capture mode, software
timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If the port pin is not used for the PCA, it can still be used for
standard I/O.
PCA ComponentExternal I/O Pin
16-bit CounterP1.2/ECI
16-bit Module 0P1.3/CEX0
16-bit Module 1P1.4/CEX1
16-bit Module 2P1.5/CEX2
16-bit Module 3P1.6/CEX3
16-bit Module 4P1.7/CEX4
The PCA timer is a common time base for all five modules (see Figure 28). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 48) and can be programmed to run at:
•1/6 the
•1/2 the
peripheral clock frequency (F
peripheral clock frequency (F
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
Watchdog Timer Enable
6WDTE
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5-
4-
3-
2CPS1
1CPS0
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Count Pulse Select
CPS1CPS0Selected PCA input
00Internal clock f
01Internal clock f
10Timer 0 Overflow
11External clock at ECI/P1.2 pin (max rate = f
PCA Enable Counter Overflow Interrupt
0ECF
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
Reset Value = 00XX X000b
Not bit addressable
CLK PERIPH
CLK PERIPH
/6
/2
CLK PERIPH
/ 4)
4338F–USB–08/07
AT89C5131A-L
The CMOD regis ter includes three additional bits associated with the PCA (See
Figure 28 and Table 48).
•The CIDL bit allows the PCA to stop during idle mode.
•The WDTE bit enables or disables the watchdog function on module 4.
•The ECF bit when set causes an interrupt and the PCA overflow flag CF (in the
CCON SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA
timer (CF) and each module (see Table 49).
•Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
•Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
•Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
can only be cleared by software.
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF may be set by either hardware or software but can only be cleared
by software.
PCA Counter Run control bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Module 4 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 3 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 2 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 1 Interrupt Flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 0 Interrupt Flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
CCF4CCF3CCF2CCF1CCF0
4338F–USB–08/07
Reset Value = 000X 0000b
Not bit addressable
57
AT89C5131A-L
Figure 29. PCA Interrupt System
CFCR
CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Module 4
Module 3
Module 2
Module 1
Module 0
ECF
PCA Timer/Counter
ECCFn
CCAPMn.0CMOD.0
IE.6IE.7
To Interrupt
priority decoder
ECEA
The watchdog timer function is implemented in module 4 (See Figure 31).
The PCA interrupt system is shown in Figure 29.
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:
•16-bit capture, positive-edge triggered
•16-bit capture, negative-edge triggered
•16-bit capture, both positive and negative-edge triggered
•16-bit Software Timer
•16-bit High-speed Output
•8-bit Pulse Width Modulator
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Table 50). The
registers contain the bits that control the mode that each module will operate in.
•The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module.
•PWM (CCAPMn.1) enables the pulse width modulation mode.
•The TOG bit (CCAPMn.2) when set causes the CEX output associated with the
module to toggle when there is a match between the PCA counter and the module's
capture/compare register.
•The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the module's
capture/compare register.
•The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
58
4338F–USB–08/07
AT89C5131A-L
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occur for either transition.
•The last bit in the register ECOM (CCAPMn.6) when set enables the comparator
function.
Table 51 shows the CCAPMn settings for the various PCA functions.
Table 50. CCAPMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
76543210
-ECOMnCAPPnCAPNnMATnTOGnPWMnECCFn
Bit
Number
7-
6ECOMn
5CAPPn
4CAPNn
3MATn
2TOGn
1PWMn
Bit
MnemonicDescription
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
Capture Positive
Cleared to disable positive edge capture.
Set to enable positive edge capture.
Capture Negative
Cleared to disable negative edge capture.
Set to enable negative edge capture.
Match
When MATn = 1, a match of the PCA counter with this module's
compare/capture register causes the
CCFn bit in CCON to be set, flagging an interrupt.
Toggle
When TOGn = 1, a match of the PCA counter with this module's
compare/capture register causes the CEXn pin to toggle.
Pulse Width Modulation Mode
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
4338F–USB–08/07
Enable CCF Interrupt
Cleared to disable compare/capture flag CCFn in the CCON register to
0ECCFn
generate an interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Reset Value = X000 0000b
Not bit addressable
59
AT89C5131A-L
Table 51. PCA Module Modes (CCAPMn Registers)
PWMmECCF
ECOMnCAPPnCAPNnMATn TOGn
0000000 No Operation
nModule Function
X10000X
X01000X
X11000X
100100X
100110X16-bit High Speed Output
10000108-bit PWM
1001X0X
16-bit capture by a positiveedge trigger on CEXn
16-bit capture by a negative
trigger on CEXn
16-bit capture by a transition on
CEXn
16-bit Software Timer/Compare
mode.
Watchdog Timer (module 4
only)
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output (see Table 52 and
Table 53)
60
4338F–USB–08/07
AT89C5131A-L
Table 52. CCAPnH Registers (n = 0-4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
76543210
--------
Bit
Number
7 - 0-
Bit
MnemonicDescription
PCA Module n Compare/Capture Control
CCAPnH Value
Reset Value = XXXX XXXXb
Not bit addressable
Table 53. CCAPnL Registers (n = 0-4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
76543210
--------
Bit
Number
7 - 0-
Bit
MnemonicDescription
PCA Module n Compare/Capture Control
CCAPnL Value
Reset Value = XXXX XXXXb
Not bit addressable
4338F–USB–08/07
Table 54. CH Register
CH - PCA Counter Register High (0F9h)
76543210
--------
Bit
Number
7 - 0-
Bit
MnemonicDescription
PCA counter
CH Value
Reset Value = 0000 0000b
Not bit addressable
61
AT89C5131A-L
Table 55. CL Register
CFCR
CCON
0xD8
CHCL
CCAPnHCCAPnL
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Counter/Timer
ECOMn
CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
Cex.n
Capture
CL - PCA Counter Register Low (0E9h)
76543210
--------
PCA Capture Mode
Figure 30. PCA Capture Mode
Bit
Number
7 - 0-
Bit
MnemonicDescription
PCA Counter
CL Value
Reset Value = 0000 0000b
Not bit addressable
To use one of the PCA modules in the capture mode either one or both of the CCAPM
bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the module's
capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(see Figure 30).
16-bit Software
Timer/Compare Mode
62
The PCA modules can be used as software timers by setting both the ECOM and MAT
bits in the modules CCAPMn register. The PCA timer will be compared to the module's
capture registers and when a match occurs an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 31).
4338F–USB–08/07
Figure 31. PCA Compare Mode and PCA Watchdog Timer
CHCL
CCAPnHCCAPnL
ECOMn
CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16-bit Comparator
Match
CCON
0xD8
PCA IT
Enable
PCA Counter/Timer
RESET
(1)
CIDLCPS1 CPS0ECF
CMOD
0xD9
WDTE
Reset
Write to
CCAPnL
Write to
CCAPnH
CFCCF2 CCF1 CCF0
CR
CCF3
CCF4
10
AT89C5131A-L
High Speed Output Mode
Note:1. Only for Module 4
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
In this mode, the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (see Figure 32).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
4338F–USB–08/07
63
AT89C5131A-L
Figure 32. PCA High-speed Output Mode
CHCL
CCAPnHCCAPnL
ECOMn
CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16-bit Comparator
Match
CFCR
CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
Enable
CEXn
PCA counter/timer
Write to
CCAPnH
Reset
Write to
CCAPnL
1
0
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
Pulse Width Modulator
Mode
All of the PCA modules can be used as PWM outputs. Figure 33 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the
modules will have the same frequency of output because they all share the PCA timer.
The duty cycle of each module is independently variable using the module's capture
register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output
will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in
the module's CCAPMn register must be set to enable the PWM mode.
64
4338F–USB–08/07
Figure 33. PCA PWM Mode
CL
CCAPnH
CCAPnL
ECOMn
CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
8-bit Comparator
CEXn
“0”
“1”
≥
<
Enable
PCA Counter/Timer
Overflow
AT89C5131A-L
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA module that can be programmed as a watchdog. However, this module can still be
used for other modes if the watchdog is not needed. Figure 31 shows a diagram of how
the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just
like the other compare modes, this 16-bit value is compared to the PCA timer value. If a
match is allowed to occur, an internal reset will be generated. This will not cause the
RST pin to be driven low.
In order to hold off the reset, the user has three options:
1.Periodically change the compare value so it will never match the PCA timer
2.Periodically change the PCA timer value so it will never match the compare values, or
3.Disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it
The first two options are more reliable because the watchdog timer is never disabled as
in option #3. If the program counter ever goes astray, a match will eventually occur and
cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
4338F–USB–08/07
65
AT89C5131A-L
Serial I/O Port
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART Framing Error Control
SM0 to UART Mode Control (SMOD0 = 0)
Set FE Bit if Stop Bit is 0 (framing error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Data Byte
RI
SMOD0 = X
Stop
Bit
Start
Bit
RXD
D7D6D5D4D3D2D1D0
FE
SMOD0 = 1
The serial I/O port in the AT89C5131A-L is compatible with the serial I/O port in the
80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates.
Serial I/O port includes the following enhancements:
•Framing error detection
•Automatic address recognition
Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 34).
Figure 34. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 56) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 35 and Figure 36).
Figure 35. UART Timings in Mode 1
66
4338F–USB–08/07
Figure 36. UART Timings in Modes 2 and 3
RI
SMOD0 = 0
Data ByteNinth
Bit
Stop
Bit
Start
Bit
RXD
D8D7D6D5D4D3D2D1D0
RI
SMOD0 = 1
FE
SMOD0 = 1
AT89C5131A-L
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s address and is terminated by a
valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e., setting SM2 bit in SCON register in mode 0 has no effect).
Given AddressEach device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t care bits (defined by zeros) to form the
device’s given address. The don’t care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 11111111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
4338F–USB–08/07
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0011b
SADEN1111 1101b
Given1111 00X1b
67
AT89C5131A-L
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast AddressA broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t care bits, e.g.:
SADDR0101 0110b
SADEN1111 1100b
Broadcast = SADDR OR SADEN1111 111Xb
The use of don’t care bits provides flexibility in defining the broadcast address, in most
applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR = 1111 0011b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Reset AddressesOn reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadcast addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial
port will reply to any address, and so, that it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition.
SADEN - Slave Address Mask Register (B9h)
76543210
Reset Value = 0000 0000b
Not bit addressable
68
4338F–USB–08/07
AT89C5131A-L
RCLK
/ 16
RBCK
INT_BRG
0
1
TIMER1
0
1
0
1
TIMER2
INT_BRG
TIMER1
TIMER2
TIMER_BRG_RX
Rx Clock
/ 16
0
1
TIMER_BRG_TX
Tx Clock
TBCK
TCLK
SADDR - Slave Address Register (A9h)
76543210
Reset Value = 0000 0000b
Not bit addressable
Baud Rate Selection for
UART for Mode 1 and 3
Baud Rate Selection Table for
UART
The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
Figure 37. Baud Rate Selection
TCLK
(T2CON)
0000Timer 1Timer 1
RCLK
(T2CON)
TBCK
(BDRCON)
RBCK
(BDRCON)
Clock Source
UART Tx
Clock Source
UART Rx
Internal Baud Rate Generator
(BRG)
4338F–USB–08/07
1000Timer 2Timer 1
0100Timer 1Timer 2
1100Timer 2Timer 2
X010INT_BRGTimer 1
X110INT_BRGTimer 2
0X01Timer 1INT_BRG
1X01Timer 2INT_BRG
XX11INT_BRGINT_BRG
When the internal Baud Rate Generator is used, the Baud Rates are determined by the
BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
69
AT89C5131A-L
Figure 38. Internal Baud Rate
BRG
0
1
/6
BRL
/2
0
1
INT_BRG
SPD
BRR
SMOD1
auto reload counter
overflow
Peripheral Clock
Baud_Rate =
2
SMOD1
x FCLK PERIPH
2 x 6
(1-SPD)
x 16 x [256 - (BRL)]
(BRL) = 256
-
2
SMOD1
x F
CLK PERIPH
2 x 6
(1-SPD)
x 16 x Baud_Rate
•The baud rate for UART is token by formula:
70
4338F–USB–08/07
AT89C5131A-L
Table 56. SCON Register – SCON Serial Control Register (98h)
76543210
FE/SM0SM1SM2RENTB8RB8TIRI
Bit
Number
7
6SM1
5SM2
4REN
3TB8
Bit
MnemonicDescription
Framing Error bit (SMOD0 = 1
FE
SM0
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8/Ninth bit to Transmit in Modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
CPU PERIPH
CPU PERIPH/
)
/6
32 or/16
Receiver Bit 8/Ninth bit received in modes 2 and 3
2RB8
1TI
0RI
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 35. and
Figure 36. in the other modes.
Reset Value = 0000 0000b
Bit addressable
4338F–USB–08/07
71
AT89C5131A-L
Example of computed value when X2 = 1, SMOD1 = 1, SPD = 1
F
= 16.384 MHzF
Baud Rates
1152002471.232430.16
576002381.232300.16
384002291.232170.16
288002201.232040.16
192002030.631780.16
96001490.311000.16
4800431.23--
OSC
BRLError (%)BRLError (%)
OSC
Example of computed value when X2 = 0, SMOD1 = 0, SPD = 0
F
= 16.384 MHzF
OSC
Baud Rates
48002471.232430.16
24002381.232300.16
12002201.232023.55
BRLError (%)BRLError (%)
OSC
= 24 MHz
= 24 MHz
UART Registers
6001850.161520.16
The baud rate generator can be used for mode 1 or 3 (refer to Figure 37.), but also for
mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 59.)
SADEN - Slave Address Mask Register for UART (B9h)
76543210
––––––––
Reset Value = 0000 0000b
SADDR - Slave Address Register for UART (A9h)
76543210
––––––––
Reset Value = 0000 0000b
SBUF - Serial Buffer Register for UART (99h)
76543210
––––––––
Reset Value = XXXX XXXXb
72
4338F–USB–08/07
AT89C5131A-L
BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
76543210
––––––––
Reset Value = 0000 0000b
Table 57. T2CON Register
T2CON - Timer 2 Control Register (C8h)
76543210
TF2EXF2RCLKTCLKEXEN2TR2C/T2#CP/RL2#
Bit
Number
7TF2
6EXF2
5RCLK
4TCLK
3EXEN2
2TR2
Bit
MnemonicDescription
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2 = 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1)
Receive Clock bit for UART
Cleared to use Timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit for UART
Cleared to use Timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
4338F–USB–08/07
Timer/Counter 2 select bit
1C/T2#
0CP/RL2#
Cleared for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0
for clock out mode.
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to Auto-reload
on Timer 2 overflow.
Cleared to Auto-reload on Timer 2 overflows or negative transitions on T2EX pin
if EXEN2 = 1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
Reset Value = 0000 0000b
Bit addressable
CLK PERIPH
).
73
AT89C5131A-L
Table 58. PCON Register
PCON - Power Control Register (87h)
76543210
SMOD1SMOD0-POFGF1GF0PDIDL
Bit
Number
7SMOD1
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
Bit
MnemonicDescription
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
Power-down Mode Bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle Mode Bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
74
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
4338F–USB–08/07
AT89C5131A-L
Table 59. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
76543210
---BRRTBCKRBCKSPDSRC
Bit
Number
7-
6-
5-
4BRR
3TBCK
2RBCK
1SPD
0SRC
Bit
MnemonicDescription
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0 for UART
Cleared to select F
mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
/12 as the Baud Rate Generator (F
OSC
CLK PERIPH
/6 in X2
4338F–USB–08/07
Reset Value = XXX0 0000b
Not bit addressable
75
AT89C5131A-L
Interrupt System
IE1
0
3
High priority
interrupt
Interrupt
Polling
Sequence, Decreasing From
High-to-Low Priority
Low Priority
Interrupt
Global DisableIndividual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IPL
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
KBD IT
SPI IT
0
3
0
3
0
3
UEPINT
USBINT
0
3
TWI IT
1
1
0
0
IT0
TCON.0
IT1
TCON.2
Overview
Figure 39. Interrupt Control System
The AT89C5131A-L has a total of 11 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt,
Keyboard interrupt, USB interrupt and the PCA global interrupt. These interrupts are
shown in Figure 39.
76
4338F–USB–08/07
AT89C5131A-L
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 61). This register also contains a global
disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 62.) and in the
Interrupt Priority High register (Table 63). Table 60. shows the bit values and priority levels associated with each combination.
Registers
The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located
at address 004BH and Keyboard interrupt vector is located at address 003BH. All other
vectors addresses are the same as standard C52 devices.
Table 60. Priority Level Bit Values
IPH.xIPL.xInterrupt Level Priority
000 (Lowest)
011
102
113 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
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AT89C5131A-L
Table 61. IEN0 Register
IEN0 - Interrupt Enable Register (A8h)
76543210
EAECET2ESET1EX1ET0EX0
Bit
Number
7EA
6EC
5ET2
4ES
3ET1
2EX1
1ET0
Bit
MnemonicDescription
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
PCA interrupt enable bit
Cleared to disable.
Set to enable.
Timer 2 overflow interrupt Enable bit
Cleared to disable Timer 2 overflow interrupt.
Set to enable Timer 2 overflow interrupt.
Serial port Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
Cleared to disable Timer 1 overflow interrupt.
Set to enable Timer 1 overflow interrupt.
External interrupt 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0EX0
External interrupt 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
78
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Table 62. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
76543210
-PPCLPT2LPSLPT1LPX1LPT0LPX0L
Bit
Number
7-
6PPCL
5PT2L
4PSL
3PT1L
2PX1L
1PT0L
0PX0L
Bit
MnemonicDescription
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA interrupt Priority bit
Refer to PPCH for priority level.
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
Serial port Priority bit
Refer to PSH for priority level.
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
External interrupt 1 Priority bit
Refer to PX1H for priority level.
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Reset Value = X000 0000b
Bit addressable
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AT89C5131A-L
Table 63. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
76543210
-PPCHPT2HPSHPT1HPX1HPT0HPX0H
Bit
Number
7-
6PPCH
5PT2H
4PSH
3PT1H
Bit
MnemonicDescription
Reserved
The value read from this bit is indeterminate. Do not set this bit.
The AT89C5131A-L implements a keyboard interface allowing the connection of a 8 x n
matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both
high or low level. These inputs are available as an alternate function of P1 and allow to
exit from idle and power down modes.
Description
The keyboard interface communicates with the C51 core through 3 special function registers: KBLS, the Keyboard Level Selection register (Table 70), KBE, The Keyboard
interrupt Enable register (Table 69), and KBF, the Keyboard Flag register (Table 68).
Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard interrupt (see Figure 40). As detailed in Figure 41 each keyboard
input has the capability to detect a programmable level according to KBLS.x bit value.
Level detection is then reported in interrupt flags KBF.x that can be masked by software
using KBE.x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage
of P1 inputs for other purpose.
Figure 40. Keyboard Interface Block Diagram
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Figure 41. Keyboard Input Circuitry
85
AT89C5131A-L
Power Reduction ModeP1 inputs allow exit from idle and power down modes as detailed in section “Power-
down Mode”.
Registers
Table 68. KBF Register
KBF - Keyboard Flag Register (9Eh)
76543210
KBF7KBF6KBF5KBF4KBF3KBF2KBF1 KBF0
Bit
Number
7KBF7
6KBF6
5KBF5
4KBF4
Bit
Mnemonic Description
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
Keyboard line 3 flag
3KBF3
2KBF2
1KBF1
0KBF0
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.
Cleared by hardware when reading KBF SFR by software.
Reset Value = 0000 0000b
86
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Table 69. KBE Register
KBE - Keyboard Input Enable Register (9Dh)
76543210
KBE7KBE6KBE5KBE4KBE3KBE2KBE1 KBE0
Bit
Number
7KBE7
6KBE6
5KBE5
4KBE4
3KBE3
2KBE2
1KBE1
Bit
Mnemonic Description
Keyboard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
Keyboard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
Keyboard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
Keyboard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
Keyboard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
Keyboard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
Keyboard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
0KBE0
Keyboard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
Reset Value = 0000 0000b
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AT89C5131A-L
Table 70. KBLS Register
KBLS-Keyboard Level Selector Register (9Ch)
76543210
KBLS7KBLS6KBLS5KBLS4KBLS3KBLS2KBLS1 KBLS0
Bit
Number
7KBLS7
6KBLS6
5KBLS5
4KBLS4
3KBLS3
2KBLS2
1KBLS1
Bit
Mnemonic Description
Keyboard line 7 Level Selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
Keyboard line 6 Level Selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
Keyboard line 5 Level Selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
Keyboard line 4 Level Selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
Keyboard line 3 Level Selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
Keyboard line 2 Level Selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
Keyboard line 1 Level Selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
0KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
Reset Value = 0000 0000b
88
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AT89C5131A-L
Programmable LED
AT89C5131A-L have up to 4 programmable LED current sources, configured by the
register LEDCON.
Table 71. LEDCON Register
LEDCON (S:F1h) LED Control Register
76543210
LED3LED2LED1LED0
Bit
Number
7:6LED3
5:4LED2
3:2LED1
Bit
Mnemonic Description
PortLED3Configuration
0 0Standard C51 Port
0 1 2 mA current source when P3.7 is low
1 0 4 mA current source when P3.7 is low
1 1 10 mA current source when P3.7 is low
Port/LED2Configuration
0 0 Standard C51 Port
0 1 2 mA current source when P3.6 is low
1 0 4 mA current source when P3.6 is low
1 1 10 mA current source when P3.6 is low
Port/LED1Configuration
0 0 Standard C51 Port
0 1 2 mA current source when P3.5 is low
1 0 4 mA current source when P3.5 is low
1 1 10 mA current source when P3.5 is low
1:0LED0
Reset Value = 00h
Port/LED0Configuration
0 0 Standard C51 Port
0 1 2 mA current source when P3.3 is low
1 0 4 mA current source when P3.3 is low
1 1 10 mA current source when P3.3 is low
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AT89C5131A-L
Serial Peripheral
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
0
1
2
3
Slave 3
MISO
MOSI
SCK
SS
Slave 4
MISO
MOSI
SCK
SS
Slave 2
MISO
MOSI
SCK
SS
VDD
Master
Interface (SPI)
The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial
communication between the MCU and peripheral devices, including other MCUs.
Features
Signal Description
Features of the SPI module include the following:
•Full-duplex, three-wire synchronous transfers
•Master or Slave operation
•Eight programmable Master clock rates
•Serial clock with programmable polarity and phase
•Master mode fault error flag with MCU interrupt capability
•Write collision flag protection
Figure 42 shows a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices:
Figure 42. SPI Master/Slaves Interconnection
Master Output Slave Input
(MOSI)
Master Input Slave Output
(MISO)
SPI Serial Clock (SCK)This signal is used to synchronize the data movement both in and out the devices
Slave Select (SS)Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay
90
The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.
This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one byte on the serial lines.
low for any message for a Slave. It is obvious that only one Master (SS high level) can
drive the network. The Master may select each Slave device by software through port
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AT89C5131A-L
pins (Figure 42). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Section “Error Conditions”, page 95).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set
•The Device is configured as a Slave with CPHA and SSDIS control bits set
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
Notes:1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in
this mode, the SS is used to start the transmission.
(1)
.
(2)
This
Baud RateIn Master mode, the baud rate can be selected from a baud rate generator which is con-
trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is
chosen from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 72 gives the different clock rates selected by SPR2:SPR1:SPR0:
Table 72. SPI Master Baud Rate Selection
SPR2SPR1SPR0Clock RateBaud Rate Divisor (BD)
000Don’t UseNo BRG
001F
010F
011F
100F
101F
110F
111Don’t UseNo BRG
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
/44
/88
/1616
/3232
/6464
/128128
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91
AT89C5131A-L
Functional Description
Shift Register
01
234567
Internal Bus
Pin
Control
Logic
MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit signal
SS
FCLK PERIPH
/32
/8
/16
Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA
SPR0
SPR1
CPOLMSTRSSDISSPEN
SPR2
SPCON
WCOLMODFSPIF
----
SSERR
Figure 43 shows a detailed structure of the SPI module.
Figure 43. SPI Module Block Diagram
Operating ModesThe Serial Peripheral Interface can be configured as one of the two modes: Master
92
mode or Slave mode. The configuration and initialization of the SPI module is made
through one register:
•The Serial Peripheral CONtrol register (SPCON)
Once the SPI is configured, the data exchange is made using:
•SPCON
•The Serial Peripheral STAtus register (SPSTA)
•The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 44).
Master ModeThe SPI operates in Master mode when the Master bit, MSTR
is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the Serial Peripheral Data Register
(SPDAT). If the shift register is empty, the byte is immediately transferred to the shift
register. The byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin.
The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA
becomes set. At the same time that SPIF becomes set, the received byte from the Slave
is transferred to the receive data register in SPDAT. Software clears SPIF by reading
the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
Slave ModeThe SPI operates in Slave mode when the Master bit, MSTR
(2)
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to’0’. SS must remain low until the transmission is complete.
In a Slave SPI module, data enters the shift register under the control of the SCK from
the Master SPI module. After a byte enters the shift register, it is immediately transferred
to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow
condition, Slave software must then read the SPDAT before another byte enters the
shift register
(3)
. A Slave SPI must complete the write to the SPDAT (shift register) at
least one bus cycle before the Master SPI starts a transmission. If the write to the data
register is late, the SPI transmits the data already in the shift register from the previous
transmission.
(1)
, in the SPCON register
, in the SPCON register is
Transmission FormatsSoftware can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock POLarity (CPOL
(4)
) and the Clock PHAse
(CPHA4). CPOL defines the default SCK line level in idle state. It has no significant
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 45 and Figure 46).
The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
1.The SPI module should be configured as a Master before it is enabled (SPEN set). Also
the Master SPI should be configured before the Slave SPI.
2.The SPI module should be configured as a Slave before it is enabled (SPEN set).
3.The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
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4.Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).
93
AT89C5131A-L
Figure 45. Data Transmission Format (CPHA = 0)
MSBbit6bit5bit4bit3bit2bit1LSB
bit6bit5bit4bit3bit2bit1MSBLSB
13245678
Capture point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK cycle number
MSBbit6bit5bit4bit3bit2bit1LSB
bit6bit5bit4bit3bit2bit1
MSBLSB
13245678
Capture point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK cycle number
Byte 1Byte 2
Byte 3
MISO/MOSI
Master SS
Slave SS
(CPHA = 1)
Slave SS
(CPHA = 0)
Figure 46. Data Transmission Format (CPHA = 1)
Figure 47. CPHA/SS Timing
94
As shown in Figure 46, the first SCK edge is the MSB capture strobe. Therefore the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each byte transmitted (Figure 43).
Figure 47 shows an SPI transmission in which CPHA is’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 42). This format may be preferable in systems having only one Master and
only one Slave driving the MISO data line.
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AT89C5131A-L
Error ConditionsThe following flags in the SPSTA signal SPI error conditions:
Mode Fault (MODF)Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)
pin is inconsistent with the actual mode of the device. MODF is set to warn that there
may have a multi-master conflict for system control. In this case, the SPI system is
affected in the following ways:
•An SPI receiver/error CPU interrupt request is generated,
•The SPEN bit in SPCON is cleared. This disable the SPI,
•The MSTR bit in SPCON is cleared
When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set
when the SS signal becomes “0”.
However, as stated before, for a system with one Master, if the SS pin of the Master
device is pulled low, there is no way that another Master attempt to drive the network. In
this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the
SPCON register and therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set,
followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared.
Write Collision (WCOL)A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA
and an access to SPDAT.
Overrun ConditionAn overrun condition occurs when the Master device tries to send several data bytes
and the Slave devise has not cleared the SPIF bit issuing from the previous data byte
transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was
last cleared. A read of the SPDAT returns this byte. All others bytes are lost.
This condition is not detected by the SPI peripheral.
InterruptsTwo SPI status flags can generate a CPU interrupt requests:
Table 73. SPI Interrupts
FlagRequest
SPIF (SP Data Transfer)SPI Transmitter Interrupt request
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests.
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Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests.
Figure 48 gives a logical view of the above statements.
95
AT89C5131A-L
Figure 48. SPI Interrupt Requests Generation
SSDIS
MODF
CPU Interrupt Request
SPI Receiver/Error
CPU Interrupt Request
SPI Transmitter
SPI
CPU Interrupt Request
SPIF
RegistersThere are three registers in the module that provide control, status and data storage
functions. These registers are describes in the following paragraphs.
Serial Peripheral Control
Register (SPCON)
•The Serial Peripheral Control Register does the following:
–Selects one of the Master clock rates
–Configure the SPI module as Master or Slave
–Selects serial clock polarity and phase
–Enables the SPI module
–Frees the SS pin for a general-purpose
Table 74 describes this register and explains the use of each bit.
Table 74. SPCON Register
76543210
SPR2SPENSSDISMSTRCPOLCPHASPR1SPR0
Bit
NumberBit Mnemonic Description
7SPR2
6SPEN
5SSDIS
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit has
no effect if CPHA = “0”.
96
5MSTR
4CPOL
3CPHA
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to “0” in idle state.
Set to have the SCK set to “1” in idle state.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle state (see
CPOL).
Set to have the data sampled when the SCK returns to idle state (see CPOL).
4338F–USB–08/07
Bit
NumberBit Mnemonic Description
SPR2 SPR1 SPR0 Serial Peripheral Rate
2SPR1
1SPR0
000Reserved
00 1F
CLK PERIPH/
010 F
CLK PERIPH/
011F
CLK PERIPH/
100F
CLK PERIPH/
10 1F
CLK PERIPH/
110F
CLK PERIPH/
1 11Reserved
Reset Value = 0001 0100b
Not bit addressable
AT89C5131A-L
4
8
16
32
64
128
Serial Peripheral Status Register
(SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
•Data transfer complete
•Write collision
•Inconsistent logic level on SS pin (mode fault error)
Table 75 describes the SPSTA register and explains the use of every bit in the register.
Table 75. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
Table 1.
76543210
SPIFWCOLSSERRMODF----
Bit
Number
7SPIF
6WCOL
Bit
Mnemonic Description
Serial Peripheral data transfer flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision flag
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
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5SSERR
4MODF
3-
Synchronous Serial Slave Error flag
Set by hardware when SS is de-
asserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
Reserved
The value read from this bit is indeterminate. Do not set this bit
97
AT89C5131A-L
Bit
Number
Bit
Mnemonic Description
Serial Peripheral Data Register
(SPDAT)
2-
1-
0-
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X0 XXXXb
Not Bit addressable
The Serial Peripheral Data Register (Table 76) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 76. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
Table 2.
76543210
R7R6R5R4R3R2R1R0
Reset Value = Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there
is no on-going exchange. However, special care should be taken when writing to them
while a transmission is on-going:
•Do not change SPR2, SPR1 and SPR0
•Do not change CPHA and CPOL
•Do not change MSTR
•Clearing SPEN would immediately disable the peripheral
•Writing to the SPDAT will cause an overflow
98
4338F–USB–08/07
AT89C5131A-L
SCL
SDA
device2device1deviceNdevice3
...
Two Wire Interface (
TWI
)
This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire
serial communication standard. It is designed primarily for simple but efficient integrated
circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA
(Serial Data) that carry information between the ICs connected to them. The serial data
transfer is limited to 100 Kbit/s in standard mode. Various communication configuration
can be designed using this bus. Figure 49 shows a typical 2-wire bus configuration. All
the devices connected to the bus can be master and slave.
Figure 49. 2-wire Bus Configuration
4338F–USB–08/07
99
AT89C5131A-L
Figure 50. Block Diagram
Address Register
Comparator
Timing &
Control
logic
Arbitration &
Sink Logic
Serial clock
generator
Shift Register
Control Register
Status Register
Status
Decoder
Input
Filter
Output
Stage
Input
Filter
Output
Stage
ACK
Status
Bits
8
8
7
8
Internal Bus
Timer 1
overflow
F
CLK PERIPH
/4
Interrupt
SDA
SCL
SSADR
SSCON
SSDAT
SSCS
100
4338F–USB–08/07
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