ATMEL AT89C5131A-L User Manual

BDTIC www.bdtic.com/ATMEL

Features

• 80C52X2 Core (6 Clocks per Instruction)

– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART) – Three 16-bit Timer/Counters: T0, T1 and T2 – 256 Bytes of Scratchpad RAM

• 16/32-Kbyte On-chip Flash EEPROM In-System Programming through USB

– Byte and Page (128 bytes) Erase and Write – 100k Write Cycles

• 3-KbyteFlash EEPROM for Bootloader

– Byte and Page (128 bytes) Erase and Write – 100k Write Cycles

• 1-Kbyte EEPROM Data (

– Byte and Page (128 bytes) Erase and Write – 100k Write Cycles

• On-chip Expanded RAM (ERAM): 1024 Bytes

• Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply

• USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion

– Endpoint 0 for Control Transfers: 32-byte FIFO – 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or

Isochronous Transfers

• Endpoint 1, 2, 3: 32-byte FIFO

• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)

• Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode) – Suspend/Resume Interrupts – Power-on Reset and USB Bus Reset – 48 MHz DPLL for Full-speed Bus Operation – USB Bus Disconnection on Microcontroller Request

• 5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed

Output, Compare/Capture, PWM and Watchdog Timer Capabilities

• Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 50 ms to

6s at 4 MHz

• Keyboard Interrupt Interface on Port P1 (8 Bits)

• TWI (Two Wire Interface) 400Kbit/s

• SPI Interface (Master/Slave Mode)

• 34 I/O Pins

• 4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical

• 4-level Priority Interrupt System (11 sources)

• Idle and Power-down Modes

• 0 to 32 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis

• Industrial Temperature Range

• Low Voltage Range Supply: 2.7V to 3.6V (3.0V to 3.6V required for USB)

• Packages: SO28, PLCC52, VQFP64

8-bit Flash Microcontroller with Full Speed USB Device

AT89C5131A-L

Rev. 4338F–USB–08/07

AT89C5131A-L

Description

AT89C5131A-L is a high-performance Flash version of the 80C51 single-chip 8-bit microcontrollers with full speed USB functions.

AT89C5131A-L features a full-speed USB module compatible with the USB specifications Version 1.1 and 2.0. This module integrates the USB transceivers with a 3.3V voltage regulator and the Serial Interface Engine (SIE) with Digital Phase Locked Loop and 48 MHz clock recovery. USB Event detection logic (Reset and Suspend/Resume) and FIFO buffers supporting the mandatory control Endpoint (EP0) and up to 6 versatile Endpoints (EP1/EP2/EP3/EP4/EP5/EP6) with minimum software overhead are also part of the USB module.

AT89C5131A-L retains the features of the Atmel 80C52 with extended Flash capacity (3 2 -Kbyt e), 256 b ytes of int ernal R AM, a 4-l evel int errup t syste m, two 16 -bit timer/counters (T0/ T1), a full duplex enhanced U ART (EUART) and an on-chip oscillator.

In addition, AT89C5131A-L has an on-chip expanded RAM of 1024 bytes (ERAM), a dual- data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA), up to 4 programmable LED current sources, a programmable hardware watchdog and a power-on reset.

AT89C5131A-L has two software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial ports and the interrupt system are still operating. In the power-down mode the RAM is saved, the peripheral clock is frozen, but the device has full wake-up capability through USB events or external interrupts.

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Block Diagram

Timer 0

INT

RAM

256x8

RxD

TxD

PSEN

ALE

XTAL2

XTAL1

EUART

CPU

Timer 1

INT1

Ctrl

INT0

(2)

C51

CORE

(2) (2) (2) (2)

Port 0P0Port 1

Port 2

Port 3

Parallel I/O Ports & Ext. Bus

ERAM

1Kx8

PCA

RST

Watch

Dog

CEX

ECI

VSS

VDD

(2)(2)

(1)(1)

Timer2

T2EX

(1)

Port 4

32Kx8 Flash

BRG

USB

D -

D +

VREF

Regu-

Key

Board

KIN

lator

AVSS

EEPROM

4Kx8

SPI

MISO

MOSI

SCK

(1) (1) (1)

(1)

AVDD

TWI

SCL

SDA

AT89C5131A-L

Notes: 1. Alternate function of Port 1

2. Alternate function of Port 3

3. Alternate function of Port 4

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AT89C5131A-L

Pinout Description

21 22 26252423 292827 30 31

5 4 3 2 1 6

52 51 50 49 48

40 39

PLCC52

32 33

P1.1/T2EX/KIN1/SS

P1.0/T2/KIN0

P0.6/AD6

ALE

P0.7/AD7

PSEN

P1.7/CEX4/KIN7/MOSI

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

P1.6/CEX3/KIN6/SCK

PLLF

P3.0/RxD

AVSS

P2.6/A14

XTAL1

P2.5/A13

P0.3/AD3

P0.5/AD5

P0.4/AD4

VREF

P0.2/AD2

P0.0/AD0

P0.1/AD1

AVDD

P3.2/INT0

P3.6/WR/LED2

XTAL2

RST

P3.1/TxD

P3.3/INT1/LED0

P3.7/RD/LED3

D-

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

VSS

P2.4/A12

P4.1/SDA

D+

P4.0/SCL

P1.2/ECI/KIN2

P1.4/CEX1/KIN4

P3.4/T0

P3.5/T1/LED1

VDD

P2.7/A15

Pinout

Figure 1. AT89C5131A-L 52-pin PLCC Pinout

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Figure 2. AT89C5131A-L 64-pin VQFP Pinout

17 18 22212019 252423 26 27

62 61 60 59 58 63

57 56 55 54 53

1 2

48 47

41 40

VQFP64

12 13

51 50

15 16

31 32

P1.1/T2EX/KIN1/SS

ALE

PSEN

P1.7/CEX4/KIN7/MOSI

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

P1.6/CEX3/KIN6/SCK

P2.7/A15

P2.6/A14

P4.1/SDA

P1.2/ECI/KIN2

P1.4/CEX1/KIN4

P1.0/T2/KIN0

PLLF

XTAL2

RST

P3.7/RD/LED3

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P3.0/RxD

VREF

P0.0/AD0

AVSS

P3.2/INT0

P3.6/WR/LED2

P3.1/TxD

P3.3/INT1/LED0

VSS

P3.4/T0

P3.5/T1/LED1

P0.6/AD6 P0.7/AD7

P2.5/A13

P0.3/AD3

P0.5/AD5

P0.4/AD4

P0.2/AD2

P0.1/AD1

D-

D+

P4.0/SCL

XTAL1

AVDD

VDD

P1.1/T2EX/KIN1/SS

PLLF

P3.0/RxD

P1.0/T2/KIN0

AVSS

VDD

XTAL1

XTAL2

P3.2/INT0

P3.5/T1/LED1

P3.6/WR/LED2

P3.7/RD/LED3

D-

P1.4/CEX1/KIN4

VSS

D+

P1.2/ECI/KIN2

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

RST

P1.6/CEX3/KIN6/SCK

P1.7/CEX4/KIN7/MOSI

P4.0/SCL

VREF P3.1/TxD

P3.4/T0

3 4

7 8

27 26

24 23

19 18

SO28

P4.1/SDA

P3.3/INT1/LED0

AT89C5131A-L

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Figure 3. AT89C5131A-L 28-pin SO Pinout

AT89C5131A-L

Signals

All the AT89C5131A-L signals are detailed by functionality on Table 1 through Table 12.

Table 1. Keypad Interface Signal Description

Signal Name Type Description

KIN[7:0) I

Keypad Input Lines

Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt if enabled. Held line is reported in the KBCON register.

Table 2. Programmable Counter Array Signal Description

Signal

Name Type Description

ECI I External Clock Input P1.2

Capture External Input

CEX[4:0] I/O

Compare External Output

Table 3. Serial I/O Signal Description

Signal Name Type Description

RxD I

Serial Input

The serial input for Extended UART.

Alternate Function

P1[7:0]

Alternate Function

P1.3

P1.4

P1.5

P1.6

P1.7

Alternate Function

P3.0

TxD O

Serial Output

The serial output for Extended UART.

Table 4. Timer 0, Timer 1 and Timer 2 Signal Description

Signal Name Type Description

Timer 0 Gate Input

INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register.

INT0 I

INT1 I

External Interrupt 0

INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits IE0 are set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by a low level on INT0.

Timer 1 Gate Input

INT1 serves as external run control for Timer 1, when selected by GATE1 bit in TCON register.

External Interrupt 1

INT1 input set IE1 in the TCON register. If bit IT1 in this register is set, bits IE1 are set by a falling edge on INT1. If bit IT1 is cleared, bits IE1 is set by a low level on INT1.

P3.1

Alternate Function

P3.2

P3.3

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AT89C5131A-L

Table 4. Timer 0, Timer 1 and Timer 2 Signal Description (Continued)

Signal Name Type Description

Alternate Function

T0 I

T1 I

T2EX I Timer/Counter 2 Reload/Capture/Direction Control Input P1.1

Timer Counter 0 External Clock Input

When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count.

Timer/Counter 1 External Clock Input

When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count.

IOTimer/Counter 2 External Clock Input

Timer/Counter 2 Clock Output

Table 5. LED Signal Description

Signal

Name Type Description

Direct Drive LED Output

LED[3:0] O

These pins can be directly connected to the Cathode of standard LEDs without external current limiting resistors. The typical current of each output can be programmed by software to 2, 6 or 10 mA. Several outputs can be connected together to get higher drive capabilities.

Table 6. TWI Signal Description

Signal

Name Type Description

P3.4

P3.5

P1.0

Alternate Function

P3.3

P3.5

P3.6

P3.7

Alternate Function

SCL I/O

SDA I/O

SCL: TWI Serial Clock

SCL output the serial clock to slave peripherals. SCL input the serial clock from master.

SDA: TWI Serial Data

SCL is the bidirectional TWI data line.

Table 7. SPI Signal Description

Signal Name Type Description

SS I/O SS: SPI Slave Select P1.1

MISO: SPI Master Input Slave Output line

MISO I/O

SCK I/O

MOSI

When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller.

SCK: SPI Serial Clock

SCK outputs clock to the slave peripheral or receive clock from the master

MOSI: SPI Master Output Slave Input line

I/O

When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller

P4.0

P4.1

Alternate Function

P1.5

P1.6

P1.7

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AT89C5131A-L

Table 8. Ports Signal Description

Signal

Name Type Description Alternate Function

Port 0

P0 is an 8-bit open-drain bidirectional I/O port. Port 0

P0[7:0] I/O

P1[7:0] I/O

pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, Floating P0 inputs must be pulled to V VSS.

Port 1

P1 is an 8-bit bidirectional I/O port with internal pull-ups.

AD[7:0]

KIN[7:0]

T2EX

ECI

CEX[4:0]

P2[7:0] I/O

P3[7:0] I/O

P4[1:0] I/O

Port 2

P2 is an 8-bit bidirectional I/O port with internal pull-ups.

Port 3

P3 is an 8-bit bidirectional I/O port with internal pull-ups.

Port 4

P4 is an 2-bit open port.

Table 9. Clock Signal Description

Signal Name Type Description

XTAL1 I

XTAL2 O

Input to the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin.

Output of the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected.

A[15:8]

LED[3:0]

RxD

TxD

INT0 INT1

T0 T1

SCL

SDA

Alternate Function

PLLF I

PLL Low Pass Filter input

Receives the RC network of the PLL low pass filter (See Figure 4 on page 11 ).

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Table 10. USB Signal Description

AT89C5131A-L

Signal Name Type Description

D+ I/O

D- I/O

VREF O

USB Data + signal

Set to high level under reset.

USB Data - signal

Set to low level under reset.

USB Reference Voltage

Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function.

Table 11. System Signal Description

Signal Name Type Description

AD[7:0] I/O

A[15:8] I/O

RD I/O

WR I/O

Multiplexed Address/Data LSB for external access

Data LSB for Slave port access (used for 8-bit and 16-bit modes)

Address Bus MSB for external access

Data MSB for Slave port access (used for 16-bit mode only)

Read Signal

Read signal asserted during external data memory read operation.

Control input for slave port read access cycles.

Write Signal

Write signal asserted during external data memory write operation.

Control input for slave write access cycles.

Alternate Function

P0[7:0]

P2[7:0]

P3.7

P3.6

RST I/O

ALE O

PSEN O

EA I

Reset

Holding this pin low for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and VSS. Asserting RST when the chip is in Idle mode or Power-down mode returns the chip to normal operation. This pin is set to 0 for at least 12 oscillator periods when an internal reset occurs (hardware watchdog or Power monitor).

Address Latch Enable Output

The falling edge of ALE strobes the address into external latch. This signal is active only when reading or writing external memory using MOVX instructions.

Program Strobe Enable / Hardware conditions Input for ISP

Used as input under reset to detect external hardware conditions of ISP mode

External Access Enable

This pin must be held low to force the device to fetch code from external program memory starting at address 0000h. It is latched during reset and cannot be dynamically changed during operation.

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AT89C5131A-L

Table 12. Power Signal Description

Signal Name Type Description

Alternate Function

AVSS GND

AVDD PWR

VSS GND

VDD PWR

VREF O

Alternate Ground

AVSS is used to supply the on-chip PLL and the USB PAD.

Alternate Supply Voltage

AVDD is used to supply the on-chip PLL and the USB PAD.

Digital Ground

VSS is used to supply the buffer ring and the digital core.

Digital Supply Voltage

VDD is used to supply the buffer ring on all versions of the device.

It is also used to power the on-chip voltage regulator of the Standard versions or the digital core of the Low Power versions.

USB pull-up Controlled Output

VREF is used to control the USB D+ 1.5 kΩ pull up.

The Vref output is in high impedance when the bit DETACH is set in the USBCON register.

4338F–USB–08/07

Typical Application

VSS

XTAL1

XTAL2

22pF

VSS

PLLF

100R

10nF

2.2nF

VSS

AVSS

VSS

D-

D+

27R

VRef

1.5K

USB

D+

D-

VBUS

GND

VSS

VDD

AVDD

VDD

4.7µF

VSS

100nF

VSS

100nF

VSS

AT89C5131A-L

Recommended External components

All the external components described in the figure below must be implemented as close as possible from the microcontroller package.

The following figure represents the typical wiring schematic.

Figure 4. Typical Application

AT89C5131A-L

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AT89C5131A-L

PCB Recommandations

D+

VRef

D-

USB Connector

Wires must be routed in Parallel and

Components must be

If possible, isolate D+ and D- signals from other signals with ground wires

must be as short as possible

close to the microcontroller

PLLFAVss

Components must be

Isolate filter components

with a ground wire

microcontroller

close to the

Figure 5. USB Pads

Figure 6. USB PLL

4338F–USB–08/07

Clock Controller

PCON.1

IDL

PCON.0

Peripheral

CPU Core

CKCON.0

Clock

EXT48

PLLCON.2

PLL

USB Clock

AT89C5131A-L

Introduction

Figure 7. Oscillator Block Diagram

The AT89C5131A-L clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller.

The AT89C5131A-L X1 and X2 pins are the input and the output of a single-stage onchip inverter (see Figure 7) that can be configured with off-chip components as a Pierce oscillator (see Figure 8). Value of capacitors and crystal characteristics are detailed in the section “DC Characteristics”.

The X1 pin can also be used as input for an external 48 MHz clock.

The clock controller outputs three different clocks as shown in Figure 7:

• a clock for the CPU core

• a clock for the peripherals which is used to generate the Timers, PCA, WD, and Port sampling clocks

• a clock for the USB controller

These clocks are enabled or disabled depending on the power reduction mode as detailed in Section “Power Management”, page 152.

Oscillator

4338F–USB–08/07

Two clock sources are available for CPU:

• Crystal oscillator on X1 and X2 pins: Up to 32 MHz

• External 48 MHz clock on X1 pin

In order to optimize the power consumption, the oscillator inverter is inactive when the PLL output is not selected for the USB device.

AT89C5131A-L

Figure 8. Crystal Connection

VSS

PLLEN

PLLCON.1

N3:0

N divider

R divider

VCO USB Clock

US Bclk

OSCclk R 1+( )×

N 1+

-----------------------------------------------=

OSC

CLOCK

PFLD

PLOCK

PLLCON.0

PLLF

CHP

Vref

Down

R3:0

USB

CLOCK

USB Clock Symbol

VSS

PLLF

VSS

PLL

PLL Description The AT89C5131A-L PLL is used to generate internal high frequency clock (the USB

Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to generate the USB interface clock. Figure 9 shows the internal structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Figure 9) is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the external filter connected on PLLF pin (see Figure 10 ) . Value o f the fil ter c o m p onents a r e d etailed i n t h e Section “ D C Characteristics”.

Figure 9. PLL Block Diagram and Symbol

The VCO block is the Voltage Controlled Oscillator controlled by the voltage V duced by the charge pump. It generates a square wave signal: the PLL clock.

Figure 10. PLL Filter Connection

The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF.

REF

pro-

4338F–USB–08/07

AT89C5131A-L

PLL

Programming

Configure Dividers

N3:0 = xxxxb R3:0 = xxxxb

Enable PLL

PLLEN = 1

PLL Locked?

LOCK = 1?

PLL Programming The PLL is programmed using the flow shown in Figure 11. As soon as clock generation

is enabled user must wait until the lock indicator is set to ensure the clock output is stable.

Figure 11. PLL Programming Flow

Divider Values To generate a 48 MHz clock using the PLL, the divider values have to be configured fol-

lowing the oscillator frequency. The typical divider values are shown in Table 13.

Table 13. Typical Divider Values

Oscillator Frequency R+1 N+1 PLLDIV

3 MHz 16 1 F0h

6 MHz 8 1 70h

8 MHz 6 1 50h

12 MHz 4 1 30h

16 MHz 3 1 20h

18 MHz 8 3 72h

20 MHz 12 5 B4h

24 MHz 2 1 10h

32 MHz 3 2 21h

40 MHz 12 10 B9h

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AT89C5131A-L

Registers

Table 14. CKCON0 (S:8Fh)

Clock Control Register 0

7 6 5 4 3 2 1 0

TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit Number

7 TWIX2

6 WDX2

5 PCAX2

4 SIX2

3 T2X2

Bit

Mnemonic Description

TWI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Watchdog Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART Clock (Mode 0 and 2) This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer2 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer1 Clock

2 T1X2

1 T0X2

0 X2

This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer0 Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

System Clock Control bit

Clear to select 12 clock periods per machine cycle (STD mode, F F

OSC

Set to select 6 clock periods per machine cycle (X2 mode, F

Reset Value = 0000 0000b

= F

CPU

2).

CPU = FPER = FOSC

PER =

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AT89C5131A-L

Table 15. CKCON1 (S:AFh)

Clock Control Register 1

7 6 5 4 3 2 1 0

- - - - - - - SPIX2

Bit Number

7-1 -

0 SPIX2

Bit

Mnemonic Description

Reserved

The value read from this bit is always 0. Do not set this bit.

SPI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Reset Value = 0000 0000b

Table 16. PLLCON (S:A3h) PLL Control Register

7 6 5 4 3 2 1 0

- - - - - EXT48 PLLEN PLOCK

Bit Number

7-3 -

2 EXT48

Bit

Mnemonic Description

Reserved

The value read from this bit is always 0. Do not set this bit.

External 48 MHz Enable Bit

Set this bit to bypass the PLL and disable the crystal oscillator. Clear this bit to select the PLL output as USB clock and to enable the crystal oscillator.

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PLL Enable Bit

1 PLLEN

0 PLOCK

Set to enable the PLL. Clear to disable the PLL.

PLL Lock Indicator

Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked.

Reset Value = 0000 0000b Table 17. PLLDIV (S:A4h) PLL Divider Register

7 6 5 4 3 2 1 0

R3 R2 R1 R0 N3 N2 N1 N0

Bit Number

7-4 R3:0 PLL R Divider Bits

3-0 N3:0 PLL N Divider Bits

Bit

Mnemonic Description

Reset Value = 0000 0000

AT89C5131A-L

SFR Mapping

The Special Function Registers (SFRs) of the AT89C5131A-L fall into the following categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP

• I/O port registers: P0, P1, P2, P3, P4

• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON

• PCA (Programmable Counter Array) registers: CCON, CMOD, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4)

• Power and clock control registers: PCON

• Hardware Watchdog Timer registers: WDTRST, WDTPRG

• Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1

• Keyboard Interface registers: KBE, KBF, KBLS

• LED register: LEDCON

• Two Wire Interface (TWI) registers: SSCON, SSCS, SSDAT, SSADR

• Serial Port Interface (SPI) registers: SPCON, SPSTA, SPDAT

• USB registers: Uxxx (17 registers)

• PLL registers: PLLCON, PLLDIV

• BRG (Baud Rate Generator) registers: BRL, BDRCON

• Flash register: FCON (FCON access is reserved for the Flash API and ISP software)

• EEPROM register: EECON

• Others: AUXR, AUXR1, CKCON0, CKCON1

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Table 18. SFR Descriptions

Reserved

Bit

Addressable Non-Bit Addressable

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

AT89C5131A-L

The table below shows all SFRs with their address and their reset value.

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

UEPINT

0000 0000

ACC

0000 0000

CCON

00X0 0000

PSW

0000 0000

T2CON

0000 0000

XXXX 1111

IPL0

X000 000

1111 1111

0000 0000

LEDCON

0000 0000

CMOD

00XX X000

FCON (1)

XXXX 0000

T2MOD

XXXX XX00

SADEN

0000 0000

IEN1

X0XX X000

CCAP0H

XXXX XXXX

CCAP0L

XXXX XXXX

UBYCTLX

0000 0000

CCAPM0

X000 0000

EECON

XXXX XX00

RCAP2L

0000 0000

UEPIEN

0000 0000

UFNUML

0000 0000

IPL1

X0XX X000

CCAP1H

XXXX XXXX

CCAP1L

XXXX XXXX

UBYCTHX 0000 0000

CCAPM1

X000 0000

RCAP2H

0000 0000

SPCON

0001 0100

UFNUMH

0000 0000

IPH1

X0XX X000

CCAP2H

XXXX XXXX

CCAP2L

XXXX XXXX

CCAPM2

X000 0000

UEPCONX

1000 0000

TL2

0000 0000

SPSTA

0000 0000

USBCON

0000 0000

CCAP3H

XXXX XXXX

CCAP3L

XXXX XXXX

CCAPM3

X000 0000

UEPRST

0000 0000

TH2

0000 0000

SPDAT

XXXX XXXX

USBINT

0000 0000

CCAP4H

XXXX XXXX

CCAP4L

XXXX XXXX

CCAPM4

X000 0000

UEPSTAX

0000 0000

USBADDR 1000 0000

USBIEN

0000 0000

UEPDATX 0000 0000

UEPNUM

0000 0000

IPH0

X000 0000

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

A8h

A0h

98h

90h

88h

80h

IEN0

0000 0000

1111 1111

SCON

0000 0000

1111 1111

TCON

0000 0000

1111 1111

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

SADDR

0000 0000

SBUF

XXXX XXXX

TMOD

0000 0000

0000 0111

AUXR1

XXXX X0X0

BRL

0000 0000

TL0

0000 0000

DPL

0000 0000

PLLCON

XXXX XX00

BDRCON

XXX0 0000

SSCON

0000 0000

TL1

0000 0000

DPH

0000 0000

1111 1000

0000 0000

Note: 1. FCON access is reserved for the Flash API and ISP software.

PLLDIV

KBLS

SSCS

TH0

KBE

0000 0000

SSDAT

1111 1111

TH1

0000 0000

WDTRST

XXXX XXXX

KBF

0000 0000

SSADR

1111 1110

AUXR

XX0X 0000

CKCON1

0000 0000

WDTPRG

XXXX X000

CKCON0

0000 0000

PCON

00X1 0000

AFh

A7h

9Fh

97h

8Fh

87h

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AT89C5131A-L

The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories:

Table 19. C51 Core SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

ACC E0h Accumulator

B F0h B Register

PSW D0h

SP 81h

DPL 82h

DPH 83h

Program Status Word

Stack Pointer

LSB of SPX

Data Pointer Low byte

LSB of DPTR

Data Pointer High byte

MSB of DPTR

Table 20. I/O Port SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

P0 80h Port 0

P1 90h Port 1

P2 A0h Port 2

P3 B0h Port 3

P4 C0h Port 4 (2bits)

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AT89C5131A-L

Table 21. Timer SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

TH0 8Ch Timer/Counter 0 High byte

TL0 8Ah Timer/Counter 0 Low byte

TH1 8Dh Timer/Counter 1 High byte

TL1 8Bh Timer/Counter 1 Low byte

TH2 CDh Timer/Counter 2 High byte

TL2 CCh Timer/Counter 2 Low byte

TCON 88h

TMOD 89h

T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

T2MOD C9h Timer/Counter 2 Mode T2OE DCEN

RCAP2H CBh

RCAP2L CAh

WDTRST A6h WatchDog Timer Reset

WDTPRG A7h WatchDog Timer Program S2 S1 S0

Timer/Counter 0 and 1 control

Timer/Counter 0 and 1 Modes

Timer/Counter 2 Reload/Capture High byte

Timer/Counter 2 Reload/Capture Low byte

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Table 22. Serial I/O Port SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

SBUF 99h Serial Data Buffer

SADEN B9h Slave Address Mask

SADDR A9h Slave Address

Table 23. Baud Rate Generator SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

BRL 9Ah Baud Rate Reload

BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC

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AT89C5131A-L

Table 24. PCA SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

CCON D8h PCA Timer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0

CMOD D9h PCA Timer/Counter Mode CIDL WDTE CPS1 CPS0 ECF

CL E9h PCA Timer/Counter Low byte

CH F9h PCA Timer/Counter High byte

CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4

CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H

CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L

DAh

PCA Timer/Counter Mode 0

DBh

PCA Timer/Counter Mode 1

DCh

PCA Timer/Counter Mode 2

DDh

PCA Timer/Counter Mode 3

DEh

PCA Timer/Counter Mode 4

FAh

PCA Compare Capture Module 0 H

FBh

PCA Compare Capture Module 1 H

FCh

PCA Compare Capture Module 2 H

FDh

PCA Compare Capture Module 3 H

FEh

PCA Compare Capture Module 4 H

EAh

PCA Compare Capture Module 0 L

EBh

PCA Compare Capture Module 1 L

ECh

PCA Compare Capture Module 2 L

EDh

PCA Compare Capture Module 3 L

EEh

PCA Compare Capture Module 4 L

CCAP0H7 CCAP1H7 CCAP2H7 CCAP3H7 CCAP4H7

CCAP0L7 CCAP1L7 CCAP2L7 CCAP3L7 CCAP4L7

ECOM0 ECOM1 ECOM2 ECOM3 ECOM4

CCAP0H6 CCAP1H6 CCAP2H6 CCAP3H6 CCAP4H6

CCAP0L6 CCAP1L6 CCAP2L6 CCAP3L6 CCAP4L6

CAPP0 CAPP1 CAPP2 CAPP3 CAPP4

CCAP0H5 CCAP1H5 CCAP2H5 CCAP3H5 CCAP4H5

CCAP0L5 CCAP1L5 CCAP2L5 CCAP3L5 CCAP4L5

CAPN0 CAPN1 CAPN2 CAPN3 CAPN4

CCAP0H4 CCAP1H4 CCAP2H4 CCAP3H4 CCAP4H4

CCAP0L4 CCAP1L4 CCAP2L4 CCAP3L4 CCAP4L4

MAT0 MAT1 MAT2 MAT3 MAT4

CCAP0H3 CCAP1H3 CCAP2H3 CCAP3H3 CCAP4H3

CCAP0L3 CCAP1L3 CCAP2L3 CCAP3L3 CCAP4L3

TOG0 TOG1 TOG2 TOG3 TOG4

CCAP0H2 CCAP1H2 CCAP2H2 CCAP3H2 CCAP4H2

CCAP0L2 CCAP1L2 CCAP2L2 CCAP3L2 CCAP4L2

PWM0 PWM1 PWM2 PWM3 PWM4

CCAP0H1 CCAP1H1 CCAP2H1 CCAP3H1 CCAP4H1

CCAP0L1 CCAP1L1 CCAP2L1 CCAP3L1 CCAP4L1

ECCF0 ECCF1 ECCF2 ECCF3 ECCF4

CCAP0H0 CCAP1H0 CCAP2H0 CCAP3H0 CCAP4H0

CCAP0L0 CCAP1L0 CCAP2L0 CCAP3L0 CCAP4L0

Table 25. Interrupt SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0

IEN1 B1h Interrupt Enable Control 1 EUSB ESPI ETWI EKB

IPL0 B8h Interrupt Priority Control Low 0 PPCL PT2L PSL PT1L PX1L PT0L PX0L

IPH0 B7h Interrupt Priority Control High 0 PPCH PT2H PSH PT1H PX1H PT0H PX0H

IPL1 B2h Interrupt Priority Control Low 1 PUSBL PSPIL PTWIL PKBL

IPH1 B3h Interrupt Priority Control High 1 PUSBH PSPIH PTWIH PKBH

Table 26. PLL SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

PLLCON A3h PLL Control EXT48 PLLEN PLOCK

PLLDIV A4h PLL Divider R3 R2 R1 R0 N3 N2 N1 N0

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AT89C5131A-L

Table 27. Keyboard SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

KBF 9Eh

KBE 9Dh

KBLS 9Ch

Keyboard Flag Register

Keyboard Input Enable Register

Keyboard Level Selector Register

KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0

KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0

KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0

Table 28. TWI SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SSCON 93h

SSCS 94h

SSDAT 95h

SSADR 96h

Synchronous Serial Control

Synchronous Serial Control-Status

Synchronous Serial Data

Synchronous Serial Address

CR2 SSIE STA STO SI AA CR1 CR0

SC4 SC3 SC2 SC1 SC0 - - -

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

A7 A6 A5 A4 A3 A2 A1 A0

Table 29. SPI SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SPCON C3h

SPSTA C4h

SPDAT C5h Serial Peripheral Data R7 R6 R5 R4 R3 R2 R1 R0

Serial Peripheral Control

Serial Peripheral Status-Control

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPIF WCOL SSERR MODF - - - -

Table 30. USB SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

USBCON BCh USB Global Control USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN

USBADDR C6h USB Address FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0

USBINT BDh USB Global Interrupt - - WUPCPU EORINT SOFINT - - SPINT

USBIEN BEh

UEPNUM C7h USB Endpoint Number - - - - EPNUM3 EPNUM2 EPNUM1 EPNUM0

UEPCONX D4h USB Endpoint X Control EPEN - - - DTGL EPDIR EPTYPE1 EPTYPE0

UEPSTAX CEh USB Endpoint X Status DIR RXOUTB1 STALLRQ TXRDY STLCRC RXSETUP RXOUTB0 TXCMP

UEPRST D5h USB Endpoint Reset - EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST

UEPINT F8h USB Endpoint Interrupt - EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

USB Global Interrupt Enable

- - EWUPCPU EEORINT ESOFINT - - ESPINT

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AT89C5131A-L

Table 30. USB SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

UEPIEN C2h

UEPDATX CFh USB Endpoint X FIFO Data FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0

UBYCTLX E2h

UBYCTHX E3h

UFNUML BAh USB Frame Number Low FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0

UFNUMH BBh USB Frame Number High - - CRCOK CRCERR - FNUM10 FNUM9 FNUM8

USB Endpoint Interrupt Enable

USB Byte Counter Low (EP X)

USB Byte Counter High (EP X)

- EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE

BYCT7 BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0

- - - - - BYCT10 BYCT9 BYCT8

Table 31. Other SFR’s

Mnemonic Add Name 7 6 5 4 3 2 1 0

PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDL

AUXR 8Eh Auxiliary Register 0 DPU - M0 - XRS1 XRS2 EXTRAM A0

AUXR1 A2h Auxiliary Register 1 - - ENBOOT - GF3 - - DPS

CKCON0 8Fh Clock Control 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

CKCON1 AFh Clock Control 1 - - - - - - - SPIX2

LEDCON F1h LED Control LED3 LED2 LED1 LED0

FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY

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AT89C5131A-L

External Data Memory

AUXR1(A2H)

DPS

DPH(83H) DPL(82H)

DPTR0

DPTR1

Dual Data Pointer Register

Figure 12. Use of Dual Pointer

The additional data pointer can be used to speed up code execution and reduce code size.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 32) that allows the program code to switch between them (see Figure 12).

Table 32. AUXR1 Register AUXR1- Auxiliary Register 1(0A2h)

7 6 5 4 3 2 1 0

- - ENBOOT - GF3 0 - DPS

Bit

Number

7 -

6 -

5 ENBOOT

4 -

3 GF3 This bit is a general-purpose user flag.

2 0 Always cleared.

1 -

0 DPS

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Enable Boot Flash

Cleared to disable boot ROM.

Set to map the boot ROM between F800h - 0FFFFh.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Cleared to select DPTR0. Set to select DPTR1.

Reset Value = XX[BLJB]X X0X0b Not bit addressable

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a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

AT89C5131A-L

ASSEMBLY LANGUAGE

; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

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AT89C5131A-L

0000h

32 Kbytes

7FFFh

Flash

32 Kbytes

External Code

FFFFh

AT89C5131A-L

8000h

Flash

EPROM

AT89C5131

AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE

Latch

OEPSEN

Program/Code Memory

The AT89C5131A-L implement 32 Kbytes of on-chip program/code memory. Figure 13 shows the split of internal and external program/code memory spaces depending on the product.

The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the Flash Memory can be programmed using only one voltage and allows Inapplication Software Programming commonly known as IAP. Hardware programming mode is also available using specific programming tool.

Figure 13. Program/Code Memory Organization

Note: If the program executes exclusively from on-chip code memory (not from external mem-

ory), beware of executing code from the upper byte of on-chip memory (7FFFh) and thereby disrupting I/O Ports 0 and 2 due to external prefetch. Fetching code constant from this location does not affect Ports 0 and 2.

External Code Memory Access

Memory Interface The external memory interface comprises the external bus (Port 0 and Port 2) as well as

the bus control signals (PSEN, and ALE).

Figure 14 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 33 describes the external memory interface signals.

Figure 14. External Code Memory Interface Structure

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AT89C5131A-L

Table 33. External Data Memory Interface Signals

ALE

PSEN

PCL

PCHPCH

PCLD7:0 D7:0

PCH

D7:0

CPU Clock

Signal Name Type Description

A15:8 O

AD7:0 I/O

ALE O

PSEN O

Address Lines

Upper address lines for the external bus.

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

Address Latch Enable

ALE signals indicates that valid address information are available on lines AD7:0.

Program Store Enable Output

This signal is active low during external code fetch or external code read (MOVC instruction).

Alternate Function

P2.7:0

P0.7:0

External Bus Cycles This section describes the bus cycles the AT89C5131A-L executes to fetch code (see

Figure 15) in the external program/code memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode (see the clock Section).

For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information.

Figure 15. External Code Fetch Waveforms

Flash Memory Architecture

AT89C5131A-L features two on-chip Flash memories:

• Flash memory FM0: containing 32 Kbytes of program memory (user space) organized into 128-byte pages,

• Flash memory FM1: 3 Kbytes for bootloader and Application Programming Interfaces (API).

The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the “In-System Programming” section.

All Read/Write access operations on Flash memory by user application are managed by a set of API described in the “In-System Programming” section.

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Figure 16. Flash Memory Architecture

7FFFh

32 Kbytes

Flash Memory

FM0

0000h

Hardware Security (1 Byte)

Column Latches (128 Bytes)

User Space

Extra Row (128 Bytes)

3 Kbytes

Flash Memory

FM1

Boot Space

FFFFh

F400h

FM1 mapped between FFFFh and F400h when bit ENBOOT is set in AUXR1 register

FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 16):

1. The memory array (user space) 32 Kbytes

2. The Extra Row

3. The Hardware security bits

4. The column latch registers

AT89C5131A-L

User Space This space is composed of a 32 Kbytes Flash memory organized in 256 pages of 128

bytes. It contains the user’s application code.

Extra Row (XRow) This row is a part of FM0 and has a size of 128 bytes. The extra row contains informa-

tion for bootloader usage. (see Table 39.Software Registers, page 39)

Hardware Security Space The hardware security space is a part of FM0 and has a size of 1 byte.

The 4 MSB can be read/written by software. The 4 LSB can only be read by software and written by hardware in parallel mode.

Column Latches The column latches, also part of FM0, have a size of full page (128 bytes).

The column latches are the entrance buffers of the three previous memory locations (user array, XRow and Hardware security byte).

Overview of FM0 Operations

The CPU interfaces to the Flash memory through the FCON register and AUXR1 register.

These registers are used to:

• Map the memory spaces in the adressable space

• Launch the programming of the memory spaces

• Get the status of the Flash memory (busy/not busy)

• Select the Flash memory FM0/FM1.

Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column

latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a

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page while bits 14 to 7 are used to select the programming address of the page.

Setting this bit takes precedence on the EXTRAM bit in AUXR register.

AT89C5131A-L

The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 34. A MOVC instruction is then used for reading these spaces.

Table 34. FM0 Blocks Select Bits

FMOD1 FMOD0 FM0 Adressable Space

0 0 User (0000h-FFFFh)

0 1 Extra Row(FF80h-FFFFh)

1 0 Hardware Security (0000h)

1 1 reserved

Launching Programming FPL3:0 bits in FCON register are used to secure the launch of programming. A specific

sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5 followed by A. Table 35 summarizes the memory spaces to program according to FMOD1:0 bits.

Table 35. Programming Spaces

Write to FCON

OperationFPL3:0 FPS FMOD1 FMOD0

5 X 0 0 No action

User

Extra Row

Security

Space

Reserved

A X 0 0

5 X 0 1 No action

A X 0 1

5 X 1 0 No action

A X 1 0 Write the fuse bits space

5 X 1 1 No action

A X 1 1 No action

Write the column latches in user space

Write the column latches in extra row space

The Flash memory enters a busy state as soon as programming is launched. In this state, the memory is not available for fetching code. Thus to avoid any erratic execution during programming, the CPU enters Idle mode. Exit is automatically performed at the end of programming.

Note: Interrupts that may occur during programming time must be disabled to avoid any spuri-

ous exit of the idle mode.

Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming.

FBUSY is set when programming is in progress.

Selecting FM0/FM1 The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped

up to F800h.

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