ATMEL AT89C51-20JC, AT89C51-20AI, AT89C51-20AC, AT89C51-16QI, AT89C51-16QC Datasheet

Features

Compatible with MCS-51™ Products

•

4K Bytes of In-System Reprogrammable Flash Memory

•

– Endurance: 1,000 Write/Erase Cycles

Fully Static Operation: 0 Hz to 24 MHz

•

Three-Level Program Memory Lock

•

128 x 8-Bit Internal RAM

•

32 Programmable I/O Lines

•

Two 16-Bit Timer/Counters

•

Six Interrupt Sources

•

Programmable Serial Channel

•

Low Power Idle and Power Down Modes

•

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
bytes of Flash P rogrammable a nd Erasable R ead Only Memo ry (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51™ instruction set and pinout. The
on-chip Flash allows the program memory to be reprogrammed in-system or by a con­ventional nonvolatile memory programmer. By combi ning a versati le 8-bit CPU with
Flash on a monolithic chip, the Atme l AT89C51 is a pow erful micro computer whic h
provides a highly flex ible and co st effe ctive solu tion to many embedd ed con trol app li­cations.

Pin Configurations

PQFP/TQFP

INDEX
CORNER

P1.5
P1.6
P1.7

RST

(RXD) P3.0

(TXD) P3.1
()P3.2INT0
()P3.3INT1

(T0) P3.4
(T1) P3.5

NC

P1.4

44

1
2
3
4
5
6
7
8
9
10
11

13

12

()P3.6WR

P1.3

P1.2

424340

41

15

14

XTAL2

()P3.7RD

P1.0

P1.1

16

GND

XTAL1

39

17

NC

38

18

GND

VCC

37

19

(A8) P2.0

P0.0 (AD0)

(A9) P2.1

P0.1 (AD1)

36

20

(A10) P2.2

P0.2 (AD2)

35

21

(A11) P2.3

P0.3 (AD3)

34

22

(A12) P2.4

33
32

31
30
29
28
27
26
25
24
23

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA/VPP

NC

ALE/PROG
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

PDIP

P1.0

1

P1.1

2

P1.2

3

P1.3

4

P1.4

5

P1.5

6
7

P1.6
P1.7

8

RST
(RXD) P3.0
(TXD) P3.1

()P3.2INT0
()P3.3INT1

(T0) P3.4
(T1) P3.5

()P3.6WR

()P3.7RD P2.3 (A11)

XTAL2 P2.2 (A10)
XTAL1 P2.1 (A9)

9
10
11
12
13
14
15
16
17
18
19

GND P2.0 (A8)

20

PLCC

INDEX
CORNER

P1.5
P1.6
P1.7

RST

(RXD) P3.0

NC

(TXD) P3.1
()P3.2INT0
()P3.3INT1

(T0) P3.4
(T1) P3.5

P1.1

P1.2

P1.4

P1.3

65444

2

3

7
8
9
10
11
12
13
14
15
16
17 29

21

181920 24

22

NC

P1.0

1

23

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

VCC

252827

(continued)

V

CC

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA/VPP
ALE/PROG
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)

P0.2 (AD2)

P0.1 (AD1)

P0.3 (AD3)

P0.0 (AD0)

424340

41

P0.4 (AD4)

39

P0.5 (AD5)

38

P0.6 (AD6)

37

P0.7 (AD7)

36

EA/VPP

35

NC

34
33

ALE/PROG

32

PSEN

31

P2.7 (A15)

30

P2.6 (A14)

26

P2.5 (A13)

8-Bit
Microcontroller
with 4K Bytes
Flash

AT89C51

()P3.6WR

()P3.7RD

XTAL2

XTAL1

GND

NC

(A9) P2.1

(A8) P2.0

(A10) P2.2

(A12) P2.4

(A11) P2.3

0265F-A–12/97

4-29

Block Diagram

V

CC

GND

RAM ADDR.

REGISTER

B

REGISTER

ACC

TMP2

P0.0 - P0.7

PORT 0 DRIVERS

RAM

PORT 0

LATCH

TMP1

PORT 2 DRIVERS

PORT 2

LATCH

POINTER

P2.0 - P2.7

FLASH

STACK

PROGRAM

ADDRESS

REGISTER

BUFFER

PSEN

ALE/PROG

EA / V

RST

PC

ALU

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PSW

TIMING

AND

PP

CONTROL

OSC

INSTRUCTION

REGISTER

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

INCREMENTER

PROGRAM

COUNTER

DPTR

4-30

AT89C51

AT89C51

The AT89C51 provides th e foll owing stan dard features : 4K
bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bi t
timer/counters, a five vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator and clock cir­cuitry. In addition, the AT89C51 is designed with static logic
for operation down to zero frequency and supports two
software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning. The
Power Down Mode saves the RAM contents b ut freezes
the oscillator disabling all other chip functions until the next
hardware reset.

Pin Description

V

CC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high­impedance inputs.

Port 0 may also be configured to be the multiplexed low­order address/data bus during accesses to ex ternal pro­gram and data memory . In this m ode P0 ha s int ernal pul­lups.

Port 0 also rece ives th e code by tes dur ing Fla sh prog ram­ming, and outputs the code bytes during program verifica­tion. External pu llups are requ ired dur ing pro gram ver ifica­tion.

Port 1

Port 1 is an 8-bit bidire ction al I/O por t w ith inter nal pullu ps.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs ,
Port 1 pins that are externally being pulled low will source
current (I

Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port 2

Port 2 is an 8-bit bidire ction al I/O por t w ith inter nal pullu ps.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs ,
Port 2 pins that are externally being pulled low will source
current (I

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addre sses ( MOVX @
DPTR). In this ap plication it uses strong internal pull ups

) because of the internal pullups.

IL

) because of the internal pullups.

IL

when emitting 1s. During accesses to external data mem­ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I

) because of the pullups.

IL

Port 3 also serv es t he fun ctions of v arious spe cial f eatures
of the AT89C51 as listed below:

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
P3.3 INT1 (external in terrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
P3.7 RD

(external interrupt 0)

(external data memory write strobe)

(external data memory read strobe)

Port 3 also receives some control signals for Flash pro­gramming and verification.

RST

Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
pin is also the program pulse input (PROG

) during Flash

programming.
In normal operation ALE is emitted at a constant rate of 1/6

the oscillator fr equen cy, and ma y be us ed for ext ernal tim­ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external Data Mem­ory.

If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8 EH. With the bit se t, ALE is activ e only du r­ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro­gram memory.

4-31

When the AT89C51 is executing code from external pro­gram memory, PSEN

cycle, except that two PSEN

is activated twice each machine

activations are skipped during

each access to external data memory.

/V

EA

PP

External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro­gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA

will be

internally latched on reset.

should be strapped to VCC for internal program execu-

EA
tions.

This pin also receives the 12-volt programming enable volt­age (V
12-volt V

) during Flash programming, for parts that require

PP

.

PP

XTAL1

Input to the inverting os cillator ampl ifier and input to the
internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, resp ectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi­mum voltage high and low time specifications must be
observed.

It should be noted that when idle is terminated by a hard
ware reset, the devic e normally res umes progr am execu­tion, from where it le ft off, up to tw o machi ne c ycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to interna l RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one th at writes to a p ort pin or to external
memory.

Figure 1.

Note: C1, C2 = 30 pF ± 10 pF for Cry s tals

Figure 2.

Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

= 40 pF ± 10 pF for Ceramic Resonators

External Clock Drive Configuration

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on­chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe­cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any en abled
interrupt or by a hardware reset.

Status of External Pins During Idle and Power Down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Po w er Do wn Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data

4-32

AT89C51

AT89C51

Power Down Mode

In the power down mode the oscillator is stopped, and the
instruction t hat invo kes po wer down is th e last instru ction
executed. The on-chip RAM and Special Function Regis­ters retain their values until the power d own m ode is ter mi­nated. The only exit fr om power do wn is a hard ware reset .
Reset redefines the SFRs but does not change the on-c hip
RAM. The reset should not be activated before V
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta­bilize.

CC

Program Memory Lock Bits

On the chip are three lock bits which can be left unpro­grammed (U) or can be programmed (P) to obtain the addi­tional features listed in the table below:

When lock bit 1 is programmed, the logic level at the EA
is sampled and latched during reset. I f the dev ice is po w­ered up without a reset, the latch initi alizes to a random

is

value, and holds that value until reset is activated. It is nec­essary that the latched value of EA
the current logic level at that pi n in order for the de vice to
function properly.

be in agreement with

Lock Bit Protection Modes

Program Lock Bits Protection Type

LB1 LB2 LB3

1 U U U No program lock features.
2 P U U MOVC instructions executed from external program memory are disabled from fetching code

bytes from in ternal memory, EA

Flash is disabled.
3 P P U Same as mode 2, also verify is disabled.
4 P P P Same as mode 3, also external execution is disabled.

is sampled and la tched on reset, an d further progr amming of the

pin

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash
memory array in th e erased st ate (that i s, con tents = FFH)
and ready to be programmed. The programming interface
accepts either a high-voltage (12-volt) or a low-voltage

) program enable signal. The low voltage program-

(V

CC

ming mode provides a convenient way to program the
AT89C51 inside the user’s system, while the high-voltage
programming mode is compatible with conventional third
party Flash or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or
low-voltage programming mode enabled. The respective
top-side marking and device signature codes are listed in
the following table.

VPP = 12V V

Top-Side Mark AT89C51

xxxx
yyww

Signature (030H)=1EH

(031H)=51H
(032H)=FFH

The AT89C51 code memo ry array is pr ogrammed byte- by­byte in eithe r progr amming mode.

To program any non ­blank byte in the on-chip Flash Mem or y , the ent ire memory
must be erased using the Chip Erase Mode.

= 5V

PP

AT8 9C51
xxxx-5
yyww

(030H)=1EH
(031H)=51H
(032H)=05H

Programming Algorithm:

Before programming the
AT89C51, the addres s, data and cont rol sig nals sho uld be
set up according to the Flash programming mode table and
Figures 3 and 4. To program the AT89C51, take the follow­ing steps.

1. Input the desired memory location on the address

lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA

/VPP to 12V for the high-voltage programming

mode.

5. Pulse ALE/PROG

once to program a byte in the Flash
array or the lock bits. The byte-write cycle is self-timed
and typically takes no more tha n 1.5 ms. Repeat ste ps
1 through 5, changing the address and data for the
entire array or until the end of the object file is reached.

Polling:

Data

The AT89C51 features Data

Polling to indi­cate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com­plement of the written datum on PO.7. Once the write cycle

has been completed, tr ue d ata a re va lid on all outputs, and
the next cycle may begin . Data

Polling may begi n any time

after a write cycle has been initiated.

Ready/Busy

be monitored by the RDY /B SY

:

The progress of byte programming can also

output signal. P3.4 is p ull ed
low after ALE goes high during programmin g to indic ate
BUSY. P3.4 is pull ed high again when programming is
done to indicate READY.

4-33