ATMEL AT27C2048-90JI, AT27C2048-90JC, AT27C2048-70VI, AT27C2048-70VC, AT27C2048-70PI Datasheet
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Features
• Fast Read Access Time - 55 ns
• Low Power CMOS Operation
– 100 µA Maximum Standby
– 35 mA Maximum Active at 5 MHz
• JEDEC Standard Packages
– 40-Lead 600 mil PDIP
– 44-Lead PLCC
– 40-Lead TSOP (10 mm X 14 mm)
• Direct Upgrade from 512K bit and 1M bit
(AT27C516 and AT27C1024) EPROMs
• 5V ± 10% Power Supply
• High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
™
• Rapid
Programming Algorithm - 50 µs/word (typical)
• CMOS and TTL Compatible Inputs and Outputs
• Integrated Product Identification Code
• Commercial and Industrial Temperature Ranges
Description
The AT27C2048 is a low-power, high performance 2,097,152-bit one-time programmable read only memor y (OTP EP ROM) organiz ed 128K by 16 bits . It requ ires a s ingle 5V power supply in nor mal read mode op eration. Any w ord can be acce ssed in
less than 55 ns , eliminatin g the need fo r speed-redu cing WAIT states. T he by-16
organization makes thi s part ideal for h igh-per forma nce 16 and 32 bit microp roce ssor
systems.
(continued)
Pin Configurations
Pin Name Function
A0 - A16 Addresses
O0 - O15 Outputs
CE
OE
PGM
NC No Connect
Note: Both GND pins must be con-
Chip Enable
Output Enable
Program
nected.
PDIP Top View
1
VPP
O15
O14
O13
O12
O11
O10
GND
CE
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
OE
40
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VCC
39
PGM
38
A16
37
A15
36
A14
35
A13
34
A12
33
A11
32
A10
31
A9
30
GND
29
A8
28
A7
27
A6
26
A5
25
A4
24
A3
23
A2
22
A1
21
A0
AT27C2048
2-Megabit
(128K x 16)
OTP EPROM
AT27C2048
PLCC Top View
O13
O14
O15CEVPPDCVCC
65432
7
O12
8
O11
9
O10
10
O9
11
O8
12
GND
13
NC
14
O7
15
O6
16
O5
17
O4
1819202122232425262728
O3O2O1
Note: PLCC package pins 1 an d 23
are DON’T CONNECT.
O0
1
OE
DC
PGM
A16
A15
4443424140
A0A1A2A3A4
A14
39
38
37
36
35
34
33
32
31
30
29
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
TSOP Top View
Type 1
1
A9
2
A10
3
A11
4
A12
5
A13
6
A14
7
A15
8
A16
9
PGM
10
VCC
11
VPP
12
CE
13
O15
14
O14
15
O13
16
O12
17
O11
18
O10
19
O9
20
O8
40
GND
39
A8
38
A7
37
A6
36
A5
35
A4
34
A3
33
A2
32
A1
31
A0
30
OE
29
O0
28
O1
27
O2
26
O3
25
O4
24
O5
23
O6
22
O7
21
GND
0632B-A–06/97
1
Description
µ
µ
µ
µ
In read mode, the AT27C2048 typically consumes 15 mA.
™
A.
Pro-
Standby mode supply current is typically less than 10
The AT27C2048 is ava ilable in industry standard
JEDEC-approved one -time programm able (OTP) plasti c
PDIP, PLCC, and TSOP pa ckages. The de vice features
two-line control (CE
high-speed systems.
With high density 128K word storage capability, the
AT27C2048 allows firmware to be store d reliabl y and to be
accessed by the system without the delays of mass storage
media.
Atmel’s AT27C2048 has additional features that ensure
high quality and efficient production use. The Rapid
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only 50
uct Identifi cation Co de elect ronicall y identi fies the d evice
and manufacturer. This feature is use d by industry standard programming equipment to select the proper programming algorithms and voltages.
, OE) to eliminate bus contention in
s/word. The Integrated Prod-
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce tr ans ie nt v olta ge e xcur sion s.
Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device
non-conformance . At a minim um, a 0.1
low inherent inductance, ceramic capacitor should be uti-
lized for each device. This capacitor shoul d be connected
between the V
close to the device as possible. Additionally, to stabilize the
supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7
be utilized, agai n connec ted betwe en the V
terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected
to the array.
and Ground terminals of the device, as
CC
F bulk electrolytic capacitor should
F high frequency,
and Ground
CC
2
AT27C2048
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias ......................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
Voltage on Any Pin with
Respect to Ground ...............................-2.0V to +7.0V
Voltage on A9 with
Respect to Ground ............................-2.0V to +14.0V
VPP Supply Voltage with
Respect to Ground .............................-2.0V to +14.0V
(1)
(1)
(1)
AT27C2048
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this spec ification is not implie d. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Note: Maximum voltage is -0.6V dc which may undershoot to -
2.0V for pulses of less than 20 ns. Maximum output pin
voltage is V
for pulses of less than 20 ns.
+ 0.75V dc which may overshoot to +7.0V
CC
Operating Modes
Mode/Pin CE OE PGM Ai V
Read V
IL
Output Disable X V
Standby V
Rapid Program
(2)
PGM Verify V
PGM Inhibit V
Product Identification
Notes: 1. X can be VIL or VIH.
2. Refer to the Programming characteristics.
= 12.0 ± 0.5V.
3. V
H
4. Tw o identi fier words m a y be selec ted. All Ai inputs ar e held lo w (VIL), except A9, which is set to VH, and A0, which is toggl ed
low (V
5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.
(4)
) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.
IL
IH
V
IL
IL
IH
V
IL
V
IL
IH
XX X X
V
IH
V
IL
XX X VPPHigh Z
V
IL
(1)
X
Ai X
XXXHigh Z
V
IL
V
IH
X
Ai V
Ai V
A9 = V
(3)
H
A0 = VIH or VIL
A1 - A16 = V
IL
V
Outputs
PP
(1)
D
OUT
(5)
High Z
D
PP
PP
CC
IN
D
OUT
Identification Code
3
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