ATMEL AT27C2048-90JI, AT27C2048-90JC, AT27C2048-70VI, AT27C2048-70VC, AT27C2048-70PI Datasheet

Features

• Fast Read Access Time - 55 ns

• Low Power CMOS Operation

– 100 µA Maximum Standby
– 35 mA Maximum Active at 5 MHz

• JEDEC Standard Packages

– 40-Lead 600 mil PDIP
– 44-Lead PLCC
– 40-Lead TSOP (10 mm X 14 mm)

• Direct Upgrade from 512K bit and 1M bit

(AT27C516 and AT27C1024) EPROMs

• 5V ± 10% Power Supply

• High Reliability CMOS Technology

– 2,000V ESD Protection
– 200 mA Latchup Immunity

™

• Rapid

Programming Algorithm - 50 µs/word (typical)

• CMOS and TTL Compatible Inputs and Outputs

• Integrated Product Identification Code

• Commercial and Industrial Temperature Ranges

Description

The AT27C2048 is a low-power, high performance 2,097,152-bit one-time program­mable read only memor y (OTP EP ROM) organiz ed 128K by 16 bits . It requ ires a s in­gle 5V power supply in nor mal read mode op eration. Any w ord can be acce ssed in
less than 55 ns , eliminatin g the need fo r speed-redu cing WAIT states. T he by-16
organization makes thi s part ideal for h igh-per forma nce 16 and 32 bit microp roce ssor
systems.

(continued)

Pin Configurations

Pin Name Function

A0 - A16 Addresses
O0 - O15 Outputs
CE
OE
PGM
NC No Connect

Note: Both GND pins must be con-

Chip Enable
Output Enable
Program

nected.

PDIP Top View

1

VPP

O15
O14
O13
O12
O11
O10

GND

CE

O9
O8

O7
O6
O5
O4
O3
O2
O1
O0
OE

40
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

VCC

39

PGM

38

A16

37

A15

36

A14

35

A13

34

A12

33

A11

32

A10

31

A9

30

GND

29

A8

28

A7

27

A6

26

A5

25

A4

24

A3

23

A2

22

A1

21

A0

AT27C2048

2-Megabit
(128K x 16)
OTP EPROM

AT27C2048

PLCC Top View

O13

O14

O15CEVPPDCVCC

65432

7

O12

8

O11

9

O10

10

O9

11

O8

12

GND

13

NC

14

O7

15

O6

16

O5

17

O4

1819202122232425262728

O3O2O1

Note: PLCC package pins 1 an d 23

are DON’T CONNECT.

O0

1

OE

DC

PGM

A16

A15

4443424140

A0A1A2A3A4

A14

39
38
37
36
35
34
33
32
31
30
29

A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5

TSOP Top View

Type 1

1

A9

2

A10

3

A11

4

A12

5

A13

6

A14

7

A15

8

A16

9

PGM

10

VCC

11

VPP

12

CE

13

O15

14

O14

15

O13

16

O12

17

O11

18

O10

19

O9

20

O8

40

GND

39

A8

38

A7

37

A6

36

A5

35

A4

34

A3

33

A2

32

A1

31

A0

30

OE

29

O0

28

O1

27

O2

26

O3

25

O4

24

O5

23

O6

22

O7

21

GND

0632B-A–06/97

1

Description

µ

µ

µ

µ

In read mode, the AT27C2048 typically consumes 15 mA.

™

A.

Pro-

Standby mode supply current is typically less than 10
The AT27C2048 is ava ilable in industry standard

JEDEC-approved one -time programm able (OTP) plasti c
PDIP, PLCC, and TSOP pa ckages. The de vice features
two-line control (CE
high-speed systems.

With high density 128K word storage capability, the
AT27C2048 allows firmware to be store d reliabl y and to be
accessed by the system without the delays of mass storage
media.

Atmel’s AT27C2048 has additional features that ensure
high quality and efficient production use. The Rapid
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Program­ming time is typically only 50
uct Identifi cation Co de elect ronicall y identi fies the d evice
and manufacturer. This feature is use d by industry stan­dard programming equipment to select the proper program­ming algorithms and voltages.

, OE) to eliminate bus contention in

s/word. The Integrated Prod-

System Considerations

Switching between active and standby conditions via the

Chip Enable pin may produce tr ans ie nt v olta ge e xcur sion s.

Unless accommodated by the system design, these tran-

sients may exceed data sheet limits, resulting in device

non-conformance . At a minim um, a 0.1

low inherent inductance, ceramic capacitor should be uti-

lized for each device. This capacitor shoul d be connected

between the V

close to the device as possible. Additionally, to stabilize the

supply voltage level on printed circuit boards with large

EPROM arrays, a 4.7

be utilized, agai n connec ted betwe en the V

terminals. This capacitor should be positioned as close as

possible to the point where the power supply is connected

to the array.

and Ground terminals of the device, as

CC

F bulk electrolytic capacitor should

F high frequency,

and Ground

CC

2

AT27C2048

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias ......................-55°C to +125°C

Storage Temperature............................-65°C to +150°C

Voltage on Any Pin with

Respect to Ground ...............................-2.0V to +7.0V

Voltage on A9 with

Respect to Ground ............................-2.0V to +14.0V

VPP Supply Voltage with

Respect to Ground .............................-2.0V to +14.0V

(1)

(1)

(1)

AT27C2048

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi­tions beyond those indicated in the operational sec­tions of this spec ification is not implie d. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.

Note: Maximum voltage is -0.6V dc which may undershoot to -

2.0V for pulses of less than 20 ns. Maximum output pin
voltage is V
for pulses of less than 20 ns.

+ 0.75V dc which may overshoot to +7.0V

CC

Operating Modes

Mode/Pin CE OE PGM Ai V

Read V

IL

Output Disable X V
Standby V
Rapid Program

(2)

PGM Verify V
PGM Inhibit V

Product Identification

Notes: 1. X can be VIL or VIH.

2. Refer to the Programming characteristics.
= 12.0 ± 0.5V.

3. V

H

4. Tw o identi fier words m a y be selec ted. All Ai inputs ar e held lo w (VIL), except A9, which is set to VH, and A0, which is toggl ed

low (V

5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.

(4)

) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.

IL

IH

V

IL
IL

IH

V

IL

V

IL
IH

XX X X

V

IH

V

IL

XX X VPPHigh Z

V

IL

(1)

X

Ai X

XXXHigh Z

V

IL

V

IH

X

Ai V
Ai V

A9 = V

(3)

H

A0 = VIH or VIL

A1 - A16 = V

IL

V

Outputs

PP

(1)

D

OUT

(5)

High Z
D

PP
PP

CC

IN

D

OUT

Identification Code

3

DC and AC Operating Conditions for Read Operation

µ

µ

µ

µ

AT27C2048

-55 -70 -90 -12 -15

Operating

Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C
Temperature
(Case)

Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

V

CC

Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C

DC and Operating Characteristics for Read Operation

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

PP1

I

SB

ICCVCC Active Current
V

V

V

OL

V

OH

Input Load Current VIN = 0V to V
Output Leakage Current V

(2)

VPP

(1)

Read/Standby Current VPP = V

(1)

V

Standby Current

CC

OUT

(CMOS)

I

SB1

= V

CE

(TTL)

I

SB2

CE

= 2.0 to V

= 0V to V

f = 5 MHz, I
CE = V

Input Low Voltage -0.6 0.8 V

IL

Input High Voltage 2.0 VCC + 0.5 V

IH

CC

CC

IL

CC

± 0.3V

CC

OUT

CC

+ 0.5V

= 0 mA,

Output Low Voltage IOL = 2.1 mA 0.4 V
Output High Voltage I

= -400 µA2.4V

OH

± 1
± 5

10

100

1mA

35 mA

A
A
A

A

Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.

2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and
.

I

PP

AC Characteristics for Read Operation

A T27C2048

-55 -70 -90 -12 -15

Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Units

ACC

t

CE

t

OE

(2)

(2)(3)

Output Delay
CE to Output Delay OE = V
OE to Output Delay CE = V

Address to

(3)

t

OE or CE High to

(4)(5)

t

DF

Output Float,
whichever occurred
first

Output Hold from

(4)

t

OH

Address, CE or OE,
whichever occurred
first

Notes: 1. 2, 3, 4, 5. See the AC Waveforms for Read Operation diagram.

CE = OE

= V

IL

55 70 90 120 150 ns

IL
IL

55 70 90 120 150 ns
20 30 35 40 50 ns

20 20 20 30 35 ns

77000ns

4

AT27C2048

AT27C2048

AC Waveforms for Read Operation

Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.

2. OE

3. OE may be delayed up to t

4. This parameter is only sampled and is not 100% tested.

5. Output float is defined as the point when data is no longer driven.

may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.

- tOE after the address is valid without impa ct on t

ACC

(1)

ACC

.

Input Test Waveforms and Measurement Levels

For -55 devices only:

t

, tF < 5 ns (10% to 90%)

R

For -70, -90, -12 and -15
devices:

, tF < 20 ns (10% to 90%)

t

R

Pin Capacitance

(f = 1 MHz T = 25°C)

C

IN

C

OUT

(1)

Typ Max Units Conditions

410pF V
812pF V

Output Test Load

Note: C L = 100 pF including jig

capacitance, e xce pt f or the -55
devices, where CL = 30 pF.

= 0V

IN

= 0V

OUT

Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

5

Programming Waveforms

µ

µ

(1)

Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.

2. tOE and t

3. When programming the AT27C2048, a 0.1

transients.

are characteristics of the device but must be accommodated by the programmer.

DFP

F capacitor is required across VPP and ground to suppress spurious voltage

DC Programming Characteristics

TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V

Limits

Symbol Parameter Test Condition s Min Max Units

I

LI

V

IL

V

IH

V

OL

V

OH

I

CC2

I

PP2

V

ID

Input Load Current VIN = VIL, V

IH

Input Low Level -0.6 0.8 V
Input High Level 2.0 V
Output Low Voltage IOL = 2.1 mA 0.4 V
Output High Voltage IOH = -400 µA2.4 V
VCC Supply Current

(Program and Verify)
VPP Supply Current CE = V

IL

A9 Product Identification Voltage 11.5 12.5 V

±

10

+ 0.5 V

CC

50 mA
30 mA

A

6

AT27C2048

AC Programming Characteristics

µ

µ

µ

µ

µ

µ

µ

µ

µ

TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V

(1)

Symbol

Test Conditions

Parameter Min Max

AC Conditions of Test

AT27C2048

Limits

Units

t

AS

t

OES

t

DS

t

AH

t

DH

t

DFP

t

VPS

t

VCS

t

PW

t

OE

t

PRT

Notes: 1. V

2. This parameter is only sampled and i s n ot 10 0% tested. Output Float i s de fined as the point where dat a is no longer driven

3. Program Pulse width tolerance is 50

Address Se tup Time
OE Setup Time 2
Data Setup Time 2

Input Rise and Fall Times

(10% to 90%) 20ns

2

Address Hold Time 0

Input Pulse Levels

Data Hold Time 2
OE High to Output Float Delay
VPP Setup Time 2

(2)

Input Timing Reference Level

0.45V to 2.4V
0 130 ns

0.8V to 2.0V

VCC Setup Time 2
PGM Program Pulse Width

(3)

Data Valid from OE 150 ns
VPP Pulse Rise Time During

Programming

must be applied simultaneously or before VPP and removed simultaneously or after VPP.

CC

—see timing diagram.

sec ± 5%.

Output Timing Reference Level

0.8V to 2.0V

47.5 52.5

50 ns

s
s
s
s
s

s
s
s

Atmel’s 27C2048 Intergrated Product Identification Code

Pins

Codes
Manufacturer

Device Type

A0 015-08 O7 O6 O5 O4 O3 O2 O1 O0

0 0 00011110001E
1 0 1111011100F7

Hex

Data

7

Rapid Programming Algorithm

µ

µ

A 50 µs CE pulse width is used to program. The address is
set to the first location. V
raised to 13.0V. Each address is first programmed with one

s CE pulse without verification. Then a verifica-

50
tion/reprogramming loop is exec uted for each address. In
the event a word fails to pass ver ific ation, up to 10 su cces ­sive 50
pulse. If the word fails to verify after 10 pulses have been
applied, the part is considered failed. After the word verifies
properly, the next address is selected until all have been
checked. V
words are read again and compared with the original data
to determine if the device passes or fails.

s pulses are applied with a verification after each

is then lower ed to 5. 0V and VCC to 5.0V. All

PP

is raised to 6.5V and VPP is

CC

AT27C2048

8

Order ing Information

(mA)

t

ACC

(ns)

Active Standby Ordering Code Package Operation Range

I

CC

AT27C2048

55 35 0.1 AT27C2048-55JC

AT27C2048-55PC
AT27C2048-55VC

35 0.1 AT27C2048-55JI

AT27C2048-55PI
AT27C2048-55VI

70 35 0.1 AT27C2048-70JC

AT27C2048-70PC
AT27C2048-70VC

35 0.1 AT27C2048-70JI

AT27C2048-70PI
AT27C2048-70VI

90 35 0.1 AT27C2048-90JC

AT27C2048-90PC
AT27C2048-90VC

35 0.1 AT27C2048-90JI

AT27C2048-90PI
AT27C2048-90VI

120 35 0.1 AT27C2048-12JC

AT27C2048-12PC
AT27C2048-12VC

44J
40P6
40V

44J
40P6
40V

44J
40P6
40V

44J
40P6
40V

44J
40P6
40V

44J
40P6
40V

44J
40P6
40V

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

35 0.1 AT27C2048-12JI

AT27C2048-12PI
AT27C2048-12VI

150 35 0.1 AT27C2048-15JC

AT27C2048-15PC
AT27C2048-15VC

35 0.1 AT27C2048-15JI

AT27C2048-15PI
AT27C2048-15VI

Package Type
44J
40P6
40V

44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
40 Lead, Plastic Thin Small Outline Package (TSOP) 10 x 14 mm

44J
40P6
40V

44J
40P6
40V

44J
40P6
40V

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

9