ATMEL AT27C2048 User Manual

BDTIC www.BDTIC.com/ATMEL

Features

•Fast Read Access Time – 55 ns

•Low Power CMOS Operation

–100 µA Maximum Standby

–35 mA Maximum Active at 5 MHz

•JEDEC Standard Packages

–40-lead PDIP

–44-lead PLCC

–40-lead VSOP

•Direct Upgrade from 512-Kbit and 1-Mbit (AT27C516 and AT27C1024) EPROMs

•5V ± 10% Power Supply

•High Reliability CMOS Technology

–2,000V ESD Protection

–200 mA Latchup Immunity

•Rapid Programming Algorithm – 50 µs/Word (Typical)

•CMOS and TTL Compatible Inputs and Outputs

•Integrated Product Identification Code

•Industrial Temperature Range

1. Description

The AT27C2048 is a low-power, high-performance 2,097,152-bit one-time programmable read-only memory (OTP EPROM) organized 128K by 16 bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16 organization makes this part ideal for high-performance 16 and 32 bit microprocessor systems.

In read mode, the AT27C2048 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA.

The AT27C2048 is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, and VSOP packages. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems.

With high density 128K word storage capability, the AT27C2048 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media.

Atmel’s AT27C2048 has additional features that ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 50 µs/word. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages.

2-Megabit

(128K x 16) OTP EPROM

AT27C2048

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2.				Pin Configurations
	Pin Name					Function
	A0 - A16					Addresses
	O0 - O15					Outputs
						Chip Enable
	CE
						Output Enable
	OE
						Program Strobe
	PGM
	NC					No Connect
	DC					Don’t Connect
Note:					Both GND pins must be connected.

2.140-lead PDIP Top View

VPP						1	40		VCC
						2	39
		CE								PGM
O15						3	38		A16
O14						4	37		A15
O13						5	36		A14
O12						6	35		A13
O11						7	34		A12
O10						8	33		A11
	O9					9	32		A10
	O8					10	31		A9
GND						11	30		GND
	O7					12	29		A8
	O6					13	28		A7
	O5					14	27		A6
	O4					15	26		A5
	O3					16	25		A4
	O2					17	24		A3
	O1					18	23		A2
	O0					19	22		A1
						20	21		A0
	OE

2.240-lead VSOP (Type 1) Top View

				GND
A9	1	40
A10	2	39		A8
A11	3	38		A7
A12	4	37		A6
A13	5	36		A5
A14	6	35		A4
A15	7	34		A3
A16	8	33		A2
PGM	9	32		A1
VCC	10	31		A0
VPP	11	30		OE
CE	12	29		O0
O15	13	28		O1
O14	14	27		O2
O13	15	26		O3
O12	16	25		O4
O11	17	24		O5
O10	18	23		O6
O9	19	22		O7
O8	20	21		GND

2.344-lead PLCC Top View

		O13	O14	O15		CE		VPP	DC	VCC	PGM	A16	A15	A14
	O12	6	5	4	3		2		1	44	43	42	41	40	A13
		7												39
	O11	8												38	A12
	O10	9												37	A11
	O9	10												36	A10
	O8	11												35	A9
	GND	12												34	GND
	NC	13												33	NC
	O7	14												32	A8
	O6	15												31	A7
	O5	16												30	A6
	O4	17	19	20	21		22		23	24	25	26	27	29	A5
		18												28
		O3	O2	O1		O0		OE	DC	A0	A1	A2	A3	A4
Note:	Note: PLCC package pins 1 and 23 are Don’t Connect.

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AT27C2048

3. System Considerations

Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.

4. Block Diagram

VCC

GND

VPP

OE					OE, CE AND
CE					PROGRAM LOGIC
A0 - A17					Y DECODER
ADDRESS					X DECODER
INPUTS

DATA OUTPUTS

O0 - O15

OUTPUT

BUFFERS

Y-GATING

CELL MATRIX

IDENTIFICATION

	5.	Absolute Maximum Ratings*
	Temperature Under Bias		°	°	*NOTICE: Stresses beyond those listed under “Absolute Maxi-
			-55 C to +125 C		mum Ratings” may cause permanent damage to the
	Storage Temperature		-65° C to +150° C
					device. This is a stress rating only and functional
	Voltage on Any Pin with				operation of the device at these or any other condi-
			-2.0V to +7.0V(1)		tions beyond those indicated in the operational sec-
	Respect to Ground .........................................
					tions of this specification is not implied. Exposure to
	Voltage on A9 with		-2.0V to +14.0V(1)		absolute maximum rating conditions for extended
	Respect to Ground ......................................				periods may affect device reliability.
	VPP Supply Voltage with		-2.0V to +14.0V(1)
	Respect to Ground .......................................
	Note:	1. Maximum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
		VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.

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6. Operating Modes

Mode/Pin

CE

OE

PGM

Ai

VPP

Outputs

Read

V

IL

V

IL

X(1)

Ai

X(1)

D

OUT

Output Disable

X

VIH

X

X

X

High Z

Standby

VIH

X

X

X

X(5)

High Z

Rapid Program(2)

VIL

VIH

VIL

Ai

VPP

DIN

PGM Verify

VIL

VIL

VIH

Ai

VPP

DOUT

PGM Inhibit

VIH

X

X

X

VPP

High Z

A9 = V (3)

Product Identification(4)

H

VIL

VIL

X

A0 = VIH or VIL

VCC

Identification Code

A1 - A16 = VIL

Notes: 1. X can be VIL or VIH.

2.

Refer to the Programming characteristics.

3.

VH = 12.0 ± 0.5V.

4.

Two identifier words may be selected. All Ai inputs are held low (VIL), except A9, which is set to VH, and A0, which is toggled

low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.

5.

Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.

7. DC and AC Operating Conditions for Read Operation

		AT27C2048
	-55		-90
Industrial Operating Temperature (Case)	-40° C - 85° C		-40° C - 85° C
VCC Power Supply	5V ± 10%		5V ± 10%

8. DC and Operating Characteristics for Read Operation

Symbol	Parameter		Condition				Min	Max	Units
ILI	Input Load Current	VIN = 0V to VCC						± 1	µA
ILO	Output Leakage Current	VOUT = 0V to VCC						± 5	µA
IPP1(2)	VPP(1) Read/Standby Current	VPP = VCC						10	µA
			ISB1 (CMOS)					100	µA
ISB	VCC(1) Standby Current		CE = VCC ± 0.3V
			ISB2 (TTL)					1	mA
			CE = 2.0 to VCC + 0.5V
ICC	VCC Active Current		f = 5 MHz, IOUT = 0 mA,			= VIL		35	mA
					CE
VIL	Input Low Voltage						-0.6	0.8	V
VIH	Input High Voltage						2.0	VCC + 0.5	V
VOL	Output Low Voltage	IOL = 2.1 mA						0.4	V
VOH	Output High Voltage	IOH = -400 µA					2.4		V

Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.

2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.

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