BDTIC www.BDTIC.com/ATMEL
Features
• Fast Read Access Time – 55 ns
• Low Power CMOS Operation
– 100 µA Maximum Standby
– 35 mA Maximum Active at 5 MHz
• JEDEC Standard Packages
– 40-lead PDIP
– 44-lead PLCC
– 40-lead VSOP
• Direct Upgrade from 512-Kbit and 1-Mbit (AT27C516 and AT27C1024) EPROMs
• 5V ± 10% Power Supply
• High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Rapid
• CMOS and TTL Compatible Inputs and Outputs
• Integrated Product Identification Code
• Industrial Temperature Range
Programming Algorithm – 50 µs/Word (Typical)
2-Megabit
(128K x 16)
OTP EPROM
AT27C2048
1. Description
The AT27C2048 is a low-power, high-performance 2,097,152-bit one-time programmable read-only memory (OTP EPROM) organized 128K by 16 bits. It requires a
single 5V power supply in normal read mode operation. Any word can be accessed in
less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16
organization makes this part ideal for high-performance 16 and 32 bit microprocessor
systems.
In read mode, the AT27C2048 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA.
The AT27C2048 is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, and VSOP packages. The device features
two-line control (CE
With high density 128K word storage capability, the AT27C2048 allows firmware to be
stored reliably and to be accessed by the system without the delays of mass storage
media.
Atmel’s AT27C2048 has additional features that ensure high quality and efficient production use. The Rapid
the part and guarantees reliable programming. Programming time is typically only
50 µs/word. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages.
, OE) to eliminate bus contention in high-speed systems.
Programming Algorithm reduces the time required to program
0632F–EPROM–12/07
2. Pin Configurations
Pin Name Function
A0 - A16 Addresses
O0 - O15 Outputs
CE
OE
PGM
Chip Enable
Output Enable
Program Strobe
NC No Connect
DC Don’t Connect
Note: Both GND pins must be connected.
2.1 40-lead PDIP Top View
2.2 40-lead VSOP (Type 1) Top View
A10
A11
A12
A13
A14
A15
A16
PGM
VCC
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
1
A9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
40
A8
39
A7
38
A6
37
A5
36
A4
35
A3
34
A2
33
A1
32
A0
31
OE
30
O0
29
O1
28
O2
27
O3
26
O4
25
O5
24
O6
23
O7
22
GND
21
2.3 44-lead PLCC Top View
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
VCC
39
PGM
38
A16
37
A15
36
A14
35
A13
34
A12
33
A11
32
A10
31
A9
30
GND
29
A8
28
A7
27
A6
26
A5
25
A4
24
A3
23
A2
22
A1
21
A0
Note: Note: PLCC package pins 1 and 23 are Don’t Connect.
GND
O13
O14
O15CEVPPDCVCC
65432
7
O12
8
O11
9
O10
10
O9
11
O8
12
13
NC
14
O7
15
O6
16
O5
17
O4
1819202122232425262728
O3O2O1
O0
OE
1
DC
PGM
A16
A15
4443424140
A0A1A2A3A4
A14
39
38
37
36
35
34
33
32
31
30
29
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
2
AT27C2048
0632F–EPROM–12/07
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient
voltage excursions. Unless accommodated by the system design, these transients may exceed
datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency,
low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor
should be connected between the V
device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards
with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the V
possible to the point where the power supply is connected to the array.
4. Block Diagram
AT27C2048
and Ground terminals of the device, as close to the
CC
and Ground terminals. This capacitor should be positioned as close as
CC
VCC
GND
VPP
OE
CE
A0 - A17
OE, CE AND
PROGRAM LOGIC
Y DECODER
ADDRESS
INPUTS
X DECODER
5. Absolute Maximum Ratings*
Temperature Under Bias............................... -55° C to +125° C
Storage Temperature .................................... -65°C to +150° C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V
DATA OUTPUTS
O0 - O15
OUTPUT
BUFFERS
Y-GATING
CELL MATRIX
IDENTIFICATION
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
(1)
(1)
(1)
tions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Note: 1. Maximum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
V
+ 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.
CC
0632F–EPROM–12/07
3
6. Operating Modes
Mode/Pin CE OE PGM Ai V
Read V
IL
Output Disable X V
Standby V
Rapid Program
(2)
PGM Verify V
PGM Inhibit V
Product Identification
(4)
IH
V
IL
IL
IH
V
IL
V
IL
IH
XX X X
V
IH
V
IL
XX X V
V
IL
(1)
X
Ai X
X X X High Z
V
IL
V
IH
X
Ai V
Ai V
A9 = V
(3)
H
A0 = VIH or VIL
A1 - A16 = V
IL
V
PP
(1)
(5)
PP
PP
PP
CC
Outputs
High Z
High Z
Identification Code
Notes: 1. X can be VIL or VIH.
2. Refer to the Programming characteristics.
3. V
= 12.0 ± 0.5V.
H
4. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9, which is set to VH, and A0, which is toggled
low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.
5. Standby V
current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.
CC
7. DC and AC Operating Conditions for Read Operation
AT27C2048
-55 -90
Industrial Operating Temperature (Case) -40° C - 85° C-40° C - 85° C
D
OUT
D
IN
D
OUT
Power Supply 5V ± 10% 5V ± 10%
V
CC
8. DC and Operating Characteristics for Read Operation
Symbol Parameter Condition Min Max Units
I
LI
I
LO
(2)
I
PP1
I
SB
I
CC
V
IL
V
IH
V
OL
V
OH
Notes: 1. V
2. V
Input Load Current VIN = 0V to V
Output Leakage Current V
(1)
V
Read/Standby Current VPP = V
PP
(1)
V
Standby Current
CC
= 0V to V
OUT
(CMOS)
I
SB1
= V
CE
(TTL)
I
SB2
= 2.0 to V
CE
VCC Active Current f = 5 MHz, I
CC
CC
CC
CC
± 0.3V
+ 0.5V
CC
= 0 mA, CE = V
OUT
IL
Input Low Voltage -0.6 0.8 V
Input High Voltage 2.0 VCC + 0.5 V
Output Low Voltage IOL = 2.1 mA 0.4 V
Output High Voltage I
must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
CC
may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
PP
= -400 µA 2.4 V
OH
± 1µA
± 5µA
10 µA
100 µA
1mA
35 mA
4
AT27C2048
0632F–EPROM–12/07
9. AC Characteristics for Read Operation
AT27C2048
AT27C2048
-55 -90
Symbol Parameter Condition
= OE
t
t
t
t
t
ACC
CE
OE
DF
OH
(3)
(2)
(2)(3)
(4)(5)
(4)
Address to Output Delay
CE to Output Delay OE = V
OE to Output Delay CE = V
OE or CE High to Output Float, Whichever Occurred First 20 20 ns
Output Hold from Address, CE or OE, Whichever
Occurred First
CE
= V
IL
IL
IL
Note: 2, 3, 4, 5. See the AC Waveforms for Read Operation diagram.
10. AC Waveforms for Read Operation
(1)
Min Max Min Max
Units
55 90 ns
55 90 ns
20 35 ns
70 ns
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE
may be delayed up to t
- tOE after the address is valid without impact on t
ACC
ACC
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
0632F–EPROM–12/07
5
11. Input Test Waveforms and Measurement Levels
For -55 devices only:
t
, tF < 5 ns (10% to 90%)
R
For -90 devices:
, tF < 20 ns (10% to 90%)
t
R
12. Output Test Load
Note: CL = 100 pF including jig capacitance, except for the -55 devices, where CL = 30 pF.
13. Pin Capacitance
Symbol Typ Max Units Conditions
C
C
Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
IN
OUT
410pFV
812pFV
IN
OUT
= 0V
= 0V
6
AT27C2048
0632F–EPROM–12/07
AT27C2048
14. Programming Waveforms
(1)
Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and t
are characteristics of the device but must be accommodated by the programmer.
DFP
3. When programming the AT27C2048, a 0.1 µF capacitor is required across V
transients.
15. DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Symbol Parameter Test Conditions
I
V
V
V
V
I
I
V
LI
IL
IH
OL
OH
CC2
PP2
ID
Input Load Current VIN = VIL, V
IH
Input Low Level -0.6 0.8 V
Input High Level 2.0 V
Output Low Voltage IOL = 2.1 mA 0.4 V
Output High Voltage IOH = -400 µA 2.4 V
VCC Supply Current (Program and Verify) 50 mA
VPP Supply Current CE = V
IL
A9 Product Identification Voltage 11.5 12.5 V
and ground to suppress spurious voltage
PP
Limits
UnitsMin Max
±10 µA
+ 0.5 V
CC
30 mA
0632F–EPROM–12/07
7
16. AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Symbol Parameter Test Conditions
Limits
(1)
UnitsMin Max
t
AS
t
OES
t
DS
t
AH
t
DH
t
DFP
t
VPS
t
VCS
t
PW
t
OE
t
PRT
Notes: 1. V
Address Setup Time
OE Setup Time 2 µs
Data Setup Time 2 µs
Input Rise and Fall Times
(10% to 90%) 20 ns
Address Hold Time 0 µs
Data Hold Time 2 µs
OE High to Output Float Delay
(2)
VPP Setup Time 2 µs
VCC Setup Time 2 µs
PGM Program Pulse Width
(3)
Data Valid from OE 150 ns
Input Pulse Levels
0.45V to 2.4V
Input Timing Reference Level
0.8V to 2.0V
Output Timing Reference Level
0.8V to 2.0V
VPP Pulse Rise Time During
Programming
must be applied simultaneously or before VPP and removed simultaneously or after VPP.
CC
2µs
0130ns
47.5 52.5 µs
50 ns
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 50 µsec ± 5%.
17. Atmel’s 27C2048 Intergrated Product Identification Code
Pins
Codes
Manufacturer 0 0 00011110 001E
Hex DataA0 O15-O8 O7 O6 O5 O4 O3 O2 O1 O0
Device Type 1 0 11110111 00F7
8
AT27C2048
0632F–EPROM–12/07
18. Rapid Programming Algorithm
A 50 µs CE pulse width is used to program. The address is set to the first location. VCC is raised
to 6.5V and V
without verification. Then a verification/reprogramming loop is executed for each address. In the
event a word fails to pass verification, up to 10 successive 50 µs pulses are applied with a verification after each pulse. If the word fails to verify after 10 pulses have been applied, the part is
considered failed. After the word verifies properly, the next address is selected until all have
been checked. V
pared with the original data to determine if the device passes or fails.
is raised to 13.0V. Each address is first programmed with one 50 µs CE pulse
PP
is then lowered to 5.0V and VCC to 5.0V. All words are read again and com-
PP
AT27C2048
0632F–EPROM–12/07
9
19. Ordering Information
19.1 Standard Package
I
(mA)
t
ACC
(ns)
CC
Ordering Code Package Operation RangeActive Standby
55 35 0.1 AT27C2048-55JI
AT27C2048-55PI
AT27C2048-55VI
90 35 0.1 AT27C2048-90JI
AT27C2048-90PI
AT27C2048-90VI
Note:
Not recommended for new designs. Use Green package option.
19.2 Green Package (Pb/Halide-free)
I
(mA)
t
ACC
(ns)
55 35 0.1 AT27C2048-55JU
90 35 0.1 AT27C2048-90JU
Note: 1. The 40-lead VSOP package is not recommended for new designs.
CC
Ordering Code Package Operation RangeActive Standby
AT27C2048-55PU
AT27C2048-90PU
44J
40P6
40V
44J
40P6
40V
44J
40P6
44J
40P6
Industrial
(-40° C to 85° C)
(1)
Industrial
(-40° C to 85° C)
(1)
Industrial
(-40° C to 85° C)
Industrial
(-40° C to 85° C)
Package Type
44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
40V 40-lead, Plastic Thin Small Outline Package (VSOP)
10
AT27C2048
0632F–EPROM–12/07
20. Packaging Information
20.1 44J – PLCC
AT27C2048
1.14(0.045) X 45˚
B
e
0.51(0.020)MAX
45˚ MAX (3X)
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
PIN NO. 1
IDENTIFIER
D1
D
1.14(0.045) X 45˚
E1 E
0.318(0.0125)
0.191(0.0075)
NOM
D2/E2
MAX
B1
A2
A1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
E1 16.510 – 16.662 Note 2
D2/E2 14.986 – 16.002
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
MIN
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
0632F–EPROM–12/07
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
44J
10/04/01
REV.
B
11
20.2 40P6 – PDIP
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
e
D
0º ~ 15º
eB
Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559
B1 1.041 – 1.651
L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP
MIN
NOM
MAX
DRAWING NO.
40P6
NOTE
09/28/01
REV.
B
12
AT27C2048
0632F–EPROM–12/07
20.3 40V – VSOP
AT27C2048
PIN 1
Pin 1 Identifier
D1
D
e
E
b
A2
A
SEATING PLANE
A1
Notes: 1. This package conforms to JEDEC reference MO-142, Variation CA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 8º
L
COMMON DIMENSIONS
SYMBOL
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 13.80 14.00 14.20
D1 12.30 12.40 12.50 Note 2
E 9.90 10.00 10.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
c
L1
GAGE PLANE
(Unit of Measure = mm)
MIN
NOM
MAX
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
0632F–EPROM–12/07
TITLE
40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
DRAWING NO.
40V
10/18/01
REV.
B
13
Loading...