ATMEL AT24C16B User Manual

1. Features

• Low-voltage and Standard-voltage Operation

– 1.8 (V

= 1.8V to 5.5V)

CC

• Internally Organized 2048 x 8 (16K)

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5V, 2.5V), 400 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware Data Protection

• 16-byte Page (16K) Write Modes

• Partial Page Writes Allowed

• Self-timed Write Cycle (5 ms max)

• High-reliability

– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years

• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini-MAP (MLP 2x3), 5-lead SOT23,

8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP and 8-ball dBGA2
Packages

• Lead-free/Halogen-free

• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers

2. Description

The AT24C16B provides 16384 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 2048 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The AT24C16B is available in space-saving
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3)
SOT23, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball
dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the
AT24C16B is available in 1.8V (1.8V to 5.5V) version.

Table 2-1. Pin Configuration

Pin Name Function

A0 - A2 No Connect

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

GND Ground

VCC Power Supply

8-lead Ultra Lead Frame

Land Grid Array (ULA)

VCC

WP
SCL
SDA

8
7
6
5

A0

1

A1

2

A2

3

GND

4

Bottom View

8-lead Ultra Thin

Mini-MAP (MLP 2x3)

VCC

WP

SCL

SDA

8
7
6
5

1
2
3
4

A0
A1
A2
GND

8-ball dBGA2

VCC

WP

SCL

SDA

Bottom View Bottom View

8-lead TSSOP

1

A0

2

A1

3

A2

GND

4

8

VCC

7

WP

6

SCL

5

SDA

8-lead SOIC

A0
A1
A2

GND

8-lead PDIP5-lead SOT23

SCL

GND

SDA

1

2

3

WP

5

VCC

4

A0
A1
A2

GND

8

7

6

5

1
2
3
4

1
2
3
4

1

A0

2

A1

3

A2

4

GND

8
7
6
5

8
7
6
5

, 5-lead

VCC
WP
SCL
SDA

VCC
WP
SCL
SDA

Two-wire
Serial EEPROM

16K (2048 x 8)

AT24C16B

5175C–SEEPR–11/07

Absolute Maximum Ratings

Operating Temperature..................................–55°C to +125°C

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground .................................... –1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 2-1. Block Diagram

VCC

GND

WP

SCL

SDA

A
A
A

2

1

0

START

STOP

LOGIC

LOAD

DEVICE

ADDRESS

COMPARATOR

R/W

*NOTICE: Stresses beyond those listed under “Absolute

SERIAL

CONTROL

LOGIC

COMP

LOAD

DATA WORD

ADDR/COUNTER

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

EN

H.V. PUMP/TIMING

DATA RECOVERY

INC

EEPROM

X DEC

Y DEC

D

IN

D

OUT

SERIAL MUX

D

/ACK

OUT

LOGIC

2

AT24C16B

5175C–SEEPR–11/07

3. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM

device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open­drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The AT24C16B does not use the device address
pins, which limits the number of devices on a single bus to one. The A0, A1, A2 are no connects
and can be connected to ground.

WRITE PROTECT (WP): The AT24C16B has a write protect pin that provides hardware data
protection. The write protect pin allows normal read/write operations when connected to ground
(GND). When the write protect pin is connected to V
and operates as shown in Table 3-1.

Table 3-1. Write Protect

Part of the Array Protected

AT24C16B

, the write protection feature is enabled

CC

WP Pin
Status

At V

CC

At GND Normal Read/Write Operations

4. Memory Organization

AT24C16B, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the

16K requires an 11-bit data word address for random word addressing.

24C16B

Full (16K) Array

5175C–SEEPR–11/07

3

Table 4-1. Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Input/Output Capacitance (SDA) 8 pF V

Input Capacitance (SCL) 6 pF VIN = 0V

I/O

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 4-2. DC Characteristics
Applicable over recommended operating range from: T

Symbol Parameter Test Condition Min Typ Max Units

V

I

I

I

I

CC1

CC1

CC2

SB1

LI

Supply Voltage 1.8 5.5 V

Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA

Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA

= 1.8V

V

Standby Current
(1.8V option)

Input Leakage
Current VCC = 5.0V

CC

= 5.0V 6.0

V

CC

VIN = V

CC or VSS

= −40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)

AI

1.0 µA

= VCC or V

V

IN

SS

0.10 3.0 µA

I

LO

V

IL

V

IH

V

OL1

V

OL2

Output Leakage
Current VCC = 5.0V

Input Low Level

Input High Level

(1)

(1)

= V

V

OUT

CC or VSS

Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

Notes: 1. VIL min and VIH max are reference only and are not tested.

0.05 3.0 µA

−0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

4

AT24C16B

5175C–SEEPR–11/07

Table 4-3. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from T

= −40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-

AI

erwise noted). Test conditions are listed in Note 2.

AT24C16B

1.8-volt 2.5, 5.0-volt

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Clock Frequency, SCL 400 1000 kHz

Clock Pulse Width Low 1.3 0.4 µs

Clock Pulse Width High 0.6 0.4 µs

Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 µs

Time the bus must be free before a new transmission
can start

(1)

Start Hold Time 0.6 0.25 µs

Start Set-up Time 0.6 0.25 µs

Data In Hold Time 0 0 µs

Data In Set-up Time 100 100 ns

Inputs Rise Time

Inputs Fall Time

(1)

(1)

Stop Set-up Time 0.6 0.25 µs

Data Out Hold Time 50 50 ns

Write Cycle Time 5 5 ms

(1)

25°C, Page Mode, 3.3V 1,000,000

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 V

CC

Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 V

CC

UnitsMin Max Min Max

1.3 0.5 µs

0.3 0.3 µs

300 100 ns

Write

Cycles

5175C–SEEPR–11/07

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5. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external

device. Data on the SDA pin may change only during SCL low time periods (see Figure 7-2 on

page 8). Data changes during SCL high periods will indicate a start or stop condition as defined

below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 7-3 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-

ure 7-3 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C16B features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.

2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any
2-wire part can be protocol reset by following these steps:

1. Create a start bit condition.

2. Clock 9 cycles.

3. Create another start bit followed by stop bit condition as shown below.

SCL

SDA

Start bit

Stop bitStart bitDummy Clock Cycles

123 89

6

AT24C16B

5175C–SEEPR–11/07

6. Bus Timing

S

S

Figure 6-1. SCL: Serial Clock, SDA: Serial Data I/O®

t

HIGH

SCL

t

F

t

LOW

AT24C16B

t

R

t

LOW

t

SU.STA

t

HD.STA

SDA IN

t

AA

SDA OUT

7. Write Cycle Timing

Figure 7-1. SCL: Serial Clock, SDA: Serial Data I/O

CL

DA

8th BIT

ACK

t

HD.DAT

t

SU.DAT

t

DH

t

SU.STO

t

BUF

WORDn

(1)

t

wr

STOP

CONDITION

START

CONDITION

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

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5175C–SEEPR–11/07

Figure 7-2. Data Validity

SDA

SCL

Figure 7-3. Start and Stop Definition

SDA

SCL

DATA STABLE DATA STABLE

DATA

CHANGE

Figure 7-4. Output Acknowledge

SCL

DATA IN

DATA OUT

START STOP

1

START ACKNOWLEDGE

8

9

8

AT24C16B

5175C–SEEPR–11/07

8. Device Addressing

The 16K EEPROM device requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure 10-1).

The device address word consists of a mandatory one, zero sequence for the first four most sig­nificant bits as shown. This is common to all the EEPROM devices.

The next 3 bits used for memory page addressing and are the most significant bits of the data
word address which follows.

The eighth bit of the device address is the read/write operation select bit. A read operation is ini­tiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the chip will return to a standby state.

9. Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the device

address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing device, such as a microcontroller,
must terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally timed write cycle, t
write cycle and the EEPROM will not respond until the write is complete (see Figure 10-2 on

page 11).

AT24C16B

, to the nonvolatile memory. All inputs are disabled during this

WR

PAGE WRITE: The 16K EEPROM is capable of an 16-byte page write.

A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to fifteen data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter­minate the page write sequence with a stop condition (see Figure 10-3 on page 11).

The data word address lower three bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the fol­lowing byte is placed at the beginning of the same page. If more than sixteen data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a zero allowing the read or write sequence to continue.

5175C–SEEPR–11/07

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