Atec MP1763C, MP1764C, MP1764D User Manual
MP1763C/MP1764C/MP1764D
Pulse Pattern Generator/Error Detector
50 Mbit/s to 12.5 Gbit/s
• High-Quality, Low-Jitter, Low-Distortion Waveform Output
• Evaluation of Transmission Modules, Buses, Backplanes using
Differential/CDR Option
• 12.5 Gbit/s BERTS with Higher Performance and Lower Price
High-Speed/Wide Band, High Quality Waveform and
Advanced Functions
Today’s demand for transfer of large amounts of data, such as
video, over the internet, is resulting in expansion of high-speed
transmission circuits and other infrastructure. In addition to the
previously used STM-64/OC-192 (9.95328 Gbit/s) standards, we
are also seeing use of 10.709225 Gbit/s (OTU-2), which includes
FEC coding, as well as 3.125 Gbit/s x 4 and 10.3125 Gbit/s in 10
Gbit Ethernet. Further more, the Fibre Channel file transfer protocol
at 4.25 Gbit/s is also coming into actual use.
As these new standards are settled upon, there is an urgent need
to be able to support evaluation of devices and circuits at these
higher bit rates.
Our MP1763C Pulse Pattern Generator and MP1764C/1764D Error
Detector are a BERTS (Bit Error Rate Test Set) supporting evaluation and testing of transmission equipment, high-speed devices,
optical modules, etc., at every stage from R&D through to manufacturing and production at speeds from 50 Mbit/s to 12.5 Gbit/s.
High-speed And Wide Band
One MP1763C/MP1764C can cover the band from STM-0/STS-1 to
10 Gbit Ethernet, STM-64/STS-192, OTU-2 and can be used with
4.25 Gbit/s Fibre Channel Systems.
Many Patterns
8 Mbit programmable pattern (corresponding to six frames of
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STM-64/STS192)
PRBS patterns from 27– 1 to 231– 1
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PRBS pattern with randomness and mark ratio variance for rigor-
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ous testing
Alternating pattern
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The MP1763C alternately sends normal and alarm patter ns to a
device for response testing.
Zero substitution pattern
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This feature is effective for testing the clock regeneration of a 3R
repeater.
Pulse Pattern Generator
High-quality Waveform
tr/tf(10% to 90%): 30 ps (typical)
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Jitter: 10 ps
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Back termination for low waveform distortion
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A pattern of isolated pulses which do not depend on mark ratios.
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MP1763C output waveform
DATA output of 12.5 GHz (top trace)
CLOCK 1 output (bottom trace)
p-p
(typical)
H: 50 ps/div, V: 1 V/div
Location Changeable Pattern Synchronization Trigger
This feature makes it simple to monitor the waveform at any point
in a long word pattern.
High Q factor
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A high Q factor can be obtained by back to back connection (typical value at 10 Gbit/s, PRBS 223– 1: 40 dB).
10 Gbit Ethernet I/O Interface Support
1/4 Differential Output (MP1763C-08 Option)
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This outputs differential data at a rate of 1/4 of the standard output
(100 Mbit/s to 3.125 Gbit/s) as 4-bit parallel data. It can be used as
a data signal for evaluating high-speed devices such as XAUI and
SFI-4 P2 4 Lane devices used in 10 Gbit Ethernet and Fibre
Channel, and for evaluating high-speed buses and backplanes
such as PCI express.
Differential Input (MP1764C-02 Option)
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This can be used for evaluation by inputting a high-speed differential signal used by XAUI, SFI-4P2 4Lane devices, PCI Express, etc.
Clock Recovery Function (MP1764C-03 Option)
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The clock recovered from input data can be used as a trigger signal for error rate detection and waveform monitoring. Evaluation
does not require an external clock, and when used jointly with differential input, high-speed differential devices can be evaluated
without an external jig.
Bit rates from 62.5 Mbit/s to 11.1 Gbit/s are supported along with
4.25 Gbit/s used by Fibre Channel.
∗The MP1764D model ships with the MP1764C-02 (Differential input) and
MP1764C-03 (Clock recovery) options installed.
Isolated pattern (superimposition of 1/64 bits and 63/64 bits)
High Resolution Clock And Data Output
Output amplitude: 0.25 to 2 Vp-p (2 mV steps)
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Output offset: –2 to +2 V (1 mV steps)
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Delay (clock): –500 to +500 ps (1 ps steps)
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DATA/DATA independently variable
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Burst Signal Generation Using External Gate Signal
This feature is effective for optical fiber-loop testing, etc.
Parallel Output I/F (1/8, 1/4, 1/4 Differential)
1/8 parallel output is standard. 1/4 parallel output (Option 03) or
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1/4 differential output (Option 08) can be selected exclusively.
It can be used as a MUX device and a data generator for WDM
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transmission.
The 1/4 differential option provides 4-bit parallel output of differ-
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ential data for the 1/4 rate standard output (100 Mbit/s to 3.125
Gbit/s). Similarly, a 1/4 rate clock can be output as a differential.
This can be used for performing detailed inspection of specifications and performance by use as a data signal for evaluation of
high-speed devices such as XAUI and SFI-4 P2 4 Lane devices
used in 10 Gbit Ethernet and Fibre Channel, and for evaluation of
high-speed buses and backplanes such as PCI express.
H: 50 ps/div, V: 0.5 V/div
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Error Detector Application Software
High Input Sensitivity And Wide Phase Margin
Input sensitivity: 50 mVp-p
•
(typical value at 10 Gbit/s, PRBS 223– 1)
Phase margin: 70 ps or more
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(typical value at 10 Gbit/s, PRBS 223– 1)
Eye Margin Measurement
The phase margin and threshold margin can be measured and displayed for any error rate.
Burst Measurement
The burst data can be measured even for the PRBS and pro-
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grammable patterns.
High-speed synchronization gain is achieved by a quick synchro-
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nous method (typical sync. gain time at 10 Gbit/s, programmable
pattern length of 2048 bits, sync. threshold at 10
Selectivity BER Measurement In Bit Units
The bit errors can be measured for any block of 32-bit segments or
any bit.
Error Analysis Function (Option)
The pattern (256 bits in total) before and after a bit in which an
error occurred can be displayed. Also, insertion and omission
errors are displayed using different LED colors.
Differential Input Support (Option)
This supports direct input of high-speed differential signals used
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by high-speed devices, buses and backplanes, such as XAUI,
SFI-4 P2 4 Lane and PCI Express.
Detailed evaluation is possible because independent thresholds
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can be set for inverted and non-inverted data
–2
: 850 ns).
MX176400A Q/Eye Analysis Software
Eye diagram and eye margin automatic measurement
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Displays a mask figure for the evaluation on the screen
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Q-factor (ITU-T G.976) automatic measurement
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∗ Single input unsupported; use at differential signal input is not supported.
MX176401A SDH/SONET Pattern Editor
Support OC-1 (STM-0) to OC-192c (STM-64c) mapping
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Alarm addition (OOF, LOF, MS-AIS, REI, RDI)
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BIP error addition (B1, B2, B3)
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Support “No frame” pattern
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Clock Recovery Function (Option)
The clock is recovered from the input data for use as a trigger
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signal at error rate detection and waveform monitoring.
Evaluation does not require an external clock and the recovered
clock can also be used as an external clock, depending on the
setting.
A wide range of bit rates from 62.5 Mbit/s to 11.1 Gbit/s is sup-
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ported, along with the 4.25 Gbit/s rate used by Fibre Channel.
When used in conjunction with differential input, it is also possible
•
to evaluate the latest high-speed differential devices that do not
use a clock without the need for an external jig.
MX176403A GbE/10GbE Pattern Editing Software
(At Order Acceptance)
Supports Gbit Ethernet, 10 Gbit Ether net (10GBASE-R, XAUI)
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frames
8B/10B, 64B/66B ON/OFF
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Header, Payload editing function
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CRC Auto-calculation
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Bit Error, FCS Error insertion function
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