Atec MP1763B User Manual
323
DIGIT AL TRANSMISSION MEASURING INSTRUMENTS
GPIB
9
The MP1763B is used in combination with the MP1764A
Error Detector.
The amplitude of the clock and data signals can be varied from 0.25
to 2 Vp-p while the offset can be adjusted to within ±2 V so that the
amplitude and the offset margin can be measured. The clock has a
variable delay function so that time-dependent characteristics or
phase margins of the input clock and data can be measured. An M
series pseudorandom pattern representative of actual conditions or
a programmable pattern can be selected as cell data.
In addition, a 3.5 inch floppy disk drive is built in for storing preset
data, enab ling rapid measurements to be perf ormed by simply pressing a key. A GPIB function is provided, enabling automatic or remote
measurement via an external controller.
The MP1763B is a pulse pattern generator ideal for research and
development of high-speed logic, ICs, and digital systems.
Features
•High quality waveform
•Low FM/PM-noise clock generator
•8 Mbit programmable pattern corresponding to six frames of STM-
64/STS-192
•Generates PRBS patterns with bit length from 2
7
–1 to 231–1 bits
•Complementar y outputs of both data and clock
•The amplitudes and offsets of all 8 data outputs that have 1/8
speed of fundamental clock signal can be set
PULSE PATTERN GENERATOR
MP1763B
12.5 GHz
Specifications
Operation
Internal clock 0.05 to 12.5 GHz (option)
frequency
External clock 0.05 to 12.5 GHz
Input level 0.4 to 2.5 Vp-p
External Square wave with rise/fall time of less than 1 ns, duty factor 50% (0.05 to 0.5 GHz); Sinusoidal wave or square
clock
Input waveform
wave with rise/fall time of less than 1 ns, duty factor 50% (>0.5 GHz)
Input connector APC-3.5
Frequency range 0.05 to 12.5 GHz (option)
Frequency setting resolution 1 kHz, 1 MHz
Internal Stability ±1 ppm
clock
SSB phase noise (at 10 kHz
–85 dBc/Hz (0.05 to 4 GHz), –80 dBc/Hz (4 to 8 GHz), –75 dBc/Hz (8 to 10 GHz), –70 dBc/Hz (10 to 12.5 GHz)
offset, 1 Hz bandwidth)
Reference signal 10 MHz (internal/external, selectable)
Pseudorandom binary
Pattern: 2
n
– 1 (n: 7, 9, 11, 15, 20, 23, 31)
sequence pattern (PRBS)
Mark ratio: 1/2, 1/4, 1/8, 0/8 (1/2, 3/4, 7/8, 8/8 are possible with logic inversion)
Number of AND bit shifts when setting mark ratio: 1, 3 bit (selectable by using DIP switch on rear panel)
Data pattern
*
1
Data length: 2 to 8388608 bits; Pattern reset/preset: ALL/PAGE selectable
Pattern Logic inversion Provided
Alternate pattern A/B pattern data length: 128 to 4194304 (128 bit steps); Loop time: A, B pattern (1 to 127, 1 steps)
Zero substitution pattern Zero bit length: 1 to (pattern length – 1) bits; Pattern: 2n(n: 7, 9, 11, 15)
Error rate: 10–n(n: 4, 5, 6, 7, 8, 9), and single error
Error addition
Addition position (selectable with rear panel DIP switch): Possible to insert into any 1 CH of 32 CH
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DIGIT AL TRANSMISSION MEASURING INSTRUMENTS
324
•Numerical relation between data length and step width
Data length Step width
2 to 65536 1 step
65536 to 131072 2 step
131072 to 262144 4 step
262144 to 524288 8 step
524228 to 1048576 16 step
1048576 to 2097152 32 step
2097152 to 4194304 64 step
4194304 to 8388608 128 step
Output waveform NRZ
Number of outputs 2 (DATA/DATA)
DATA/DATA tracking mode ON/OFF selectable
Amplitude 0.25 to 2 Vp-p, 2 mV steps (setting error: ±15% or ±100 mV, whichever is greater)
Voltage: –2 to ±2 V (VOH), 1 mV steps (setting error: ±15% of offset voltage, ±100 mV or ±15% of amplitude
Data Offset voltage whichever is the greatest
output
Display: VOH, VTHor VOLselectable
Rise/fall time Typical 30 ps (10% to 90% of amplitude)
Pattern jitter ≤20 psp-p (typical 10 psp-p)
Waveform distortion ≤15% or ≤150 mV whichever is greater
Load impedance 50 Ω (with back termination)
Connector APC-3.5
Number of outputs 3 (CLOCK 1, CLOCK 1, CLOCK 2)
CLOCK delay ±500 ps (1 ps steps)
Amplitude 0.25 to 2 Vp-p (2 mV steps)
(CLOCK 1, CLOCK 1) Setting error: ±15% (1.5 to 2 Vp-p), ±25% (0.5 to 1.5 Vp-p), ±100 mV (0.25 to 0.5 Vp-p)
Amplitude (CLOCK 2) 1 Vp-p ±35%
Clock Voltage: –2 to ±2 V (VOH), 1 mV steps (setting error: ±15% of offset voltage, ±100 mV or ±15% of amplitude
output
Offset voltage
whichever is the greatest)
(CLOCK 1, CLOCK 1)
Display: V
OH
, VTHor VOLselectable
Offset voltage (CLOCK 2) 0 V ±200 mV (VOH)
Rise/fall time Typical 30 ps (10% to 90% of amplitude)
Waveform distortion ≤15% or ≤150 mV whichever is greater
Duty factor adjust function
CLOCK 1, CLOCK 1 adjustable
Clock
Load impedance 50 Ω (CLOCK 1, CLOCK 1: with back termination)
output
Connector APC-3.5 (CLOCK 1, CLOCK 1), SMA (CLOCK 2)
Number of outputs DATA: 4, CLOCK: 1
Output level 0.5 to 2 Vp-p, 2 mV steps (setting error: ±15% or ±100 mV, whichever is greater)
Voltage: –1.5 to +1.5 V (VOH), 1 mV steps (setting error: ±15% of offset voltage or ±15% of amplitude or
Offset voltage ±100 mV whichever is the greatest)
1/4 data
Display: VOH, VTHor VOLselectable
and clock Rise/fall time ≤150 ps (20% to 80% of amplitude)
output
*
2
Data output jitter ≤100 psp-p
Waveform distortion ≤15%
Skew
(DATA/DATA, DATA/CLOCK)
≤100 ps
Connector SMA
Number of outputs: DATA 8, CLOCK 1
1/8 data, clock output
*
3
Output level: ECL
Connector: SMA
Sync. signal
Number of outputs 1 (1/32 clock, fixed position pattern, or variable position pattern selectable)
output
Output level Amplitude: 1 Vp-p ±20%, offset voltage: 0 V ±200 mV (VOH)
External control GPIB, IEEE 488.2
Operating temperature range 0˚ to +50˚C
Media: 3.5 inch FD (2HD, 2DD)
Parameter memory Format: MS-DOS (Rev. 3.1)
*
4
Content: Programmable pattern and other parameters
Power
*5Vac ±10%, 50/60 Hz, ≤700 VA
Dimensions and mass 426 (W) x 221 (H) x 451 (D) mm, ≤33 kg
EN55011: 1991, Group 1, Class A
EMC EN50082-1: 1992
Harmonic current emissions: EN61000-3-2 (1995)
Safety EN61010-1: 1993 (Installation Category ΙΙ, Pollution Degree ΙΙ)
*
1: Relationship between number of pages and items of word length, number of words, and data length
•Relationship between pages of WORD mode and DATA mode
Output pattern/mode Variable page range
WORD
1 word to the number of words that have
been set, 1 step width
1 to < data length/16, 1 step width (up to
quotient value when the remainder is 0, up to
quotient value +1, 1 step width)
DATA Data length Number of pages
2 to 16 1
17 to 32 2
33 to 48 3
≥49 ≥4
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