ATC AM24LC08 User Manual

查询AM24LC08供应商

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

Features



•State- of- the- art architecture

- Non-volatile data storage

- Standard voltage and low voltage operation
(Vcc = 2.7V to 5.5V) for AM24LC08

• 2-wire I

- Provides bi-directional data transfer protocol

• 16-byte page write mode

- Minimizes total write time per word

• Self-timed write-cycle (including auto-erase)

• Durable and Reliable

- 40 years data retention

- Minimum of 1M write/erase cycles per word

- Unlimited read cycles

- ESD protection

• Low standby current

• Packages: PDIP-8L, SOP-8L

2

C serial interface

Connection Diagram



NC

NC

A2

VSS

1

2

3

4

PDIP / SOP

8

7

6

5

VCC

WP

SCL

SDA

Ordering Information



AM 24 LC

General Description



The AM24LC08 is a non-volatile, 8192-bit serial
EEPROM with conforms to all specifications in I
wire protocol. The whole memory can be disabled
(Write Protected) by connecting the WP pin to Vcc.
This section of memory then becomes unalterable
unless WP is switched to Vss. The AM24LC08
communication protocol uses CLOCK(SCL) and
DATA I/O(SDA) lines to synchronously clock data
between the master (for example a
microcomputer)and the slave EEPROM
devices(s) .In addition, the bus structure allows for a
maximum of 16K of EEPROM memory. This
supports the family in 2K, 4K, 8K devices, allowing
the user to configure the memory as the application
requires with any combination of EEPROMs (not to
exceed 16K).
Anachip EEPROMs are designed and tested for
application requiring high endurance, high reliability,
and low power consumption.

Pin Assignments



08 X X

ATC

Name Description

NC No connect

A2
VSS Ground
SDA Data I/O
SCL Clock input

WP Write protect

VCC Power pin

X

AM24LC08

Device address inputs

2

C 2

Operating Voltage

LC: 2.7~5.5V, CMOS

This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.

Type

08 =8K

Blank :

I :

V :

Temp. grade

1/10

oo

C70~C0

+

oo

C85~C40-

+

oo

C125~C40-

+

Package

S: SOP-8L
N: PDIP-8L

Packing

Blank : Tube
A : Taping

Rev.A1 Oct 20, 2003

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

Block Diagrams



WP

ATC

AM24LC08

SDA

SCL

A2

VCC

VSS

START

STOP

LOGIC

SLAVE

ADDRESS

REGISTER

&

COMPARATOR

Din

R/W ~ , device
address bit A0

CONTROL

LOGIC

incload

WORD
ADDRESS
COUNTER

ck

start cycle

XDEC

H.V.

GENERATION

TIMING

&

CONTROL

EEPROM

ARRAY

64x16x8

YDEC

DATA

REGISTER

DOUT

ACK

Dout

Absolute Maximum Ratings



Characteristics Symbol Values Unit

Storage Temperature TS -65 to + 125

C

°

Voltage with Respect to Ground -0.3 to + 6.5 V V

Note: These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the

part. Prolonged exposure to maximum ratings may affect device reliability.

Operating Conditions



Temperature under bias Values Unit

AM24LC08 0 to + 70
AM24LC08I -40 to + 85
AM24LC08V -40 to +125

C

°

C

°

C

°

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

2/10

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

Electrical Characteristics



DC Electrical Characteristics

Parameter Symbol Conditions

Operating Current (Program) **
Operating Current (Read) **
Standby Current
Standby Current
Input Leakage IIL VIN = 0 V to VCC -1 +1 µA
Output Leakage IOL VOUT = 0 V to Vcc -1 +1 µA
Input Low Voltage** VIL -0.1 Vcc x 0.3 V
Input High Voltage** VIH Vcc x 0.7 VCC+ 0.2 V
Output Low Voltage V
Output Low Voltage V

VCC Lockout Voltage VLK

Note ** : I



AC Electrical Characteristics

Clock frequency Fscl 0 100 kHz
Clock high time Thigh 4000 — ns
Clock low time Tlow 4700 — ns
SDA and SCL rise time** Tr — 1000 ns
SDA and SCL fall time** Tf — 300 ns
START condition hold time Thd:Sta 4000 — ns
START condition setup time Tsu:Sta 4700 — ns
Data input hold time Thd:Dat 0 — ns
Data input setup time Tsu:Dat 250 — ns
STOP condition setup time Tsu:Sto 4000 — ns
Output valid from clock Taa 300 3500 ns
Bus free time ** Tbuf 4700 — ns
Data out hold time Tdh 300 — ns
Write cycle time Twr — 10 ms
5V, 25ºC, Byte Mode Endurance** 1M — write cycles

Note **: This parameter is characterized and is not 100% tested.

Pin Capacitance **

C
CIN Input capacitance 5 pF

Note ** : This parameter is characterized and is not 100% tested.

AC. Conditions of Test

Input Rise and Fall times 10 ns
Input and Output Timming level Vcc x 0.5
Output Load 1 TTL Gate and CL = 100pf

Anachip Corp.

www.anachip.com.tw

, I

, VIL min and VIH max are for reference only and are not tested.

CC1

CC2

Switching Characteristics

Parameter Symbol

( Ta= 25°C, f=250KHz )

Symbol Parameter Max Units

Output capacitance 5 pF

OUT

Input Pulse Levels Vcc x 0.1 to Vcc x 0.9

Rev. A1 Oct 20, 2003

(Vcc =2.7~5.5V, Ta = 25oC )

(Vcc =2.7~5.5V)

I
I
I
I

CC1

CC2

SB1

SB2

SCL = 100KHZ CMOS Input Levels — 3 mA
SCL = 100KHZ CMOS Input Levels — 200 µA
SCL=SDA=0V, Vcc=5V — 10 µA
SCL=SDA=0V, Vcc=3V — 1 µA

IOL = 2.1mA TTL — 0.4 V

OL1

IOL = 10uA CMOS — 0.2 V

OL2

Programming Command Can Be

Executed

(Under Operating Conditions)

AM24LC08

Min

3/10

AM24LC08

AM24LC08

Min Max

Default — V

Max

ATC

Units

Units

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

Pin Descriptions



Serial Clock (SCL)

The SCL input is used to clock all data into and out
of the device.

Serial Data (SDA)

SDA is a bidirection pin used to transfer data into
and out of the device.
It is an open drain output and may be wire-ORed
with any number of open drain or open collector
outputs. Thus, the SDA bus requires a pull-up
resistor to Vcc (typical 4.7KΩ for 100KHz)

Device Address Inputs (A0, A1, A2)

The following table (Table A) shows the active pins
across the AM24LCXX device family.

Table A

Device A0 A1 A2

AM24LC02 ADR ADR ADR
AM24LC04 XP ADR ADR
AM24LC08 XP XP ADR
AM24LC16 XP XP XP

ADR indicates the device address pin.
XP indicates that device address pin don’t care but
refers to an internal PAGE BLOCK memory
segment.

Write Protection (WP)

If WP is connected to Vcc, PROGRAM operation
onto the whole memory will not be executed. READ
operations are possible. If WP is connected to Vss,
normal memory operation is enabled, READ/WRITE
over the entire memory is possible.

Functional Description



Applications

ATC’s electrically erasable programmable read only
memories (EEPROMs) write protect function, two
write modes, three read modes, and a wide variety
of memory size. Typical applications for the I
and AM24LCXX memories are included in
SANs(small-area-networks), stereos, televisions,
automobiles and other scaled-down systems that
don't require tremendous speeds but instead cost
efficiency and design simplicity.

Endurance and Data Retention

The AM24LC08 is designed for applications requiring

up to 1M programming cycles (BYTE WRITE and
PAGE WRITE). It provides 40 years of secure data
retention without power.

Device Operation

The AM24LC08 support a bi-directional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is the master and the device that is
controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
AM24LC08 is considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH
are reserved for indicating start and stop conditions.

Anachip Corp.

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Rev. A1 Oct 20, 2003

2

C bus

(Shown in Figures 1 and 2)

Start Condition

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START
condition. (Shown in Figure 2)

Stop Condition

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition.
All operations must be ended with a STOP condition.
(Shown in Figure 2)

Acknowledge

Each receiving device, when addressed, is obliged
to generate an acknowledge after the reception of
each byte. The master device must generate an
extra clock pulse which is associated with this
acknowledge bit. The device that acknowledges,
has to pull down the SDA line during the
acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by
not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable
the master to generate the STOP condition. (Shown
in Figure 3)

4/10

ATC

AM24LC08

ATC

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

Functional Description (Continued)



Devices Addressing

After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit
device code (1010) for the AM24LC08, 3-bit device
address (A2 A1 A0) and 1-bit value indicating the
read or write mode. All I
internal protocol that defines a PAGE BLOCK size of
8K bits. The eighth bit of slave address determines if
the master device wants to read or write to the
AM24LC08. (Refer to table B).

Write Operations



2

C EEPROMs use and

The AM24LC08 monitor the bus for its
corresponding slave address all the time. It
generates an acknowledge bit if the slave address
was true and it is not in a programming mode.
Table B

Operation Control Code Chip

Read

Write

A2 are used to access device address for
AM24LC08; A0, A1 are no connect.

1010
1010

AM24LC08

Select

A2 A1 A0
A2 A1 A0

R/W

1
0

Byte Write

Following the start signal from the master, the slave
address is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver that a byte with a word address will follow
after it has generated a acknowledge bit during the
ninth clock cycle.

Therefore the next byte transmitted by the master is
the word address and will be written into the address
pointer of the AM24LC08. After receiving another
acknowledge signal from the AM24LC08 the master
device will transmit the data word to be written into
the addressed memory location. The AM24LC08
acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this period the AM24LC08 will not
generate acknowledge signals. (Shown in Figure 4)

Page Write

The write control byte, word address and the first
data byte are transmitted to the AM24LC08 in the
same way as in a byte write. But instead of
generating a stop condition the master transmit up
to 16 data bytes to the AM24LC08 which are
temporarily stored in the on-chip page buffer and will
be written into the memory after the master has
transmitted a stop condition. After the receipt of
each byte, the four lower order address pointer bits
are internally incremented by one. The higher order
six bits of the word address remains constant. If the
master should transmit more than 16 bytes prior to
generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once
the stop condition is received an internal write cycle
will begin. (Shown in Figure 5).

Anachip Corp.

www.anachip.com.tw Rev.A1 Sep 16, 2003

Acknowledge Polling

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle
is complete (this feature can be used to maximize
bus throughout). Once the stop condition for a write
command has been issued from the master, the
device initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves
the master sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle , then no ACK
will returned. If the cycle is complete then the device
will return the ACK and the master can then proceed
with the next read or write commands.

Write Protection

Programming will not take place if the WP pin of the
AM24LC08 is connected to Vcc. The AM24LC08 will
accept slave and byte addresses. But if the memory
accessed is write protected by the WP pin, the
AM24LC08 will not generate an acknowledge after
the first byte of data has been received, and thus the
programming cycle will not be started when the stop
condition is asserted.

Read Operations

Read operations are initiated in the same way as
write operations with the exception that the R/W bit
of the slave address is set to one. There are three
basic types of read operations: current address read,
random read, and sequential read.

5/10

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

Write Operations (Continued)



Current Address Read

The AM24LC08 contains an address counter that
maintains the address of the last accessed word,
internally incremented by one. Therefore if the
previous access (either a read or write operation )
was to address n, the next current address read
operation would access data from address n + 1.
Upon receipt of the slave address with R/W bit set to
one, the AM24LC08 issues an acknowledge and
transmits the eight bit data word. The master will not
acknowledge the transfer but does generate a stop
condition and the AM24LC08 discontinues
transmission. (Shown in Figure 6)

Random Read

Random read operations allow the master to access
any memory location in a random manner. To
perform this type of read operation, first the word
address must be set. This is done by sending the
word address to the AM24LC08 as part of a write
operation. After the word address is sent, the master
generates a start condition following the

acknowledge. This terminates the write operation,
but not before the internal address pointer is set.
Then the master issues the control byte again but
with R/W bit set to a one. The AM24LC08 will then
issue an acknowledge and transmit the eight bit data
word. The master will not acknowledge the transfer
but does generate a stop condition and the
AM24LC08 discontinues transmission. (Shown in
Figure 7)

Sequential Read

Sequential reads are initiated by either a current
address read or a random read. After the master
receives a data word, it responds with an
acknowledge. As long as the E
acknowledge, it will continue to increment the data
words. When the memory address limit is reached,
the data word address will “roll over” and the
sequential read will continue. The sequential read
operation is terminated when the master does not
respond with a zero but does generate a following
stop condition.

ATC

AM24LC08

2

PROM receives an

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www.anachip.com.tw

Rev. A1 Oct 20, 2003

6/10

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

Timing Diagram



Bus Timing

Tf

Tlow

SCL

Thigh

Tr

Tlow

ATC

AM24LC08

SDA

IN

SDA
OUT

SDA

SCL

Thd:Sta

Taa

DATA STABLE

Thd:Dat

DATA

CHANGE

Figure 1. Data Validity

Tsu:Dat

Tdh

Tsu:StaTsu:Sta

Tbuf

Anachip Corp.

www.anachip.com.tw

SDA

SCL

BITSTOPSTART BIT

Figure 2. Definition of Start and Stop

Rev. A1 Oct 20, 2003

7/10

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

SCL FROM MASTER

DATA OUTPUT FROM

TRANSMITTER

DATA OUTPUT FROM

RECEIVER

81 9

ATC

AM24LC08

BUS ACTIVITY

MASTER

SDA
LINE

BUS ACTIVITY

SLAVE

BUS ACTIVITY

MASTER

BUS ACTIVITY

SLAVE

BUS ACTIVITY

MASTER

SDA

LINE

BUS ACTIVITY

SLAVE

ACKNOWLEDGE

A
C
K

DATA n

STOP

A
C
K

BUS ACTIVITY

MASTER

SDA
LINE

BUS ACTIVITY

SLAVE

START

Figure 3. Acknowledge Response from Receiver

START

SLAVE

ADDRESS

S P

A

C

K

BYTE

ADDRESS

Figure 4. Byte Write for Data

SLAVE

A
C
K

A
C
K

A
C
K

START

A

C

K

DATA n

SLAVE

ADDRESS

DATA n+1

DATA

DATA n+15

A
C
K

STOP

P

NO

A
C
K

A
C
K

DATA n

A
C
K

DATA n+x

START

SLAVE

ADDRESS

S P

A
C
K

BYTE

ADDRESS n

Figure 5. Page Write for Data

SDA
LINE

START

s

ADDRESS

BUS ACTIVITY

MASTER

BUS ACTIVITY

SLAVE

Figure 6. Current Address Read for Data

BYTE

ADDRESS n

SDA
LINE

START

SLAVE

ADDRESS

A
C
K

Figure 7. Random Read for Data

START

SLAVE

ADDRESS

S

A
C
K

DATA n

Figure 8. Sequential Read for Data

STOP

A
C
K

STOP

PSS

NO

A
C
K

STOP

P

NO

A
C
K

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Rev. A1 Oct 20, 2003

8/10

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

Package Information



(1)Package Type: PDIP-8L

D

E-PIN O0.118 inch

E1

(4X)

15

PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch

E

ATC

AM24LC08

7

(4X)

AL

B

S

e

B1

A2A1

B2

eB

C

Symbol

A - ­A1 0.38 - - 0.015 - ­A2 3.1 3.30 3.5 0.122 0.130 0.138

B 0.36 0.46 0.56 0.014 0.018 0.022
B1 1.4 1.52 1.65 0.055 0.060 0.065
B2 0.81 0.99 1.14 0.032 0.039 0.045

C 0.20 0.25 0.36 0.008 0.010 0.014

D 9.02 9.27 9.53 0.355 0.365 0.375

E 7.62 7.94 8.26 0.300 0.313 0.325
E1 6.15 6.35 6.55 0.242 0.250 0.258

e - 2.54 - - 0.100 ­L 2.92 3.3 3.81 0.115 0.130 0.150

eB 8.38 8.89 9.40 0.330 0.350 0.370

S 0.71 0.84 0.97 0.028 0.033 0.038

Dimensions in millimeters Dimensions in inches
Min. Nom. Max. Min. Nom. Max.

5.33

- - 0.210

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Rev. A1 Oct 20, 2003

9/10

2-Wire Serial 8K-Bit (1024 x 8) CMOS Electrically Erasable PROM

(2)Package Type: SOP-8L

H

E

VIEW "A"

ATC

AM24LC08

L

(4X)

7

e

Symbol

A 1.40 1.60 1.75 0.055 0.063 0.069
A1 0.10 - 0.25 0.040 - 0.100
A2 1.30 1.45 1.50 0.051 0.057 0.059

B 0.33 0.41 0.51 0.013 0.016 0.020

C 0.19 0.20 0.25 0.0075 0.008 0.010

D 4.80 5.05 5.30 0.189 0.199 0.209

E 3.70 3.90 4.10 0.146 0.154 0.161

e - 1.27 - - 0.050 -

H 5.79 5.99 6.20 0.228 0.236 0.244

L 0.38 0.71 1.27 0.015 0.028 0.050
y - - 0.10 - - 0.004

θ

Marking Information



D

A

A2

B

y

Dimensions In Millimeters Dimensions In Inches

Min. Nom. Max. Min. Nom. Max.

O

- 8O 0

0

A1

C

O

- 8O

0.015x45

VIEW "A"

(4X)

7

Anachip Corp.

www.anachip.com.tw

Top view

ATC

Part Number & grade

+=

o

+-=

+-=

Rev. A1 Oct 20, 2003

o

)C70~0(BlankX

)C85~40(I

o

)C125~40(V

24LC08 X

XX

XX X

PDIP/SOP

10/10

Logo

ID code: internal

Nth week: 01~52

Year:

"01" = 2001
"02" = 2002