Asus W3V-A Schematics

A

B

W3V/A SCHEMATIC V2.1

C

D

E

1 1

PAGE Content

SYSTEM PAGE REF.

DOTHAN CPU-1

4

DOTHAN CPU-2

5

CPU CAP/THERMAL SENSOR/ITP

6

ALVISO: CPU

7

ALVISO: DDR2 & DMI & PEG

8 9

ALVISO: DDR2

10

ALVISO: POWER & Caps

11

ALVISO: GND & NCTF & Straps CLOCK GEN (ICS954213)

2 2

3 3

12 13

DDR2 SODIMM(0) & Caps DDR2 SODIMM(1) & Caps

14

DDR2 TERMINATOR

15

ATI M24: MAIN

16

ATI M24: MEMORY/SS

17

ATI M24: PWR & GND

18 19

ATI M24: Strapping LVDS/INVERTER

20 21

CRT/TV/TPM CONN ICH6: SATA/LPC/IDE/ACZ (1)

22

ICH6: PCI/DMI/USB/PCIE(2)

23 24

ICH6M: PWR/GND/CAPS(3) ICH6: PULL UP & Straping

25 26

SATA to PATA BRIDGE HDD CON

27 28

SWAP BAY CON USB PORTS

29 30

SUPER I/O (LPC47N207)

PAGE Content

POWER PAGE REF.

49

VCORE_MAX1987 SYSTEM

50 51

1.5V,1.8V,2.5V,1.05V

5253VGA VCORE

1.5VA & DDR2

54

PIC16C54/BATCON/PWOK

55

CHARGER

56

BATLOW/SD#

57

LOAD SWITCH

58

BATCON Power Flowchart

59

HISTORY

60 61 DC_IN CONN. 62 ODD CONN. 63 TP&LED CONN

31 FIR & FWH 32

KBC 38857

33

Azalia AUDIO (ALC861-VS) AUDIO AMP/JACKS

34 35

4 4

5 5

MIC AMP SMBUS

36

PCI GIGA LAN (88E8001)

37

RJ11_RJ45/MDC/BT

38 39

MINIPCI

40

PCI CARDBUS (R5C841) PCI PCMCIA SOCKET A

41

IEEE1394A/3in1 CONN

42 43

LEDs & DEBUG PORT DJ/HOTKEY/TP LED

44 45

PWR SW/RESET/KBC LED

46

FAN & DC_IN

47

POWER-ON SEQUENCE

48

DISCHARGE/EMI/VCCA

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

1 63

DESCRIPTION:

Content & History

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

E

A

B

C

D

E

W3V/A:Dothan & Alviso-PM+M24-CSP/Alviso-GM

BLOCK DIAGRAM

1 1

2nd BATTERY (3S2P)

58 58

TV CONN

21

2 2

LVDS & INVERTER CONN

20

CRT CONN

21

3 3

KEYBOARD COVER FPC

LEDs

LID SENSOR

TOUCHPAD BOARD

LED FPC

LEDs

TOUCHPAD

MAIN BATTERY (4S2P)

CLOCK GEN. ICS954213

ATI

M24/M22

16,17,18,19

USB x3

29

PATA

SWAP BAY

28

12

PCI-E x16

SATA to PATA BRIDGE SILICON IMAGE Sil3811

USB2.0

IDE_BUS SATA

26

Dothan

478 uFCPGA

HOST BUS AGTL 1.468V,133MHZ

ALVISO

1257 uFCBGA

7,8,9,10,11

DMI x4

ICH6-M

609 BGA

22,23,24,25

CPU

....

4,5

DDR2 SDRAM 400/533MHz

PCI_BUS

CAP/RES

3.3V, 33MHz

Azalia

RESET

6

DDR2 400/533 SODIMM X2

+1.8V +0.9VS

GIGA LAN

MARVELL 88E8001

SM_BUS

45 36

...

13,14

MINI-PCI

37

TYPEII

DDR CAP/RES

39

15

DCIN RTC FAN CON.

Thermal Sensor (MAX6657)

3-IN-1 CARD READER

46

6

VCORE

SYSTEM

1.5V,1.8V,

1.05V,2.5V

CHARGE

PIC16C54

BATLOW/SD#

LOAD Switch

VGA VCORE

1.5VA,0.9VS

CARDBUS

RICOH R5C841

49

50

51

55

54

56

57

52

53

4042

PATA

D

RJ11+RJ45 JACK CONN

1394

38

SLOT

42

DESIGN ENGINEER :SCHEMATIC FILE NAME :

CARDBUS 1 SLOT

VCCA, VCCB VPPA, VPPB

Alice Shih

E

41

AUDIO DJ FPC

AUDIO DJ SWITCH

4 4

AUDIO DJ LED

HDD

27

LPC, 33MHz

HOTKEY FPC

INSTANT KEYS

SUPER I/O

DC-IN BOARD

DC-IN JACK

ODD BOARD

5 5

ODD CON.

bom

PROJECT:

A

W3V

SMSC 47N207

FIR

31

REVISION

2.1

KEYBOARD CONTROLLER M3885XHP

INTERNAL KEYBOARD

DATE: SHEET OF

B

32

Monday, January 17, 2005

2 63

FWH

3130

MIC AMP NJM2100

Azalia CODEC ALC861-VS

AUDIO AMP TPA0212

35

DESCRIPTION:

C

Azalia MDC CONN.

33

34

Headphone

34

MIC IN

34

38

BLOCK DIAGRAM

LAN IO

38

RELEASE DATE :

A

B

C

D

E

PCI Device Chipset (Host to PCI)

IDSEL#

(AD30 internal) AD18

1 1

LAN --88E8001

CardBus

1394

AD16 AD17 AD17

REQ/GNT#

n/a

3Mini_PCI

1 1

Interrupts

B,D

C0 B A

3 IN 1 1 C

PC/PCI

SMBUS ADDRESS :

Azalia : PCI_INTB# USB 0,1 : PCI_INTA# USB 2,3 : PCI_INTD# USB 4,5 : PCI_INTC#

CLK = 1101001x ( D2 ) DDR_SODIMM0 = 1010010x ( A4 ) DDR_SODIMM1 = 1010000x ( A0 )

M38857_GPIO Used_As Signal_Name

P20

ICH6M_GPIO Used As Signal Name

GPIO00 GPI

2 2

GPIO01 GPI GPIO06 GPI GPIO07 GPI GPIO08 GPI GPIO11 GPI GPIO12 GPI GPIO13 GPI GPIO14 GPI

3 3

GPIO15 GPI GPIO16 GPO GPIO17 GPO GPIO21 GPO GPIO23 GPO GPIO24 GPO GPIO25 BLINK

4 4

GPIO26 GPI GPIO27 GPI GPIO28 GPI GPIO29 GPI GPIO30 GPI GPIO31 GPI GPIO33 GPO GPIO34 GPO

5 5

GPIO40 GPI GPIO41 GPI

bom

PROJECT:

A

W3V

KBDDT0 KBDDT1 PM_BMBUSY# FIR_SEL EXTSMI#_3A LID_ICH#_3A KBDSCI_3 ATI_OVERTEMP# GPI14 CHG_EN#_OC GPO16 GPO17 BACK_OFF# FWH_WP# CB_SD# ICH6_1HZ SATA_DET_#0 PCB_VID0 PCB_VID1 PCB_VID2 SATA_DET_#2 AGP_EXT XIDE_EN#_3 OP_SD# PID0 PID1

REVISION

2.1

DATE: SHEET OF

Monday, January 17, 2005

B

363

P21 GPO

P22

P23

P42

P43

P44 GPO KBCPURST_3Q

P45

P46 GPO KBSCI_3Q

P50

P51

P52

P53 GPO BAT_LOW#_KBC

P54

P55

P56

P57

P60

P61

P62

P63

P64

P65

P66

P67

P76

P77

DESCRIPTION:

GPO KBCRSM

BAT_SEL

GPO BAT_LEARN

GPO MSK_INSTKEY#

GPO

GPO KBC_GA20

GPIP47 PM_CLKRUN#

GPI BAT_LLOW#_KBC

GPO

GPO WIRELESS_LED#

GPI

GPO FAN_DA

GPO

GPI

GPI ACIN_OC

GPI

GPO

GPI

GPIO

GPO

WATCHDOG

SWDJ_EN#GPI

DJ_LED_EN

BAYDOCK_IN#

BAT1_IN#_OC

ADJ_BL

BT_#

INTERNET_#

CPUFAN_SPD_A

WIRELESS_#

MARATHON_#

PANLOCK_#

BAT2_IN#_OC

SMD_BAT_KBC

SMC_BAT_KBC

SYSTEM INFORMATION

C

RELEASE DATE :

THERMAL = 1001100x ( 98 )

M38857_GPIO Used_As Signal_Name

P27

P26

P25

P24

P41

P40 GPO KBC_EXTSMI

47N207_GPIO Used_As Signal_Name

GP10

GP11

GP12

GP13

GP14

GP15

GP16

GP17

GP34

GP35

GP36

D

GPO

GPO BT_LED#

GPI

GPIO

GPO

GPO OVER_CLK1

GPO

--

NUM_LED#

CAP_LED#

SET_PCIRSTNS#

BAY_IN0

BAY_IN1

--

SW_RST#

--

BAY_RST

DJKEY_EN

802_EN#

OVER_CLK2

--

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

E

5

H_A#[16:3]7

D D

H_ADSTB#07

H_REQ#[4:0]7

H_A#[31:17]7

C C

H_ADSTB#17

DPWR#7

H_A#16 H_A#15 H_A#14 H_A#13 H_A#12 H_A#11 H_A#10 H_A#9 H_A#8 H_A#7 H_A#6 H_A#5 H_A#4 H_A#3

H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0

H_A#31 H_A#30 H_A#29 H_A#28 H_A#27 H_A#26 H_A#25 H_A#24 H_A#23 H_A#22 H_A#21 H_A#20 H_A#19 H_A#18 H_A#17

AA2 AA3

AF1 AE1 AF3 AD6 AE2 AD5 AC6 AB4 AD2 AE4 AD3 AC3 AC7 AC4 AF4 AE5

C19

Y3

U1

Y1 Y4

W2

T4

W1

V2

R3

V3

U4

P4

U3

T1 P1 T2 P3

R2

U52B

A[16]# A[15]# A[14]# A[13]# A[12]# A[11]# A[10]# A[9]# A[8]# A[7]# A[6]# A[5]# A[4]# A[3]# ADSTB[0]# REQ[4]# REQ[3]# REQ[2]# REQ[1]# REQ[0]#

A[31]# A[30]# A[29]# A[28]# A[27]# A[26]# A[25]# A[24]# A[23]# A[22]# A[21]# A[20]# A[19]# A[18]# A[17]# ADSTB[1]#

DPWR#

SOCKET479P

ADS# PRDY# PREQ#

BNR#

BPRI#

DBR#

ADDRESS GROUP 0ADDRESS GROUP 1

DEFER#

DRDY# DBSY#

BR0#

CONTROL

IERR#

INIT#

LOCK#

RESET#

RS[2]# RS[1]# RS[0]#

TRDY#

HIT#

HITM#

P/N = 12-046004791

U52C

CLK_CPU_BCLK12

CLK_CPU_BCLK#12

H_A20M#22

H_FERR#22 H_IGNNE#22 H_DPSLP#22

B B

VCCA layout: T/S: 100mil/25mil

H_CPUSLP#7,22

H_STPCLK#22

H_PWRGD22

VR_VID[5:0]49

120mA

THERMDA6 THERMDC6

H_THRMTRIP_S#6

PM_PSI#49

CPU_BSEL012,48

A A

FSB BSEL1 BSEL0 BSEL0

CPU_BSEL112

A-STEP B-STEP

1 2

R756 49.9Ohm 1%

1 2

R754 49.9Ohm 1%

H_INTR22

H_NMI22

H_SMI#22

1.05V OUTPUT

+1.8VS_VCCA

+1.8VS_PROC

H_PROCHOT_S#

R192 0Ohm

H_PWRGD VR_VID5

VR_VID4 VR_VID3 VR_VID2 VR_VID1 VR_VID0

T124 T312

T125

B15

BCLK[0]

B14

BCLK[1]

A16

ITP_CLK[0]

A15

ITP_CLK[1]

C2

A20M#

D3

FERR#

A3

IGNNE#

A6

SLP#

D1

LINT0

D4

LINT1

B4

SMI#

C6

STPCLK#

E4

PWRGOOD

H4

VID[5]

G4

VID[4]

G3

VID[3]

F3

VID[2]

F2

VID[1]

E2

VID[0]

AC26

VCCA[3]

N1

VCCA[2]

B1

VCCA[1]

F26

VCCA[0]

B18

THERMDA

A18

THERMDC

C17

THERMTRIP#

B17

PROCHOT#

E1

12

RSVD5

C16

RSVD4

C3

1

RSVD3

C14

RSVD2

AF7

1

RSVD1

1

B2

RSVD0

SOCKET479P

COMP[3] COMP[2]

HOSTCLKLEGACY CPU

COMP[1] COMP[0]

BPM[3]#DPSLP# BPM[2]# BPM[1]# BPM[0]#

GTLREF[3] GTLREF[2] GTLREF[1] GTLREF[0]

MISC

VCCSENSE

VSSSENSE

400 0 N/A 1 533 0 N/A 0

bom

PROJECT:

5

W3V

REVISION

2.1

4

N2 A10 B10

L1 J3

A7

L4 H2 M2

N4

H_IERR#

A4

B5

J2

B11

H_RS#2

L2

H_RS#1

K1

H_RS#0

H1 M3

K3 K4

AB1 AB2 P26 P25

C9B7 A9 B8 C8

AC1

1 G1 E26

1 AD26

R740 1KOhm /*

C5

TEST1 TEST2

TRST#

R781 1KOhm /*

F23

A13

TCK

C12

TDO TMS

TDI

R750 150Ohm 1%

A12 C11 B13

VCCSENSE

AE7

VSSSENSE

AF6

Monday, January 17, 2005

DATE: SHEET OF

4

H_ADS# 7 H_BPM#4 6 H_BPM#5 6

H_BNR# 7 H_BPRI# 7

H_DBRESET# 6,22

H_DEFER# 7 H_DRDY# 7 H_DBSY# 7

H_BR0# 7

R738 56Ohm

H_COMP3 H_COMP2 H_COMP1 H_COMP0

T126 T326

1 2

R753 680Ohm

12

H_INIT# 22

H_LOCK# 7

H_RS#[2:0] 7 H_TRDY# 7

H_HIT# 7 H_HITM# 7

H_BPM#3 6 H_BPM#2 6 H_BPM#1 6 H_BPM#0 6

H_DPRSTP# 22

12 12

R195 54.9Ohm 1%

R194 54.9Ohm 1%

12

/*

12

/*

4 63

+VCCP

12

R748

54.9Ohm

1% /*

GTLREF0

TDI 6 TCK 6

TDO 6 TMS 6

TRST# 6

H_CPURST# 6,7

+VCCP

12

R791 1KOhm

R790 2KOhm

1%

1 2

DESCRIPTION:

3

H_DINV#07

H_DSTBN#07

H_DSTBP#07

H_DINV#17

H_DSTBN#17

H_DSTBP#17

+1.8VS

+1.5VS

DOTHAN CPU(1)

3

VCCA_+1.5VS_+1.8VS +1.8VS_VCCA

R784 0Ohm

1 2

/*

R783 0Ohm

1 2

/*

2

H_D#15 H_D#14 H_D#46 H_D#13 H_D#12 H_D#11 H_D#10 H_D#9 H_D#8 H_D#7 H_D#6 H_D#5 H_D#4 H_D#3 H_D#2 H_D#1 H_D#0

H_D#31 H_D#30 H_D#29 H_D#28 H_D#27 H_D#26 H_D#25 H_D#24 H_D#23 H_D#22 H_D#21 H_D#20 H_D#19 H_D#18 H_D#17 H_D#16

1 2

+1.8VS_PROC

12

C769 10UF/10V

R785 0Ohm /*

R782 0Ohm

C25 E23 B23 C26 E24 D24 B24 C20 B20 A21 B26 A24 B21 A22 A25 A19 D25 C23 C22

K25 N25 H26 M25 N24 L26 J25 M23 J23 G24 F25 H24 M26 L23 G25 H23 J26 K24 L24

1 2

12

C770

0.01UF

U52A

D[15]# D[14]# D[13]# D[12]# D[11]# D[10]# D[9]# D[8]# D[7]# D[6]# D[5]# D[4]# D[3]# D[2]# D[1]# D[0]# DINV[0]# DSTBN[0]# DSTBP[0]#

D[31]# D[30]# D[29]# D[28]# D[27]# D[26]# D[25]# D[24]# D[23]# D[22]# D[21]# D[20]# D[19]# D[18]# D[17]# D[16]# DINV[1]# DSTBN[1]# DSTBP[1]#

SOCKET479P

12

C198 10UF/10V

DATA GROUP 0DATA GROUP 1

D[47]# D[46]# D[45]# D[44]# D[43]# D[42]# D[41]# D[40]# D[39]# D[38]# D[37]# D[36]#

DATA GROUP 2DATA GROUP 3

D[35]# D[34]# D[33]# D[32]#

DINV[2]# DSTBN[2]# DSTBP[2]#

D[63]# D[62]# D[61]# D[60]# D[59]# D[58]# D[57]# D[56]# D[55]# D[54]# D[53]# D[52]# D[51]# D[50]# D[49]# D[48]#

DINV[3]# DSTBN[3]# DSTBP[3]#

12

C201

0.01UF

Y25 AA26 Y23 V26 U25 V24 U26 AA23 R23 R26 R24 V23 U23 T25 AA24 Y26 T24 W25 W24

AF26 AF22 AF25 AD21 AE21 AF20 AD24 AF23 AE22 AD23 AC25 AC22 AC20 AB24 AC23 AB25 AD20 AE24 AE25

+1.8VS_VCCA

12

H_D#47 H_D#45

H_D#44 H_D#43 H_D#42 H_D#41 H_D#40 H_D#39 H_D#38 H_D#37 H_D#36 H_D#35 H_D#34 H_D#33 H_D#32

H_D#63 H_D#62 H_D#61 H_D#60 H_D#59 H_D#58 H_D#57 H_D#56 H_D#55 H_D#54 H_D#53 H_D#52 H_D#51 H_D#50 H_D#49 H_D#48

C200 10UF/10V

12

C202

0.01UF

Place near CPU pin

Layout note: COMP0 and COMP2 need to be Zo=27.4ohm traces. Best estimate is 18mil wide trace for outer layers and 14mil if on internal layer. See RDDP of Banias. Traces should be shorter than 0.5". Refer to latest CS layout

COMP1, COMP3 should be routed as Zo=55ohm traces shorter than 0.5"

R190 54.9Ohm 1%

H_COMP3 H_COMP2 H_COMP1 H_COMP0

Reserve for ITP => check

H_BPM#5 H_PROCHOT_S# H_PWRGD

RELEASE DATE :

R189 27.4Ohm 1% R786 54.9Ohm 1% R787 27.4Ohm 1%

+VCCP

12

R745 56Ohm

/*

2

12

R757 56Ohm

12

+VCCP+VCCP

12

R737 200Ohm

R736 1KOhm

12

Reserve for ITP

ITP: Stuff No ITP: N/A

/*

H_D#[63:0] 7

H_DINV#2 7 H_DSTBN#2 7 H_DSTBP#2 7

H_DINV#3 7 H_DSTBN#3 7 H_DSTBP#3 7

12

C778 10UF/10V

H_PWRGD_ITP 6

DESIGN ENGINEER :SCHEMATIC FILE NAME :

1

12

1

R1.1#1

C768

0.01UF

M.Y.

5

4

3

2

1

D D

C C

B B

P23

D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16

L21 M22 N21 P22 R21 T22

U21

U52D

W4

VCCQ[1] VCCQ[0]

VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8 VCCP9 VCCP10 VCCP11

K6

VCCP12

L5

VCCP13 VCCP14

M6

VCCP15 VCCP16

N5

VCCP17 VCCP18

P6

VCCP19 VCCP20

R5

VCCP21 VCCP22

T6

VCCP23 VCCP24 VCCP25

VCC66

VCC67

VCC68

VCC69

VCC70

VCC71

VCC72

AE19

AF8

AF10

AF12

AF14

AF16

AF18

VCC

VCC63

VCC62

VCC61

VCC64

VCC65

AE13

AE11

AE9

AE15

AE17

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8

VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60

SOCKET479P

D6 D8 D18 D20 D22 E5 E7 E9 E17 E19 E21 F6 F8 F18 F20 F22 G5 G21 H6 H22 J5 J21 K22 U5 V6 V22 W5 W21 Y6 Y22 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC9 AC11 AC13 AC15 AC17 AC19 AD8 AD10 AD12 AD14 AD16 AD18

+VCORE+VCCP

AF24

AF21

AF19

AF17

AF15

AF13

AF11

AF9

AF5

AF2

AE26

AE23

AE20

AE18

AE16

AE14

AE12

AE10

AE8

AE6

AE3

AD25

AD22

AD19

AD17

AD15

AD13

AD11

AD9

AD7

AD4

VSS167

VSS90

VSS166

VSS91

AD1

VSS165

VSS164

VSS163

VSS162

VSS95

VSS94

VSS93

VSS92

P2

N26

N23

N22N6N3

P5

VSS161

VSS96

VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100

VSS99 VSS98 VSS97

AC24 AC21 AC18 AC16 AC14 AC12 AC10 AC8 AC5 AC2 AB26 AB23 AB21 AB19 AB17 AB15 AB13 AB11 AB9 AB7 AB5 AB3 AA25 AA22 AA20 AA18 AA16 AA14 AA12 AA10 AA8 AA6 AA4 AA1 Y24 Y21 Y5 Y2 W26 W23 W22 W6 W3 V25 V21 V5 V4 V1 U24 U22 U6 U2 T26 T23 T21 T5 T3 R25 R22 R6 R4 R1 P24 P21

Mobile Dothan VID Table

0 0 0 0 0 0 1.708V 0 0 0 0 0 1 1.692V 0 0 0 0 1 0 1.676V 0 0 0 0 1 1 1.660V 0 0 0 1 0 0 1.644V 0 0 0 1 0 1 1.628V 0 0 0 1 1 0 1.612V 0 0 0 1 1 1 1.596V 0 0 1 0 0 0 1.580V 0 0 1 0 0 1 1.564V 0 0 1 0 1 0 1.548V 0 0 1 0 1 1 1.532V 0 0 1 1 0 0 1.516V 0 0 1 1 0 1 1.500V 0 0 1 1 1 0 1.484V 0 0 1 1 1 1 1.468V 0 1 0 0 0 0 1.452V 0 1 0 0 0 1 1.436V 0 1 0 0 1 0 1.420V 0 1 0 0 1 1 1.404V 0 1 0 1 0 0 1.388V 0 1 0 1 0 1 1.372V 0 1 0 1 1 0 1.356V 0 1 0 1 1 1 1.340V 0 1 1 0 0 0 1.324V 0 1 1 0 0 1 1.308V 0 1 1 0 1 0 1.292V 0 1 1 0 1 1 1.276V 0 1 1 1 0 0 1.260V 0 1 1 1 0 1 1.244V 0 1 1 1 1 0 1.228V 0 1 1 1 1 1 1.212V

VID[5..0]VID[5..0]

1 0 0 0 0 0 1.196V 1 0 0 0 0 1 1.180V 1 0 0 0 1 0 1.164V 1 0 0 0 1 1 1.148V 1 0 0 1 0 0 1.132V 1 0 0 1 0 1 1.116V 1 0 0 1 1 0 1.100V 1 0 0 1 1 1 1.084V 1 0 1 0 0 0 1.068V 1 0 1 0 0 1 1.052V 1 0 1 0 1 0 1.036V 1 0 1 0 1 1 1.020V 1 0 1 1 0 0 1.004V 1 0 1 1 0 1 0.988V 1 0 1 1 1 0 0.972V 1 0 1 1 1 1 0.956V 1 1 0 0 0 0 0.940V 1 1 0 0 0 1 0.924V 1 1 0 0 1 0 0.908V 1 1 0 0 1 1 0.892V 1 1 0 1 0 0 0.876V 1 1 0 1 0 1 0.860V 1 1 0 1 1 0 0.844V 1 1 0 1 1 1 0.828V 1 1 1 0 0 0 0.812V 1 1 1 0 0 1 0.796V 1 1 1 0 1 0 0.780V 1 1 1 0 1 1 0.764V 1 1 1 1 0 0 0.748V 1 1 1 1 0 1 0.732V 1 1 1 1 1 0 0.716V 1 1 1 1 1 1 0.700V

VoltageVoltage

A2 A5

A8 A11 A14 A17 A20 A23 A26

B3

B6

B9 B12 B16 B19 B22 B25

C1

C4

C7 C10 C13 C15 C18 C21 C24

D2

D5

D7

D9 D11 D13 D15 D17 D19 D21 D23 D26

E3

E6

E8 E10 E12 E14 E16 E18 E20 E22 E25

F1

F4

F5

F7

F9 F11 F13 F15 F17 F19 F21 F24

G2

G6 G22

SOCKET479P

U52E

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64

G23

VSS192

VSS65

G26H3H5

VSS191

VSS66

VSS190

VSS67

VSS189

VSS68

VSS188

VSS69

H21

VSS187

VSS186

VSS185

VSS70

VSS71

VSS72

H25J1J4J6J22

VSS184

VSS73

VSS183

VSS74

J24K2K5

VSS182

VSS75

VSS181

VSS76

VSS180

VSS77

K21

VSS179

VSS178

VSS177

VSS176

VSS175

GND

VSS82

VSS81

VSS80

VSS79

VSS78

K26

K23

VSS174

VSS173

VSS172

VSS171

VSS170

VSS169

VSS168

VSS89

VSS88

VSS87

VSS86

VSS85

VSS84

VSS83

M24

M21M5M4M1L25

L22L6L3

A A

bom

PROJECT:

5

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

4

5 63

DESCRIPTION:

DOTHAN CPU (2)

3

RELEASE DATE :

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

1

A

VCORE 10uF/10V* 35

220uF/2V * 4

VCCP 0.1uF * 10 for CPU

150uF * 1 for CPU

0.1uF * 10 for Alviso 150uF * 2 for Alviso

4.7uF * 1 for Alviso

1 1

+VCORE

27A for 1.8G

12

2 2

12

10UF/10V

12

10UF/10V

3 3

+VCCP

4 4

12

C231 10UF/10V

C228 10UF/10V

C217

C213

C210 10UF/10V

12

10UF/10V

12

10UF/10V

12

10UF/10V

2.5A for 1.8G

12

+

CE29

150U/4.0V

C241

C218

C225

12

10UF/10V

12

10UF/10V

12

10UF/10V

12

0.1UF

12

0.1UF

C211 10UF/10V

C242

C245

C223

C212

C226

2.2uF * 1 for Alviso

0.47uF * 2 for Alviso on A6 B2 G1 V1

0.22uF * 2 for Alviso on A6 B2 G1 V1

Decoupling guide from INTEL

12

10UF/10V

12

10UF/10V

12

10UF/10V

12

C749 10UF/10V

C234

C229

C233

C216

0.1UF

C207

0.1UF

12

C748 10UF/10V

12

C230

10UF/10V

12

C235

10UF/10V

12

C755

10UF/10V

12

0.1UF

12

0.1UF

C209

C205

12

C237 10UF/10V

12

10UF/10V

12

10UF/10V

DOTHAN VID TABLE

2.1

LFM

0.6G

1G1.4G

0.844V

CPU

HFM VOLTAGE

FREQ.

1.8G

1.7G

5 5

bom

PROJECT:

1.308V

A

1.6G 1.2G

W3V

REVISION

B

12

C756 10UF/10V

12

C224

C221

12

C746

10UF/10V

12

C219

10UF/10V

+

CE14

Do Not Stuff

12

C208

0.1UF

C3/C4

0.748V1.196V1.228V1.260V1.292V

Monday, January 17, 2005

DATE: SHEET OF

B

12

C754 10UF/10V

12

C723

10UF/10V

12

C215

10UF/10V

12

+

C222

CE30

Do Not Stuff

NEAR CPU PIN W4

12

+

12

C244

0.1UF

6 63

12

C753 10UF/10V

12

C728

10UF/10V

12

C214

10UF/10V

CE12

220UF/2V

NEAR CPU PIN P23

12

C722 10UF/10V

12

C732

10UF/10V

12

C227

10UF/10V

12

+

CE13

Do Not Stuff

/*

C206

0.1UF

DESCRIPTION:

C

H_BPM#54 H_BPM#44

H_BPM#34 H_BPM#24

H_BPM#14 H_BPM#04

+VCCP

ITP: Stuff

1 2

+3VS

1 2

R821

2.2KOhm

/*

R240 Do Not Stuff

/*

+VCCP

/*

No ITP: N/A

R789 54.9Ohm

1 2

12

H_PWRGD_ITP4

CTL_DATA8

CTL_CLK8

TCK4 TMS 4

R788

+2.5VS

H_THRMTRIP_S#4

GMCH_THRMTRIP#8

2.2KOhm

/*

1 2

ITP: Stuff No ITP: N/A

SCL_3S12,13,14,19,21,36

SDA_3S12,13,14,19,21,36

PM_THRM#19,22,25

R769 0Ohm

1 2

R767 0Ohm

1 2

R1.1#33

Caps & THERMAL & ITP

C

1 2

1% /*

R822

27.4Ohm

1%

1 2

R239

U18

Do Not Stuff

/*

8

SMBCLK

7

SMBDATA

6

ALERT#

MAX6657

R772 75Ohm

RELEASE DATE :

D

CN28

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

NP_NC1

ITP_CON_60P

/*

ITP

+3VS

R212 200Ohm

1%

1 2

1

VCC OVERT

DXP DXN

GND

5

H_THRMTRIP#_R

+VCCP

12

R775 330Ohm

B

C

E12

3

Q132 PMBS3904

BUF_PLT_RST#8,21,22,23,28,30,31,32

D

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

NP_NC2

12

4 2 3

SM Bus Address fix at: 1001 100x (98, 99), Resolution : +/- 1 degree

C767

1 2

0.1UF

C239

0.1UF

1 2

C243 2200PF/10V

S

2

G

+VCCP

ITP: Stuff No ITP: N/A

R798

R796

54.9Ohm

220Ohm

1%

/*

1 2

/*

12

R799 27.4Ohm

1% /*

12

R800 22.6Ohm

1% /*

1 2

R801 220Ohm

/*

Reserve for ITP Place resistance close ITP

THERMAL SENSOR

R1.1#16

R210 100KOhm

1 2

OS#_OC 47 THERMDA 4 THERMDC 4

R766 56Ohm

1 2

D

3

Q134

1

2N7002

DESIGN ENGINEER :SCHEMATIC FILE NAME :

E

R797

39.2Ohm

1%

1 2

10/10/10 mil

C920 100PF

1 2

/*

M.Y.

E

CLK_ITP_BCLK 12 CLK_ITP_BCLK# 12

H_DBRESET# 4,22 TDO 4

TRST# 4 TDI 4

H_CPURST# 4,7

H_THRMTRIP# 22

OTP_RESET# 47,53

5

H_XRCOMP

24.9

R682

24.9Ohm

1%

1 2

D D

+VCCP

54.9 1%

C C

24.9 1%

B B

A A

54.9 1%

221 1%

100 1%

R675

54.9Ohm

1%

1 2

H_XSCOMP

+VCCP

221

R690 221Ohm

1%

1 2

100 1%

1 2

R706

24.9Ohm

1%

1 2

+VCCP

R698

54.9Ohm

1%

1 2

+VCCP

R705 221Ohm

1%

1 2

R704 100Ohm

1%

1 2

R685 100Ohm

1%

H_YRCOMP

H_YSCOMP

H_XSWING

12

C614 10UF/10V

/*

H_YSWING

12

C655 10UF/10V

/*

12

C592

0.1UF

12

C654

0.1UF

4

H_D#[0..63]4

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING

3

U48D

E4

HD0#

E1

HD1#

F4

HD2#

H7

HD3#

E2

HD4#

F1

HD5#

E3

HD6#

D3

HD7#

K7

HD8#

F2

HD9#

J7

HD10#

J8

HD11#

H6

HD12#

F3

HD13#

K8

HD14#

H5

HD15#

H1

HD16#

H2

HD17#

K5

HD18#

K6

HD19#

J4

HD20#

G3

HD21#

H3

HD22#

J1

HD23#

L5

HD24#

K4

HD25#

J5

HD26#

P7

HD27#

L7

HD28#

J3

HD29#

P5

HD30#

L3

HD31#

U7

HD32#

V6

HD33#

R6

HD34#

R5

HD35#

P3

HD36#

T8

HD37#

R7

HD38#

R8

HD39#

U8

HD40#

R4

HD41#

T4

HD42#

T5

HD43#

R1

HD44#

T3

HD45#

V8

HD46#

U6

HD47#

W6

HD48#

U3

HD49#

V5

HD50#

W8

HD51#

W7

HD52#

U2

HD53#

U1

HD54#

Y5

HD55#

Y2

HD56#

V4

HD57#

Y7

HD58#

W1

HD59#

W3

HD60#

Y3

HD61#

Y6

HD62#

W2

HD63#

C1

HXRCOMP

C2

HXSCOMP

D1

HXSWING

T1

HYRCOMP

L1

HYSCOMP

P1

HYSWING

ALVISO_BGA1257

HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

HADS# HADSTB0# HADSTB1#

HVREF

HBNR#

HBPR#

HBREQ0#

HCPURST#

HCLKINN

HOST

HCLKINP

HDBSY#

HDEFER#

HDINV0# HDINV1# HDINV2# HDINV3#

HDPWR#

HDRDY# HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3# HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3#

HEDRDY#

HHITM#

HLOCK#

HPCREQ#

HREQ0#

HREQ1#

HREQ2#

HREQ3#

HREQ4#

HRS0# HRS1# HRS2#

HCPUSLP#

HTRDY#

HA3# HA4# HA5# HA6# HA7# HA8# HA9#

HHIT#

G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13

F8 B9 E13 J11 A5 D5 E7 H10

AB1 AB2

C6 E6 H8 K3 T7 U5 G6 F7 G4 K1 R3 V3 G5 K2 R2 W4 F6 D4 D6 B3 A11 A7 D7 B8 C7 A8 A4 C5 B4 G8 B5

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_ADS# H_ADSTB#0 H_ADSTB#1

H_BNR# H_BPRI# H_BR0# H_CPURST#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2

H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

TP_H_EDRDY#

TP_H_PCREQ# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0

H_RS#1

H_RS#2

R115 0Ohm

1 2

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4

H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_CPURST# 4,6

CLK_MCH_BCLK# 12 CLK_MCH_BCLK 12

H_DBSY# 4

H_DRDY# 4 H_DSTBN#0 4 H_DSTBN#1 4 H_DSTBN#2 4 H_DSTBN#3 4 H_DSTBP#0 4 H_DSTBP#1 4 H_DSTBP#2 4 H_DSTBP#3 4

H_HIT# 4 H_HITM# 4 H_LOCK# 4

H_REQ#0 4 H_REQ#1 4 H_REQ#2 4 H_REQ#3 4 H_REQ#4 4

/*

2

H_A#[3..31] 4

+VCCP

100 1%R

R125 100Ohm

1%

1 2

H_VREF

200 1%R

12

1 2

H_DEFER# 4 H_DINV#0 4 H_DINV#1 4 H_DINV#2 4 H_DINV#3 4 DPWR# 4

T55

1

T264

1

H_RS#0 4 H_RS#1 4 H_RS#2 4 H_CPUSLP# 4,22 H_TRDY# 4

R124 200Ohm

1%

C120

0.1UF

1

bom

PROJECT:

5

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

4

7 63

DESCRIPTION:

MCH: CPU

3

RELEASE DATE :

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

1

5

DMI_TXN[0..3]23

DMI_TXP[0..3]23

D D

DMI_RXN[0..3]23

DMI_RXP[0..3]23

TP_SMCK2

1

T109

TP_SMCK5

1

T99

TP_SMCK#2

1

T106

TP_SMCK#5

1

C C

T105

Layout Note: Route as short as possible.

R166

R172

40.2Ohm

1%

1 2

+1.8V

1 2

R734 80.6Ohm

B B

TVDAC_A_GM TVDAC_B_GM TVDAC_C_GM

TV_REFSET_GM

A A

DisableTV_OUT: TVDAC A/B/C, TVIRTN A/B/C, TV_REFSET, VCCA_TV,DAC A/B/C... (ALL TV POWER) connect to GND.

bom

1%

Ext VGA: 0 ohm Int VGA: 150 ohm_1%

R651 0Ohm

1 2

R650 0Ohm

1 2

R649 0Ohm

1 2

Ext VGA: 0 ohm Int VGA: 4.99K ohm_1%

R130 0Ohm

1 2

PROJECT:

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 PEG_RXN11

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DCLK014 DCLK114

DCLK313 DCLK413

DCLK0#14 DCLK1#14

DCLK3#13 DCLK4#13

SCKE014,15 SCKE114,15 SCKE213,15 SCKE313,15

SCS0#14,15 SCS1#14,15 SCS2#13,15 SCS3#13,15

M_OCDCOMP0 M_OCDCOMP1

ODT014,15 ODT114,15 ODT213,15 ODT313,15

M_RCOMPN M_RCOMPP

VTT_REF

SMXSLEW SMYSLEW

R735

80.6Ohm

1%

1 2

TVDAC_A_GM# TVDAC_B_GM# TVDAC_C_GM#

W3V

5

U48A

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

ALVISO_BGA1257

Ext VGA: 0 ohm Int VGA: N/A

+VCC_GMCH_CORE

DAC_B_GM DAC_G_GM DAC_R_GM

DAC_VSYNC_GM16 DAC_HSYNC_GM16

REVISION

2.1

DMIDDR MUXING

PM

DREF_CLKN

CLK

DREF_SSCLKN

DREF_SSCLKP

NC

+VCC_GMCH_CORE

4

SDVO SMbus Int PD

SDVOCRTL_DATA Int PD 0: No SDVO device 1: SDVO device present

R119 1KOhm

G16

CFG0

H13

CFG1

G14

CFG2

F16

CFG3

F15

CFG4

G15

CFG5

E16

CFG6

D17

CFG7

J16

CFG8

D15

CFG9

E15

CFG10

D14

CFG11

E14

CFG12

H12

CFG13

C14

CFG14

H15

CFG15

J15

CFG16

H14

CFG17

G22

CFG18

G23

CFG19

D23

CFG20

G25

RSVD21

G24

RSVD22

J17

RSVD23

A31

RSVD24

A30

RSVD25

D26

RSVD26

D25

RSVD27

J23

BM_BUSY#

J21

EXT_TS0#

H22

EXT_TS1#

F5

THRMTRIP#

AD30

PWROK

AE29

RSTIN#

DREF_CLKP

12

R80 0Ohm

R120 0Ohm

Ext VGA: 0 ohm Int VGA: N/A

R164 100Ohm

A24 A23 C37 D37

AP37

NC1

AN37

NC2

AP36

NC3

AP2

NC4

AP1

NC5

AN1

NC6

B1

NC7

A2

NC8

B37

NC9

A36

NC10

A37

NC11

12

R79 0Ohm

1 2

R76 39Ohm /*

1 2

R77 39Ohm /*

1 2

Ext VGA: N/A Int VGA: 39 ohm

DATE: SHEET OF

4

+2.5VS

R1.1#4

1 2

R941 2.2KOhm

/*

CLK_MCH_3GPLL#12 CLK_MCH_3GPLL12

12

+2.5VS MCH_SEL1 12

CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

PM_EXTTS#0 PM_EXTTS#1

TP_NC1 TP_NC2 TP_NC3 TP_NC4 TP_NC5 TP_NC6 TP_NC7 TP_NC8 TP_NC9 TP_NC10 TP_NC11

R78 0Ohm

1 1

1 1 1 1 1

1

1 1 1 1 1 1 1 1

12

1%

REFSET_GM

Ext VGA: N/A Int VGA: 150 ohm_1%

R92 0Ohm R88 0Ohm R93 0Ohm

MCH_SEL0 12

T63 T75

CFG5 11 CFG6 11 CFG7 11

T80

CFG9 11

T69 T42 T61 T71 T62 T70

CFG16 11

T83

CFG18 11 CFG19 11

T57 T77 T68 T87 T268 T267 T76 T263

PM_BMBUSY# 22

GMCH_THRMTRIP# 6 VRM_PWRGD 12,45,48,49,54 BUF_PLT_RST# 6,21,22,23,28,30,31,32

DREFCLK# 12 DREFCLK 12 DREFSSCLK# 12 DREFSSCLK 12

T302

1

T298

1

T304

1

T305

1

T303

1

T300

1

T270

1

T266

1

T269

1

T265

1

T261

1

DisableCRT: R/G/B, R#/G#/B#, REFSET, VCCA_CRTDAC connect to GMCH Core. HSYNC/VSYNC/VCC_SYNC connect to GND.

1 2

/*

1 2

/*

1 2

/*

R101 0Ohm

1 2

Ext VGA: 0 ohm Int VGA: 255 ohm_1%

VSYNC_GM HSYNC_GM

Monday, January 17, 2005

TVDAC_A_GM21 TVDAC_B_GM21 TVDAC_C_GM21

DDC2BC_GM21 DDC2BD_GM21

DAC_B_GM21 DAC_G_GM21 DAC_R_GM21

LCD_BACKEN_GM20

CTL_DATA6

EDID_CLK_GM20 EDID_DAT_GM20

LCD_VDD_EN_GM20

R1.1_No5

DAC_B_GM# DAC_G_GM# DAC_R_GM#

1 2

R90 0Ohm

1 2

R91 0Ohm

Ext VGA: 0 ohm Int VGA: N/A

DESCRIPTION:

CTL_CLK6

8 63

3

AB29 AC29

H24 H25

A15 C16 A17

J18 B15 B16 B17

E24 E23 E21 D21 C20 B20 A19 B19 H21 G21

J20

E25 F25 C23 C22 F23 F22 F26 C33 C31 F28 F27

B30 B29 C25 C24

B34 B33 B32

A34 A33 B31

C29 D28 C27

C28 D27 C26

U48F

SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP

TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC

DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET

LBKLT_CRTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL

LACLKN LACLKP LBCLKN LBCLKP

LADATAN0 LADATAN1 LADATAN2

LADATAP0 LADATAP1 LADATAP2

LBDATAN0 LBDATAN1 LBDATAN2

LBDATAP0 LBDATAP1 LBDATAP2

ALVISO_BGA1257

+1.5VS

+2.5VS

SDVO_SMDATA SDVO_SMCLK

T85

1

TVDAC_A_GM TVDAC_B_GM TVDAC_C_GM TV_REFSET_GM TVDAC_A_GM# TVDAC_B_GM# TVDAC_C_GM#

DAC_B_GM DAC_B_GM# DAC_G_GM DAC_G_GM# DAC_R_GM DAC_R_GM# VSYNC_GM HSYNC_GM REFSET_GM

T262

1

EDID_CLK_GM EDID_DAT_GM

1

T47

1

T58

1

T78

1

T65

LVDS_CLKAM_GM20

LVDS_CLKAP_GM20

LVDS_CLKBM_GM20

LVDS_CLKBP_GM20

LVDS_YA0M_GM20 LVDS_YA1M_GM20 LVDS_YA2M_GM20

LVDS_YA0P_GM20 LVDS_YA1P_GM20 LVDS_YA2P_GM20

LVDS_YB0M_GM20 LVDS_YB1M_GM20 LVDS_YB2M_GM20

LVDS_YB0P_GM20 LVDS_YB1P_GM20 LVDS_YB2P_GM20

1 2

R99 0Ohm /*

Ext VGA: N/A Int VGA: 0 ohm

L_IBG L_LVBG L_LVREFH L_LVREFL

MCH: DDR2/DMI/PEG

3

MISCTVVGALVDS

Ext VGA: 0 ohm Int VGA: N/A

R647 0Ohm

1 2

R648 0Ohm

1 2

R670 0Ohm

1 2

R671 0Ohm

1 2

R81 1.5KOhm

1%

1 2

10KOhm

3 4

10KOhm

5 6

10KOhm

7 8

10KOhm

D36

EXP_COMPI

EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8

EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15

EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8

EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15

L_IBG

D34 E30

F34 G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34

D30 E34 F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34

E32 F36 G32 H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36

D32 E36 F32 G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36

DREFSSCLK# DREFSSCLK

PM_EXTTS#0 PM_EXTTS#1 EDID_DAT_GM EDID_CLK_GM

EXP_ICOMPO

PCI-EXPRESS GRAPHICS

RN4A RN4B RN4C RN4D

RELEASE DATE :

2

R680 24.9Ohm 1%

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10

PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

DREFCLK# DREFCLK

2

1 2

+1.5VS_PCIE

Ext VGA: stuff Int VGA: N/A

PEG_TXN0 PEG_TXP0

C96 0.1UF

PEG_TXN1 PEG_TXP1

C610 0.1UF

PEG_TXN2 PEG_TXP2

C104 0.1UF

PEG_TXN3 PEG_TXP3

C615 0.1UF

PEG_TXN4 PEG_TXP4

C110 0.1UF

PEG_TXN5 PEG_TXP5

C619 0.1UF

PEG_TXN6 PEG_TXP6

C123 0.1UF

PEG_TXN7 PEG_TXP7

C633 0.1UF

PEG_TXN8 PEG_TXP8

C137 0.1UF

PEG_TXN9 PEG_TXP9

C652 0.1UF

PEG_TXN10 PEG_TXP10

C147 0.1UF

PEG_TXN11 PEG_TXP11

C656 0.1UF

PEG_TXN12 PEG_TXP12

C151 0.1UF

PEG_TXN13 PEG_TXP13

C665 0.1UF

PEG_TXN14 PEG_TXP14

C157 0.1UF

PEG_TXN15 PEG_TXP15

C668 0.1UF

PEG_RXN[0..15] 16

PEG_RXP[0..15] 16

1 2

C89 0.1UF

1 2

C596 0.1UF

1 2

C102 0.1UF

1 2

C613 0.1UF

1 2

C106 0.1UF

1 2

C616 0.1UF

1 2

C118 0.1UF

1 2

C620 0.1UF

1 2

C127 0.1UF

1 2

C637 0.1UF

1 2

C141 0.1UF

1 2

C653 0.1UF

1 2

C149 0.1UF

1 2

C657 0.1UF

1 2

C153 0.1UF

1 2

C666 0.1UF

1 2

PEG_G_RXN0 PEG_G_RXP0

PEG_G_RXN1 PEG_G_RXP1

PEG_G_RXN2 PEG_G_RXP2

PEG_G_RXN3 PEG_G_RXP3

PEG_G_RXN4 PEG_G_RXP4

PEG_G_RXN5 PEG_G_RXP5

PEG_G_RXN6 PEG_G_RXP6

PEG_G_RXN7 PEG_G_RXP7

PEG_G_RXN8 PEG_G_RXP8

PEG_G_RXN9 PEG_G_RXP9

PEG_G_RXN10 PEG_G_RXP10

PEG_G_RXN11 PEG_G_RXP11

PEG_G_RXN12 PEG_G_RXP12

PEG_G_RXN13 PEG_G_RXP13

PEG_G_RXN14 PEG_G_RXP14

PEG_G_RXN15 PEG_G_RXP15

DESIGN ENGINEER :SCHEMATIC FILE NAME :

1

M.Y.

PEG_G_RXN[0..15] 16

PEG_G_RXP[0..15] 16

5

D D

4

3

2

1

M_A_DQ[0..63]14

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18

C C

B B

M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AG35 AH35

AL35 AL37

AH36

AJ35

AK37

AL34 AM36 AN35 AP32 AM31 AM34 AM35

AL32 AM32 AN31 AP31 AN28 AP28

AL30 AM30 AM28

AL28 AP27 AM27 AM23 AM22

AL23 AM24 AN22 AP22

AM9

AP7 AP11 AP10

AM7

AN5

AN6

AN3

AP3

AP6

AM6

AM3

AK2

AK3

AG2

AG1

AM2

AH3

AG3

AF3

AE3

AD6

AC4

AF2

AF1

AD4

AD5

AL9 AL6

AL7

AL4

AL3

U48B

SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63

ALVISO_BGA1257

SA_BS0# SA_BS1# SA_BS2#

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4

DDR SYSTEM MEMORY A

SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_CAS# SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

SA_WE#

AK15 AK16 AL21

M_A_DM0

AJ37

M_A_DM1

AP35

M_A_DM2

AL29

M_A_DM3

AP24

M_A_DM4

AP9

M_A_DM5

AP4

M_A_DM6

AJ2

M_A_DM7

AD3

M_A_DQS0

AK36

M_A_DQS1

AP33

M_A_DQS2

AN29

M_A_DQS3

AP23

M_A_DQS4

AM8

M_A_DQS5

AM4

M_A_DQS6

AJ1

M_A_DQS7

AE5

M_A_DQS#0

AK35

M_A_DQS#1

AP34

M_A_DQS#2

AN30

M_A_DQS#3

AN23

M_A_DQS#4

AN8

M_A_DQS#5

AM5

M_A_DQS#6

AH1

M_A_DQS#7

AE4

M_A_A0

AL17

M_A_A1

AP17

M_A_A2

AP18

M_A_A3

AM17

M_A_A4

AN18

M_A_A5

AM18

M_A_A6

AL19

M_A_A7

AP20

M_A_A8

AM19

M_A_A9

AL20

M_A_A10

AM16

M_A_A11

AN20

M_A_A12

AM20

M_A_A13

AM15 AN15

AP16

TP_MA_RCVENIN#

AF29

TP_MA_RCVENOUT#

AF28 AP15

M_A_BS#0 14,15 M_A_BS#1 14,15 M_A_BS#2 14,15

M_A_WE# 14,15

M_A_DM[0..7] 14

M_A_DQS[0..7] 14

M_A_DQS#[0..7] 14

M_A_A[0..13] 14,15

M_A_CAS# 14,15 M_A_RAS# 14,15

R169 0Ohm

1 2

M_B_DQ[0..63]13

AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31

AJ31

AK30

AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23

AJ22 AK22 AH24 AH23 AG22

AJ21 AG10

AH11 AH10

AG9 AG8 AH8

AJ9 AK9 AJ7 AK6 AJ4 AH5 AK8 AJ8 AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5

U48C

SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63

ALVISO_BGA1257

SB_BS0# SB_BS1# SB_BS2#

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7

DDR SYSTEM MEMORY B

SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13

SB_CAS# SB_RAS#

SB_RCVENIN#

SB_RCVENOUT#

SB_WE#

AJ15 AG17 AG21

M_B_DM0

AF32

M_B_DM1

AK34

M_B_DM2

AK27

M_B_DM3

AK24

M_B_DM4

AJ10

M_B_DM5

AK5

M_B_DM6

AE7

M_B_DM7

AB7

M_B_DQS0

AF34

M_B_DQS1

AK32

M_B_DQS2

AJ28

M_B_DQS3

AK23

M_B_DQS4

AM10

M_B_DQS5

AH6

M_B_DQS6

AF8

M_B_DQS7

AB4

M_B_DQS#0

AF35

M_B_DQS#1

AK33

M_B_DQS#2

AK28

M_B_DQS#3

AJ23

M_B_DQS#4

AL10

M_B_DQS#5

AH7

M_B_DQS#6

AF7

M_B_DQS#7

AB5

M_B_A0

AH17

M_B_A1

AK17

M_B_A2

AH18

M_B_A3

AJ18

M_B_A4

AK18

M_B_A5

AJ19

M_B_A6

AK19

M_B_A7

AH19

M_B_A8

AJ20

M_B_A9

AH20

M_B_A10

AJ16

M_B_A11

AG18

M_B_A12

AG20

M_B_A13

AG15 AH14

AK14

TP_MB_RCVENIN#

AF15

TP_MB_RCVENOUT#

AF14 AH16

M_B_BS#0 13,15 M_B_BS#1 13,15 M_B_BS#2 13,15

M_B_CAS# 13,15 M_B_RAS# 13,15

R165 0Ohm

1 2

M_B_WE# 13,15

M_B_DM[0..7] 13

M_B_DQS[0..7] 13

M_B_DQS#[0..7] 13

M_B_A[0..13] 13,15

/*

12

C174 10UF/10V

/*

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48

/*

12

C189 10UF/10V

/*

M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

A A

bom

PROJECT:

5

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

4

9 63

DESCRIPTION:

MCH: DDR2

3

RELEASE DATE :

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

1

5

Ext VGA: stuff Int VGA: N/A

+VCC_GMCH_CORE

+2.5VS

Ext VGA: N/A Int VGA:

D D

stuff

12

C559

0.1UF

C C

12

C581

0.1UF

+1.5VS

B B

L35 120Ohm/100Mhz

+1.5VS

L101 120Ohm/100Mhz

A A

bom

1 2

L32 0Ohm

1 2

L29 0Ohm

/*

12

C138

0.1UF

/*

+VCCP

1.05V

VCCP_GMCH_CAP1 VCCP_GMCH_CAP2 VCCP_GMCH_CAP3

CAP4

12

C618

0.1UF

12

C669

0.1UF

+2.5VS

21

VTT48

VTT49

VTT50

VTT51

VSSA_3GBG

G37

C82

0.1UF

1 2

+1.5VS_3GPLL

12

C163

0.1UF

+1.5VS_PCIE

12

+

CE26 150U/4.0V

/*

+1.5VS

L102 120Ohm/100Mhz

PROJECT:

5

VTT47

VCCA_3GBG

F37

12

+

CE24 150U/4.0V

/*

VTT46

Y27

12

21

C100

0.01UF

VTT41

VTT42

VTT43

VTT44

VTT45

VCC3G6

VCCA_3GPLL0

VCCA_3GPLL1

VCCA_3GPLL2

J37

Y29

Y28

C158 10UF/10V

12

C684

0.1UF

+1.5VS_DDRDLL

W3V

12

C101

0.1UF

12

C650

0.1UF

A6

VTT39

VTT40

VCC3G4

VCC3G5

R37

N37

L37

C687 10UF/10V

VTT38

VCC3G3

U37

12

VTT37

VCC3G2

W37

C708

0.1UF

12

C639 10UF/10V

VTT34

VTT35

VTT36

VCC3G0

VCC3G1

AE37

REVISION

VTT32

VTT33

VCCA_SM2

VCCA_SM3

AF19

AF18

12

+

CE9 150U/4.0V

AP19

2.1

VTT30

VTT31

VCCA_SM0

VCCA_SM1

AF20

+2.5VS

Ext VGA: GND Int VGA: +2.5VS

VTT27

VTT28

VTT29

VCCTX_LVDS2

A28

A27

4

+1.5VS_MPLL

W10

AG12

VTT13

VCCSM54

12

12 12

P11

N11

M11

L11

K11

VTT9

VTT10

VTT11

VTT12

VCCSM50

VCCSM51

VCCSM52

VCCSM53

AM12

AL12

AK12

AJ12

AH12

12

C699

0.1UF

L100 120Ohm/100Mhz C672

0.1UF

VCCA_CRTDAC

VCC_SYNC

V11

U11

T11

R11

VTT4

VTT5

VTT6

VTT7

VTT8

VCCSM45

VCCSM46

VCCSM47

VCCSM48

VCCSM49

AF13

AE13

AP12

AN12

12

C704

0.1UF

VTT26

VCCTX_LVDS1

VTT25

VCCTX_LVDS0

B28

12

VTT24

C107

0.1UF

J10Y9W9U9R9P9N9M9L9J9N8M8N7M7N6M6N5M5N4M4N3M3N2M2B2V1N1M1G1

VTT23

VCCSM64

AM1

AE1

+2.5VS

R10

P10

N10

M10

K10

VTT17

VTT18

VTT19

VTT20

VTT21

VTT22

VCCSM58

VCCSM59

VCCSM60

VCCSM61

VCCSM62

VCCSM63

AC11

AB11

AB10

AB9

AP8

V1.8_DDR_CAP6 V1.8_DDR_CAP4 V1.8_DDR_CAP3

12

C143 10UF/10V

/*

12

+

CE27 150U/4.0V

R126 0Ohm /* R140 0Ohm

V10

U10

T10

VTT14

VTT15

VTT16

VCCSM55

VCCSM56

VCCSM57

AF12

AE12

AD11

Note: All VCCSM pins shorted internally.

12

C688

0.1UF

Ext VGA: N/A Int VGA: stuff

R1.1#34

+1.5VS +2.5VS

12

DATE: SHEET OF

4

C555

C556

10UF/10V

0.1UF

Place near pin A25, B25, B26

Monday, January 17, 2005

10 63

W11

AG13

K12

VTT2

VTT3

VCCSM43

VCCSM44

AH13

21

J13

AJ13

K13

VTT1

VCCSM42

AK13

12

VTT0

VCCSM40

VCCSM41

AL13

C285 10UF/10V

F19

E19

G19

H20

VCC_SYNC

VSSA_CRTDAC

VCCA_CRTDAC0

VCCA_CRTDAC1

VCCSM33

VCCSM34

VCCSM35

VCCSM36

VCCSM37

VCCSM38

VCCSM39

AE17

AE16

AE15

AE14

AP13

AN13

AM13

Note: All VCCSM pins shorted internally.

12

C707

0.1UF

12

C776

0.1UF

12

C557

0.1UF

Place near pin A35

DESCRIPTION:

AA1

AA2

VCCA_HPLL

VCCA_MPLL

VCCSM31

VCCSM32

AE19

AE18

+1.8V

3

12

+

150U/4.0V

Ext VGA: N/A Int VGA: stuff

12

+

150U/4.0V

/*

R1.1#34

AC2

AC1

B23

C35

VCCA_DPLLA

VCCA_DPLLB

VCCH_MPLL1

VCCH_MPLL0

VCCSM27

VCCSM28

VCCSM29

VCCSM30

AE24

AE23

AE22

AE21

AE20

12

C694

0.1UF

12

+

CE8 150U/4.0V

12

C558

0.01UF

3

+1.5VS_HPLL

L99 120Ohm/100Mhz

12

K17

VCC48

T18

K18

VCC46

VCC47

C675

0.1UF

+1.5VS_DPLLB

L25 120Ohm/100Mhz

12

C85

0.1UF

K20

V19

U19

K19

W18

V18

VCC41

VCC42

VCC43

VCC44

VCC45

VCC40

CE25

CE5

POWER

VCCSM17

VCCSM18

VCCSM19

VCCSM20

VCCSM21

VCCSM22

VCCSM23

VCCSM24

VCCSM25

VCCSM26

AN25

AM25

AL25

AK25

AJ25

AH25

AG25

AF25

AE25

V1.8_DDR_CAP5 V1.8_DDR_CAP2 V1.8_DDR_CAP1

12

C702

0.1UF

MCH: POWER

2

21

K27

J27

H27

K26

H26

K25

J25

K24

K23

K22

K21

W20

U20

T20

VCC27

VCC28

VCC29

VCC30

VCC31

VCC32

VCC33

VCC34

VCC35

VCC36

VCC37

VCC38

VCC39

VCCSM4

VCCSM5

VCCSM6

VCCSM7

VCCSM8

VCCSM9

VCCSM10

VCCSM11

VCCSM12

VCCSM13

VCCSM14

VCCSM15

VCCSM16

AD28

AD27

AC27

AP26

AN26

AM26

AL26

AK26

AJ26

AH26

AG26

AF26

AE26

AP25

+2.5VS

12

C71 10UF/10V

C74

0.1UF

+1.5VS_DPLLA

R1.1#34

12

+

CE3

150U/4.0V

/*

Ext VGA: N/A Int VGA: stuff

U27

T27

R27

P27

N27

M27

L27

VCC20

VCC21

VCC22

VCC23

VCC24

VCC25

VCC26

VCCHV1

VCCHV2

VCCSM0

VCCSM1

VCCSM2

VCCSM3

B22

B21

A21

AM37

AH37

AP29

+1.5VS

VCCA_TVBG

12

R150 0Ohm

VCCD_TVDAC VCCA_TVDACB

12

R104 0Ohm

VCCDQ_TVDAC

12

R137 0Ohm

RELEASE DATE :

L16 120Ohm/100Mhz

12

C83

0.1UF

12

C146 10UF/10V

L28

K28

J28

H28

G28

V27

VCC14

VCC15

VCC16

VCC17

VCC18

VCC19

VCCD_LVDS1

VCCD_LVDS2

VCCA_LVDS

VCCHV0

B26

B25

A25

A35

12

C678

0.1UF

12

C156

C155

0.1UF

0.01UF

/*

C91

0.1UF

/*

12

C133

C134

0.01UF

0.1UF

/*

2

21

12

C119 10UF/10V

R28

P28

N28

M28

VCC10

VCC11

VCC12

VCC13

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0

D19

H17

VCCDQ_TVDAC

VCCD_TVDAC

C681

0.01UF

L37 120Ohm/100MHz

1 2

R98 0Ohm /*

L34 120Ohm/100MHz

12

C140 10UF/10V

M29

K29

J29

V28

U28

T28

VCC4

VCC5

VCC6

VCC7

VCC8

VCC9

VCCA_TVDACC0

VCCA_TVDACC1

VCCA_TVBG

VSSA_TVBG

C18

F18

E18

H18

G18

VCCA_TVDACC

VCCA_TVBG

21

/*

21

/*

+1.5VS

Ext VGA: N/A Int VGA: stuff

+VCC_GMCH_CORE

1.05V

12

C154

C113

0.1UF

T29

R29

N29

U48G ALVISO_BGA1257

VCC0

VCC1

VCC2

VCC3

1.8V: 1A for DDR2 400 1 channel 2A for DDR2 400 2 channel

1.3A for DDR2 533 1 channel

2.7A for DDR2 533 2 channel

1.05VS:850mA for CPU 3100mA for external gfx

1.5VS: 1264mA

2.5VS: 293mA

VCCA_TVDACA0

VCCA_TVDACA1

VCCA_TVDACB0

VCCA_TVDACB1

3VS: 120mA

F17

E17

D18

VCCA_TVDACA

VCCA_TVDACB

Ext VGA: stuff R, no-stuff L,C Int VGA: stuff L,C, no-stuff R

12

R64 0Ohm

+1.5VS

12

R94 0Ohm

+1.5VS

12

R138 0Ohm

1

+VCC_GMCH_CORE

1

2

3

R631 1KOhm

/*

1 2

+2.5VS +3VS

12

C144

0.1UF

VCCA_TVDACA

12

C68

0.1UF

/*

12

C87

0.1UF

/*

VCCA_TVDACC

12

C142

0.1UF

/*

L23 120Ohm/100MHz

12

C67

0.01UF

/*

L26 120Ohm/100MHz

12

C94

0.01UF

/*

L36 120Ohm/100MHz

12

C148

0.01UF

/*

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

1

D52 BAT54C

/*

+1.5VS

1

2

D49 BAT54C

/*

3

R632 1KOhm

/*

1 2

+3VS+3VS

21

/*

21

/*

21

/*

5

AL24

AN24

A26

E26

G26

J26

B27

E27

G27

W27

AA27

AB27

AF27

AG27

AJ27

AL27

AN27

E28

W28

AA28

AB28

AC28

A29

D29

E29

F29

G29

H29

L29

P29

VSS267

VSS266

VSS265

VSS264

VSS263

VSS262

VSS261

VSS129

VSS128

VSS127

VSS126

VSS125

VSS124

VSS123

VSS122

VSS121

VSS120

VSS119

VSS118

VSS117

VSS116

VSS115

VSS114

VSS113

VSS112

VSS111

VSS110

VSS109

AD15

VSS244

VCCSM_NCTF22

VSS108

VSS243

VSS242

VSS241

VSS240

VSS239

VSS238

AF4

AN4E5W5

AC16

AD16

AC17

AD17

AC18

AD18

AC19

VCCSM_NCTF21

VCCSM_NCTF20

VCCSM_NCTF19

VCCSM_NCTF18

VCCSM_NCTF17

VCCSM_NCTF16

D D

VSSALVDS

VSS271

VSS270

VSS269

VSS268

VSS260

VSS259

VSS258

VSS257

VSS256

VSS255

VSS254

VSS253

VSS252

VSS251

VSS250

VSS249

VSS248

VSS247

VSS246

VSS245

B36Y1D2G2J2L2P2T2V2

C C

AD2

AE2

AH2

AL2

AN2A3C3

AA3

AB3

AC3

AJ3C4H4L4P4U4Y4

AB12

AC12

AD12

AB13

AC13

AD13

AC14

AD14

AC15

VCCSM_NCTF31

VCCSM_NCTF30

VCCSM_NCTF29

VCCSM_NCTF28

VCCSM_NCTF27

VCCSM_NCTF26

VCCSM_NCTF25

VCCSM_NCTF24

VCCSM_NCTF23

VSS107

VSS237

VCCSM_NCTF15

U29

AD19

VSS106

VSS236

VCCSM_NCTF14

V29

VSS105

VSS235

AL5

AC20

VCCSM_NCTF13

4

W29

AA29

AD29

AG29

AJ29

VSS104

VSS103

VSS102

VSS101

VSS100

VSS234

VSS233

VSS232

VSS231

VSS230

AP5B6J6L6P6T6AA6

AD20

AC21

AD21

AC22

AD22

VCCSM_NCTF9

VCCSM_NCTF8

VCCSM_NCTF12

VCCSM_NCTF11

VCCSM_NCTF10

3

AM29

C30

Y30

AA30

AB30

AC30

AE30

AP30

D31

E31

F31

G31

H31

J31

K31

L31

M31

N31

P31

R31

T31

U31

V31

W31

AD31

AG31

AL31

A32

C32

Y32

AA32

AB32

AC32

AD32

AJ32

AN32

D33

E33

F33

G33

H33

J33

K33

L33

M33

N33

P33

R33

T33

U33

V33

W33

AD33

AF33

AL33

C34

AA34

AB34

AC34

VSS85

VSS84

VSS83

VSS82

VSS81

VSS80

VSS79

VSS78

VSS77

VSS76

VSS75

VSS74

VSS73

VSS72

VSS71

VSS70

VSS69

VSS68

VSS67

VSS66

VSS65

VSS64

VSS63

VSS62

VSS61

VSS60

VSS59

VSS58

VSS57

VSS56

VSS55

VSS54

VSS53

VSS52

VSS51

VSS50

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS99

VSS98

VSS97

VSS96

VSS95

VSS94

VSS93

VSS92

VSS91

VSS90

VSS89

VSS88

VSS87

VSS86

VSS42

2

AD34

AH34

AN34

B35

D35

E35

F35

G35

H35

J35

K35

L35

M35

N35

P35

R35

T35

U35

V35

W35

Y35

AE35

C36

AA36

AB36

AC36

AD36

AE36

AF36

AJ36

AL36

AN36

VSS41

VSS40

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS18

VSS17

VSS16

VSS9

VSS15

VSS14

VSS13

VSS12

VSS11

VSS10

1

E37

H37

K37

M37

P37

T37

V37

Y37

AG37

U48H

VSS4

VSS3

VSS2

ALVISO_BGA1257

VSS1

VSS0

VSS8

VSS7

VSS6

VSS5

VSS

VSS229

VSS228

VSS227

VSS226

VSS225

VSS224

VSS223

VSS222

VSS221

VSS220

VSS219

VSS218

VSS217

VSS216

VSS215

VSS214

VSS213

VSS212

VSS211

VSS210

VSS209

VSS208

VSS207

VSS206

VSS205

VSS204

VSS203

VSS202

VSS201

VSS200

VSS199

VSS198

VSS197

VSS196

VSS195

VSS194

VSS193

VSS192

VSS191

VSS190

VSS189

VSS188

VSS187

VSS186

VSS185

VSS184

VSS183

VSS182

VSS181

VSS180

VSS179

VSS178

VSS177

VSS176

VSS175

VSS174

VSS173

VSS172

VSS171

VSS170

VSS169

VSS168

VSS167

VSS166

VSS165

VSS164

VSS162

VSS161

VSS160

VSS159

VSS158

VSS157

VSS156

VSS155

VSS154

VSS153

VSS152

VSS151

VSS150

VSS149

VSS148

VSS147

VSS146

VSS145

VSS144

VSS143

VSS142

VSS141

VSS140

VSS139

VSS138

VSS137

VSS136

VSS135

VSS134

VSS133

VSS132

VSS131

VSS163

AC6

AE6

AJ6G7V7

AA7

AG7

AK7

AN7C8E8L8P8Y8AL8A9H9K9T9V9AA9

AC23

AD23

AC24

AD24

AC25

AD25

AC26

AD26

L17

M17

N17

P17

T17

U17

V17

W17

VCC_NCTF78

VCC_NCTF77

VCC_NCTF76

VCC_NCTF75

VCC_NCTF74

VCC_NCTF73

VCC_NCTF72

VCCSM_NCTF7

VCCSM_NCTF6

VCCSM_NCTF5

VCCSM_NCTF4

VCCSM_NCTF3

VCCSM_NCTF2

VCCSM_NCTF1

VCCSM_NCTF0

VCC_NCTF71

AC9

AE9

AH9

AN9

D10

L10

Y10

AA10

F11

H11

Y11

AA11

AF11

AG11

AJ11

AL11

AN11

B12

D12

J12

A14

B14

F14

J14

K14

AG14

AJ14

AL14

AN14

C15

K15

A16

D16

H16

K16

AL16

C17

G17

AF17

AJ17

AN17

A18

B18

AL18

C19

H19

J19

T19

W19

AG19

AN19

A20

D20

E20

F20

G20

V20

AK20

C21

F21

AF21

AN21

A22

D22

E22

J22

AH22

AL22

+VCC_GMCH_CORE+1.8V

V26

W26

U48E

VCC_NCTF1

VCC_NCTF0

H23

ALVISO_BGA1257

U18

L18

M18

N18

P18

R18

Y18

L19

M19

N19

P19

R19

Y19

L20

M20

N20

P20

R20

Y20

L21

M21

N21

P21

T21

U21

V21

W21

L22

M22

N22

P22

R22

T22

U22

V22

W22

L23

M23

N23

P23

R23

T23

U23

V23

W23

L24

M24

N24

P24

R24

T24

U24

V24

W24

L25

M25

N25

P25

R25

T25

U25

V25

W25

L26

M26

N26

P26

R26

T26

U26

VCC_NCTF9

VCC_NCTF8

VCC_NCTF7

VCC_NCTF6

VCC_NCTF5

VCC_NCTF4

VCC_NCTF3

VCC_NCTF15

VCC_NCTF14

VCC_NCTF13

VCC_NCTF12

VCC_NCTF11

VCC_NCTF70

VCC_NCTF69

VCC_NCTF68

VCC_NCTF67

VCC_NCTF66

VCC_NCTF65

VCC_NCTF64

VCC_NCTF63

VCC_NCTF62

VCC_NCTF61

VCC_NCTF60

VCC_NCTF59

VCC_NCTF58

VCC_NCTF57

VCC_NCTF56

VCC_NCTF55

VCC_NCTF54

VCC_NCTF53

VCC_NCTF52

VCC_NCTF51

VCC_NCTF50

VCC_NCTF49

VCC_NCTF48

VCC_NCTF47

VCC_NCTF46

VCC_NCTF45

VCC_NCTF44

VCC_NCTF43

VCC_NCTF42

VCC_NCTF41

VCC_NCTF40

VCC_NCTF39

VCC_NCTF38

VCC_NCTF37

VCC_NCTF36

VCC_NCTF35

VCC_NCTF34

VCC_NCTF33

VCC_NCTF32

VCC_NCTF31

VCC_NCTF30

VCC_NCTF29

VCC_NCTF28

VCC_NCTF27

VCC_NCTF26

VCC_NCTF25

VCC_NCTF24

VCC_NCTF23

VCC_NCTF22

VCC_NCTF21

VCC_NCTF20

VCC_NCTF19

VCC_NCTF18

NCTF

VCC_NCTF17

VCC_NCTF10

VCC_NCTF16

VCC_NCTF2

VSS130

AF23

B24

D24

F24

J24

AG24

AJ24

+VCC_GMCH_CORE

VTT_NCTF17

VTT_NCTF16

VTT_NCTF15

VTT_NCTF14

VTT_NCTF13

VTT_NCTF12

VTT_NCTF11

VTT_NCTF10

VTT_NCTF9

VTT_NCTF8

VTT_NCTF7

VTT_NCTF6

VTT_NCTF5

VTT_NCTF4

VTT_NCTF3

VTT_NCTF2

VTT_NCTF1

VTT_NCTF0

VSS_NCTF68

VSS_NCTF67

VSS_NCTF66

VSS_NCTF65

VSS_NCTF64

VSS_NCTF63

VSS_NCTF62

VSS_NCTF61

VSS_NCTF60

VSS_NCTF59

VSS_NCTF58

VSS_NCTF57

VSS_NCTF56

VSS_NCTF55

VSS_NCTF54

VSS_NCTF53

VSS_NCTF52

VSS_NCTF51

VSS_NCTF50

VSS_NCTF49

VSS_NCTF48

VSS_NCTF47

VSS_NCTF46

VSS_NCTF45

VSS_NCTF44

VSS_NCTF43

VSS_NCTF42

VSS_NCTF41

VSS_NCTF40

VSS_NCTF39

VSS_NCTF38

VSS_NCTF37

VSS_NCTF36

VSS_NCTF35

VSS_NCTF34

VSS_NCTF33

VSS_NCTF32

VSS_NCTF31

VSS_NCTF30

VSS_NCTF29

VSS_NCTF28

VSS_NCTF27

VSS_NCTF26

VSS_NCTF25

VSS_NCTF24

VSS_NCTF23

VSS_NCTF22

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF13

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VSS_NCTF0

L12

M12

N12

P12

R12

T12

U12

V12

W12

L13

M13

N13

P13

R13

T13

U13

V13

W13

Y12

AA12

Y13

AA13

L14

M14

N14

P14

R14

T14

U14

V14

W14

Y14

AA14

AB14

L15

M15

N15

P15

R15

T15

U15

V15

W15

Y15

AA15

AB15

L16

M16

N16

P16

R16

T16

U16

V16

W16

Y16

AA16

AB16

R17

Y17

AA17

AB17

AA18

AB18

AA19

AB19

AA20

AB20

R21

Y21

AA21

AB21

Y22

AA22

AB22

Y23

AA23

AB23

Y24

AA24

AB24

Y25

AA25

AB25

Y26

AA26

AB26

NCTF pin can share the via each other or even leave NC

B B

CFG5: LOW = DMI X 2

CFG58

HIGH = DMI X 4 (Default)

R67

2.2KOhm

/*

1 2

CFG7: CPU STRAP

CFG78

A A

bom

PROJECT:

LOW = Mobile Prescot t HIGH = Dothan CPU (Default)

R68

2.2KOhm

/*

1 2

W3V

5

REVISION

CFG9: PCIE GRAPHIC LANE

CFG98

CFG18: CPU VCC SELECT

CFG188

2.1

LOW = REVERSE LANE HIGH = NORMAL OPERATION (Default)

R69

2.2KOhm

/*

1 2

+2.5VS

LOW = 1.05V (Default) HIGH = 1.5V

R56 1KOhm

/*

1 2

Monday, January 17, 2005

DATE: SHEET OF

4

11 63

CFG[17..3] have internal pullup resistors. CFG[19..18] have internal pulldown resistors. SDVOCRTL_DATA has internal pulldown resistors.

DESCRIPTION:

CFG16: FSB DYNAMIC ODT

CFG168

SDVOCRTL_DATA : LOW = No SDVO device present (Default)

LOW = Dynamic ODT Disabled HIGH = Dynamic ODT Enabled (Default)

R66

2.2KOhm

/*

1 2

MCH: GND/NCTF/Strap

3

RELEASE DATE :

2

CFG19: CPU VTT SELECT

+2.5VS

R55 1KOhm

/*

1 2

CFG198

CFG6: LOW = DDR2 SDRAM

HIGH = DDR SDRAM (Default)

CFG68

R72

2.2KOhm

1 2

LOW = 1.05V (Default) HIGH = 1.2V

DESIGN ENGINEER :SCHEMATIC FILE NAME :

1

M.Y.

5

+3VS

L53 120Ohm/100Mhz C265

0.1UF

21

C321 5PF

1 2 /*

C316 5PF

C317 5PF

C320 5PF

1 2

/*

12

C264

0.1UF

D D

CLK_VGA2716,17 CLK_USB4823 CLK_CBPCI40 CLK_LANPCI37 CLK_KBCPCI32

C C

CLK_MINIPCI39 CLK_SIOPCI30

CLK_TPMPCI21 CLK_DBPCI43

CLK_FWHPCI31 CLK_ICHPCI23

B B

12

C287

0.1UF

+3.3VS_CLKVDD

C278 5PF

C300 5PF

1 2

/*

+3VS_CLK

12

C290 10UF/10V

R360 10KOhm

1%

1 2

C279 5PF

1 2 /*

12

C313

C277

0.1UF

0.47U

X3 14.318Mhz

12

C309 47pF/50V

R318 33Ohm R343 33Ohm R307 33Ohm R306 33Ohm R298 33Ohm R277 33Ohm R278 33Ohm

R279 33Ohm/* R280 33Ohm

R315 33Ohm R314 33Ohm

R1.1#38

C318 5PF

C281 5PF

C280 5PF

C319 5PF

1 2

/*

B STEP

CPU_BSEL0

FS_C FS_B FS_A

0 0 0

V

0 0 1 0 1 0

A A

0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

bom

CPU_BSEL1 HOST CLOCK

PCI MHz

133 100

REF MHz

W3V

USB MHz

0 1

ICS 954213 FREQUENCY TABLE

0 0

CPU

SRC

MHz

266 100 33.33 14.318 48.00 96.00 133 100 33.33 14.318 48.00 96.00 200 100 33.33 14.318 48.00 96.00 166 100 33.33 14.318 48.00 96.00 333 100 33.33 14.318 48.00 96.00 100 100 33.33 14.318 48.00 96.00 400 100 33.33 14.318 48.00 96.00 200 100 33.33 14.318 48.00 96.00

PROJECT:

5

DOT MHz

Ext VGA: N/A Int VGA: N/A in default

+3VS

R338 10KOhm

/*

1 2

R310 10KOhm

/*

1 2

Ext VGA: N/A Int VGA: stuff

REVISION

2.1

4

+3VS_CLK

12

C293

0.1UF

12

+3.3VS_CLKVDD

+3VS

1 2

12

C288

C306

0.1UF

12

R339 10KOhm

/*

R311 10KOhm

/*

C294

C296

0.1UF

10UF/10V

12

C310 47pF/50V

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

R362 10KOhm

1%

1 2

10K PU +3VS: pin 34/35 as ITP CLK 10K PD GND: pin 34/35 as SRC CLK

+3VS

R340 10KOhm

/*

SSC_S1

1 2

SSC_S2 SSC_S3

R312 10KOhm

/*

1 2

Monday, January 17, 2005

DATE: SHEET OF

4

+3VS

+3VS_CLK

R303

2.2OHM

12

+3VS_CLKA

XIN_CLKGEN XOUT_CLKGEN 27VGA 48USB 33PCI5_FSA 33PCI4 33PCI3 33PCI2 33PCI1 33PCI0 33PCIF1

IREF

R292 475Ohm

1%

1 2

SDA_3S SCL_3S

Ext VGA: N/A Int VGA: stuff

SCL_3S SDA_3S

+3VS_GM_SS

SDA_3S 6,13,14,19,21,36 SCL_3S 6,13,14,19,21,36

CLK_14 SSC_S3

SSC_S2 SSC_S1

R294 0Ohm /*

1 2

R300 0Ohm /*

1 2

CLK_EN_ICS#

R1.1#5

R313 10KOhm /*

12 63

21

L51 120Ohm/100Mhz

U24

22

VDDSRC1

29

VDDSRC2

33

VDDSRC3

42

VDDCPU

37

VDDA

38

GNDA

50

X1

49

X2

17

27MHZ

11

48MHz

5

FSLA/PCICLK5

4

PCICLK4

3

PCICLK3

56

PCICLK2

55

PCICLK1

54

PCICLK0

9

PCICLK_F1

8

ITP_EN/PCICLK_F0

46

SCLK

47

SDATA

39

IREF

2

GND1

6

GND2

12

GND3

30

GND4

45

GND5

51

GND6

ICS954213

1 2

3 4

7 8

5

12

6

DESCRIPTION:

3

+3.3VS_CLKVDD

+3.3VS_CLKVDD +3.3VS_CLK48

1 2

VDD_REF_CR

S_PCI# S_CPU#

CPU1 CPU1#

CPU0 CPU0#

CPU2 CPU2#

PCIE4 PCIE#4

PCIE3 PCIE#3

PCIE2 PCIE#2

PCIE1 PCIE#1

PCIE0 PCIE#0

DOC_2 DOC_1

DOT96 DOT96#

CLK_EN_ICS#

CLK_BSEL1 CLK_BSEL0

R297: Ext VGA: 33 OHM

R335 0Ohm R309 0Ohm

R271 33Ohm R272 33Ohm

R269 33Ohm R270 33Ohm

R273 33Ohm/* R274 33Ohm/*

R275 33Ohm R276 33Ohm

R323 33Ohm R324 33Ohm

R321 33Ohm R322 33Ohm

R319 33Ohm R320 33Ohm

R256 0Ohm /* R346 0Ohm /*

R316 33Ohm/* R317 33Ohm/*

R1.1_No5

R291 33Ohm R297 33Ohm

R296 15Ohm/*1%

Int VGA: 15 OHM

1

7

VDDPCI

CPUCLKT2_ITP/SRCCLKT5

CPUCLKC2_ITP/SRCCLKC5

VDDPCI0

PCI_SRC_STOP#

CPU_STOP#

CPUCLKT1 CPUCLKC1

CPUCLKT0 CPUCLKC0

SRCCLKT4 SRCCLKC4

SRCCLKT3_SATA SRCCLKC3_SATA

SRCCLKT2 SRCCLKC2

SRCCLKT1 SRCCLKC1

SRCCLKT0 SRCCLKC0

DOTT_96MHz

DOTC_96MHz

VTT_PWRGD#/PD

REF1/FSLB REF0/FSLC

VDD48

VDDREF

DOC_2 DOC_1

R361

2.2OHM

13

48

18 10

41 40

44 43

35 34

32 31

27 28

25 26

23 24

20 21

36 19

14 15

16

52 53

R2.0#8

U25

CLKIN S3

S2 S1

CLKOUT

CLKOUT# SCLK SDATA

VSSIREF PWRDWN REF/SEL

MK1493_05GT /*

VDDA

VDD

IREF

VSSA

VSS

16 9

DREFSSCK_D

12

DREFSSCK#_D

11

IREF_R1

14 13 10 15

+3VS_GM_SS

12

R285 0Ohm

/*

12

C292

C291

0.1UF

/*

R283 33Ohm /*

1 2

R284 33Ohm /*

1 2

R282 475Ohm

/* 1%

1 2

CLOCK GEN (ICS954213)

3

12

C312

0.1UF

1 2 1 2

1

T330

1

T332

1 2 1 2

1 2

For EMI

L54 120Ohm/100MHz

12

C295 10UF/10V

/*

2

R252 1Ohm

1 2

C286 0.1UF

STP_PCI# 22 STP_CPU# 22,49

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7

CLK_ITP_BCLK 6 CLK_ITP_BCLK# 6

CLK_PCIE_PEG 16 CLK_PCIE_PEG# 16

CLK_PCIE_SATA 22 CLK_PCIE_SATA# 22

CLK_MCH_3GPLL 8 CLK_MCH_3GPLL# 8

CLK_PCIE_ICH 23 CLK_PCIE_ICH# 23

OVER_CLK2 30 OVER_CLK1 30

DREFCLK 8 DREFCLK# 8

C304 5PF

C297 5PF

C305 5PF

1 2

/*

+3VS

21

/*

DREFSSCLK 8 DREFSSCLK# 8

RELEASE DATE :

2

PLACE termination close to clock gen.

12

C311

C308

0.1UF

CLK_ICH14 22 CLK_SIO14 30

CLK_14

+3.3VS_CLKVDD

0.1UF

ITP: Stuff No ITP: N/A

Ext VGA: N/A Int VGA: stuff

Install when use Dothan B-Step CPU

CPU_BSEL04,48

CPU_BSEL14

12

R249 1KOhm

/*

ITP: Stuff No ITP: N/A

Ext VGA: N/A Int VGA: stuff

VRM_PWRGD8,45,48,49,54

R917 100KOhm

12

R265 1KOhm

/*

+VCCP

12

1 2

12

R250 47KOhm

R251 10KOhm

/*

CLK_CPU_BCLK CLK_CPU_BCLK#

CLK_MCH_BCLK CLK_MCH_BCLK#

CLK_ITP_BCLK CLK_ITP_BCLK#

CLK_PCIE_PEG CLK_PCIE_PEG#

CLK_PCIE_SATA CLK_PCIE_SATA#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

CLK_PCIE_ICH CLK_PCIE_ICH#

DREFCLK DREFCLK#

DREFSSCLK DREFSSCLK#

R1.1#5

1 2

R363 10KOhm

R919 100KOhm

B

E12

12

+VCCP

E12

Q168 PMBS3904

C

3

R289 1KOhm

/*

R286 47KOhm

DESIGN ENGINEER :SCHEMATIC FILE NAME :

1

R257 49.9Ohm

1 2

R253 49.9Ohm

1 2

R254 49.9Ohm

1 2

R255 49.9Ohm

1 2

R258 49.9Ohm

1 2

R259 49.9Ohm

1 2

R260 49.9Ohm

1 2

R261 49.9Ohm

1 2

R337 49.9Ohm

1 2

R336 49.9Ohm

1 2

R349 49.9Ohm

1 2

R350 49.9Ohm

1 2

R347 49.9Ohm

1 2

R348 49.9Ohm

1 2

R344 49.9Ohm

1 2

R345 49.9Ohm

1 2

R263 49.9Ohm

1 2

R264 49.9Ohm

1 2

12

C893

0.47U

12

R930 330Ohm

1 2

C877 0.01UF

Q169

B

PMBS3904

CPUSEL0

C

1 2

3

R920 1KOhm

1 2

R933 1KOhm

R1.1#12

1 2

R266 1KOhm

CLK_BSEL1 CLK_BSEL0

1 2

R267 1KOhm

M.Y.

1

+3VS_CLK

3

1

G

2

1% 1%

1% /* 1% /*

1% 1%

/* 1% /* 1%

R374 10KOhm

1%

CLK_EN_ICS#

1 2

D

Q50 2N7002

S

CLK_BSEL0

CLK_BSEL1CPUSEL1

MCH_SEL1 8

MCH_SEL0 8

5

4

3

2

1

12

C255

0.1UF

M_B_DQ[0..63] 9

Layout Note: Place these Caps near SO DIMM 0Layout Note: Place these Caps near SO DIMM 0Layout Note: Place these High-Freq decoupling Caps near the GMCH

+1.8V

12

C744 1UF/10V

12

C752 1UF/10V

+3VS

+1.8V

U16B

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

C731 1UF/10V

VDDSPD

83

NC1

120

NC2

50

NC3

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

203

NP_NC1

204

NP_NC2

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

DDR_DIMM_200P

12

C266

0.01UF

12

C254

0.1UF

VTT_REF

12

C259 1UF/10V

C258

2.2uF/6.3V

12

C743 1UF/10V

C253

0.1UF

12

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

12

R247 10KOhm

1%

R248 10KOhm

1%

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

1 2

R1011 0Ohm

T108

1

12

R2.1

C267 1UF/10V

+5V+1.8V

12

C261

0.1UF

VTT_REF

52

V+

1

+

3

/*

4

V-

U20 LMV321

D D

C C

B B

A A

C747 10PF

1 2

C745 10PF

1 2

+3VS

R204 10KOhm

DCLK3

PLACE NEAR SO-DIMM_0

DCLK3#

DCLK4

PLACE NEAR SO-DIMM_0

DCLK4#

12

R205 10KOhm

1 2

+1.8V

12

C706

0.1UF

M_B_A[0..13]9,15

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

M_B_BS#29,15 M_B_BS#09,15

M_B_BS#19,15

SCS2#8,15 SCS3#8,15 DCLK38 DCLK3#8 DCLK48 DCLK4#8 SCKE28,15

SCKE38,15 M_B_CAS#9,15 M_B_RAS#9,15 M_B_WE#9,15

SCL_3S6,12,14,19,21,36 SDA_3S6,12,14,19,21,36

ODT28,15 ODT38,15

M_B_DM[0..7]9

M_B_DQS[0..7]9

M_B_DQS#[0..7]9

12

C713

C709

0.1UF

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

12

C710

0.1UF

U16A

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

DDR_DIMM_200P

+1.8V

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

12

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

C774

0.1UF

M_B_DQ0

5

M_B_DQ1

7

M_B_DQ2

17

M_B_DQ3

19

M_B_DQ4

4

M_B_DQ5

6

M_B_DQ6

14

M_B_DQ7

16

M_B_DQ8

23

M_B_DQ9

25

M_B_DQ10

35

M_B_DQ11

37

M_B_DQ12

20

M_B_DQ13

22

M_B_DQ14

36

M_B_DQ15

38

M_B_DQ16

43

M_B_DQ17

45

M_B_DQ18

55

M_B_DQ19

57

M_B_DQ20

44

M_B_DQ21

46

M_B_DQ22

56

M_B_DQ23

58

M_B_DQ24

61

M_B_DQ25

63

M_B_DQ26

73

M_B_DQ27

75

M_B_DQ28

62

M_B_DQ29

64

M_B_DQ30

74

M_B_DQ31

76

M_B_DQ32

123

M_B_DQ33

125

M_B_DQ34

135

M_B_DQ35

137

M_B_DQ36

124

M_B_DQ37

126

M_B_DQ38

134

M_B_DQ39

136

M_B_DQ40

141

M_B_DQ41

143

M_B_DQ42

151

M_B_DQ43

153

M_B_DQ44

140

M_B_DQ45

142

M_B_DQ46

152

M_B_DQ47

154

M_B_DQ48

157

M_B_DQ49

159

M_B_DQ50

173

M_B_DQ51

175

M_B_DQ52

158

M_B_DQ53

160

M_B_DQ54

174

M_B_DQ55

176

M_B_DQ56

179

M_B_DQ57

181

M_B_DQ58

189

M_B_DQ59

191

M_B_DQ60

180

M_B_DQ61

182

M_B_DQ62

192

M_B_DQ63

194

12

C777

C252

0.1UF

bom

PROJECT:

5

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

4

13 63

DESCRIPTION:

DDR2 SO-DIMM (1)

3

RELEASE DATE :

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

1

5

4

3

2

1

D D

C C

B B

DCLK0

C256 10PF

PLACE NEAR SO-DIMM_1

1 2

DCLK0#

DCLK1

C260 10PF

PLACE NEAR SO-DIMM_1

1 2

DCLK1#

12

R243

10KOhm

R242

10KOhm

12

M_A_A[0..13]9,15

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_BS#29,15 M_A_BS#09,15

M_A_BS#19,15

SCS0#8,15 SCS1#8,15 DCLK08 DCLK0#8 DCLK18 DCLK1#8 SCKE08,15

SCKE18,15 M_A_CAS#9,15 M_A_RAS#9,15 M_A_WE#9,15

SCL_3S6,12,13,19,21,36 SDA_3S6,12,13,19,21,36

ODT08,15 ODT18,15

M_A_DM[0..7]9

M_A_DQS[0..7]9

M_A_DQS#[0..7]9

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

102 101 100

99 98 97 94 92 93 91

105

90 89

116

86 84 85

107 106 110 115

30

32 164 166

79

80 113 108 109 198 200 197 195

114 119

10

26

52

67 130 147 170 185

13

31

51

70 131 148 169 188

11

29

49

68 129 146 167 186

U53A

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2

BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA

ODT0 ODT1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

DDR_DIMM

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

M_A_DQ0

5

M_A_DQ1

7

M_A_DQ2

17

M_A_DQ3

19

M_A_DQ4

4

M_A_DQ5

6

M_A_DQ6

14

M_A_DQ7

16

M_A_DQ8

23

M_A_DQ9

25

M_A_DQ10

35

M_A_DQ11

37

M_A_DQ12

20

M_A_DQ13

22

M_A_DQ14

36

M_A_DQ15

38

M_A_DQ16

43

M_A_DQ17

45

M_A_DQ18

55

M_A_DQ19

57

M_A_DQ20

44

M_A_DQ21

46

M_A_DQ22

56

M_A_DQ23

58

M_A_DQ24

61

M_A_DQ25

63

M_A_DQ26

73

M_A_DQ27

75

M_A_DQ28

62

M_A_DQ29

64

M_A_DQ30

74

M_A_DQ31

76

M_A_DQ32

123

M_A_DQ33

125

M_A_DQ34

135

M_A_DQ35

137

M_A_DQ36

124

M_A_DQ37

126

M_A_DQ38

134

M_A_DQ39

136

M_A_DQ40

141

M_A_DQ41

143

M_A_DQ42

151

M_A_DQ43

153

M_A_DQ44

140

M_A_DQ45

142

M_A_DQ46

152

M_A_DQ47

154

M_A_DQ48

157

M_A_DQ49

159

M_A_DQ50

173

M_A_DQ51

175

M_A_DQ52

158

M_A_DQ53

160

M_A_DQ54

174

M_A_DQ55

176

M_A_DQ56

179

M_A_DQ57

181

M_A_DQ58

189

M_A_DQ59

191

M_A_DQ60

180

M_A_DQ61

182

M_A_DQ62

192

M_A_DQ63

194

M_A_DQ[0..63] 9

+3VS

+1.8V

12

C764

0.1UF

VTT_REF

12

C765

0.1UF

112 111 117

96 95

118

81 82 87

103

88

104 199

83

120

50 69

163

201 202

203 204

47 133 183

77

12

48 184

78

71

72 121 122 196 193

U53B

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12

VDDSPD NC1

NC2 NC3 NC4 NCTEST

1

VREF GND0

GND1 NP_NC1

NP_NC2 VSS1

VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14

8

VSS15

DDR_DIMM

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

Layout Note: Place these Caps near SO DIMM 1Layout Note: Place these Caps near SO DIMM 1

+1.8V

12

C763

C762

0.1UF

A A

bom

PROJECT:

5

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

4

14 63

DESCRIPTION:

DDR2 SO-DIMM (2)

3

12

C283

C771

0.1UF

RELEASE DATE :

2

+1.8V

12

C263 1UF/10V

12

C760 1UF/10V

12

C761 1UF/10V

DESIGN ENGINEER :SCHEMATIC FILE NAME :

12

C257 1UF/10V

1

12

C779 1UF/10V

M.Y.

5

D D

+0.9VS

21

L52 120Ohm/100Mhz

/*

C C

+0.9VS

12

B B

+0.9VS

12

A A

C737

C736

0.1UF

Layout note: Place one cap close to every 2 pullup resistors terminated to +0.9VS

12

C738

C735

0.1UF

R2.1

12

C757

0.1UF

12

C726

0.1UF

12

C742

0.1UF

12

C758

0.1UF

VTT_REF

12

C741

0.1UF

12

C759

0.1UF

4

M_A_A[0..13] 9,14

M_A_BS#[0..2] 9,14

M_B_A[0..13] 9,13

M_B_BS#[0..2] 9,13

SCKE[0:3] 8,13,14

ODT[0:3] 8,13,14

12

C780

C271

0.1UF

12

C725

C775

0.1UF

12

C269

0.1UF

12

C274

0.1UF

12

C268

0.1UF

12

C724

0.1UF

12

C276

C275

0.1UF

12

C740

C739

0.1UF

3

+0.9VS

12

C262

C272

0.1UF

12

C273

C270

0.1UF

2

R758 56Ohm

1 2

R803 56Ohm

1 2

R231 56Ohm

1 2

R751 56Ohm

1 2

R802 56Ohm

1 2

R759 56Ohm

1 2

R744 56Ohm

1 2

R238 56Ohm

1 2

R762 56Ohm

1 2

R804 56Ohm

1 2

R760 56Ohm

1 2

R246 56Ohm

1 2

R245 56Ohm

1 2

R763 56Ohm

1 2

R234 56Ohm

1 2

R741 56Ohm

1 2

R232 56Ohm

1 2

R236 56Ohm

1 2

R742 56Ohm

1 2

R235 56Ohm

1 2

R805 56Ohm

1 2

R761 56Ohm

1 2

R743 56Ohm

1 2

R237 56Ohm

1 2

1 16

56Ohm

2 15

56Ohm

3 14

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

1 16

56Ohm

2 15

56Ohm

3 14

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

1 16

56Ohm

2 15

56Ohm

3 14

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

1 16

56Ohm

2 15

56Ohm

3 14

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

RN12A RN12B RN12C RN12D RN12E RN12F RN12G RN12H

RN13A RN13B RN13C RN13D RN13E RN13F RN13G RN13H

RN27A RN27B RN27C RN27D RN27E RN27F RN27G RN27H

RN28A RN28B RN28C RN28D RN28E RN28F RN28G RN28H

SCKE0 SCKE1 SCKE2 SCKE3

ODT0 ODT1 ODT2 ODT3

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_B_BS#0 M_B_BS#1 M_B_BS#2

M_A_A12 M_A_A11 M_A_A8 M_A_A7 M_A_A9 M_A_A6 M_A_A5 M_A_A1

M_A_A4 M_A_A0 M_A_A2 M_A_A3 M_A_A10 M_A_A13

M_B_A8 M_B_A12 M_B_A9 M_B_A5 M_B_A7 M_B_A6 M_B_A4 M_B_A1

M_B_A3 M_B_A0 M_B_A2 M_B_A10 M_B_A13 M_B_A11

M_A_CAS# 9,14 M_A_RAS# 9,14 M_A_WE# 9,14

M_B_CAS# 9,13 M_B_RAS# 9,13 M_B_WE# 9,13

SCS0# 8,14 SCS1# 8,14 SCS2# 8,13 SCS3# 8,13

1

bom

PROJECT:

5

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

4

15 63

DESCRIPTION:

3

DDR2 Res

RELEASE DATE :

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

1

5

D D

C C

B B

A A

PEG_RXP[0..15]8 PEG_RXN[0..15]8

+3VS

R106 10KOhm

/*

1 2

M26_EN#

M26: install when disable M26

Memory SS (Reserved)

27M_SSIN_X117 27M_SSIN_X217

27M_ATI17

bom

R111 0Ohm /*

1 2

R112 0Ohm /*

1 2

R127 0Ohm /*

1 2

R695 0Ohm

1 2

R697 0Ohm /*

1 2

PROJECT:

5

PEG_RXP0 PEG_RXN0

PEG_RXP1 PEG_RXN1

PEG_RXP2 PEG_RXN2

PEG_RXN3 PEG_RXP4

PEG_RXN4 PEG_RXP5

PEG_RXN5 PEG_RXP6

PEG_RXN6 PEG_RXP7

PEG_RXN7 PEG_RXP8

PEG_RXN8 PEG_RXP9

PEG_RXN9 PEG_RXP10

PEG_RXN10 PEG_RXP11

PEG_RXN11 PEG_RXP12

PEG_RXN12 PEG_RXP13

PEG_RXN13 PEG_RXP14

PEG_RXN14 PEG_RXP15

PEG_RXN15

27M_X1 27M_X2

XTALIN XTALOUT

W3V

PEG_G_RXP[0..15]8 PEG_G_RXN[0..15]8

1 2

C621 0.1UF

1 2

C606 0.1UF

1 2

C640 0.1UF

1 2

C623 0.1UF

1 2

C598 0.1UF

1 2

C642 0.1UF

1 2

C625 0.1UF

1 2

C600 0.1UF

1 2

C644 0.1UF

1 2

C627 0.1UF

1 2

C602 0.1UF

1 2

C646 0.1UF

1 2

C629 0.1UF

1 2

C604 0.1UF

1 2

C648 0.1UF

1 2

C631 0.1UF

1 2

R658 10KOhm /*

+3VS

CLK_VGA27 12,17

PEG_G_TXP0 PEG_G_TXN0

1 2

C622 0.1UF

PEG_G_TXP1 PEG_G_TXN1

1 2

C607 0.1UF

PEG_G_TXP2 PEG_G_TXN2

1 2

C641 0.1UF

PEG_G_TXP3PEG_RXP3 PEG_G_TXN3

1 2

C624 0.1UF

PEG_G_TXP4 PEG_G_TXN4

1 2

C599 0.1UF

PEG_G_TXP5 PEG_G_TXN5

1 2

C643 0.1UF

PEG_G_TXP6 PEG_G_TXN6

1 2

C626 0.1UF

PEG_G_TXP7 PEG_G_TXN7

1 2

C601 0.1UF

PEG_G_TXP8 PEG_G_TXN8

1 2

C645 0.1UF

PEG_G_TXP9 PEG_G_TXN9

1 2

C628 0.1UF

PEG_G_TXP10 PEG_G_TXN10

1 2

C603 0.1UF

PEG_G_TXP11 PEG_G_TXN11

1 2

C647 0.1UF

PEG_G_TXP12 PEG_G_TXN12

1 2

C630 0.1UF

PEG_G_TXP13 PEG_G_TXN13

1 2

C605 0.1UF

PEG_G_TXP14 PEG_G_TXN14

1 2

C649 0.1UF

PEG_G_TXP15 PEG_G_TXN15

1 2

C632 0.1UF

+3VS

R659

10KOhm

/*

R660 10KOhm R661 1KOhm

1 2

X2

12

27Mhz

/*

1 2

R117 1MOhm

12

C105 12PF/50V

/*

REVISION

2.1

4

+PCIE_VDDR

1 2

12

/*

PLT_RST#23

R1.1#9

27M_X1 27M_X2

12

/*

C126 12PF/50V

/*

DATE: SHEET OF

4

PEG_G_RXP0 PEG_G_RXN0 PEG_G_RXP1 PEG_G_RXN1 PEG_G_RXP2 PEG_G_RXN2 PEG_G_RXP3 PEG_G_RXN3 PEG_G_RXP4 PEG_G_RXN4 PEG_G_RXP5 PEG_G_RXN5 PEG_G_RXP6 PEG_G_RXN6 PEG_G_RXP7 PEG_G_RXN7 PEG_G_RXP8 PEG_G_RXN8 PEG_G_RXP9 PEG_G_RXN9 PEG_G_RXP10 PEG_G_RXN10 PEG_G_RXP11 PEG_G_RXN11 PEG_G_RXP12 PEG_G_RXN12 PEG_G_RXP13 PEG_G_RXN13 PEG_G_RXP14 PEG_G_RXN14 PEG_G_RXP15 PEG_G_RXN15

PEG_G_TXP0 PEG_G_TXN0 PEG_G_TXP1 PEG_G_TXN1 PEG_G_TXP2 PEG_G_TXN2 PEG_G_TXP3 PEG_G_TXN3 PEG_G_TXP4 PEG_G_TXN4 PEG_G_TXP5 PEG_G_TXN5 PEG_G_TXP6 PEG_G_TXN6 PEG_G_TXP7 PEG_G_TXN7 PEG_G_TXP8 PEG_G_TXN8 PEG_G_TXP9 PEG_G_TXN9 PEG_G_TXP10 PEG_G_TXN10 PEG_G_TXP11 PEG_G_TXN11 PEG_G_TXP12 PEG_G_TXN12 PEG_G_TXP13 PEG_G_TXN13 PEG_G_TXP14 PEG_G_TXN14 PEG_G_TXP15 PEG_G_TXN15

CLK_PCIE_PEG12 CLK_PCIE_PEG#12

R677 150Ohm 1%

1 2

R692 100Ohm 1%

1 2

R674 10KOhm 1%

1 2 Straping / Internal PD

PLT_RST#_MASK

place close to ASIC

R95 715 Ohm 1%

TV_Y_ATI21 TV_C_ATI21

TV_CVBS_ATI21

M24_SCL19 M24_SDA19

R105 1KOhm

R118 0Ohm /*

1 2

R123 0Ohm /*

1 2

R109 1KOhm

1 2

R672 10KOhm

1 2

T275 T74

1 2

12

M24_R2SET

TV_Y_ATI TV_C_ATI TV_CVBS_ATI

1

M26_EN#

1

T67

T274

Monday, January 17, 2005

16 63

U6A

AH30

PCIE_RX0P

AG30

PCIE_RX0N

AG29

PCIE_RX1P

AF29

PCIE_RX1N

AE29

PCIE_RX2P

AE30

PCIE_RX2N

AD30

PCIE_RX3P

AD29

PCIE_RX3N

AC29

PCIE_RX4P

AB29

PCIE_RX4N

AB30

PCIE_RX5P

AA30

PCIE_RX5N

AA29

PCIE_RX6P

Y29

PCIE_RX6N

W29

PCIE_RX7P

W30

PCIE_RX7N

V30

PCIE_RX8P

V29

PCIE_RX8N

U29

PCIE_RX9P

T29

PCIE_RX9N

T30

PCIE_RX10P

R30

PCIE_RX10N

R29

PCIE_RX11P

P29

PCIE_RX11N

N29

PCIE_RX12P

N30

PCIE_RX12N

M30

PCIE_RX13P

M29

PCIE_RX13N

L29

PCIE_RX14P

K29

PCIE_RX14N

K30

PCIE_RX15P

J30

PCIE_RX15N

AF26

PCIE_TX0P

AE26

PCIE_TX0N

AC25

PCIE_TX1P

AB25

PCIE_TX1N

AC27

PCIE_TX2P

AB27

PCIE_TX2N

AC26

PCIE_TX3P

AB26

PCIE_TX3N

Y25

PCIE_TX4P

W25

PCIE_TX4N

Y27

PCIE_TX5P

W27

PCIE_TX5N

Y26

PCIE_TX6P

W26

PCIE_TX6N

U25

PCIE_TX7P

T25

PCIE_TX7N

U27

PCIE_TX8P

T27

PCIE_TX8N

U26

PCIE_TX9P

T26

PCIE_TX9N

P25

PCIE_TX10P

N25

PCIE_TX10N

P27

PCIE_TX11P

N27

PCIE_TX11N

P26

PCIE_TX12P

N26

PCIE_TX12N

L25

PCIE_TX13P

K25

PCIE_TX13N

L27

PCIE_TX14P

K27

PCIE_TX14N

L26

PCIE_TX15P

K26

PCIE_TX15N

AF27

PCIE_REFCLKP

AE27

PCIE_REFCLKN

AC23

PCIE_CALRP

AB24

PCIE_CALRN

AB23

PCIE_CALI

AE25

PCIE_TEST

AD25

PERSTb

AD24

PERSTb_MASK

AH21

R2SET

AK21

Y_G

AJ22

C_R_PR

AK22

COMP_B_PB

AJ24

H2SYNC

AK24

V2SYNC

AG22

DDC3CLK

AG23

DDC3DATA

AJ23

SSIN

AH24

1

SSOUT

XTALIN

AH28

XTALOUT

TESTEN

XTALIN

AJ29

XTALOUT

AH27

TESTEN

E8

TEST_YCLK

B6

TEST_MCLK

1

AF25 AF11

PLLTEST DPLUS

AH25

STEREOSYNC

M24_CSP64

DESCRIPTION:

3

PCI EXPRESS

DAC2

SS

CLK

3

Part 1 of 6

GPIO_PWRCNTL

GPIO_MEMSSIN

DVO / EXT TMDS / GPIOTMDSDAC1

LVDS

GPIO__AUXWIN

THERM

AJ5

GPIO_0

AH5

GPIO_1

AJ4

GPIO_2

AK4

GPIO_3

AH4

GPIO_4

AF4

GPIO_5

AJ3

GPIO_6

AK3

GPIO_7

AH3

GPIO_8

AJ2

GPIO_9

AH2

GPIO_10

AH1

GPIO_11

AG3

GPIO_12

AG1

GPIO_13

AG2

GPIO_14

AF3 AF2

AE10

DVOVMODE

AH6

DVPDATA_0

AJ6

DVPDATA_1

AK6

DVPDATA_2

AH7

DVPDATA_3

AK7

DVPDATA_4

AJ7

DVPDATA_5

AH8

DVPDATA_6

AJ8

DVPDATA_7

AH9

DVPDATA_8

AJ9

DVPDATA_9

DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCNTL_3

VREFG

TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P TXOUT_L2N TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXCLK_LN

TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P

TXCLK_UN

TXCLK_UP

DIGON

BLON TX0M

TX0P

TX1M

TX1P

TX2M

TX2P TXCM TXCP

DDC2CLK

DDC2DATA

HPD1

HSYNC VSYNC

RSET

DDC1DATA

DDC1CLK

DMINUS

AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10

AJ10 AK10 AJ11 AH11

AG4

AH15 AH16 AJ16 AJ17 AJ18 AK18 AJ20 AJ21 AK19 AJ19 AG16 AG17 AF16 AF17 AE18 AE19 AF19 AF20 AG19 AG20

AE12 AG12

AK13 AJ13 AJ14 AJ15 AK15 AK16 AJ12 AK12

AE13 AE14

AF12 AK27

R

AJ27

G

AJ26

B

AJ25 AK25

AH26 AG25

AF24 AG24

AE11

DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

M24: MAIN

ATI_GPIO0 ATI_GPIO1 ATI_GPIO2 ATI_GPIO3 ATI_GPIO4 ATI_GPIO5

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

LCDDATA18 LCDDATA19

1 1 1

DVPCNTL0 DVPCNTL1 DVPCNTL2 DVPCNTL3

ATI_GPIO6 ATI_GPIO8

ATI_GPIO9 ATI_GPIO10 ATI_GPIO11 ATI_GPIO12 ATI_GPIO13

DVOMODE

T246 T24 T27 T251 T239 T244 T240 T238 T237 T29 T45 T49 T233 T245 T241 T243 T250 T248

T249 T51 T256

1 2

R23 0Ohm

1

(Reserved)

R602 0Ohm /* R614 0Ohm /* R613 8.2KOhm

M22/24: High - no slave VI P ho st M26: no stuff

1 2 3 4 5 6 7 8

For I/O power reference

LVDS_YA0M_ATI 20 LVDS_YA0P_ATI 20 LVDS_YA1M_ATI 20 LVDS_YA1P_ATI 20 LVDS_YA2M_ATI 20 LVDS_YA2P_ATI 20

LVDS_CLKAM_ATI 20 LVDS_CLKAP_ATI 20 LVDS_YB0M_ATI 20 LVDS_YB0P_ATI 20 LVDS_YB1M_ATI 20 LVDS_YB1P_ATI 20 LVDS_YB2M_ATI 20 LVDS_YB2P_ATI 20

LVDS_CLKBM_ATI 20 LVDS_CLKBP_ATI 20

PD

LCD_VDD_EN_ATI 20

PD

LCD_BACKEN_ATI 20

PD

1 2

R625 100KOhm

DAC_R_ATI 21 DAC_G_ATI 21 DAC_B_ATI 21

DAC_HSYNC_ATI DAC_VSYNC_ATI

place close to ASIC

M24_RSET

1 2

R693 499Ohm 1%

DDC2BD_ATI 21 DDC2BC_ATI 21

GPIO_AUX

R673 10KOhm

VGA_THERMDA 19 VGA_THERMDC 19

2

ATI_GPIO0 19 ATI_GPIO1 19 ATI_GPIO2 19 ATI_GPIO3 19 ATI_GPIO4 19 ATI_GPIO5 19 ATI_GPIO6 19

ATI_GPIO8 19

T7

1 2 1 2 1 2

10KOhm 10KOhm 10KOhm 10KOhm

12

ATI_GPIO9 19 ATI_GPIO11 19

ATI_GPIO12 19 ATI_GPIO13 19

ATI_PERF# 52 MEM_SSIN 17

R626 10KOhm /*

1 2

R623 10KOhm

1 2

RN18A RN18B RN18C RN18D

DAC_VSYNC_GM8

DAC_HSYNC_GM8

RELEASE DATE :

2

12

C33

0.1UF

PWR_OK_VGA 52,54

GPIO_AUX

+1.8VS

+3VS

1 2

R36 499Ohm R32 499Ohm

1 2

place close to ASIC

1 2

R17 0Ohm

1 2

R15 0Ohm /*

EDID_DAT_ATI 20 EDID_CLK_ATI 20

R1.1#33

+3VS

Ext VGA: N/A Int VGA: stuff

1 2

R684 0Ohm

/*

DAC_VSYNC_ATI

Ext VGA: N/A Int VGA: stuff

1 2

R688 0Ohm

/*

DAC_HSYNC_ATI

1 2

1

+3VS

R16 10KOhm

/*

1 2

3

Q5

D

2N7002

/*

1

G

S

2

ATI_PERF# (int. PD): H(1.0V) / L(1.2V)

DVOMODE = VSS: 3.3V Mode (ZV or GPIO)

DVPDATA18/19: I2C Data/Clock DVPDATA(1:7,20:23): can be GPIO (Int. PD) DVPCNTL(0:3): PU to VDDR4 if not used DVPDATA(0:23): can NC if not used GPIO(0:13): can NC if not used

1 2 3 4

R686 0Ohm

Ext VGA: 0 ohm Int VGA: N/A

1 2 3 4

R689 0Ohm

Ext VGA: 0 ohm Int VGA: N/A

TV_C_ATI TV_CVBS_ATITV_Y_ATI

R103 150Ohm

1%

M24_THRM# 19

= 1.8V: 1.8V Mode (Ext. TMDS)

U43

B

A

GND

74LVC1G32GV

/*

1 2

U47

B

A

GND

74LVC1G32GV

/*

1 2

R96 150Ohm

1%

1 2

+3VS

5

VCC

Y

+3VS

5

VCC

Y

1 2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

1

R100 150Ohm

1%

R2.0#14

VSYNC_5 21

HSYNC_5 21

1

A A

B B

C C

2

U6B

H28 H29

J28 J29

J26 H25 H26 G26 G30 D29 D28 E28 E29 G29 G28 F28 G25 F26 E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10

C9

B9 B10 E13 E12 E10 F12 F11

E9

F9

F8

VSS169 VSS170 VSS180 VSS181 VSS178 VSS166 VSS167 VSS149 VSS152 VSS82 VSS81 VSS107 VSS108 VSS151 VSS150 VSS133 VSS148 VSS131 VSS106 VSS130 VSS104 VSS128 VSS103 VSS78 VSS38 VSS64 VSS60 VSS62 VSS37 VSS34 VSS61 VSS35 VSS124 VSS97 VSS75 VSS123 VSS95 VSS121 VSS94 VSS120 VSS52 VSS27 VSS26 VSS24 VSS48 VSS23 VSS49 VSS51 VSS5 VSS4 VSS47 VSS21 VSS45 VSS44 VSS18 VSS19 VSS93 VSS92 VSS90 VSS119 VSS118 VSS89 VSS116 VSS115

M24_CSP64

Part 2 of 6

VSS102

VSS31 VSS32 VSS33 VSS58

VSS57 VSS127 VSS126

VSS56

VSS10

VSS59

VSS11 VSS101

VSS29

VSS54 VSS177

VSS134 VSS105

VSS12 VSS122

VSS50

VSS46

VSS91 VSS179

VSS135 VSS129

VSS36

VSS96

VSS25

VSS20 VSS117

VSS8 VSS98 VSS99

VSS100 VSS125

VSS28

VSS30 VSS55

VSS53

VSS7

MVREFA

MVREFM

VSS83 VSS22

MEMORY CHANNEL A MEMORY CHANNEL B

3

E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19

J25 F29 E25 A27 F15 C15 C11 E11

J27 F30 F24 B27 E16 B16 B11 F10

A19 E18 E19 E20 F20 B19

B21 C20

C18 A18

MVREFA

B7

MVREFM

B8

D30 B13

12

C43

0.1UF

As close to ASIC as possible

+ATI_MEM

1 2

R33 100Ohm

1%

R37 100Ohm

1%

12

C51

0.1UF

+ATI_MEM

1 2

4

R54 100Ohm

1%

R53 100Ohm

1%

AD6 AD5

AC2 AC3 AD3

D7

G6 G5

C4 C5

C2 D3 D1 D2 G4 H6 H5

G2 H2

H3 U6 U5 U3

W5 W4

U2

W3

AA2 AA6 AA5 AB6 AB5

AE5 AE4 AB2 AB3

AE1 AE2 AE3

F7 E7

F5 E5

B5 A4

B4

J6 K5 K4 L6 L5

F3 E2

F2 J3 F1

V6

Y6 Y5

V2 V1 V3

Y2 Y3

U6C

VSS71 VSS114 VSS88 VSS141 VSS140 VSS112 VSS86 VSS42 VSS17 VSS43 VSS2 VSS16 VSS40 VSS68 VSS66 VSS67 VSS139 VSS157 VSS156 VSS174 VSS186 VSS185 VSS194 VSS193 VSS137 VSS111 VSS153 VSS84 VSS110 VSS172 VSS109 VSS154 VSS244 VSS243 VSS241 VSS252 VSS259 VSS258 VSS268 VSS267 VSS240 VSS249 VSS248 VSS250 VSS257 VSS264 VSS265 VSS269 VSS272 VSS271 VSS277 VSS276 VSS293 VSS292 VSS301 VSS300 VSS274 VSS275 VSS280 VSS281 VSS291 VSS297 VSS298 VSS299

M24_CSP64

5

Part 3 of 6

VSS205 VSS195 VSS197 VSS191 VSS190 VSS196 VSS198 VSS212 VSS204 VSS183 VSS184 VSS171 VSS211 VSS209 VSS208

VSS87

VSS14 VSS173 VSS138 VSS260 VSS256 VSS284 VSS290

VSS113

VSS15 VSS187 VSS136 VSS251 VSS255 VSS283 VSS289

VSS215 VSS231 VSS232 VSS217 VSS218 VSS216 VSS202

VSS203 VSS229

VSS230

VSS85 VSS270

ROMCSb

MEMVMODE_0 MEMVMODE_1

MEMTEST

N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2

E6 B2 J5 G3 W6 W2 AC6 AD2

F6 B3 K6 G1 V5 W1 AC5 AD1

R2 T5 T6 R5 R6 R3 N1

N2 T2

T3

E3 AA3

AF5 C6

C7 C8

1 2

R65 47Ohm

1%

6

7

8

VDDR1 MEMVMODE_0 MEMVMODE_1

+1.8VSGND

GND+1.8VS

+1.8VS

M26: no staff

R44

4.7KOhm

/*

1 2

1.8V

V

2.5V

R29 4.7KOhm /* R42 4.7KOhm

R25

4.7KOhm

1 2

1 2 1 2

1 2

Memory Clock SS (Reserved)

S0 (Spread Percentage Select): GND: -1.8% VDD: -2.5% (default PU) NC : -0.6%

D D

bom

PROJECT:

1

W3V

REVISION

2.1

2

27M_ATI16

27M_SSIN_X216

27M_SSIN_X116

MEM_SSIN16

1.2V

DATE: SHEET OF

3

1 2

R667 71.5Ohm

R679

71.5Ohm

1%

1 2

R70 22.1Ohm /*1%

Place close to MK1726

Monday, January 17, 2005

17 63

1%

Place close to M24

R1.1#35

R678 0Ohm

27M_SSOUT

R75 10KOhm

/*

1 2

DESCRIPTION:

4

CLK_VGA27 12,16

1 2

R71 22.1Ohm

Place close to MK1726

U7

1

X1/ICLK

2

GND

3

S0

4 5

SSCLK REFCLK

MK1726_08STR /*

VDD PD#

/*1%

8

X2

7 6

M24: MEMORY & SS

5

+3VS

21

L28 120Ohm/100MHz /*

12

C111

C77

22UF/6.3V

0.1UF

/*

RELEASE DATE :

6

7

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

8

5

+ATI_MEM

1.8V

12

L84

21

+A2VDD

+A2VDDQ

+AVDD

+MPVDD

+PVDD

12

L88

C14

0.1UF

LVDDR

C593 10UF/10V

21

+1.8VS

W3V

12

C578 1000PF

+VDD_MEM_CLK

12

C526 10UF/10V

12

120Ohm/100Mhz

12

+3VS

12

C617 10UF/10V

12

C667 10UF/10V

12

C537 10UF/10V

C538

0.1UF

+3.3V_BUS +VDDR4

L90 120Ohm/100Mhz

L92 120Ohm/100Mhz L94 120Ohm/100Mhz L89 120Ohm/100Mhz L82 120Ohm/100Mhz L97 120Ohm/100Mhz L86 120Ohm/100Mhz

L80 120Ohm/100Mhz

R160 0Ohm

L38 80Ohm/100Mhz

D D

+2.5VS

+1.8VS

C C

+1.5VS

+1.2VSP

B B

+MPVDD/10mA

A A

+PVDD/30mA +VDDI/10mA +AVDD/70mA +A2VDDQ/5mA +A2VDD/120mA VDDR4/1.3mA

bom

12

C591 1000PF

+ATI_MEM

21

21 21 21 21 21 21

21

1 2

21

+AVDD

12

C597 1UF/10V

+PVDD

12

C635 1UF/10V

PVSS

+MPVDD

12

C534 1UF/10V

MPVSS

+PNL_PLL/15mA +PNL_IO/60mA +LVDDR_25/200mA +VDDC_CT/40mA PCIE_VDDR, PCIE_PVDD_12/1.52A PCIE_PVDD_18/500mA +ATI_VCORE/8A VDDR1_VDDM/N/A

C533

0.1UF

120Ohm/100Mhz

+PCIE_PVDD_18

+PCIE_PVDD_12

+1.8VS

C532 1000PF

+PNL_PLL

+VDDC_CT

+PCIE_VDDR

120Ohm/100Mhz

PROJECT:

5

12

C523

0.1UF

1 2

R645 0Ohm

C550 1UF/10V

C567 10UF/10V

+A2VDD

C611 10UF/10V

+A2VDDQ

C638 10UF/10V

L98

12

+

CE22

150U/4.0V

/*

12

C580 1UF/10V

12

C574 1UF/10V

12

C584 1UF/10V

12

C587 1UF/10V

21

REVISION

C544 1000PF

12

C664 10UF/10V

2.1

C13

0.1UF

12

C577

0.1UF

12

+LVDDR_25

C554 10UF/10V

+PNL_PLL

C547 100PF

+PNL_IO

C573 100PF

LPVSS

12

4

VDDR1_VDDM

12

+

CE23 150U/4.0V

12

C527 1000PF

12

+VDD_MEM_CLK

C612 1UF/10V

DATE: SHEET OF

R4 R1 N8 N7 M4

K23 K24

N4

H10 H13 H15 H17

AA1 AA4 AA7 AA8

A15 A21 A28

B30 D26 D23 D20 D17 D14 D11

D8 D5

E27

G7

C564

G10 G13

0.1UF

G15 G19 G22 G27 H22 H19

AD4

L23

AE16 AE17 AF15 AE15

AH13 AH12 AF13

AF14

F18

N6

AF21 AE20

AF23

+AVDD

AH23

AE23

+VDDI

AE22 AE21

+PVDD

AK28 AJ28

+MPVDD

Monday, January 17, 2005

4

+3.3V_BUS

U6D

T7

VDDR1_45 VDDR1_44 VDDR1_43 VDDR1_42 VDDR1_41 VDDR1_39

L8

VDDR1_37 VDDR1_35 VDDR1_36 VDDR1_40

J8

VDDR1_34

J7

VDDR1_33

J4

VDDR1_32

J1

VDDR1_31 VDDR1_25 VDDR1_26 VDDR1_27 VDDR1_28

T8

VDDR1_46

V4

VDDR1_47

V7

VDDR1_48

V8

VDDR1_49 VDDR1_50 VDDR1_51 VDDR1_52 VDDR1_53

A3

VDDR1_1

A9

VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5

B1

VDDR1_6 VDDR1_7 VDDR1_15 VDDR1_14 VDDR1_13 VDDR1_12 VDDR1_11 VDDR1_10 VDDR1_9 VDDR1_8 VDDR1_16

F4

VDDR1_17 VDDR1_18 VDDR1_19 VDDR1_20 VDDR1_21 VDDR1_22 VDDR1_23 VDDR1_24 VDDR1_30 VDDR1_29 VDDR1_54 VDDR1_38

LVDDR_25_1 LVDDR_25_2 LVDDR_18_1 LVDDR_18_2

TPVDD TPVSS TXVDDR1

TXVDDR2

VDDRH0 VDDRH1

A2VDD2 A2VDD1

A2VDDQ AVDD

VDD1DI VDD2DI VSS2DI

PVDD PVSS

A7 A6

MPVDD MPVSS

M24_CSP64

Part 4 of 6

1 2

MMSZ4681T1 /*

PCIE_VDDR_12_1 PCIE_VDDR_12_5 PCIE_VDDR_12_4 PCIE_VDDR_12_3 PCIE_VDDR_12_2

PCIE_PVDD_12_2 PCIE_PVDD_12_1 PCIE_PVDD_12_3

PCIE_PVDD_18_2 PCIE_PVDD_18_1 PCIE_PVDD_18_3 PCIE_PVDD_18_4

I/O

POWER

D50

VDDC37 VDDC40 VDDC41 VDDC38 VDDC39

VDD15_4 VDD15_5 VDD15_7 VDD15_8 VDD15_2 VDD15_1 VDD15_3 VDD15_6

VDDR3_5 VDDR3_6 VDDR3_7 VDDR3_4 VDDR3_1 VDDR3_3 VDDR3_2

VDDR4_5 VDDR4_3 VDDR4_1 VDDR4_2 VDDR4_4

VDDM1 VDDM2 VDDM3 VDDM4 VDDM5 VDDM6 VDDM7

AVSSQ

LVSSR1 LVSSR4 LVSSR2 LVSSR3

LPVSSLPVDD

TXVSSR3 TXVSSR1 TXVSSR2

VSSRH0 VSSRH1

A2VSSN2 A2VSSN1

A2VSSQ

AVSSN

VSS1DI

DESCRIPTION:

18 63

3

DIODE SUPPLIES POWER TO VDDC WHILE VDDC REGULATOR STABALIZES DURING POWER ON

2.4V

12

AC13 AD13 AD15 AC15 AC17

2.4V

P8 Y8 AC11 AC20 H20 H11 M23 Y23

AD7 AD19 AD21 AC22 AC8 AC21 AC19

AG7 AD9 AC9 AC10 AD10

AG26 AK29 AJ30 AG28

+PCIE_VDDR

AG27 N24

N23

+PCIE_PVDD_12

P23 U23

T23 V23

+PCIE_PVDD_18

W23 D9

D13 D19 D25 E4 T4

VDDR1_VDDM

AB4

AD22

AF18 AH17 AG15 AG18

LPVSS

AH18AH19

AH14 AG13 AG14

F19 M6

AH20 AG21

AF22 AH22

AE24

PVSS

MPVSS

3

+

12

C548

CE6

10UF/10V

220UF/2V

/*

12

D40 MMSZ4681T1 /*

+VDDC_CT

12

C531 10UF/10V

12

C522 1UF/10V

12

C520 10UF/10V

JP23 SHORT_PIN /*

1 2

JP25 SHORT_PIN /*

1 2

JP22 SHORT_PIN /*

1 2

M24: POWER

2

CP5A

CP5B

0.1UF

1 2

3 4

5 6

+3.3V_BUS

12

C540

0.1UF

12

C579 1UF/10V

12

C539 1UF/10V

Power Sequence: VDDR3(+3VS)->VDDR4(+3VS)< 1ms VDDR3(+3VS)->VDDR1(+1.8VS)< 1ms VDDR4(+3VS)->VDDC(+ATI_VCORE)< 1ms PCIE_PVDD_18(+1.8VS)->PCIE_PVDD_12(+1.2VSP)> 0 PCIE_PVDD_12(+1.2VSP)->VDDC(+ATI_VCORE)> 0 VDDC(+ATI_VCORE)->VDD_15(+1.5VS)< 1ms

Conclusion: +3VS -> 1.8VS -> 1.2VSP -> VCORE -> 1.5VS

CP4B

CP4A

CP5D

CP5C

0.1UF

7 8

3 4

1 2

12

C565

0.1UF

L81

+3.3V_BUS

21

120Ohm/100Mhz

L79

+VDDR4

21

120Ohm/100Mhz

12

C167 10UF/16V

12

C166 10UF/16V

12

C589 10UF/16V

<1ms

---------------------> VCORE

CP7A

CP4C

CP4D

0.1UF

5 6

7 8

3 4

1 2

C552

0.1UF

+ATI_VCORE

C165 1UF/10V

C175 1UF/10V

C583 1UF/10V

CP1A

0.01UF

1 2

CP2A

0.01UF

1 2

CP9A

0.01UF

1 2

12

>0ms >0ms <1ms

<1ms

RELEASE DATE :

CP7B

CP7C

CP7D

0.1UF

5 6

7 8

L87

120Ohm/100Mhz

+PCIE_VDDR

CP1B

CP1C

0.01UF

3 4

5 6

CP2B

CP2C

0.01UF

5 6

3 4

CP9B

CP9C

0.01UF

3 4

5 6

2

0.01UF

7 8

0.01UF

7 8

0.01UF

7 8

CP8A

0.1UF

1 2

3 4

21

CP1D

CP2D

CP9D

+ATI_VCORE

CP8B

CP8C

0.1UF

5 6

7 8

VDDC

12

C566

0.1UF

CP8D

VDDC: M22= 1.15/ 1.0V M24= 1.2/ 1.0V

0.1UF

12

C575

C576

0.1UF

12

AD12

AG5 AG9

AG11

C562

0.1UF

A10 A16 A22 A29

C1

C3 C28 C30 D27 D24 D21 D18 D15 D12 D10

D6

D4

F27

G9 G12 G16 G18 G21 G24 H27 H23 H21 H18 H16 H14 H12

H9

H8

H4

J23 J24

R7

M7

M8

R8

A2

P4

L4 K1 K7 K8

T1

P17 P18

P19 U12 U13 U14 U17 U18 U19

V19

V18

V17

V14

V13

V12 N18 N17 N14

W17 W18 W12 W13 W14

N13 N19 M19 M18 M12 N12 M13 M14

P12

P13

P14 M17

W19

U6E

VSS1 VSS3 VSS6 VSS9 VSS13 VSS39 VSS41 VSS63 VSS65 VSS80 VSS79 VSS77 VSS76 VSS74 VSS73 VSS72 VSS70 VSS69

VSS132 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS168 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS155 VSS175 VSS176

VSS294 VSS302 VSS303 VSS304

VSS219 VSS210 VSS199 VSS200 VSS192 VSS182 VSS188 VSS189 VSS220 VSS228

M24_CSP64

U6F

VDDC16 VDDC17 VDDC18 VDDC19 VDDC20 VDDC21 VDDC22 VDDC23 VDDC24 VDDC30 VDDC29 VDDC28 VDDC27 VDDC26 VDDC25 VDDC11 VDDC10 VDDC9 VDDC34 VDDC35 VDDC31 VDDC32 VDDC33 VDDC8 VDDC12 VDDC6 VDDC5 VDDC1 VDDC7 VDDC2 VDDC3 VDDC13 VDDC14 VDDC15 VDDC4 VDDC36

M24_CSP64

Part 5 of 6

DESIGN ENGINEER :SCHEMATIC FILE NAME :

1

Part 6 of 6

CENTER ARRAY

CORE GND

PCIE_VSS12 PCIE_VSS10 PCIE_VSS11 PCIE_VSS13 PCIE_VSS14 PCIE_VSS15 PCIE_VSS17 PCIE_VSS16 PCIE_VSS18 PCIE_VSS19 PCIE_VSS21 PCIE_VSS22 PCIE_VSS20 PCIE_VSS23 PCIE_VSS26 PCIE_VSS24 PCIE_VSS25 PCIE_VSS30 PCIE_VSS31 PCIE_VSS27 PCIE_VSS28 PCIE_VSS29 PCIE_VSS32 PCIE_VSS33 PCIE_VSS34 PCIE_VSS37 PCIE_VSS35 PCIE_VSS36 PCIE_VSS38 PCIE_VSS39 PCIE_VSS40

Alice Shih

1

VSS201 VSS207 VSS206 VSS213 VSS214 VSS227 VSS226 VSS225 VSS224 VSS223 VSS222 VSS221 VSS233 VSS234 VSS235 VSS263 VSS254 VSS253 VSS246 VSS247 VSS239 VSS238 VSS237 VSS236

VDDCI4 VDDCI1 VDDCI2 VDDCI3

VSS242 VSS245 VSS261 VSS262 VSS266 VSS279 VSS278 VSS273 VSS282 VSS285 VSS286 VSS295 VSS287 VSS288 VSS296 VSS306 VSS305

PCIE_VSS1 PCIE_VSS2 PCIE_VSS6 PCIE_VSS5 PCIE_VSS3 PCIE_VSS4 PCIE_VSS7 PCIE_VSS9 PCIE_VSS8

M16 N16 N15 P15 P16 R18 R17 R16 R15 R14 R13 R12 T13 T14 T15 W15 V16 V15 U15 U16 T19 T18 T17 T16

W16 M15 R19 T12

U4 U8 W7 W8 Y4 AB8 AB7 AB1 AC4 AC12 AC14 AD16 AC16 AC18 AD18 AK2 AJ1

K28 L28 M27 M26 M24 M25 M28 P28 N28 R25 R23 R24 R26 R27 R28 T28 T24 U28 V24 V26 V27 V25 V28 Y28 W24 W28 AA26 AA27 AA23 AA24 AA25 AA28 AB28 AC28 AD28 AD26 AD27 AE28 AF28 AH29

VDDC

8

7

6

5

4

3

2

1

STRAPS

OPTION STRAPS

+3VS

D D

C C

B B

ATI_GPIO016

ATI_GPIO116

ATI_GPIO216

ATI_GPIO316

ATI_GPIO416

ATI_GPIO516

ATI_GPIO616

ATI_GPIO1116

ATI_GPIO1216

ATI_GPIO1316

ATI_GPIO916

ATI_GPIO816

ATI_GPIO0

ATI_GPIO1

ATI_GPIO2

ATI_GPIO3

ATI_GPIO4

ATI_GPIO5

ATI_GPIO6

ATI_GPIO11

ATI_GPIO12

ATI_GPIO13

ATI_GPIO9

ATI_GPIO8

GPIO[0:13] : Internal PD

1 2

R562 10KOhm

1 2

R561 10KOhm /*

1 2

R537 10KOhm /*

1 2

R538 10KOhm

1 2

R520 10KOhm /*

1 2

R519 10KOhm

1 2

R517 10KOhm /*

1 2

R518 10KOhm

1 2

R522 10KOhm /*

1 2

R521 10KOhm

1 2

R554 10KOhm /*

1 2

R555 10KOhm

1 2

R579 10KOhm /*

1 2

R580 10KOhm

1 2

R544 10KOhm /*

1 2

R543 10KOhm

1 2

R542 10KOhm /*

1 2

R541 10KOhm

1 2

R539 10KOhm /*

1 2

R540 10KOhm

1 2

R558 10KOhm /*

1 2

R557 10KOhm

1 2

R559 10KOhm /*

1 2

R560 10KOhm

ATI_GPIO4: 0: no reversed lanes 1: reversed lanes Check layout!

B_PRX_IDLE_MODE (for A21) B_PTX_PDNB_MODE

B_PTX_PWRS_ENB

B_PTX_DEEMPH_EN

PCIE_MODE(1:0)

(For M24 A21/M22 A11)

REVERSE LANES (For M24A23/M22 A13)

FORCE_COMPLIANCE

B_PPLL_BW (For M24 A21/M22 A11)

CM_RANGE (For M24A23/M22 A13)

DEBUG_ACCESS Controls whether ROM bytes 77-76 are used as SUBSYS_VEN_ID strap or

VIP_DEVICE

PKGTYPE(4:0)

PCIE_TEST

GPIO0

GPIO1

GPIO(3:2)

GPIO4

GPIO5

GPIO6

GPIO8

GPIO(9,13:11)ROMIDCFG(3:0)

DVPDATA_20

DVPDATA(15:11)

(For A21) PHY Receiver Idle Detector

0: Normal idle detector / 1: Alternate idle detector

ATI internal use only. Other logic must not affect this signal during RESET

Transmitter Power Savings Enable 0: 50% Tx output swing for mobile mode 1: full Tx output swing (recommended)

V

Must have an external 10K pullup to 3.3V

Transmitter De-emphasis Enable 0: Tx de-emphasis disable for mobile mode

V

1: Tx de_emphasis enable

00: PCI Express 1.0A mode

V

01: Kyrene-compatible mode 10: PCI Express 1.0 mode 11: PCI Express 1.0A mode and short-circuit internal loopback mode

(Rx connected directly to Tx of PHY)

0: normal mode

V

1: extra current in Tx output stage

V

0: non-reversed lanes layout 1: reversed lanes layout

Force chip to go to compliance state quickly for test purposes

0: Full PLL Bandwidth

V

1: Reduced PLL Bandwidth (ATI internal use only. Other logic must not attect this during RESET.)

0: normal common-mode range

V

1: extended commeon-mode range

DEBUG_PORT_MUX_SELECT strap.

If no ROM attached, controls chip IDis. If ROM attached identifies ROM type 0x0x - No ROM, CHG_ID=0

V

0x1x - No ROM, CHG_ID=1 1000 - Parallel ROM, chip IDis from ROM 1001 - 1M Serial AT25F1024 ROM (Atmel) 1010 - 1M Serial AT45DB011 ROM (Atmel) 1011 - 1M Serial M25P10 ROM (ST) 1100 - 512K Serial M25P05 ROM (ST) 1101 - 1M Serial SST45LF010 (SST), W45B512 (Winbond), 512K W45B012 (Winbond) 1110 - 1M SST25VF010 (SST), 512K SST25VF512 (SST) 1111 - 1M Serial NX25F011B (NextFlash)

0: Slave VIP host port device peesent 1: No slave VIP host port device

V

ATI internal use only Identifies package/memory combinations

DESCRIPTIONPIN

ASIC DEFAULT

0

00

0B_PTX_IEXT

0

0000 (internal PD)

(internal PD)

M26: GPIO11 is memory aperture size (0=128M, 1=256M)

R2.1

+3VS

R640 0Ohm /*

SCL_3S6,12,13,14,21,36 SDA_3S6,12,13,14,21,36

A A

bom

PROJECT:

8

1 2

R628 0Ohm /*

1 2

M24_SCL16 M24_SDA16

M24_THRM#16 PM_THRM#6,22,25

W3V

7

REVISION

2.1

R646

6.8KOhm

1 2

M24_THRM#

DATE: SHEET OF

R608

R644

6.8KOhm

1 2

R617 0Ohm

1 2

R607 0Ohm

1 2

Monday, January 17, 2005

19 63

6

SCLK_S SDATA_S

/*

8 7

OD

6

R59 200Ohm

1%

+3VS_ATI_TS

1 2

1

U5

VCC

SMBCLK

OVERT SMBDATA ALERT#

GND

G781_1

5

/*

DESCRIPTION:

5

DXN

DXP

12

OD

4 2 3

C64

0.1UF

1 2

R46 0Ohm /*

1 2

C54 2200PF/10V

1 2

R40 10KOhm

/*

Place close to ASIC

M24: STRAPING/THERMAL

4

M24 THERMAL SENSOR

Reserved: SMBus, Alert (ICH6): turn on FAN Overtemp (ICH6): Windows Shutdown

ATI_OVERTEMP# 22,25 VGA_THERMDA 16 VGA_THERMDC 16

(10/10/10 mil)

RELEASE DATE :

3

Ext VGA: stuff Int VGA: N/A

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

1

A

B

C

D

E

Ext VGA: 0 ohm Int VGA: N/A

0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm

0Ohm 0Ohm 0Ohm 0Ohm

0Ohm

0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm

12 34 56 78

RN3A RN3B RN3C RN3D RN6A RN6B RN6C RN6D RN5A RN5B RN5C RN5D RN7A RN7B RN7C RN7D

RN21A RN21B RN21C RN21D

RN23A

RN23B RN23C RN23D RN22A RN22B RN22C RN22D RN24A RN24B RN24C RN24D

LVDS_YA0P LVDS_YA1M LVDS_YA1P LVDS_YA2M LVDS_YA2P LVDS_CLKAM LVDS_CLKAP LVDS_YB0M LVDS_YB0P LVDS_YB1M LVDS_YB1P LVDS_YB2M LVDS_YB2P LVDS_CLKBM LVDS_CLKBP

LVDS_YA0M

/*

LVDS_YA0P

/* /*

LVDS_YA1M

/*

LVDS_YA1P LVDS_YA2M

/*

LVDS_YA2P

/* /*

LVDS_CLKAM

/*

LVDS_CLKAP

/*

LVDS_YB0M

/*

LVDS_YB0P

/*

LVDS_YB1M

/*

LVDS_YB1P

/*

LVDS_YB2M

/*

LVDS_YB2P

/*

LVDS_CLKBM

/*

LVDS_CLKBP

PID122

PID023

EDID_CLK_GM8 EDID_DAT_GM8

+2.5VS

EDID_CLK_ATI16 EDID_DAT_ATI16

LVDS_YA0M_ATI16

1 1

2 2

3 3

LVDS_YA0P_ATI16 LVDS_YA1M_ATI16 LVDS_YA1P_ATI16 LVDS_YA2M_ATI16 LVDS_YA2P_ATI16 LVDS_CLKAM_ATI16 LVDS_CLKAP_ATI16 LVDS_YB0M_ATI16 LVDS_YB0P_ATI16 LVDS_YB1M_ATI16 LVDS_YB1P_ATI16 LVDS_YB2M_ATI16 LVDS_YB2P_ATI16 LVDS_CLKBM_ATI16 LVDS_CLKBP_ATI16

LVDS_YA0M_GM8

LVDS_YA0P_GM8

LVDS_YA1M_GM8

LVDS_YA1P_GM8

LVDS_YA2M_GM8

LVDS_YA2P_GM8

LVDS_CLKAM_GM8

LVDS_CLKAP_GM8

LVDS_YB0M_GM8

LVDS_YB0P_GM8

LVDS_YB1M_GM8

LVDS_YB1P_GM8

LVDS_YB2M_GM8

LVDS_YB2P_GM8 LVDS_CLKBM_GM8 LVDS_CLKBP_GM8

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

Ext VGA: N/A Int VGA: 0 ohm

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

LVDS_YA0M

LCD CABLE ID PID1 PID0 14" WXGA (AU/SS/CMO/CPT) 0 0

+3VS

12

R8 100KOhm

Ext VGA: stuff Int VGA: N/A

12

R4 100KOhm

R5 1KOhm

R9 1KOhm

12

+3VS

R1.1#6

Ext VGA: N/A Int VGA: stuff

D

3

Q84 2N7002

/*

S

D

3

2

G

Q88

1

2N7002

/*

S

2

G

1

2 1

L17 1KOhm/100MHz

+3VS

Ext VGA: N/A Int VGA: stuff

R571

2.2KOhm

/*

1 2

For EMI

R556

2.2KOhm

/*

1 2

R2.0#18

+LCD_VCC

12

C515 Do Not Stuff

/*

For EMI

12

C508

C50

Do Not Stuff

0.1UF

/*

12

C49 Do Not Stuff

/*

LVDS_YA0M LVDS_YA0P

LVDS_YA1M LVDS_YA1P

LVDS_YA2M LVDS_YA2P

LVDS_CLKAM LVDS_CLKAP

LVDS_YB0M LVDS_YB0P

LVDS_YB1M LVDS_YB1PLVDS_YB1P

LVDS_YB2M LVDS_YB2P

LVDS_CLKBM LVDS_CLKBP

12

C514 Do Not Stuff

/*

LVDS Connector

CN4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

WTOB_CON_30P

12

C46 Do Not Stuff

/*

GND1

NP_NC1

NP_NC2

GND2

33 31 34

34

35

32 36

Q9 2N7002

S

D

3

2

G

+3VSUS +12VS +3V

3

1

G

2

W3V

R533 10KOhm

1 2

D37 1SS355

1 2

R532 470KOhm

D

Q82 2N7002

S

4 4

Ext VGA: N/A Int VGA: 0 ohm

LCD_VDD_EN_GM8

LCD_VDD_EN_ATI16

5 5

bom

1 2

R534 0Ohm /*

PROJECT:

A

1

12

REVISION

2.1

R573 1MOhm

1 2

3

D

Q81

1

2N7002

G

S

2

C495

0.01UF

DATE: SHEET OF

B

R1.1#20

R951 100Ohm

1 2

R22 100Ohm

1 2

+3VS

123

G

D

Q80 SI3456DV

S

C509 3900PF/50V

564

R2.0/2.1

L21

400Ohm/100Mhz

12

C505

0.1UF

21

12

R1.1#20

Monday, January 17, 2005

20 63

+LCD_VCC

12

C69 1UF/10V

BACK_OFF#22,25 LCD_BACKEN_ATI16 LCD_BACKEN_GM8

12

C70 10UF/10V

DESCRIPTION:

LID_SW#44,45,47

12

R41 0Ohm

/*

Ext VGA: N/A Int VGA: 0 ohm

LVDS / INVERTER

C

12

R51 100KOhm

1%

+LCD_VCC

R2.0#1

R48

D11 RB717F

147

VCC

12 13

GND

U28D LV08A

2 1

11

ADJ_BL32

1 2

3

R988 100Ohm

R2.0#12

21

L12 1KOhm/100MHz

For EMI

RELEASE DATE :

D

100KOhm

1 2

AC_BAT_SYS

21

L11 1KOhm/100MHz

12

C29

C30

0.1UF

100PF

21

L8 400Ohm/100Mhz

AC_INV

12

C34

0.1UF/25V

DESIGN ENGINEER :SCHEMATIC FILE NAME :

R2.1

12

C35

0.1UF/25V

Alice Shih

E

Inverter side pin define

10

AC_BAT_SYS

9

AC_BAT_SYS

8

GND

7

(NC)

6

PWM/DC

5

EN

4

GND

3

(NC)

2

GND

1

GND

INVERTOR Connector

CN3

6 5 4 3 2 1 7

WTOB_CON_6P_INVERTER

6

SIDE2 5 4 3 2 1SIDE1

8

A

Place near CRT connector

DAC_R_ATI16 DAC_G_ATI16 DAC_B_ATI16

1 1

DAC_R_GM8 DAC_G_GM8 DAC_B_GM8

HSYNC_516 VSYNC_516

+12VS

2 2

+3VS

+2.5VS

Ext VGA: +3VS Int VGA: +2.5VS

DDC2BD_ATI16

DDC2BC_ATI16

DDC2BD_GM8 DDC2BC_GM8

3 3

1 2

R593 0Ohm

R564 0Ohm

R575 0Ohm

/*

Zo= 75 ohm

Zo= 50 ohm

+DAC_IO_P

12

R656

2.2KOhm

1 2

R668 0Ohm /* R574 0Ohm /*

1 2 3 4 5 6 7 8

S

D

3

2

G

Q90

1

2N7002

DAC_IO_P

R563

2.2KOhm

1 2

12 12

Ext VGA: N/A Int VGA: 0 ohm

Ext VGA: 0 ohm Int VGA: N/A

RN1A

0Ohm

RN1B

0Ohm

RN1C

0Ohm

RN1D

0Ohm

Ext VGA: N/A Int VGA: 0 ohm

RN17A

0Ohm

RN17B

0Ohm

RN17C

0Ohm

RN17D

0Ohm

S

2

G

1

+5VS

3

D

1

G

S

2

/* /* /* /*

R622 0Ohm R582 0Ohm

D

Ext VGA: 0 ohm

3

Int VGA: 39 ohm

Q92 2N7002

1 2

D48 F01J4L

Q107 2N7002

DAC_R DAC_G DAC_B

1 2 1 2

3

1

G

2

12

R636

4.7KOhm

D

S

Q83 2N7002

HSYNC_CRT VSYNC_CRT

12

DAC_R DAC_G DAC_B

R627

4.7KOhm

DDC_DATA DDC_CLK

B

place close to CRT connector

D4 BAV99

3

D3 BAV99

3

D2 BAV99

3

+DAC_IO_P

12

C18

0.1UF

1 2

12

R35 75Ohm

1%

12

R47 75Ohm

1%

R24 75Ohm

1%

Ext VGA: 75 ohm_1% Int VGA: 150 ohm_1%

C

D

E

CRT Connector

6 1 7 2 8 3 9 4

10

5

D_SUB_15P3R

R2.0#20

1617

CN21

11

DDCDA

12

HSYNC

13

VSYNC

14

DDCCL

15

Ext VGA: 3.3PF/68nH/5PF Int VGA: 10PF/47ohm@100MHz/22PF/47ohm@100MHz/10PF

82nH 68nH

1 2

L19 0Ohm

1 2

L10 0Ohm

1 2

L7 0Ohm

21

L85 120Ohm/100Mhz

21

L83 120Ohm/100Mhz

21

L6 120Ohm/100Mhz

21

L4 120Ohm/100Mhz

12

C45

3.3pf

/*

12

C25

3.3pf

/*

12

C52

3.3pf

/*

DAC_RED

DAC_GREEN

DAC_BLUE

12

C66

3.3pf

12

C44

3.3pf

21

L24 0.068UH

21

L18 0.068UH

21

L9 0.068UH

12

C38

3.3pf

12

C73

R85 0Ohm

1 2

RED GREEN BLUE

DDCDA HSYNC VSYNC DDCCL

12

C65

C41

5P

12

C23

C15 47P

7PF/50V

R60 0Ohm

1 2

R45 0Ohm

1 2

12

C541

C549 47P

R2.0#15

Place close to

+3VS

TV connector

1 2

12

C721

0.1UF

RELEASE DATE :

TPM B2B Connector

+3VALWAYS +5V

12

R836

CLK_TPMPCI12 LPC_FRAME#22,30,31,32,43

BUF_PLT_RST#6,8,22,23,28,30,31,32

LPC_AD322,30,31,32,43

4 4

5 5

bom

+3VS LPC_AD022,30,31,32,43 SCL_3S6,12,13,14,19,36 SDA_3S 6,12,13,14,19,36

+3VALWAYS

PM_SUS_STAT#22,25,30

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

+3VS +5V

12

C812

0.1UF

/*

PROJECT:

A

CN29

12 34 56 78 910 11 12 13 14 15 16 17 18 19 20

P_GND1 P_GND2

NP_NC1 NP_NC2

P_GND4 P_GND3

P_GND6 P_GND5

BtoB_CON_20P

21 22

23 24

25 26

27 28

/*

+3VALWAYS

12

C813

0.1UF

/*

W3V

REVISION

10KOhm

/*

LPC_AD2 22,30,31,32,43 LPC_AD1 22,30,31,32,43

INT_SERIRQ 22,25,30,32,40 PM_CLKRUN# 22,25,30,32,37,39,40 LPC_DRQ#0 22,25,30

12

C811

0.1UF

/*

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

21 63

Ext VGA: 0 ohm Int VGA: N/A

Zo= 50 ohm

TV_C_ATI16 TV_Y_ATI16

TV_CVBS_ATI16

TVDAC_A_GM8 TVDAC_B_GM8 TVDAC_C_GM8

1 2

0Ohm

3 4

0Ohm

5 6

0Ohm

7 8

0Ohm

Ext VGA: N/A Int VGA: 0 ohm

1 2

0Ohm

3 4

0Ohm

5 6

0Ohm

7 8

0Ohm

DESCRIPTION:

TV_CVBS

TV_Y

TV_C

D21 BAV99

RN19A RN19B RN19C RN19D

RN20A RN20B RN20C RN20D

TV_CVBS

/* /* /* /*

TV_C TV_Y

TV_Y TV_C

1

3

2

D17 BAV99

1

3

2

D20 BAV99

1

3

2

CRT, TV, TPM CONN

C

Ext VGA: 82PF / 1.8uH / 82PF Int VGA: 5.6PF / 150ohm@100MHz / 5.6PF

L104 1.8UH

12

R746 150Ohm

1%

R739 150Ohm

1%

R752 150Ohm

1%

D

C733 82P

L103 1.8UH

12

C729 82P

L105 1.8UH

12

C750 82P

21

12

C734 82P

21

12

C730 82P

21

12

C751 82P

CVBS_CON

Y_CON C_CON

DESIGN ENGINEER :SCHEMATIC FILE NAME :

TV Connector

CN25

2

CVBS1

7

CVBS2

4

Y

6

C

5

NC

1

GND0

3

GND1

MINI_DIN_7P

8 9

Alice Shih

E

HC1 HC2

5

SATA_ICH_RXN0 SATA_ICH_RXP0

SATA_0RXN SATA_0RXP SATA_0TXN SATA_0TXP SATA_1RXN SATA_1RXP SATA_1TXN SATA_1TXP SATA_2RXN SATA_2RXP SATA_2TXN SATA_2TXP SATA_3RXN SATA_3RXP SATA_3TXN SATA_3TXP

SATA_CLKN SATA_CLKP

SATARBIAS#

SATARBIAS

SMBCLK

SMBDATA

LINKALERT#

SMLINK_0 SMLINK_1

SATALED# SATA_0GP/GPI26 SATA_1GP/GPI29 SATA_2GP/GPI30 SATA_3GP/GPI31

INTRUDER#

RSMRST#

RTCX1

RTCX2

RTCRST#

INTVRMEN

SPKR

SATA_HDD_RXN0 27 SATA_HDD_RXP0 27

SATA_BRIDGE_RXN0 26 SATA_BRIDGE_RXP0 26

SATA_SWAP_RXN2 28 SATA_SWAP_RXP2 28

REVISION

2.1

AE3 AD3 AG2 AF2 AC5 AD5 AF4 AG4 AD7 AC7 AF6 AG6 AC9 AD9 AF8 AG8

AC2 AC1

AG11 AF11

Y4 W5

Y5 W4 U6

AC19 AF17 AE18 AF18 AG18 AA3

Y3

Y1

Y2

AA2

AA5

F8

IDE_PDD[0..15]28

D D

IDE_PDDACK#28

C C

IDE_PDD15 IDE_PDD14 IDE_PDD13 IDE_PDD12 IDE_PDD11 IDE_PDD10 IDE_PDD9 IDE_PDD8 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0

IDE_PDDREQ28

IDE_PDIOR#28 IDE_PDIOW#28 IDE_PIORDY28

IDE_PDA028 IDE_PDA128 IDE_PDA228

IDE_PDCS1#28 IDE_PDCS3#28

INT_IRQ1425,28

AD13 AG15 AE15 AC13 AB13 AB12 AF13 AE13 AB11 AD11 AC11 AE14 AD12 AF14 AF15 AD14

AB15 AB14 AE16 AC14 AF16

AC16 AB17 AC17

AD16 AE17

AB16

U30C

DD_15 DD_14 DD_13 DD_12 DD_11 DD_10 DD_9 DD_8 DD_7 DD_6 DD_5 DD_4 DD_3 DD_2 DD_1 DD_0

DDACK# DDREQ DIOR# DIOW# IORDY

DA0 DA1 DA2

DCS1# DCS3#

IDEIRQ

R1.1#17

1 2

C353 12P

1 2

C356 12P

B B

Unused SATA pin

- Connect RX, RBIAS, CLK to GND

- Leave TX, LED# as NC

SATA_ICH_TXN0 SATA_ICH_TXP0

A A

SATA_ICH_TXN2 SATA_ICH_TXP2

bom

RTC_X1

GND1GND2

2 3

4

X2

X1

1

12

Y1

32.768KHZ

RTC_X2

C337 3900PF/50V

C336 3900PF/50V

C333 3900PF/50V

R382 10MOhm

12

/*

12

PLACE CLOSELY TOGETHER

12

PROJECT:

5

ICH6_M

12

C335 3900PF/50V

/*

12

C334 3900PF/50V

12

C332 3900PF/50V

W3V

4

R354 0Ohm/*

1 2

R357 0Ohm/*

1 2

R355 0Ohm

1 2

R356 0Ohm

1 2

PLACE CLOSELY TOGETHER

SATA_ICH_TXN0 SATA_ICH_TXP0

R331 0Ohm

1 2

SATA_ICH_TXN2 SATA_ICH_TXP2

R330 0Ohm

1 2

SATARBIAS_PN

R376 1MOhm

RTC_X1

RTC_X2

RTC_RST#

1 2

R332 10KOhm R333 0Ohm /*

ICH_SPKR 25,33

RTC CMOS CLEAR

DATE: SHEET OF

4

1 1

R373

24.9Ohm

1%

1 2

SCL_3A 25,36 SDA_3A 25,36

LINKALERT# 25 SM_LINK0 25,36 SM_LINK1 25,36

SATALED# 28 SATA_DET_#0 25,27 PCB_VID2 25 SATA_DET_#2 25,28 AGP_EXT 25

12

PM_RSMRST# 45

+VCC_RTC

12

Monday, January 17, 2005

22 63

T171 T170

SATA_ICH_RXN2 28 SATA_ICH_RXP2 28

T342 T341

CLK_PCIE_SATA# 12 CLK_PCIE_SATA 12

+VCC_RTC

12

R379 180KOhm

J3

12

C349

12

0.1U

X7R

/*

1MM_OPEN_5MIL

SATA_ICH_HDD_RXN0 27 SATA_ICH_HDD_RXP0 27

SATA_ICH_BRIDGE_RXN0 26 SATA_ICH_BRIDGE_RXP0 26

Install R315 for future CPU d e ep er sleep function.

1 2

+VCCP

R367 56Ohm

H_FERR#4

RTC_BAT46

DELAY 18~25ms

ACZ_SYNC ACZ_RST# ACZ_SDOUT ACZ_BCLK

12

C430 10PF

/*

DESCRIPTION:

ICH6: SATA/LPC/IDE/ACZ(1)

3

LPC_AD021,30,31,32,43 LPC_AD121,30,31,32,43 LPC_AD221,30,31,32,43 LPC_AD321,30,31,32,43

LPC_DRQ#021,25,30 LPC_FRAME#21,30,31,32,43

ACZ_SDIN033 ACZ_SDIN138

ACZ_SDOUT25 ACZ_SYNC25

CLK_ICH1412

EEP_DOUT25

EE_DOUT: Int e rn a l w ea k PU EE_CS: Internal weak PD

H_CPUSLP# R365 : B-STEP no stuff H_DPRSTP# R372 : A-STEP no stuff

HA20GATE32

H_A20M#4

H_CPUSLP#4,7

PM_DPRSLPVR49

H_DPRSTP#4

H_DPSLP#4 H_IGNNE#4

FWH_INIT#31

H_INIT#4

H_INTR4

H_NMI4

KBDCPURST32

INT_SERIRQ21,25,30,32,40

H_SMI#4

H_STPCLK#4

H_THRMTRIP#6

T367

1

1 2

R378 1KOhm

1 2

R450 39Ohm

1 2

R467 39Ohm

1 2

R470 39Ohm

1 2

R465 39Ohm

1 2

R451 39Ohm

1 2

R449 39Ohm

1 2

R452 39Ohm

1 2

R466 39Ohm

3

R423 33Ohm R421 33Ohm

R365 0Ohm R372 0Ohm

R364 0Ohm

R371 56Ohm

R366 0Ohm R368 0Ohm

+3VALWAYS

2 1

1

T390

PID120

33Ohm 33Ohm 33Ohm 33Ohm

1 2 1 2

T375

T373

+VCC_RTC

RN16A RN16B RN16C RN16D

1

3

12

C345 1UF/10V

1 2 3 4 5 6 7 8

ACZ_BCLK ACZ_RST# ACZ_SDIN0 ACZ_SDIN1

ACZ_SDOUT ACZ_SYNC

1 2 1 2

1 2

1 2 1 2

D25 RB715F

ACZ_SYNC_AUD 33 ACZ_RST#_AUD 33,34 ACZ_SDOUT_AUD 33 ACZ_BCLK_AUD 33

ACZ_SYNC_MDC 38 ACZ_RST#_MDC 38 ACZ_SDOUT_MDC 38 ACZ_BCLK_MDC 38

AF22 AF23 AE27 AE20 AE24 AD27

AG26

AE22 AF27

AG24

AF24 AF25 AD23 AB20

AG27

AE26 AE23

P4

P2 N3 N5 N4

N6

P3

C10 A10 F11 F10 B10

C9

B9

E10

D12 F13 D11 B12

F12 B11 E12 E11 C13 C12 C11 E13

U30D

LDRQ_1#/GPIO41

LAD_0/FWH0 LAD_1/FWH1 LAD_2/FWH2 LAD_3/FWH3

LDRQ_0# LFRAME#/FWH4

ACZ_BIT_CLK ACZ_RST# ACZ_SDIN_0 ACZ_SDIN_1 ACZ_SDIN_2 ACZ_SDOUT ACZ_SYNC CLK14

EE_CS EE_DIN EE_DOUT EE_SHCLK

LAN_CLK LAN_RSTSYNC LAN_RXD_0 LAN_RXD_1 LAN_RXD_2 LAN_TXD_0 LAN_TXD_1 LAN_TXD_2

A20GATE A20M# CPUSLP# DPRSLPVR/TP_1 DPRSLP#/TP_2 DPSTP# IGNNE# INIT3_3V# INIT# INTR FERR# NMI RCIN# SERIRQ SMI# STPCLK# THRMTRIP#

ICH6_M

RELEASE DATE :

2

BMBUSY#/GPI6

GPI7

SMBALERT#/GPIO11

CPUPWRGD/GPIO49

SUS_STAT#/LPCPD#

GPI8

GPI12 GPI13

STP_PCI#/GPO18

GPIO19

STP_CPU#/GPO20

GPIO21 GPIO23 GPIO24 GPIO25 GPIO27 GPIO28

CLKRUN#/GPIO32

GPIO33 GPIO34

MCH_SYNC#

PWRBTN#

SLP_S3# SLP_S4# SLP_S5#

SUSCLK

SYS_RESET#

LAN_RST#

BATLOW#

TP_3

VRMPWRGD

THRM#

WAKE#

PWROK

2

1

R370 8.2KOhm

1 2

R351 0Ohm

AD19 AE19 R1 W6 M2 R6 AC21 AB21 AD22 AD20 AD21 V3 P5 R3 T3 AF19 AF20 AC18 AG25

AG21 U1 T2

RI#

T4 T5

1

T6

W3

SUSCLK

V6 U2

LAN_RST#

V5 V2 U3

PM_VGATE

AF21 AC20

R419 1KOhm

U5 AA1

1 2

FIR_SEL 25,30,31 EXTSMI#_3A 32 LID_ICH#_3A 47 KBDSCI_3 25,32 ATI_OVERTEMP# 19,25 STP_PCI# 12

STP_CPU# 12,49 BACK_OFF# 20,25 FWH_WP# 25,31 CB_SD# 25,40 ICH6_1HZ 25,43 PCB_VID0 25 PCB_VID1 25 PM_CLKRUN# 21,25,30,32,37,39,40 XIDE_EN#_3 28 OP_SD# 25,34 H_PWRGD 4

MCH_SYNC# 25 PM_PWRBTN# 47 PM_RI# 25

PM_SUSB# 33,34,40,43,47,54,57 PM_SUSC# 43,44,47,48,57

T349

PM_SUS_STAT# 21,25,30

T348

1

1 2

R402 10KOhm

1 2

R397 0Ohm /*

1 2

R391 0Ohm

1 2

R393 10KOhm

R369 0Ohm

1 2

PM_THRM# 6,19,25

12

ICH6_PWROK

12

R388 0Ohm

1 2

R390 0Ohm /*

+3VS

PM_BMBUSY# 8

1

R2.0#3

T389

SYS_RESET# 45 +3VSUS

H_DBRESET# 4,6 BUF_PLT_RST# 6,8,21,23,28,30,31,32 PM_BATLOW# 25 TP3 25

ICH6_PWROK

+3VSUS

ITP: Stuff No ITP: N/A

ICH6_PWROK 45

POWERGD 54

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

1

5

4

3

2

1

U30A

AD_0 AD_1 AD_2 AD_3 AD_4 AD_5 AD_6 AD_7 AD_8

AD_9 AD_10 AD_11 AD_12 AD_13 AD_14 AD_15 AD_16 AD_17 AD_18 AD_19 AD_20 AD_21 AD_22 AD_23 AD_24 AD_25 AD_26 AD_27 AD_28 AD_29 AD_30 AD_31

E2 E5 C2 F5 F3 E9 F2 D6 E6 D3 A2 D2 D5 H3 B4 J5 K2 K5 D4 L6 G3 H4 H2 H5 B3 M6 B2 K6 K3 A5 L1 K4

G2 G4 H6 J6

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_GNT#2

E1

PAR

C3

DEVSEL#

G6

PCICLK

R2

PCIRST#

R5

PLTRST#

A3

IRDY#

P6

PME#

G5

SERR#

J1

STOP#

C5

PLOCK#

J2

TRDY#

E3

PERR#

J3

FRAME#

C1

GNT_0#

B6

GNT_1#

F1

GNT_2#

C8

GNT_3#

E7

GNT_4#/GPIO48

F6

GNT_5#/GPIO17

D8

GNT_6#/GPIO16

L5

REQ_0#

B5

REQ_1#

M5

REQ_2#

B8

REQ_3#

F7

REQ_4#/GPIO40

E8

REQ_5#/GPIO1

B7

REQ_6#/GPIO0

N2

PIRQA#

L2

PIRQB#

M1

PIRQC#

L3

PIRQD#

D9

PIRQE#/GPIO2

C7

PIRQF#/GPIO3

C6

PIRQG#/GPIO4

M3

PIRQH#/GPIO5

C_BE_3# C_BE_2# C_BE_1# C_BE_0#

PCI_PAR37,39,40 PCI_DEVSEL#25,37,39,40

R1.1#14

D D

C C

PLT_RST#_SB

CLK_ICHPCI12

R949 33Ohm

1 2

PCI_IRDY#25,37,39,40 PCI_PME#25,37,39,40 PCI_SERR#25,37,39,40 PCI_STOP#25,37,39,40 PCI_LOCK#25 PCI_TRDY#25,37,39,40 PCI_PERR#25,37,39,40 PCI_FRAME#25,37,39,40

PCI_GNT#037 PCI_GNT#140

PCI_GNT#339 GPO1725

GPO1625

PCI_REQ#025,37 PCI_REQ#125,40 PCI_REQ#225 PCI_REQ#325,39 PID020 KBDDT125,32 KBDDT025,32

PCI_INTA#25,40 PCI_INTB#25,39,40 PCI_INTC#25,37,39,40

PCI_INTD#25,39 PCI_INTE#25 PCI_INTF#25 PCI_INTG#25 PCI_INTH#25

T185 T369

PCI_RST#_ICH PLT_RST#_SB1

1 1

PCI_AD[0..31] 37,39,40

PCI_C/BE#3 37,39,40 PCI_C/BE#2 37,39,40 PCI_C/BE#1 37,39,40 PCI_C/BE#0 37,39,40

DMI_RXN08 DMI_RXP08

DMI_RXN18 DMI_RXP18

DMI_RXN28 DMI_RXP28

DMI_RXN38 DMI_RXP38

DMI_TXN08 DMI_TXP08 USB_PP1 29

DMI_TXN18 DMI_TXP18

DMI_TXN28 DMI_TXP28

DMI_TXN38 DMI_TXP38

+1.5VS

Place within 500 mils of ICH.

1

T184

1

T182

1

T364

1

T365

1

T359

1

T356

1

T354

1

T351

1 2

R436 24.9Ohm

1%

AB24 AB23 AA27 AA26

R27 R26

U27 U26

W27 W26

H25 H24 G27 G26

M25 M24

N27 N26

T25 T24

V25 V24

Y25 Y24

K25 K24 J27 J26

L27 L26 P24 P23

F24 F23

U30B

DMI_0RXN DMI_0RXP DMI_0TXN DMI_0TXP DMI_1RXN DMI_1RXP DMI_1TXN DMI_1TXP DMI_2RXN DMI_2RXP DMI_2TXN DMI_2TXP DMI_3RXN DMI_3RXP DMI_3TXN DMI_3TXP

HSIN_0 HSIP_0 HSON_0 HSOP_0 HSIN_1 HSIP_1 HSON_1 HSOP_1 HSIN_2 HSIP_2 HSON_2 HSOP_2 HSIN_3 HSIP_3 HSON_3 HSOP_3

DMI_ZCOMP DMI_IRCOMP

USBP_0N

USBP_0P

USBP_1N

USBP_1P

USBP_2N

USBP_2P

USBP_3N

USBP_3P

USBP_4N

USBP_4P

USBP_5N

USBP_5P

USBP_6N

USBP_6P

USBP_7N

USBP_7P

OC_0# OC_1# OC_2# OC_3#

OC_4#/GPIO9 OC_5#/GPIO10 OC_6#/GPIO14 OC_7#/GPIO15

USBRBIAS

USBRBIAS#

CLK48

C21 D21 A20 B20 D19 C19 A18 B18 E17 D17 B16 A16 C15 D15 A14 B14

C27 B27 B26 C26 C23 D23 C25 C24

B22 A22

A27

USBRBIAS

USB_PN5

USB_PP5

USB_PN6

USB_PP6

USB_PN7

USB_PP7

1 2

D29 1SS355

Place within 500 mils of ICH.

CLK_USB48 12

T376

1

T190

1

T374

1

T370

1

T378

1

T377

1

1 2

R464 22.6Ohm

1%

USB_PN0 29 USB_PP0 29 USB_PN1 29

USB_PN2 29 USB_PP2 29 USB_PN3 38 USB_PP3 38 USB_PN4 40 USB_PP4 40

for Express Card

USB_OC#0 25,29 USB_OC#12 25,29

USB_OC#3 25 USB_OC#45 25

GPI14 25 CHG_EN# 54,55

CHG_EN#_OC 25

R1.1#10

1

T391

CLK_PCIE_ICH#12

6

CLK_PCIE_ICH12

PCI_RST#_ICH

U28B

147

LV08A

VCC

4 5

GND

+3V

B B

ICH6_M

1 2

PCI_RST#28,37,39,40

+3V

12

C302

SET_PCIRSTNS#32

A A

bom

1 2

R329 10KOhm

12

R328 47KOhm

PROJECT:

5

PCI_RST#

12

C314

0.01UF

W3V

U26

1

A

VCC

2

B

3 4

GND Y

SN74LVC1G32

REVISION

2.1

5

0.1UF

1 2

R983 100Ohm

R2.0#6

DATE: SHEET OF

4

PCI_RSTNS# 32,37

Monday, January 17, 2005

23 63

1 2

R984 33Ohm

R2.0#7

DESCRIPTION:

ICH6: PCI/DMI/USB/PCIE(2)

BUF_PLT_RST#6,8,21,22,28,30,31,32

C324

0.1UF

+3V

U28A

147

LV08A

VCC

3

1 2

GND

3

AD25 AC25

1 2

R295 0Ohm

12

C303

0.01UF

/*

DMI_CLKN DMI_CLKP

ICH6_M

PLT_RST#16

PLT_RST#_SB

RELEASE DATE :

2

U28C

147

LV08A

VCC

8

GND

R358 47KOhm

9 10

12

C325

0.1UF/25V

1 2

Ext VGA: stuff Int VGA: N/A

PLT_RST#_SB

SW_RST# 30

R1.1#36

Can be issue SCI or SMI List: GPIO0~GPIO15

Resume Power Well GPI O Li st: G PI O8,11,13,14,15,24,2 5, 27 ,2 8 Only GPI Pin: GPI0~8,11~15,26,29,30,31,40(5V),41 Only GPO Pin: GPIO16~17,19,21,23,48 Can be GPIO: GPIO24,25,27,28,33,34

Resume Power Input Pin List: BATLOW #,AC_SDI N[0:1],LAN_RST#, OC[7:0]#,PME#,PWRBTN #,RI #,SMB ALER T#,SYS _RES ET#,U S B RB I AS #

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

1

5

+3VS

+VCC_RTC

+1.5VSUS

REVISION

2.1

+1.5VS

+3VS

+3.3VS_LAN

R476 0Ohm

Place near PIN A13

Place near PIN V7

+3VSUS

Place BOTH within 100mils of ICH near pin A17

1 2

R846 0Ohm

+1.5VS

Place 0.01uF within 100mils of ICH near pin AA19

D D

C C

Place 0.1uFx1 near AG10 Place 0.1uFx1 near E26, E27 Place 0.1uFx2 near AG13, AG16

+3VS

+5VS

12

D31

R479 100Ohm

F01J4L

V5REF

12

B B

C443 1UF/10V

C431

0.1UF

Place 0.1uFx3 near A2~A6, D1~H1

Place near PIN A8

+5VSUS +3VSUS

12

D28

R442

F01J4L

10Ohm

V5REF_SUS

12

C412

C409

1UF/10V

0.1UF

A A

Place near PIN F21

bom

PROJECT:

5

W3V

4

12

C374

C338

0.01UF

Place BOTH within 100mils of ICH near pin D27

C396

0.1UF

Place 0.1uF within 100mils of ICH near pin AG23

PCI_IDE_CORE

12

C323

C433

10UF/10V

0.1UF

12

C398

C413

0.1UF

1 2

+3VSUS

R455

0Ohm

1 2

R475

0Ohm

12

C347

C348

0.1UF

/*

1 2

R457 0Ohm

DATE: SHEET OF

4

ICH6_CORE

12

C408

0.1UF

USB_CORE

12

C380

0.1UF

12

C416

0.1UF

12

C402

0.1UF

12

C428

0.1UF

+VCCPSUS

C429

0.1UF

+3.3VA_ICH

12

C426

0.1UF

+3.3VA_ICH

12

C376

0.1UF

12

C339

0.1UF

12

C391

0.1UF

+1.5VA_USB

12

C419 0.1UF

C432

0.1UF

Place 4X0.1uF Distribute near pin ICH6 Package edge

C420

0.1UF

+VCCP

12

C330

0.1UF

12

C329

0.1UF

12

C427

0.1UF

12

C425

0.1UF

12

C423

0.1UF

12

C371

0.1UF

+1.5VS_LAN

Monday, January 17, 2005

24 63

U30E

AA19

VCC1_5_21

AA20

VCC1_5_22

AA21

VCC1_5_23

L11

VCC1_5_24

L12

VCC1_5_25

L14

VCC1_5_26

L16

VCC1_5_27

L17

VCC1_5_28

M11

VCC1_5_29

M17

VCC1_5_30

P11

VCC1_5_31

P17

VCC1_5_32

T11

VCC1_5_33

T17

VCC1_5_34

U11

VCC1_5_35

U12

VCC1_5_36

U14

VCC1_5_37

U16

VCC1_5_38

U17

VCC1_5_39

G8

VCC1_5_40

D24

VCC1_5_41

D25

VCC1_5_42

D26

VCC1_5_43

D27

VCC1_5_44

E20

VCC1_5_45

E21

VCC1_5_46

E22

VCC1_5_47

E23

VCC1_5_48

E24

VCC1_5_49

F20

VCC1_5_50

G20

VCC1_5_51

F9

VCC1_5_52

AB22

V_CPU_IO_1

AD26

V_CPU_IO_2

AG23

V_CPU_IO_3

AA12

VCC3_3_1

AA14

VCC3_3_2

AA15

VCC3_3_3

AA17

VCC3_3_4

AC15

VCC3_3_5

AD17

VCC3_3_6

AG13

VCC3_3_7

AG16

VCC3_3_8

AG19

VCC3_3_9

A6

VCC3_3_10

B1

VCC3_3_11

E4

VCC3_3_12

H1

VCC3_3_13

H7

VCC3_3_14

J7

VCC3_3_15

L4

VCC3_3_16

L7

VCC3_3_17

M7

VCC3_3_18

P1

VCC3_3_19

E26

VCC3_3_20

AA10

VCC3_3_21

AG10

VCC3_3_22

A13

VCCSUS3_3_1

F14

VCCSUS3_3_2

G13

VCCSUS3_3_3

G14

VCCSUS3_3_4

A11

VCCSUS3_3_5

U4

VCCSUS3_3_6

V1

VCCSUS3_3_7

V7

VCCSUS3_3_8

W2

VCCSUS3_3_9

Y7

VCCSUS3_3_10

A17

VCCSUS3_3_11

B17

VCCSUS3_3_12

C16

VCCSUS3_3_13

C17

VCCSUS3_3_14

D16

VCCSUS3_3_15

E16

VCCSUS3_3_16

F15

VCCSUS3_3_17

F16

VCCSUS3_3_18

F18

VCCSUS3_3_19

G15

VCCSUS3_3_20

G16

VCCSUS3_3_21

G17

VCCSUS3_3_22

G18

VCCSUS3_3_23

A24

VCCSUS3_3_24

AB3

VCCRTC

R7

VCCSUS1_5_A

U7

VCCSUS1_5_B

G19

VCCSUS1_5_C

G10

VCCSUS1_5_D

G11

VCCSUS1_5_E

DESCRIPTION:

3

V5REF

T392

+2.5VS_PCI_IDE

V5REF_SUS

VCCDPLL

+1.5VS_SATAPLL

+1.5VS_USBPLL

12

+

150U/4.0V

1

T393

1

12

C342

0.01UF

12

CE16

C327

Place 150uF, 3 X 0.1uF within 100mils of ICH near pin F27, P27, AB27

+1.5VS_SATAPLL

+1.5VS_USBPLL

+1.5VS_SATA

12

C400

0.1UF

12

C346

0.1UF

V5REF1 V5REF2

VCC2_5_1 VCC2_5_2

V5REF_SUS

VCCDMIPLL

VCCSATAPLL

VCCUSBPLL

VCCDMIPWR1 VCCDMIPWR2 VCCDMIPWR3 VCCDMIPWR4 VCCDMIPWR5 VCCDMIPWR6 VCCDMIPWR7 VCCDMIPWR8

VCCDMIPWR9 VCCDMIPWR10 VCCDMIPWR11 VCCDMIPWR12 VCCDMIPWR13 VCCDMIPWR14 VCCDMIPWR15 VCCDMIPWR16 VCCDMIPWR17 VCCDMIPWR18 VCCDMIPWR19 VCCDMIPWR20 VCCDMIPWR21 VCCDMIPWR22 VCCDMIPWR23 VCCDMIPWR24 VCCDMIPWR25 VCCDMIPWR26 VCCDMIPWR27 VCCDMIPWR28 VCCDMIPWR29 VCCDMIPWR30 VCCDMIPWR31 VCCDMIPWR32 VCCDMIPWR33 VCCDMIPWR34 VCCDMIPWR35 VCCDMIPWR36 VCCDMIPWR37 VCCDMIPWR38 VCCDMIPWR39 VCCDMIPWR40 VCCDMIPWR41 VCCDMIPWR42 VCCDMIPWR43 VCCDMIPWR44 VCCDMIPWR45

VCC1_5_1 VCC1_5_2 VCC1_5_3 VCC1_5_4 VCC1_5_5 VCC1_5_6 VCC1_5_7 VCC1_5_8

VCC1_5_9 VCC1_5_10 VCC1_5_11 VCC1_5_12 VCC1_5_13 VCC1_5_14 VCC1_5_15 VCC1_5_16 VCC1_5_17 VCC1_5_18 VCC1_5_19 VCC1_5_20

A8 AA18

AB18 P7

F21

AC27 AE1 A25 AA22

AA23 AA24 AA25 AB25 AB26 AB27 F25 F26 F27 G22 G23 G24 G25 H21 H22 J21 J22 K21 K22 L21 L22 M21 M22 N21 N22 N23 N24 N25 P21 P25 P26 P27 R21 R22 T21 T22 U21 U22 V21 V22 W21 W22 Y21 Y22

AA6 AB4 AB5 AB6 AC4 AD4 AE4 AE5 AG5 AF5 AA7 AA8 AA9 AB8 AC8 AD8 AE8 AE9 AF9 AG9

ICH6_M

ICH6: PWR/GND/CAPS(3)

3

12

C328

0.1UF

L55

21

120Ohm/100Mhz

0.1UF

C422

0.01UF

C322

10UF/10V

12

C434

0.1UF

R375

1 2

0Ohm

12

C344

0.1UF

/*

R463

1 2

0Ohm

12

Place within 100mils of ICH near pin AG5

Place within 100mils of ICH near pin AG9

RELEASE DATE :

2

12

2

+2.5VS

12

C331

0.1UF

+1.5VS

1.5VS: 2.355A

2.5VS: 15mA 3VS: 243mA 3VSUS: 23mA

1.5VSUS: 170mA 5VSUS: 10mA VCCP: 14mA RTC: 5uA

1

U30F

A1

VSS1

A12

VSS2

A15

VSS3

A19

VSS4

A21

VSS5

A23

VSS6

A26

VSS7

A4

VSS8

A7

VSS9

A9

VSS10

AA11

VSS11

AA13

VSS12

AA16

VSS13

AA4

VSS14

AB1

VSS15

AB10

VSS16

AB19

VSS17

AB2

VSS18

AB7

VSS19

AB9

VSS20

AC10

VSS21

AC12

VSS22

AC22

VSS23

AC23

VSS24

AC24

VSS25

AC26

VSS26

AC3

VSS27

AC6

VSS28

AD1

VSS29

AD10

VSS30

AD15

VSS31

AD18

VSS32

AD2

VSS33

AD24

VSS34

AD6

VSS35

AE10

VSS36

AE11

VSS37

AE12

VSS38

AE2

VSS39

AE21

VSS40

AE25

VSS41

AE6

VSS42

AE7

VSS43

AF1

VSS44

AF12

VSS45

AF26

VSS46

AF3

VSS47

AF7

VSS48

AG1

VSS49

AG12

VSS50

AG14

VSS51

AG17

VSS52

AG20

VSS53

AG22

VSS54

AG3

VSS55

AG7

VSS56

B13

VSS57

B15

VSS58

B19

VSS59

B21

VSS60

B23

VSS61

B25

VSS62

C14

VSS63

C18

VSS64

C20

VSS65

C22

VSS66

C4

VSS67

D1

VSS68

D10

VSS69

D13

VSS70

D14

VSS71

D18

VSS72

D20

VSS73

D22

VSS74

D7

VSS75

E14

VSS76

E15

VSS77

E18

VSS78

E19

VSS79

E25

VSS80

F17

VSS81

F19

VSS82

F22

VSS83

F4

VSS84

G1

VSS85

G12

VSS86

ICH6_M

Power Seq. +1.8V rise time < 2ms +1.5VS --> +VCCP +5VS --> +3VS --> +2.5VS +5VSUS --> +3VSUS --> +1.5VSUS

VCCRTC --> RTCRST# > 5ms +3VALWAYS --> RSMRST# > 5ms +3VALWAYS --> LAN_RST# > 10ms +3VS(LAN) --> LAN_RST# > 10ms +3VS,+1.5VS --> PWROK,PM_VATE > 99ms

VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173

G21 G7 G9 H23 H26 H27 J23 J24 J25 J4 K1 K23 K26 K27 K7 L13 L15 L23 L24 L25 M12 M13 M14 M15 M16 M23 M26 M27 M4 N1 N11 N12 N13 N14 N15 N16 N17 N7 P12 P13 P14 P15 P16 P22 R11 R12 R13 R14 R15 R16 R17 R23 R24 R25 R4 T1 T12 T13 T14 T15 T16 T23 T26 T27 T7 U13 U15 U23 U24 U25 V23 V26 V27 V4 W1 W23 W25 W7 Y23 Y26 Y27 Y6 W24 E27 B24 AF10

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

1

5

4

3

2

1

+3VS +3VSUS

RP3A

PCI_FRAME#23,37,39,40

PCI_IRDY#23,37,39,40 PCI_TRDY#23,37,39,40

D D

C C

B B

A A

MB R1.0

MB R2.1 0 01

bom

PCI_STOP#23,37,39,40 PCI_SERR#23,37,39,40

PCI_DEVSEL#23,37,39,40

PCI_PERR#23,37,39,40 PCI_LOCK#23

INT_SERIRQ21,22,30,32,40

PM_THRM#6,19,22 PCI_REQ#023,37 PCI_REQ#123,40 PCI_REQ#223 PCI_REQ#323,39

KBDSCI_322,32 PCI_INTD#23,39 PCI_INTC#23,37,39,40 PCI_INTA#23,40 PCI_INTB#23,39,40

SATA_DET_#022,27 SATA_DET_#222,28 MCH_SYNC#22

USB_OC#023,29

PM_RI#22

CHG_EN#_OC23

USB_OC#1223,29 USB_OC#4523 USB_OC#323

ATI_OVERTEMP#19,22

GPI1423

00MB R1.1 0

00MB R2.0 1

PCB_VID0 PCB_VID1 PCB_VID2

W3V

PCB_VID022 PCB_VID122 PCB_VID222

PCB_VID2 PCB_VID1 PCB_VID0

000

PROJECT:

5

1 5 2 5 3 5 4 5 6 5 7 5 8 5 9 5 1 5 2 5 3 5 4 5 6 5 7 5 8 5 9 5 1 5 2 5 3 5 6 5 8 5 1 5 3 5 6 5

1 5 2 5 3 5 4 5 6 5 7 5 8 5 9 5

R2.1

12

8.2KOhm

10KOhm 10KOhm 10KOhm 10KOhm 10KOhm 10KOhm 10KOhm 10KOhm

R422 100KOhm

/*

R420 10KOhm

REVISION

10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

10 10 10 10 10 10 10 10

+3VSUS

2.1

RP3B RP3C RP3D RP3E RP3F RP3G RP3H RP6A RP6B RP6C RP6D RP6E RP6F RP6G RP6H RP4A RP4B RP4C RP4E RP4G RP2A RP2C RP2E

RP5A RP5B RP5C RP5D RP5E RP5F RP5G RP5H

12

R417 100KOhm

12

R418 10KOhm

/*

12

C441

0.1UF

+3VSUS

+3VS

12

R341 100KOhm

/*

12

R342 10KOhm

DATE: SHEET OF

Monday, January 17, 2005

4

25 63

+3VS

R469 10KOhm

+3VS

R468 10KOhm

R409 10KOhm

+3VS

R473 1KOhm

R474 1KOhm

R448 1KOhm

R480 1KOhm

INTERNAL PULL-DOWN PULL-UP : PCI Express Port config bit 1

12

/*

INTERNAL PULL-DOWN PULL-UP : PCI Express Port config bit 0

12

/*

12

1 2

/*

INTERNAL PULL-UP PULL-DOWN : PCI Express Port chain test

INTERNAL PULL-DOWN PULL-UP : NO REBOOT

INTERNAL PULL-UP PULL-DOWN : RESERVED

INTERNAL PULL-UP PULL-DOWN : Boot BIOS destination select

INTERNAL PULL-UP PULL-DOWN :TOP-BLOCK SWAP

INTERNAL PULL-DOWN SIGNALS :

AC_BITCLK, AC_RST# , AC_SDIN[2:0] , AC_SDOUT , AC_SYNC , DPSLPVR , LAN_CLK , PDD[7] , PDDREQ , SPKR , USB[7:0][P,N]

INTERNAL PULL-UP SIGNALS : EE_DIN , EE_DOUT , EE_CS ,

GPIO[17:16] , LAD[3:0]# , LDRQ[0:1] , LAN_RXD[2:0] , PME# , PWRBTN# , TP3 , SATALED# , GNT[4:0]

DESCRIPTION:

ICH6M:Res & Straps

3

ACZ_SDOUT 22

ACZ_SYNC 22

TP3 22

ICH_SPKR 22,33

EEP_DOUT 22

GPO17 23

GPO16 23

RELEASE DATE :

2

LINKALERT#22

SCL_3A22,36

SDA_3A22,36

SM_LINK022,36 SM_LINK122,36

PM_BATLOW#22

CB_SD#22,40

PCI_PME#23,37,39,40

ICH6_1HZ22,43

BACK_OFF#20,22

PM_SUS_STAT#21,22,30

LPC_DRQ#021,22,30

FIR_SEL22,30,31

FWH_WP#22,31

AGP_EXT22 OP_SD#22,34

KBDDT023,32

KBDDT123,32 PCI_INTE#23 PCI_INTF#23 PCI_INTG#23 PCI_INTH#23

PM_CLKRUN#21,22,30,32,37,39,40

INT_IRQ1422,28

R385 10KOhm

R401 2.2KOhm

R386 2.2KOhm

R412 10KOhm

R931 10KOhm

R359 10KOhm

R415 4.7KOhm

R424 8.2KOhm

R308 100KOhm R325 100KOhm R302 10KOhm R304 10KOhm

1 2

10KOhm

3 4

10KOhm

5 6

10KOhm

7 8

10KOhm

RP4D RP4F RP4H RP2B RP2D RP2F RP2G RP2H

1 2

12

RN15A RN15B RN15C RN15D

12

4 5

8.2KOhm

7 5

8.2KOhm

9 5

8.2KOhm

2 5

8.2KOhm

4 5

8.2KOhm

7 5

8.2KOhm

8 5

8.2KOhm

9 5

8.2KOhm

12

/*

12 12 12

DESIGN ENGINEER :SCHEMATIC FILE NAME :

1

+3VS

10 10 10 10 10 10 10 10

+3VS

M.Y.

A

B

C

D

E

IDE_BDD[0:15]27 IDE_BDA[0:2]27 IDE_BDCS0#27

+3VS

IDE_BDCS1#27

R426 0Ohm

1 2

C377

0.1UF

IDE_BINTRQ27

IDE_BDMACK#27

IDE_BIORDY27

IDE_BDIOR#27

IDE_BDIOW#27

IDE_BDMARQ27

IDE_BRST#27

12

+1.8VS

IDE_BDA2 IDE_BDA0 IDE_BDA1

IDE_BDD15 IDE_BDD0 IDE_BDD14 IDE_BDD1

1 2

R844 0Ohm

10KOhm

/*

1 1

2 2

3 3

4 4

R384

+3VS

12

R434 10KOhm

/*

R435 0Ohm

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

+3VS

IDE_BDCS0#

1 2

484746454443424140393837363534

U29

IDE_CS0_b

IDE_DA2 IDE_DA0 IDE_DA1 VDDO_1 IDE_INTRQ IDE_DMACK_b IDE_IORDY VDDI_1 VSS1 IDE_DIOR_b IDE_DIOW_b IDE_DMARQ_b IDE_DD15 IDE_DD00 IDE_DD14 IDE_DD01 GND

IDE_DD13

IDE_DD02

123456789101112131415

12

IDE_BDD2

IDE_BDD13

+3VS

IDE_BDCS1#

VSS4

IDE_CS1_b

IDE_DD12

VDDO_2

IDE_BDD3

IDE_BDD12

R383 0Ohm

3

+3VS

+1.8VS +3VS

VSS3

VDDO_3

Reserved1

Reserved2

IDE_DD03

IDE_DD11

IDE_DD04

VSS2

IDE_BDD4

IDE_BDD11

1 2

D27 RB717F

/*

T358

1

VDDI_3

VDDI_2

IDE_BDD10

STP_PIN38

STP_PIN39

Reserved3

Reserved4

IDE_DD10

IDE_DD05

IDE_BDD5

IDE_BDD9

1 2

12

R431 10KOhm

/*

STP_PIN34

STP_PIN35

STP_PIN36

ODCS

Reserved5

Reserved6

Reserved7

XTALI/CLKI

DD_DISABLE_b

SYS_RESET_b

IDE_DD09

IDE_DD06

IDE_DD08

IDE_DD07

IDE_BDD6

IDE_BDD8

IDE_BDD7

IDE_BRESET#

IDERST#_5

STP_PIN33

33

Reserved8

Reserved9

GNDA2 VDDA2

REXT GNDA1 VDDA1 XTALO

IOINSEL1

IOINPIN

IOINSEL0

IDE_RESET_b

SII3811CNU

16

TXN

RXN RXP

TXP

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

12

SATA_BRIDGE_TXP0 SATA_BRIDGE_TXN0

XO_STP XI_STP

STP_DISABLE#

IOINSEL1 IOINPIN IOINSEL0 IDERST#_5

+1.8VS

IDERST#_5 28

C378

0.1UF

12

C375

1 2

R850 0Ohm

FOR 88SA8040

12

C382

0.1UF

12

C386 3900PF/50V

R849 1KOhm

R845

10KOhm

STP_DISABLE#

R847

10KOhm

/*

L112 120Ohm/100Mhz

1 2

Sil3811 -1K; 88SA8040 -12.1K

+3VS

12

L111 120Ohm/100MHz

/*

21

12

C384 3900PF/50V

1%

ENABLE ATA Sil3811 -10K 88SA8040 -NP

+1.8VS

FOR SIL3811

+3VS +1.8VS

12

C390

0.1UF

SATA_ICH_BRIDGE_RXP0 22 SATA_ICH_BRIDGE_RXN0 22

SATA_BRIDGE_RXN0 22 SATA_BRIDGE_RXP0 22

R416 10MOhm

1 2

X4

12

25Mhz C350 18P

1 2

R1.1#17

+3VS +3VS

12

R396

10KOhm

/*

IOINSEL0 IOINSEL1

12

C358

0.1UF

XO_STP XI_STP

C354 18P

1 2

12

R841

10KOhm

/*

12

C389

0.1UF

12

C372

IOINPIN

0.1UF

12

C357

R413

10KOhm

R400

10KOhm

0.1UF

+3VS

12

/*

12

/*

R433

10KOhm

/*

STP_PIN39

RELEASE DATE :

+3VS

12

ALL FOR 88SA8040, UNINSTALL ALL FOR SIL3811

DESIGN ENGINEER :SCHEMATIC FILE NAME :

D

E

M.Y.

+3VS +3VS +3VS

12

R427

10KOhm

/*

5 5

bom

PROJECT:

A

STP_PIN33

W3V

STP_PIN34

REVISION

2.1

12

R428

10KOhm

/*

DATE: SHEET OF

B

12

R429

10KOhm

/*

STP_PIN35 STP_PIN36

Monday, January 17, 2005

26 63

12

R430

10KOhm

/*

DESCRIPTION:

SATA TO PATA BRIDGE

C

STP_PIN38

R432

10KOhm

/*

12

A

E E

B

C

D

E

IDE_BDD[15:0]26

D D

C C

B B

SATA_ICH_HDD_RXN022

SATA_ICH_HDD_RXP022

IDE_BRST#26

IDE_BDMARQ26 IDE_BDIOW#26

IDE_BDIOR#26

IDE_BIORDY26

IDE_BDMACK#26

IDE_BINTRQ26

IDE_BDA126

IDE_BDA026 IDE_BDCS0#26 IDE_BDASP#28

C826 3900PF/50V /*

C827 3900PF/50V /*

IDE_BDD[15:0]

+3VS +5VS

R857

4.7KOhm

IDE_BRST# IDE_BDD7 IDE_BDD6 IDE_BDD5 IDE_BDD4 IDE_BDD3 IDE_BDD2 IDE_BDD1 IDE_BDD0

IDE_BDMARQ IDE_BDIOW# IDE_BDIOR# IDE_BIORDY IDE_BDMACK# IDE_BINTRQ IDE_BDA1 IDE_BDA0 IDE_BDCS0# IDE_BDASP#

12

SATA_HDD_TXN0

SATA_HDD_TXP0

+3VS

CN32 BTOB_CON_50P

1 2

R860 8.2KOhm

1 2

R1.1#18

HDD CNT

53

54

50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10

8 6 4 2

49

50

47

48

GND3

GND4

45

46

43

44

41

42

39

40

37

38

35

36

33

34

31

32

29

30

27

28

25

26

23

24

21

22

19

20

17

18

15

16

13

14

11

12

9

10

7

8

5

6

3

4

1

2

GND1

GND2

51

52

IDE_BDMARQ IDE_BDD7 IDE_BINTRQ

/*

49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

R856 5.6KOhm R852 10KOhm R855 10KOhm

12

C832 10UF/10V

IDE_BDD8 IDE_BDD9 IDE_BDD10 IDE_BDD11 IDE_BDD12 IDE_BDD13 IDE_BDD14 IDE_BDD15

IDE_BCSEL

IDE_BDIAG IDE_BDA2 IDE_BDCS1#

1 2

R885 10KOhm

1 2 1 2 1 2

12

C824

0.1UF

T371

1

IDE_BDA2 26 IDE_BDCS1# 26

+3VS SATA_DET_#0 22,25

SATA_HDD_RXP0 22 SATA_HDD_RXN0 22

IDE_BCSEL

+3VS

12

1 2

R883 1KOhm

/*

R884 470Ohm

A A

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

27 63

DESCRIPTION:

HDD CON.

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

E

A

B

C

D

E

+5VDOCK+5VS

12

C715

10UF/10V

+12VS

R377 100KOhm

1 2

Q140

3

2N7002

D

1

G

S

2

R2.1

C315

0.47U

+3VS

R1.1#32

R813 1KOhm

/*

1 2

12

R814 470Ohm

R832 100KOhm

1 2

R828 1KOhm

3

1 2

D58 1SS355

12

C717

0.1UF

XIDE_EN_12VS

1

G

R991 100KOhm

D74 1SS355

R2.1

12

D57

2 1

DAP202K

/*

REVISION

2.1

Q144

3

2N7002

D

S

2

1 2

+5VS

1

D

2 3

G

Q124 SI3456DV

12

C720

0.1UF

12

C915

0.47U

CSEL (ASUS) H : Master L : Slave

+3VS

IDE_PDASP#

IDE_BDASP# 27

DATE: SHEET OF

B

C718

1 1

0.1UF

R2.0#16

+3VS

R334

+3VS

R835

4.7KOhm

1 2

R826

5.6KOhm

/*

1 2

10KOhm

1 2

R353 100KOhm

D23 1SS355

BAYDOCK_IN#

2N7002

A

1 2

D

Q147

S

12

IDE_PCSEL

3

1

G

2

W3V

2 2

XIDE_EN#_322

3 3

IDE_PIORDY IDE_PDDREQ

4 4

HDD_LED_EN43

5 5

SATALED#22

bom

PROJECT:

12

C781 10UF/10V

6 5

S

4

+5VDOCK

12

R299 100KOhm

12

C719

0.1UF

R2.1

CSEL (standard) L : Master H : Slave

IDE_PIORDY22

INT_IRQ1422,25

IDE_PIORDY

Monday, January 17, 2005

28 63

12

C787

0.1UF

+3VS

BAY_RST30

R293 10KOhm

C783

0.1UF

XIDE_EN_12VS

3

D

Q146 2N7002

12

Q145 2N7002

12

C785

10UF/10V

1 2

R287 10KOhm

IDERST#_5

BAY_RST#

12

C301 100PF

1 2

1

G

2

S

1

G

3

2

D

S

DESCRIPTION:

C791

0.1UF

1

3

1

G

2

IDE_PIORDY_X

IDE_IRQ14

SWAP BAY

C

U27

A

1

PCI_RST#23,37,39,40

BUF_PLT_RST#6,8,21,22,23,30,31,32

3

D

Q47 2N7002

G

S

2

D

Q193 2N7002

S

3

D

Q192

1

2N7002

G

S

2

R326 0Ohm

R327 0Ohm

U23

A

1

VCC

B

2 3 4

GND

Y

NC7SZ08P5X

1 2

+5VS

5

IDERST#_5S

C914 0.1UF

1 2

/*

B

2 3 4

GND

NC7SZ08P5X

ODD CNT

6162

6364

CN27

1

2

3

4

NP_NC1NP_NC2

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

RELEASE DATE :

D

31

32

33

GND1GND2

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

BTOB_CON_60P

IDE_PDDACK#22

IDE_PDDREQ22

IDE_PDIOR#22

IDE_PDIOW#22

IDE_PDCS3#22

IDE_PDCS1#22

IDE_PDA222

IDE_PDA122 IDE_PDA022

BAY_IN030

FLP_DRATE0

BAY_IN130

T167

IDE_PDD1 IDE_PDD0

IDE_PDIAG

1

FLP_DR0#

FLP_DSKCHG#

IDE_PDASP# BAY_IN0 IDE_PCSEL PIN22_+5V_PH

FLP_MTR0#

FLP_3MODE#

FLP_INDEX#

FLP_DIR#

BAY_IN1

+5VS

5

VCC

Y

+5VDOCK

R812

4.7KOhm

/*

1 2

PIN22_+5V_PH

+5VDOCK+5VDOCK

For EMI

1 2

C803 0.1UF

FLP_STEP#

BAYDOCK_IN#

FLP_TRK0#

SATA_SWAP_TXN2

FLP_WDATA#

SATA_SWAP_TXP2

FLP_WP# FLP_RDATA#

FLP_WGATE#

FLP_HDSEL#

IDE_PDD15 IDE_PDD2 IDE_PDD14 IDE_PDD3 IDE_PDD13 IDE_PDD4 IDE_PDD12 IDE_PDD5 IDE_PDD11 IDE_PDD6 IDE_PDD10 IDE_PDD7 IDE_PDD9 IDERST#_5S IDE_PDD8 CD_GND_A CD_GND_A CD_L_A CD_R_A

IDERST#_5

IDE_PDD[15:0]22

C801 3900PF/50V

CD_L_A

CD_R_A

BAYDOCK_IN# 32

CD_GND_A 33 CD_L_A 33 CD_R_A 33

IDERST#_5 26

+3VS

12

C282

0.1UF

12

C800 3900PF/50V

1 2

12

/*

10KOhm

7 8

5 6

3 4

1 2

RN14B

RN14A

RN14D

RN14C

12

C284

0.1UF

12

R288 0Ohm

R809 10KOhm

R808 10KOhm

DESIGN ENGINEER :SCHEMATIC FILE NAME :

E

IDE_PDD[15:0]

IDERST#_5S

BAY_IN0 BAY_IN1 BAYDOCK_IN#

12

C289

0.1UF

SATA_DET_#2 22,25

SATA_ICH_RXN2 22 SATA_ICH_RXP2 22

SATA_SWAP_RXN2 22 SATA_SWAP_RXP2 22

CD_GND_A

M.Y.

A

1 1

B

C

D

E

C903 10UF/10V

/*

C904 10UF/10V

/*

R2.0#4

12

R981 10KOhm

/*

R191 0Ohm

R193 0Ohm

2 2

USB_PN023 USB_PP023

Co-Layout

R530 0Ohm

R531 0Ohm

3 3

USB_PN123 USB_PP123

USB_PN223 USB_PP223

4 4

R528 0Ohm

R529 0Ohm

12

/*

12

/*

L49 180Ohm/330mA

1 4

2 3

12

/*

12

/*

14

23

L77 180Ohm/330mA

14

23

L76 180Ohm/330mA

12

/*

12

/*

USBP0-_3 USBP0+_3

USBP1-_3 USBP1+_3

USBP2-_3 USBP2+_3

USB *1 port

+5V_USB0 +5VUSB_0

CN11

5 1 2 3 4 6

USB_CON_1X4P

DATA0DATA0+

SIDE_G1

SIDE_G2

7

SIDE_G3

VCC

GND

8

SIDE_G4

USB *2 ports

+5V_USB12

10

CN17

GND4

8

GND2

7

0P+

6

0P-

5

VCC2

4

GND1

3

1P+

2

1P-

1

VCC1

GND3

USB_CON_2X4P

9

For EMI

12

C3

0.1UF

For EMI

80Ohm/100Mhz

12

C203

0.1UF

80Ohm/100Mhz

12

C2

0.1UF

L50

21

12

+

CE28 150UF/6.3V

L1

21

12

+

CE21 150UF/6.3V

FLG#: OD

+5VUSB_12

U51

EN#/ENFLG

6

OUT_3

7

OUT_2

8

GND

OUT_1

G528P1U

(Iset = 1.4A)

R982 10KOhm

/*

U1

EN#/ENFLG

6

OUT_3

7

OUT_2

8

GND

OUT_1

G528P1U

(Iset = 1.4A)

IN_2 IN_1

12

IN_2 IN_1

12

C905

0.01UF/16V

/*

528: EN#

45 3 2 1

12

C906

0.01UF/16V

/*

45 3 2 1

12

C204 1UF/10V

C4 1UF/10V

USB_OC#0 23,25

+5V

12

USB_OC#12 23,25

+5V

12

5 5

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

29 63

DESCRIPTION:

USB PORTS

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

E

A

1 1

B

C

+3VS

D

E

SYSOPT0=0, SYSOPT1=0 --> 0x002e SYSOPT0=1, SYSOPT1=0 --> 0x004e SYSOPT0=0, SYSOPT1=1 --> 0x162e SYSOPT0=1, SYSOPT1=1 --> 0x164e

2 2

+3VS

R793 10KOhm /* R806 10KOhm /*

SYSOPT0

12 12

SYSOPT1

R792 10KOhm R807 10KOhm

12 12

+3VS

12

C793 10UF/10V

1 2 3 4 5 6 7 8

12

C790

0.1UF

10KOhm 10KOhm 10KOhm 10KOhm

12

RN30A RN30B RN30C RN30D

C792

0.1UF

12

C773

0.1UF

DSRA# CTSA# RIA# DCDA#

12

C782

0.1UF

Super I/O

DCDA#

RIA#

+3VS

T162

LPC_AD021,22,31,32,43

3 3

LPC_AD121,22,31,32,43 LPC_AD221,22,31,32,43

LPC_AD321,22,31,32,43

LPC_FRAME#21,22,31,32,43

PM_CLKRUN#21,22,25,32,37,39,40

4 4

CLK_SIOPCI CLK_SIOPCI

12

C788 5PF

/*

INT_SERIRQ21,22,25,32,40 CLK_SIOPCI12

BUF_PLT_RST#6,8,21,22,23,28,31,32

CLK_SIO1412

LPC_DRQ#021,22,25

PM_SUS_STAT#21,22,25

R810 0Ohm /*

+3VS

12

U54

1

DLAD1

2

LAD1

3

DLAD2

4

LAD2

5

VCC1

6

DLAD3

7

LAD3

8

VSS1

9

DLPC_CLK_33

10

LPC_CLK_33

11

DLDRQ1#

12

LDRQ1#

13

DLFRAME#

14

LFRAME#

15

nDCLKRUN

16

nCLKRUN

+3VS

R811 10KOhm

1

646362616059585756555453525150

nRI1

LAD0

VSS6

GP37

VCC5

DLAD0

VCC2

DSER_IRQ

171819202122232425262728293031

nCTS1

nDCD1

nRTS1/SYSOPT0

nDTR1/SYSOPT1

SER_IRQ

VSS2

PCI_CLK

PCI_RESET#

SIO_14M

LDRQ0#

LPCPD#

DSIO_14M

12

SYSOPT1

CTSA#

SYSOPT0

DSRA#

FIR_SEL 22,25,31 IR_RXD 31

49

TXD1

RXD1

IRTX2

IRRX2

nDSR1

IRMODE/IRRX3

GP14/IRQIN2

GP10

GP11

VSS3

GP12/IO_SMI#

VCC3

GP13/IRQIN1

32

1

T159

VTR

nIO_PME

GP36 VSS5 GP35 GP34

VCC4

GP33 GP32 GP31 GP30 VSS4 GP17 GP16 GP15

LPC47N207

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

+3VS

1

1 1 1 1

802_EN# BAY_RST

1

SW_RST#

T327

T158 T155 T160 T157

T328

RN29A RN29B RN29C RN29D

IR_TXD 31

R794 0Ohm

1 2

R795 0Ohm /*

1 2

OVER_CLK2 12 OVER_CLK1 12

+3VS

802_EN# 39 DJKEY_EN 44 BAY_RST 28

SW_RST# 23

BAY_IN1 28 BAY_IN0 28

10KOhm

802_EN#

12

SW_RST#

10KOhm

34

10KOhm

56

BAY_RST

10KOhm

78

+3VS

+3V

5 5

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

30 63

DESCRIPTION:

SUPER I/O (LPC47N207)

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

E

A

1 1

B

C

+3VS

12

C691

0.1UF

12

C697 10UF/10V

12

C701

0.1UF

/*

D

E

U49

T104 T286

T103

24

INIT#

2

RST#

31

CLK

30

FGPI4

3

FGPI3

4

FGPI2

5

FGPI1

6

FGPI0

9

1

ID3

10

1

ID2

11

ID1

12

1

ID0

26

GND2

28

GNDA

SST 49LF004A-33-4C-N

PLCC32 Socket Part Number : 12-043000321

IR_LEDA

12

C799 470P

FWH

IR_TXD30

IR_RXD30

FIR_SEL22,25,30

FWH_INIT#22

CLK_FWHPCI12

2 2

3 3

4 4

BUF_PLT_RST#6,8,21,22,23,28,30,32

C692 10PF

/*

R731 10KOhm

DIS_FWH43

W=40mil

12

C789

4.7U

12

+3VS

R722 100Ohm

12

1 2

10KOhm

3 4

10KOhm

5 6

10KOhm

7 8

10KOhm

boot device ID[3:0 ] = 000 0 Int. PD

1 2

R815 2.7Ohm

12

C784

0.1UF

RN25A RN25B RN25C RN25D

1 2

FWH_FGPI4 FWH_FGPI3 FWH_FGPI2 FWH_FGPI1 FWH_FGPI0

3.3VS: IR_LEAD = 750mA

1

VPP

25

VCC1

32

VCC2

27

VCCA

8

TBL#

7

WP#

23

FWH4

17

FWH3

15

FWH2

14

FWH1

13

FWH0

29

IC

2216

RSVD5GND1

21

RSVD4

20

RSVD3

19

RSVD2

18

RSVD1

IR_TXD

IR_RXD

Isupply = 5mA

+3VSUS+3VS

R707 10KOhm

1 2

R733 10KOhm

(PD: FWH mode)

1 2

U55

9

TXD

8

RXD

3

FIR_SEL

6

NC

4

MD0

5

MD1

11

SHLD

1 2

GND

7

R708 10KOhm

/*

10

LEDA

AGND

2

VCC

1

FWH_WP# 22,25 LPC_FRAME# 21,22,30,32,43

LPC_AD3 21,22,30,32,43 LPC_AD2 21,22,30,32,43 LPC_AD1 21,22,30,32,43 LPC_AD0 21,22,30,32,43

HSDL-3600

+3VS

12

C786

0.47U

5 5

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

31 63

DESCRIPTION:

C

FIR & FWH

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

E

A

B

C

D

E

+3V

1 2

+5V

12

2.1

CPUFAN_SPD_A46

MSK_INSTKEY#44

C150

0.1UF

SWDJ_EN#44

PM_CLKRUN#21,22,25,30,37,39,40

DJ_LED_EN43,44

PANLOCK_#44

MARATHON_#44 WIRELESS_#44 INTERNET_#44

INTCLK_5S44

INTDATA_5S44

R148 10KOhm /*

10KOhm 10KOhm 10KOhm 10KOhm

EC should set OP_SD low in S3, keep from leakage.

KBCRSM47

BT_#44

MOUSECLK_5S MOUSEDATA_5S KBDDATA_5S KBDCLK_5S

DATE: SHEET OF

B

P2.1 Low : Power Button Override disable

1 1

2 2

3 3

4 4

R2.0#5

+3VALWAYS

5 5

bom

Input Event only at P54, P55, P60 - P67

P50, P43, P54, P55 are wake-up event inputs when KBC in standby mode

1 2

WATCHDOG46

BAT_LLOW#_OC54

WIRELESS_LED#43

BAT_LOW#_KBC43

BAYDOCK_IN#28

BAT1_IN#_OC56

FAN_DA46

ADJ_BL20

BAT2_IN#_OC56

ACIN_OC56

10KOhm

12

RN11A

10KOhm

34

RN11B

10KOhm

56

RN11C

10KOhm

78

RN11D

BAT_SEL

SMCLK_BAT254,58 SMCLK_BAT154,58

SMDATA_BAT254,58 SMDATA_BAT154,58

SMCLK_BAT2 SMCLK_BAT1 SMC_BAT_KBC SMDATA_BAT2 SMDATA_BAT1 SMD_BAT_KBC

PROJECT:

R107 470KOhm

SMDATA_BAT1 SMDATA_BAT2 SMCLK_BAT1 SMCLK_BAT2

A

+3V

10

10KOhm

3 5

2 5

RP1B

RP1C

1 2 3 4 5 6 7 8 9

W3V

10

10KOhm

4 5

1 5

RP1A

RP1D

U10

S IA0 IA1 YA IB0 IB1 YB GND YC

PI5C3257

10

10KOhm

6 5

VCC

E# ID0 ID1

YD IC0 IC1

+5VS

10

10KOhm

8 5

9 5

7 5

RP1E

RP1F

RP1G

RP1H

16 15 14 13 12 11 10

REVISION

KBSCI_3Q

KBC_GA20

RN10A

12

KBCPURST_3Q

RN10B

34

INTCLK_5S

RN10C

56

INTDATA_5S

RN10D

78

INT_SERIRQ21,22,25,30,40 CLK_KBCPCI12

BUF_PLT_RST#6,8,21,22,23,28,30,31

LPC_FRAME#21,22,30,31,43

LPC_AD321,22,30,31,43 LPC_AD221,22,30,31,43 LPC_AD121,22,30,31,43 LPC_AD021,22,30,31,43

1 2

R152 1MOhm

KBCPURST_3Q KBC_GA20 KBSCI_3Q

BAT_LLOW#_KBC

KBDCLK_5S MOUSECLK_5S INTCLK_5S KBDDATA_5S MOUSEDATA_5S INTDATA_5S

SMC_BAT_KBC SMD_BAT_KBC

BAT_SEL

RN9A

10KOhm

1 2

3 4

+5VS

RN9B

RN9C

10KOhm

7 8

5 6

Monday, January 17, 2005

32 63

63 64 65 66 67 68 69 70

35 36 37 38

23 22 21 20 19 18

17 16 15 14 13 12 11 10

74 75 76 77 78 79 80

1

4 5 6 7 8 9

2 3

RN9D

C84 5PF

1 2

/*

U8

P87/SERIRQ P86/LCLK P85/LRESET# P84/LFRAME# P83/LAD3 P82/LAD2 P81/LAD1 P80/LAD0

P23 P22 P21 P20

P42/INT0 P43/INT1* P44/RXD P45/TXD P46/SCLK1 P47/SRDY1#/CLKRUN#

P50/INT5* P51/INT20 P52/INT30/1-WIRE1 P53/INT40/1-WIRE2 P54/CNTR0* P55/CNTR1* P56/DA1/PWM01 P57/DA2/PWM11

P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0

P75/INT41 P74/INT31 P73/INT21 P72 P71 P70

P77/SCL P76/SDA

M38857

DESCRIPTION:

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

P54,P55,P43,P50 are wake-up event inputs when KBC in standby mode

80mA

KBC_GA20

KBCPURST_3Q

C

1 5

10KOhm

RP7A

2 5

10KOhm

RP7B

3 5

10KOhm

RP7C

4 5

10KOhm

RP7D

6 5

10KOhm

RP7E

7 5

10KOhm

RP7F

8 5

10KOhm

RP7G

9 5

10KOhm

RP7H

P17/KSO15 P16/KOS14 P15/KSO13 P14/KSO12 P13/KSO11 P12/KSO10

P11/KSO9 P10/KSO8 P07/KSO7 P06/KSO6 P05/KSO5 P04/KSO4 P03/KSO3 P02/KSO2 P01/KSO1 P00/KSO0

P37/KSI8 P36/KSI7 P35/KSI6 P34/KSI5 P33/KSI4

P32/KSI3 P31/PWM10/KSI2 P30/PWM00/KSI0

P40/XCOUT

P41/XCIN

RESET#

+5VS +3VS

6 1

Q28A UM6K1N

KBC (M38857)

VCC

VREF

XOUT

CNVSS

VSS

AVSS

2

10 10 10 10 10 10 10 10

P27 P26 P25 P24

XIN

3 4

+3V

71

72

31 32 33 34

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

55 56 57 58 59 60 61 62

28 29

27 26

25 24

30 73

Q28B UM6K1N

+3V

1

KBC_EXTSMI

5

1 2

C88 0.1UF

1 2

C97 0.1UF

T40

NUM_LED# CAP_LED#

KSO15 KSO14 KSO13 KSO12 KSO11 KSO10 KSO9 KSO8 KSO7 KSO6 KSO5 KSO4 KSO3 KSO2 KSO1 KSO0

KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0

X1_KBC

X2_KBC

R142 10KOhm

1 2

10KOhm

1 2

R156 10KOhm

+3V

RN2A

RN2B

10KOhm

5 6

3 4

RN2D

RN2C

10KOhm

7 8

NUM_LED# 45 CAP_LED# 45 SET_PCIRSTNS# 23BAT_LEARN55

KSO3 44

KSI6 44 KSI5 44 KSI4 44 KSI3 44

BT_LED# 38,43,45

PCI_RSTNS# 23,37

HA20GATE 22

KBDCPURST 22

RELEASE DATE :

R1.1#29R1.1#29

D

KEYBOARD CON.

CN9

29

GND1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

30

GND2

ZIF_FPC_28P_KB

KBDDT1 KBDDT0 Matrix

1 1 US 1 0 UK 0 1 JP

+3VS

10K

R

B1

KBSCI_3Q

X1_KBC

X2_KBC

KBC_EXTSMI

12

2

R162 10KOhm

E

C

Q33 DTC114TKA

12

R97 1MOhm

/*

+3VSUS

1

G

3

2

12

D

S

3

1 2

R161 10KOhm

Q35 2N7002

DESIGN ENGINEER :SCHEMATIC FILE NAME :

X1 8MHZ

KSI1

KSO7

KSI7

KSO0

KSI6

KSO9

KSI5

KSO3

KSI4

KSO1

KSI2

KSI3 KSO5 KSO13

KSI0 KSO2 KSO4 KSO8 KSO6 KSO11 KSO10 KSO12 KSO14 KSO15

KBDDT0 KBDDT1

KBDSCI_3 22,25

R1.1#17

1 2

C93 5PF

1 2

C78 5PF

EXTSMI#_3A 22

M.Y.

E

KBDDT0 23,25 KBDDT1 23,25

5

D D

EPAD34 SPDIF34

C C

R2.1

AUD_GPIO034

ACZ_SDOUT_AUD22

ACZ_BCLK_AUD22

ACZ_SDIN022

ACZ_SYNC_AUD22

ACZ_RST#_AUD22,34

B B

R506 1KOhm

SPKRCB40

ICH_SPKR22,25

1 2

C487 0.1UF

1 2

C480 0.1UF

1 2

R503 1KOhm

1 2

PCBEEP34

12

R502 10KOhm

+3VS

12

2 1

R508 10KOhm

4

Reference resistor for Jack detection: ALC880: 20K_1% ALC861: 5.1K_1%

C883

C863

10UF/10V

0.1UF

1 2

/*

T388

1 2

R918 33Ohm

C879 10PF

/*

R1.1#22

3

C474 1UF/10V

D36 DAN202K

12

R500 10KOhm

1 2

R937 20KOhm/*1%

AGND_A AGND_A

C874

0.1UF

1

12

U61

1 2 3 4 5 6 7 8

9 10 11 12

48

DVDD1 GPIO0 GPIO1 DVSS1 SDATA_OUT BITCLK DVSS2 SDATA_IN DVDD2 SYNC RESET# PCBEEP

13

SPDIFO

SPDIFI/EPAD

SURRBACK_OUT_R

LINE2_L

LINE2_R

Sense_A

1415161718

LFE_OUT

SURRBACK_OUT_L

MIC2_L

MIC2_R

AVSS2

CEN_OUT

JDREF/NC

SURR_OUT_R

FRONT_OUT_R

FRONT_OUT_L

MIC1_VREFO_R

LINE2_VREFO

MIC2_VREFO

LINE1_VREFO_L

MIC1_VREFO_L

CD_R

MIC1_L

CD_L

CD_GND

2021222324

19

SURR_OUT_L

MIC1_R

3

3738394041424344454647

AVDD2

LINE1_VREFO_R

Sense_B

DCVOL

VREF AVSS1 AVDD1

LINE1_L

LINE1_R

ALC861-VS

+5VA

AGND_A

12

C486 10UF/10V

36 35 34 33 32 31 30 29 28 27 26 25

AGND_A

+5V

LINEOUT_R

LINEOUT_L

C886 1UF/10V /*

C887 1UF/10V /*

Pin35/36: default OP ON

+5VA

C888 10UF/10V

C865 1UF/10V

C860 1UF/10V

12

C475 10UF/10V

12

C838 1UF/10V

12

C842 1UF/10V

12

C841 1UF/10V

12

C840 1UF/10V

LINE_OUT_R

LINE_OUT_L

12

>30 mil or shape

L68

21

80Ohm/100Mhz

DIGITAL

12

C854

0.1UF

1 2

/*

12

R891 47KOhm

AGND_A

12

R888 47KOhm

2

PM_SUSB#22,34,40,43,47,54,57

+5V_AUD

12

R890 47KOhm

R889 47KOhm

C471 10UF/10V

12

C849 1UF/10V

1 2

C469

0.1UF

1

G913C: Vo=Vref(=>1.25V)*[1 +(R_H /R_L )]

U33

1

SHDN# GND IN OUT

G913C

1 2

R511 0Ohm

SET

2 3 4

OUTR_A 34

OUTL_A 34

VREFOUT 34,35

MIC_A 35

CD_R_A 28

CD_GND_A 28

5

12

C454 2200P

12

R487 100KOhm

0.1%

R477

34.8KOhm

1%

1 2

34K/1% for MAX8863

34.8K/1% for G913C

12

C457 10UF/10V

R2.1

T394

+5VA

1

C461

C462

0.1UF

1 2

AGND_A

12

A A

bom

PROJECT:

5

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

4

33 63

DESCRIPTION:

Azalia AUDIO (ALC861-VS)

3

C839 1UF/10V

1 2

R894 47KOhm

12

R887 47KOhm

AGND_A

RELEASE DATE :

CD_L_A 28

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

1

A

+5VAMP

Q159

1 1

OPTIC_HP

1

G

3

2

JACK_IN#

12

C825

0.1UF

AGND_A

2 2

OPTIC_VCC_EN#

D

S

Q160 2N7002

SI2301DS

2 3

2

12

R865 100KOhm

D

S

G

1

HEADPHONE/SPDIF

OPTIC_HP# JACK_IN# STATE

0 0 LINE_OUT : OPTIC VCC OFF 1 0 SPDIF_OUT : OPTIC VCC ON 1 1 NC : OPTIC VCC OFF

PHONE_JACK_8P_SPDIF

CN16

3 3

11 12

R501 0Ohm

4 4

5 4 2 3 1

10mA

8 7

9

6

10

12

C866

12

C488

100PF

/*

GND_AUDJACK

L65 1KOhm/100MHz

EARL__J

L75 1KOhm/100MHz

EARR_J

L67 1KOhm/100MHz L74 1KOhm/100MHz

OPTIC_VCC_J

12

C876

C468

100PF

/*

SPDIF33

OPTIC_VCC

3

12

C880

R935

0.1UF

100KOhm

21 21

L70 1KOhm/100MHz L73 1KOhm/100MHz

12

C869

C478

100PF

/*

L115 120Ohm/100Mhz

R492 10KOhm

For EMI

+5VAMP

12

21 21

21

U62

A

1

B

2 3 4

GND

NC7SZ08M5

12

R504 10KOhm

JACK_IN#

EARL__R EARR_R

OPTIC_HP

AGND_A

B

5

VCC

SPDIF_O

Y

DIGITAL

R971 33Ohm R967 33Ohm

R505 1KOhm

1 2

OPTIC_VCC_D

AGND_A

+5VS

1 2 1 2

R496 1KOhm

1 2

Q188 2SC5376F

/*

D35 RB751V_40

12

C476

0.1UF

OUTL_A33

2SC5376F

2 E

C 3

OPTIC_VCC

SPDIF_O

Q187

/*

1 2

R510 68KOhm

R507 33Ohm R497 33Ohm

B

1

AGND_A

2 E

C

3

12 12

1 2

B

1

R966 1KOhm

1 2

R965 1KOhm

C

+5VAMP

12

R499 10KOhm

R498 0Ohm

/*

1 2

AGND_A

OUTL_A_AMP1

R509 30KOhm

1 2

AGND_A

EARL_C EARL

C878 47UF/6.3V

EARR_C

C858 47UF/6.3V

MUTE

/*

R1.1#23

D

AUDIO AMP

GND4

VDD

GND3

D60 DAP202K

Q197 2N7002

/*

AGND_A

+5VAMP

24 23 22 21 20 19 18 17 16

SE/BTL#

15 14 13

AGND_A

3

MUTE

3

D

1

G

S

2

GAIN0 GAIN1 SE/BTL# AV (V/V) 0 0 0 -2 0 1 0 -6 1 0 0 -12 1 1 0 -24

GAIN1

GAIN0

OUTL_A_AMP

12

C485 1UF/10V

C482

C483

0.47U

1 2

AGND_A AGND_A

X X 1 -1

10 11 12

C484

0.47U

1 2

AGND_A

1 2 3 4 5 6 7 8 9

U34

GND1 GAIN0 GAIN1 LOUT+ LLINEIN LHPIN PVDD1 RIN LOUTLIN BYPASS GND2

TPA0212

RLINEIN

SHUTDOWN#

ROUT+

RHPIN

PVDD2

HP/LINE#

ROUT-

SE/BTL#

PC-BEEP

R2.1

PM_SUSB#22,33,40,43,47,54,57

AUD_GPIO033

12

+

EARR

12

+

ACZ_RST#_AUD22,33

GND_AUDJACK

12

R1012 0Ohm

12

R1013 0Ohm /*

OP_SD#22,25

1 2

R877 100KOhm

EPAD33

21

L116 120Ohm/100Mhz

1 2

R2.0#17

1 2

GND_AUDJACK

R1.1#26

AGND_A

R992 0Ohm

21

L113 120Ohm/100Mhz

1 2

R960 0Ohm

1 2

R881 0Ohm

1 2

R493 0Ohm

For EMI

+5VAMP +5VS

12

OUTR_A_AMP1

R1.1#22

12

C452

C481

0.1UF

DEPOP#

SE/BTL# HP_IN

12

C418 1UF/10V

12

C464

1UF/10V

AGND_A

OUTR_A_AMP SPKR+SPKL+

SPKR-SPKL-

R485 10KOhm

C455 1UF/10V

/*

+3V

R868 100KOhm

/*

1 2

12

C448 10UF/10V

AGND_A

R2.0#13

OP_SD#

1 2

C451 1UF/10V

1 2

12

D59 1SS355

1 2

R879 1.5MOhm

+5VAMP

PCBEEP 33

R2.1

+3VALWAYS +12V

12

R446 100KOhm

3

D

Q58

1

2N7002

G

S

2

R445

4.7MOhm

1 2

3

D

Q57

1

2N7002

G

S

2

E

12

C453

0.1UF

1 2

R471 68KOhm

R481 30KOhm

1 2

3

D

Q60 2N7002

12

C830 1UF/10V

21

L57 80Ohm/100Mhz

OUTR_A 33

1

G

2

S

3

D

Q59 2N7002

1

G

S

2

AGND_A

SPKR+

2

S

G

1

Q163 2N7002

D

3

EARR SPKL+

2

S

G

1

Q162 2N7002

D

3

EARL

JACK_IN#

Ext MIC CON

CN14

7 8 9

10

PHONE_5P_EXT_MIC

5 5

GND_AUDJACK

R2.0#17

bom

PROJECT:

R

L

AUDIO JACK

A

5 4 3 6 2 1

W3V

INTMIC_J MIC_J

C463 100PF

1 2

/*

For EMI

L60 1KOhm/100MHz /*

For EMI

L59 1KOhm/100MHz L58 1KOhm/100MHz

C424

C449

100PF

1 2

/*

REVISION

2.1

21

21 21

DATE: SHEET OF

B

VREFOUT 33,35

INTMIC

Monday, January 17, 2005

34 63

MIC_JACK 35

For EMI

SPKL-

L61 120Ohm

SPKL+

L63 120Ohm

SPKR-

L64 120Ohm

SPKR+

L62 120Ohm

AGND_A

DESCRIPTION:

21 21 21 21

1 2

150PF

3 4

150PF

5 6

150PF

7 8

150PF

/*

AUDIO AMP / JACKS

C

Int Speaker CON

CP3A CP3B CP3C CP3D

CN15

6

NC2

4

3

2

1

5

NC1

WtoB_CON_4P_SPEAKER

SPEAKER 0.5W

RELEASE DATE :

R1.1#24

D

INTMIC

AGND_A

21

L3 1KOhm/100MHz

21

L2 1KOhm/100MHz

For EMI

Int MIC CON

CN1

1

2

C5

C6

100PF

1 2

/*

DESIGN ENGINEER :SCHEMATIC FILE NAME :

3

12SIDE1

4

SIDE2

fpc_con_2p_INT_MIC

Alice Shih

E

A

E E

B

C

D

E

VREFOUT

D D

MIC_JACK

12

C465 220PF /*

1 2

R494 75KOhm /*

1 2

C466

0.01UF

/*

AGND_A

4490_POS 4490_NEG

R495

2.2KOhm

/*

1 2

C467 1UF/10V

1 2

/*

52

V+

1

+

3

V-

U32 MAX4490AXK

/*

AGND_A

1 2

R488 56KOhm /*

12

C459 220PF /*

+5VMIC

MIC_A

4

MIC AMP Option

C C

1 2

C843 39P

VREFOUT33,34

R2.1

+5VMIC

12

R958 1KOhm

/*

R959 1KOhm

/*

B B

MIC_JACK34

R486

2.2KOhm

1 2

AGND_A

12

C857 10UF/10V

R898 270KOhm

12

C852 1UF/10V

AGND_A

1 2

C456 0.1uF/10V

AGND_A

12

R896 10KOhm

12

C844 1UF/10V

AGND_A

R893 10KOhm

12

R886 100KOhm

1 2

R491 100KOhm

12

4490_POS 4490_NEG

U59

A+

3

8

VCC

+

1

A-

AO

2

-

B+

5

+

BO

7

B-

4

6

-

GND

NJM2100M

12

R892 270KOhm

1 2

C835 39P

+5VMIC

R478 0Ohm

AGND_A

L114

12

C833

0.1UF

AGND_A

MIC_A 33

120Ohm/100Mhz

MIC_A

12

/*

+5VA

21

AGND_A

A A

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

35 63

R2.1

DESCRIPTION:

C

MIC AMP

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

E

A

E E

SM_LINK022,25

ICH6-M

SM_LINK122,25

D D

SCL_3A22,25 SCL_3S 6,12,13,14,19,21

ICH6-M

B

Connect SMLINK and SMBUS for SMBus 2.0 compliance.

+5VS

61

Q51A UM6K1N

2

/*

34

Q51B UM6K1N

5

/*

6 1

+5VS

Q52A UM6K1N

C

+3VS+3VS

12

R381

R380

4.7KOhm

2

5

3 4

Q52B UM6K1N

D

System Thermal Sensor ATI Thermal Sen so r Clock Genera to r DDR2 SO-DIMM

SDA_3S 6,12,13,14,19,21SDA_3A22,25

TPM

E

+3VALWAYS

+3VSUS

C C

B B

A A

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

+5VALWAYS

+5VSUS

+1.5VSUS

+3V

+5V +12V +3VS +5VS

+12VS

+VCORE

+VCCP

+1.2VSP

+2.5VS +1.8VS +0.9VS +1.5VS

+VCC_RTC

+1.8V

+VCC_GMCH_CORE

+VCCCB

+VPPCB

VTT_REF

A/D_DOCK_IN

+ATI_VCORE

DESCRIPTION:

36 63

+3VALWAYS 21,22,32,34,43,44,45,47,48,50,51,57 +3VSUS 20,22,24,25,31,32,37,45,47,53,57 +5VALWAYS 48,51,53 +5VSUS 24,57 +1.5VSUS 24,53 +3V 20,23,30,32,34,37,38,39,40,41,42,43,44,47,48,53,57 +5V 13,21,29,32,33,41,43,44,45,48,52,56,57 +12V 34,42,57 +3VS 6,10,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,30,31,32,33,37,38,39,40,43,45,47,48,49,52,53,54,57 +5VS 21,24,27,28,32,34,37,39,43,45,46,48,57 +12VS 20,21,28,44,57 +VCORE 5,6,49 +VCCP 4,5,6,7,10,12,22,24,48,53 +1.2VSP 18,52 +2.5VS 6,8,10,11,18,20,21,24,48,51,52 +1.8VS 4,16,17,18,26,48,52,53,57 +0.9VS 15,53 +1.5VS 4,8,10,18,23,24,48,51 +VCC_RTC 22,24 +1.8V 8,10,11,13,14,40,51,53 +VCC_GMCH_CORE 8,10,11,53 +VCCCB 40,41 +VPPCB 41 VTT_REF 8,13,14,15 A/D_DOCK_IN 46,55,56 +ATI_VCORE 18,52

C

SMBUS

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

E

A

+5VS

1

Q18

G

2N7002

3

+3VS

2

S

R63 0Ohm /*

PCI_AD16

LAN_REQ#

PCI_AD18 PCI_AD17 PCI_AD16

PCI_AD15 PCI_AD14

PCI_AD13 PCI_AD12

PCI_AD11 PCI_AD10

PCI_AD9 PCI_AD8

PCI_AD7 PCI_AD6

PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

LAN_EECLK LAN_EEDATA

1 1

2 2

3 3

PCI_REQ#023,25

CLK_LANPCI12

PCI_PERR#23,25,39,40 PCI_SERR#23,25,39,40

PCI_GNT#023

PCI_C/BE#223,39,40 PCI_C/BE#123,39,40

PCI_AD[31:0]23,39,40

+1.5V_LAN

PCI_C/BE#023,39,40

LAN_REQ#

D

12

R652 33Ohm

1 2

12

C561 10P

/*

U44

103

AD15

104

VDD0

105

AD14

106

AD13

107

VDDO_PCI0

108

AD12

109

AD11

110

AD10

111

M66EN

112

AD9

113

CBE_[0]n

114

AD8

115

AD7

116

VDDO_PCI1

117

AD6

118

AD5

119

AD4

120

AD3

121

AD2

122

AD1

123

AD0

124

VDD1

125

NC0

126

VPD_CLK

127

VPD_DATA

128

SPI_DI

129

GND

+3VS

LAN_IDSEL

+1.5V_LAN

100

101

102

AD17

AD16

CBE[1]n

CBE_[2]n

B

R639 2.7KOhm

1 2

R653 27Ohm

1 2

R655 33Ohm

1 2

93949596979899

91

92

90

AD18

GNTn

VDD9

REQn

SERRn

ZP_REF

ZN_REF

VDDO_PCI4

VDDO_PCI5

PERRn

VDD10

CLK_RUNn

ZP_REF ZN_REF Y8K_REQ64#

CLK

IDSEL

STOPn

DEVSELn

Y8K_REQ64# ZN_REF

ZP_REF

IRDYn

TRDYn

FRAMEn

VDDO_PCI6

12

R654 0Ohm /*

PAR

AD22

AD21

AD20

AD19

VDD11

VDDO_PCI7

C

+3VS

+3VSUS

12

C658

C570

10UF/10V

0.1UF

+3VS

PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23

PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27

65666768697071727374757677787980818283848586878889

AD27

AD26

AD25

AD24

AD23

CBE_[3]n

VDDO_PCI8

VDDO_PCI2

VDDO_PCI3

AVDDL0

AVDDL1

HSDACN HSDACP

AVDDL2

AVDDL3

AD28 AD29

VDD2

AD30 AD31

PMEn

RSTn VIOB

INTAn

TSTPT

MDIN[3] MDIP[3]

MDIN[2] MDIP[2]

AVDDH CTRL25

MDIN[1] MDIP[1]

12

C588

0.1UF

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

12

C572

C634

0.1UF

1000P

1 2

PM_CLKRUN# 21,22,25,30,32,39,40 PCI_DEVSEL# 23,25,39,40

PCI_STOP# 23,25,39,40 PCI_IRDY# 23,25,39,40 PCI_TRDY# 23,25,39,40

PCI_FRAME# 23,25,39,40 PCI_PAR 23,39,40

PCI_C/BE#3 23,39,40

PCI_AD28 PCI_AD29

PCI_AD30 PCI_AD31

PCI_RSTLAN#

L_TRDM3 L_TRDP3

L_TRDM2 L_TRDP2

+3V_LAN_ANALOG

2.5V_CTL L_RDN

L_RDP

+3VSUS

+1.5V_LAN

+3VS

+2.5V_LAN

C568 1000P

+3V

PCI_PME# 23,25,39,40

PCI_INTC# 23,25,39,40

L_TRDM3 38 L_TRDP3 38

L_TRDM2 38 L_TRDP2 38

L_RDN 38 L_RDP 38 PCI_RSTNS# 23,32

L31 120Ohm/100MHz

+3V

L30 120Ohm/100Mhz

21

L40 120Ohm/100MHz

/*

21

L41 120Ohm/100Mhz

/*

+3VS

12

D

21

C115

0.1UF

+3V_LAN_ANALOG

+3V_LAN_DIGITAL

12

C173 10UF/10V

12

C90 10UF/10V

1.5V_CTL

12

R163

4.7KOhm

12

C168

0.1UF

PCI_RSTLAN#

12

E12

3

2.5V_CTL

R116

4.7KOhm

C92

0.1UF

E

place PNP to chip ACAP 2.5V_CTL pin trace is 25MIL

25mil

B

Q26 HM772

C

E12

3

12

C98

C651

10UF/10V

0.1UF

place PNP to chip ACAP 2.5V_CTL pin trace is 25MIL

25mil

B

Q34 HM772

C

12

C76 10UF/10V

/*

+1.5V_LAN

C563 1000P

1 2

R62 0Ohm

1 2

R61 0Ohm /*

C661 1000P

C164 10UF/10V

C569 1000P

1 2

C571

0.1UF

C663 1000P

1 2

PCI_RST# 23,28,39,40

+2.5V_LAN

T395

1

T396

12

C659

0.1UF

1

12

C662

0.1UF

12

+1.5V_LAN

12

C609

0.1UF

C660

0.1UF

12

C108

0.1UF

12

C586

0.1UF

AVDDLF

VDD3

SPI_DO

SPI_CLK

CTRL15

SPI_CS

VDD4

VDDO_TTL0

VDDO_TTL1

LED_LINK1000n

VDD5

LED_TXn

LED_LINK10n

LED_LINK100n

VDDO_TTL2

LED_RXn

LED_DUPLEXn

LED_STATn

VDD6

TESTMODE

VDDO_TTL3

TDO

VDD7

VAUX_AVLBL

SWITCH[1]

SWITCH[0]

TDI

TRSTn

VDD8

TMS

TCK

XTALO

XTALI

VSSC

NC1

RSET

MDIP[0]

4 4

+2.5V_LAN +1.5V_LAN

+3V_LAN_DIGITAL

12

C159

LAN_EECLK LAN_EEDATA

0.1UF

5 5

bom

PROJECT:

A

U13

8

VCC

7

WP

6

SCL

5

SDA

AT24C08N

W3V

GND

A0 A1 A2

88E8001

1.5V_CTL +3V_LAN_DIGITAL

1 2 3 4

12345678910111213141516171819202122232425262728293031323334353637

R153 200KOhm

REVISION

2.1

1 2

+3V_LAN_DIGITALR

Monday, January 17, 2005

DATE: SHEET OF

B

37 63

MDIN[0]

38

LAN_RSET

XIN_LAN

XOUT_LAN

DESCRIPTION:

1 2

R141 2.49KOhm

R1.1#13

12

C673 12P

PCI GIGA LAN (88E8001)

C

X7

25MHZ

L_TDN L_TDP

12

C674 12P

L_TDN 38 L_TDP 38

R2.1

32bit bus width, 33MHz bus clock gigabit link speed: VDD: +1.5V_LAN = 1.5V / 371.50mA AVDDH: +3V_LAN = 3.3V / 102.52mA AVDDL: +2.5V_LAN = 2.5V / 257.10mA

RELEASE DATE :

L_TDP

R136 49.9Ohm

L_TDN L_RDP L_RDN

L_TRDP2 L_TRDM2 L_TRDP3 L_TRDM3

1 2

R135 49.9Ohm

1 2

R139 49.9Ohm

1 2

R131 49.9Ohm

1 2

R122 49.9Ohm

1 2

R113 49.9Ohm

1 2

R110 49.9Ohm

1 2

R108 49.9Ohm

1 2

D

C131 1000P

1 2

C136 1000P

1 2

C117 1000P

1 2

C109 1000P

1 2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

E

Alice Shih

A

B

C

D

E

[ACZ_SDOUT/SYNC/BITCLK/RST#]:

Azalia MDC MODEM

1 1

CN20 BTOB_CON_12P

1 2

12

ACZ_SDOUT_MDC22

ACZ_SYNC_MDC22

ACZ_SDIN122

ACZ_RST#_MDC22

2 2

3 3

4 4

+2.5V_LAN

1 2

R600 33Ohm

CLose to RDC net

L_TDP37

L_TDN37

L_RDP37

L_RDN37

L_TRDP237

L_TRDM237

L_TRDP337

L_TRDM337

12

C116

0.1UF

12

C103

0.1UF

PLACE NEAR TRANSFORMER

L_CMT L_RXC L_CMT2

5 5

bom

L_CMT3

PROJECT:

A

3 4 5 6 7 8 9 10

11 12

+2.5V_LAN

RDC

12

C585

C139

0.1UF

7 8

75Ohm

5 6

75Ohm

3 4

75Ohm

1 2

75Ohm

W3V

34 56 78 910 11 12

12 13 10 11

ICH6: 39 ohm to Audio / 39 ohm to MDC [ACZ_SDIN]: Audio 33 ohm to ICH6 / MDC 33 ohm to ICH6

1314

1920

1516

1718

GND1GND2

GND3GND4

GND5GND6

NP_NC1NP_NC2

1 2

C99 1000PF

1 2

C112 1000PF

1 2

C582 1000PF

1 2

C128 1000PF

PLACE NEAR RJ45

U46

TRD0P MTRD0P CTRD0 TRD0N

9

TRD1P

7

CTRD1

8

TRD1N

6

TRD2P

4

CTRD2

5

TRD2N

3

TRD3P

1

CTRD3

2

TRD3N

1GB

RN8D RN8C RN8B RN8A

MCTRD0 MTRD0N MTRD1P MCTRD1 MTRD1N MTRD2P MCTRD2 MTRD2N MTRD3P MCTRD3 MTRD3N

FGND1S

15 14 16 18 17 19 21 20 22 24 23

12

C124 1000P

REVISION

2.1

ACZ_BCLK_MDC 22

L_TXP L_CMT L_TXN L_RXP L_RXC L_RXN L_TRLP2 L_CMT2 L_TRLM2 L_TRLP3 L_CMT3 L_TRLM3

Monday, January 17, 2005

DATE: SHEET OF

B

1 2

R595 0Ohm

12

C513

0.1UF

L_TXP L_TXN L_RXP L_RXN

L_TRLP2 L_TRLM2 L_TRLP3 L_TRLM3

38 63

+3V

L_TXN

L_TXP

L_RXN

L_RXP

L_TRLM2

L_TRLP2

L_TRLM3

L_TRLP3

BT_DATA39

BT_CLK39

1 2

R703 0Ohm

1 2

R702 0Ohm

1 2

R701 0Ohm

1 2

R700 0Ohm

14

23

L96 200Ohm

/*

14

23

L95 200Ohm

/*

14

23

L93 200Ohm

/*

14

23

L91 200Ohm

/*

1 2

R699 0Ohm

1 2

R696 0Ohm

1 2

R694 0Ohm

1 2

R691 0Ohm

DESCRIPTION:

U70

1

GP5

2

GP4

3

4 5

45

PIC12C508

/*

LTXP LTXN LRXP LRXN

LTXN

LTXP

Co-Layout Reserved for EMI

LRXN

LRXP

LTRLM2

LTRLP2

LTRLM3

LTRLP3

LTRLP2 LTRLM2 LTRLP3 LTRLM3

Co-Layout Reserved for EMI

RJ11+RJ45 / MDC

C

8 7 6

+3V

1 2

12

R944 0Ohm

/*

12

C895

0.1UF

/*

8

GP0

7

GP1

6

12

R943 0Ohm

/*

LTRLM3 LTRLP3 LRXN LTRLM2 LTRLP2 LRXP LTXN LTXP

RELEASE DATE :

D

R945 0Ohm

23

2

Q179

S

SI2301DS

1

G

D

3

R1.1#37

BT_VCC

8 7 6 5 4 3 2 1

14

RING_J

13 12

TIP_J

11 10

9

L43 1KOhm/100MHz L42 1KOhm/100MHz

+3VS

12

C894

0.1UF

CN22

GND2

P_GROUND2

TRLM3

NP_NC2 TRLP3 RXN TRLM2 TRLP2 RXP TXN TXP

NC2 RING2 RING1 TIP2 TIP1 NC1

NP_NC1

P_GROUND1

GND1

MODULAR_JACK_14P

21 21

R2.0#3

BT_LED# 32,43,45

GP5

GP0

GP4

20 16 18

17 15 19

TIP

RING

12

C176 1000P

/*

CN33

2

4

6

8

10

12

14

16

18

20

AXK5F20545Y

CHASSIS_GND

12

C171 1000P

/*

CHASSIS_GND

DESIGN ENGINEER :SCHEMATIC FILE NAME :

1 3 5 7

9 11 13 15 17 19

BT

R1.1#10

1 3 5 7 9 11 13 15 17 19

GP1

RJ11+RJ45

CN23

2

1

fpc_con_2p_modem

4

SIDE2

3

12SIDE1

Alice Shih

E

USB_PN3 23

USB_PP3 23

A

B

C

D

E

PCI_AD[31:0]23,37,40

1 1

+3V

R18 10KOhm

/*

1 2

802_EN

3

D

802_EN#30

2 2

3 3

4 4

1

G

S

2

PCI_AD[31:0]

Intel PRO/Wireless 2915ABG: pin11: LED_WLAN_LINK

12: LED_WLAN_ACT 13: HW_RadioXMIT_OFF# 14: WLAN_Radio_State# (H:5G/L:2.4G)

ASUS WL-222 a/b/g: pin11: LED_WLAN_ACT

12: WLAN_Radio_State 13: HW_RadioXMIT_OFF#

125

CN19

1

TIP

3

Q7 2N7002

/*

802_ON43

PCI_INTD#23,25

CLK_MINIPCI12

PCI_REQ#323,25

R1.1#10 R1.1#10

BT_DATA38

PCI_C/BE#323,37,40

PCI_C/BE#223,37,40

PCI_IRDY#23,25,37,40

PM_CLKRUN#21,22,25,30,32,37,40 PCI_SERR#23,25,37,40

PCI_PERR#23,25,37,40 PCI_C/BE#123,37,40

+5VS

R19 0Ohm /* R13 0Ohm /*

12

PCI_AD31

C22

PCI_AD29

5PF

PCI_AD27

/*

PCI_AD25

R948 0Ohm

PCI_AD23 PCI_AD21

PCI_AD19 PCI_AD17

PCI_AD14 PCI_AD12

PCI_AD10 PCI_AD8

PCI_AD7 PCI_AD5 PCI_AD3 PCI_AD1

12 12

12

CODEC_ID#1

802_LED802_ON

LAN_RESERV1

5

LAN_RESERV3

7

LAN_RESERV4

9

LAN_RESERV6

11

LAN_RESERV8

13

LAN_RESERV9

15

LAN_RESERV11

17

INTB#

19

3.3V_7

21

RESERVED9

23

GROUND15

25

CLK

27

GROUND4

29

REQ#

31

3.3V_4

35

AD[29]

37

GROUND8

39

AD[27]

41

AD[25]

43

RESERVED8

45

C/BE[3]#

47

AD[23]

49

GROUND11

51

AD[21]

53

AD[19]

55

GROUND13

57

AD[17]

59

C/BE[2]#

61

IRDY#

63

3.3V_8

65

CLKRUN#

67

SERR#

69

GROUND14

71

PERR#

73

C/BE[1]#

75

AD[14]

77

GROUND16

79

AD[12]

81

AD[10]

83

GROUND2

85

AD[08]

87

AD[07]

89

3.3V_2

91

AD[05]

93

RESERVED4

95

AD[03]

97

5V_2

99

AD[01]

101

GROUND6

103

AC_SYNC

105

AC_SDATA_IN

107

AC_BIT_CLK

109

AC_CODEC_ID1#

111

MOD_AUDIO_MON

113

AUDIO_GND2

115

S_AUDIO_OUT

117

S_AUDIO_OGND

119

AUDIO_GND1

121

RESERVED7

123

VCC5A

MINI_PCI

126

LAN_RESERV2

SIDE1

SIDE2

LAN_RESERV5

LAN_RESERV7 LAN_RESERV10 LAN_RESERV12 LAN_RESERV13 LAN_RESERV14

RESERVED3

3.3VAUX1

GROUND7

RESERVED6

GROUND9

GROUND10

DEVSEL#

GROUND12

GROUND1

RESERVED1 RESERVED2

GROUND3

AC_SDATA_OUT

AC_CODEC_ID0#

AC_RESET#

RESERVED5

GROUND5

S_AUDIO_IN

S_AUDIO_I GND

AUDIO_GND

MCPIACT#

3.3VAUX2

POST1

POST2

127

128

RING

5V_1

INTA#

RST#

3.3V_3 GNT#

PME#AD[31]

AD[30]

3.3V_5

AD[28] AD[26] AD[24]

IDSEL

AD[22] AD[20]

PAR AD[18] AD[16]

FRAME#

TRDY# STOP#

3.3V_6

AD[15] AD[13] AD[11]

AD[09]

C/BE[0]#

3.3V_1 AD[06] AD[04] AD[02] AD[00]

M66EN

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3433 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124

+3VS

R20 0Ohm /*

+5VS

+3V

R947 0Ohm

12

R21 100Ohm

CODEC_ID#0

802_LED

12

R979 0Ohm /* R980 0Ohm

PCI_AD30 PCI_AD28

PCI_AD26 PCI_AD24 PCI_AD18

PCI_AD22 PCI_AD20

PCI_AD18 PCI_AD16

PCI_AD15 PCI_AD13 PCI_AD11

PCI_AD9

PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0

+3V

1 2 3 4

12 12

PCI_RST# 23,28,37,40 PCI_GNT#3 23 PCI_PME# 23,25,37,40

U2

A

B

GND

NC7SZ08P5X

/*

PCI_PAR 23,37,40

PCI_FRAME# 23,25,37,40 PCI_TRDY# 23,25,37,40 PCI_STOP# 23,25,37,40

PCI_DEVSEL# 23,25,37,40

PCI_C/BE#0 23,37,40

+3VS

5

VCC

802_ON

Y

PCI_INTC# 23,25,37,40 PCI_INTB# 23,25,40

BT_CLK 38

R1.1#30

+3VS

12

+3V

12

+5VS

12

C20 10UF/10V

C26 10UF/10V

C11 10UF/10V

C9

0.1UF

12

C7

C21

0.1UF

12

C19

C16

0.1UF

12

C24

0.1UF

12

C525

0.1UF

12

C10

C8

0.1UF

5 5

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

39 63

CODEC_ID#0

CODEC_ID#1

R30 1KOhm /*

1 2

R11 1KOhm /*

1 2

DESCRIPTION:

MINIPCI

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

E

+3VS

2mA

+1.8V

1 1

2 2

3 3

4 4

5 5

bom

58mA

1 2

R425 0Ohm

1 2

R458 0Ohm R459 100KOhm /*

Open Drain: CLKRUN#, PME#, SERR#, INTn#

PCI_C/BE#[3:0]23,37,39

VCC_3V POWER : PME#, SPKROUT, RI_OUT#, HWSUSP#, GBRST#, IRQn CCD1#, CCD2#, VS1# , VS2#, TEST, VCC5EN#, VCC3EN#, VPPEN0, VPPEN1, SD/MS I/F

VCCPCI POWER : PCI BUS

VCC_SLOT POWER : CARD_BUS, CAUDIO , CSTSCHG

A

12

PCI_AD[31:0]23,37,39

PCI_REQ#123,25 PCI_GNT#123

PCI_FRAME#23,25,37,39

PCI_IRDY#23,25,37,39 PCI_TRDY#23,25,37,39

PCI_DEVSEL#23,25,37,39

PCI_STOP#23,25,37,39 PCI_PERR#23,25,37,39 PCI_SERR#23,25,37,39

PCI_RST#23,28,37,39 CLK_CBPCI12

PM_CLKRUN#21,22,25,30,32,37,39

PCI_PME#23,25,37,39

C438 10UF/10V

C444 10UF/10V

12

PCI_PAR23,37,39

12

+1.8V_CB

12

C439

0.1UF

C436

0.1UF

C401

0.1UF

R1.1#38

PROJECT:

A

12

C435

0.1UF

12

C437

0.1UF

12

C387

0.1UF

12

CB_GBRST#

C395 7PF/50V

PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#0 CB_IDSEL_J

12

C397 5PF

/*

W3V

U31B

W3

VCC_PCI3V_1

R11

VCC_PCI3V_2

R12

VCC_PCI3V_3

R6

VCC_RIN_1

E13

VCC_RIN_2

L1

VCC_ROUT_1

E14 A4

VCC_ROUT_2 VCC_MD3V

R7

REGEN#

M2

AD31

M1

AD30

N5

AD29

N4

AD28

N2

AD27

N1

AD26

P5

AD25

P4

AD24

R4

AD23

R2

AD22

R1

AD21

T2

AD20

T1

AD19

U2

AD18

U1

AD17

V1

AD16

T7

AD15

V7

AD14

W7

AD13

R8

AD12

T8

AD11

V8

AD10

W8

AD9

R9

AD8

V9

AD7

W9

AD6

T11

AD5

V11

AD4

W11

AD3

T12

AD2

V12

AD1

W12

AD0

V6

PAR

P2

C/BE3#

W2

C/BE2#

W6

C/BE1#

T9

C/BE0#

P1

IDSEL

M4

REQ#

M5

GNT#

V3

FRAME#

V4

IRDY#

W4

TRDY#

T5

DEVSEL#

V5

STOP#

W5

PERR#

T6

SERR#

G2

GBRST#

L4

PCIRST#

K1

PCICLK

L5

CLKRUN#

G4

RI_OUT#/PME#

R5C841

PCI_AD17 CB_IDSEL_J

R438 100Ohm

CB_GBRST#

R410 100KOhm

1 2

C366 0.22UF/10V

R2.1

REVISION

2.1

B

F5

VCC_3V_1

J19

VCC_3V_3

K19

VCC_3V_4

G5

VCC_3V_2

J1

GND1

J5

GND2

K5

GND3

E9

GND4

R10

GND5

T10

GND6

V10

GND7

W10

GND8

L15

GND9

M19

GND10

A9

AGND_1

B9

AGND_2

D9

AGND_3

D14

AGND_4

A15

AGND_5

B15

AGND_6

F4

TEST

F2

HWSPND#

F1

SPKROUT

G1

UDIO5

H5

UDIO4

H4

UDIO3

H2

UDIO2

H1

UDIO1

UDIO0/SRIRQ#

12

DATE: SHEET OF

J4

J2

INTA#

K4

INTB#

K2

INTC#

L2

NC1

+3V

+3V => CB_GBRST# 1ms <T< 100ms

Monday, January 17, 2005

B

40 63

+3V

37mA

12

C394

C399

10UF/10V

0.1UF

+3V

12

CB_HWSUSP#

R447 100KOhm

C359 10UF/10V

+3V

R387 10KOhm

1 2

12

C403 1000PF

C365 0.1UF

SPKRCB PD : Use SROM

1

T361

1

T181

1

T183

12

R456 0Ohm

C

12

C392

C368

1000PF

+MC_VCC+3V+3V_CB

1 2

R407 0Ohm

12

C367

1 2

R398 0Ohm /*

0.1UF

MDIO02--> xD Enable# MDIO05--> SD Power1 Control / xD WP# MDIO06--> xD/MS/SD LED Control MDIO14--> xD Data 4 MDIO15--> xD Data 5 MDIO16--> xD Data 6 MDIO17--> xD Data 7 MDIO18--> xD CLE MDIO19--> xD ALE

1 2

SPKRCB 33

1394_SDA 42 1394_SCL 42

INT_SERIRQ 21,22,25,30,32

PCI_INTB# 23,25,39 PCI_INTA# 23,25 PCI_INTC# 23,25,37,39

MDIO00--> SD Card Detect# MDIO01--> MS Card Detect# MDIO03--> SD Write Protect /

MDIO04--> SD Card Power0 Control /

MDIO07--> SD/MS External Clock MDIO08--> SD Command / MS Bus State

MDIO09--> SD/MS Clock / xD RE# MDIO10--> SD/MS/xD Data 0 MDIO11--> SD/MS/xD Data 1 MDIO12--> SD/MS/xD Data 2 MDIO13--> SD/MS/xD Data 3

xD R/B

MS/xD Power Control

/ xD WE#

DESCRIPTION:

PCI CARDBUS (R5C841)

SHIELD GND

SDCLK_MSCLK42

SHIELD GND

C

SDD3_MSD342 SDD2_MSD242 SDD1_MSD142 SDD0_MSD042

SDCMD_MSBS42

SDPWR_MSPWR42

T360

1

T363

1

T355

1

T350

1

T366

1

T357

1

12

R399 0Ohm

12

R411 0Ohm

T352

1

T178

1

SDWP42

T175

1

MSCD#42 SDCD#42

D

U31A

J18

CADR25

J15

CADR24

C1

NC2

D1

NC3

E1

NC4

C2

NC5

D2

NC6

E2

NC7

E4

NC8

MDIO19

E8

MDIO18

MDIO17 MDIO16 MDIO15 MDIO14

MDIO6 MDIO5

MDIO2

Global Reset POWER SEQ : +3V => CB_GBRST# / CB_HWSUSP# => PCI_RST#

H/W SUSPEND# POWER SEQ : SUSPEND : CB_HWSUSP# LO => PCIRST# LO => +3VS OFF RESUME : +3VS ON => PCIRST# HI => CB_HWSUSP# HI

CB_HWSUSP#

MDIO19

D8

MDIO18

B8

MDIO17

A8

MDIO16

E7

MDIO15

D7

MDIO14

B7

MDIO13

A7

MDIO12

E6

MDIO11

D6

MDIO10

B6

MDIO09

A6

MDIO08

D5

MDIO07

B5

MDIO06

A5

MDIO05

B4

MDIO04

B3

MDIO03

A3

MDIO02

A2

MDIO01

B1

MDIO00

R5C841

3

D26 DAP202K

RELEASE DATE :

D

1 2

K16

CADR23

L16

CADR22

L18

CADR21

M16

CADR20

N19

CADR19

N16

CADR18

P16

CADR17

L19

CADR16

K15

CADR15

N18

CADR14

N15

CADR13

K18

CADR12

R18

CADR11

U19

CADR10

R19

CADR9

P15

CADR8

J16

CADR7

H15

CADR6

H18

CADR5

G15

CADR4

G18

CADR3

F15

CADR2

F18

CADR1

E16

CADR0

U18

CDATA15

W18

CDATA14

V17

CDATA13

V16

CDATA12

V15

CDATA11

B19

CDATA10

C18

CDATA9

D18

CDATA8

W17

CDATA7

W16

CDATA6

W15

CDATA5

T15

CDATA4

R14

CDATA3

C19

CDATA2

D19

CDATA1

E19

CDATA0

T19

OE#

M15

WE#

T18

CE2#

V19

CE1#

F16

REG#

H19

RESET

G16

WAIT#

A18

WP/IOIS16#

M18

RDY/IREQ#

F19

BVD2

E18

BVD1

H16

VS2#

R16

VS1#

D15

CD2#

T14

CD1#

G19

INPACK#

P18

IORD#

P19

IOWR#

V14

USBDP

W14

USBDM

W13

VPPEN1

V13

VPPEN0

T13

VCC3EN#

R13

VCC5EN#

PM_SUSB# 22,33,34,43,47,54,57 CB_SD# 22,25

AD19/A25 41 AD17/A24 41 CFRAME#/A23 41 CTRDY#/A22 41 CDEVSEL#/A21 41 CSTOP#/A20 41 CBLOCK#/A19 41,43 RFU/A18 41,43 AD16/A17 41

CIRDY#/A15 41 CPERR#/A14 41,43 CPAR/A13 41 CBE2#/A12 41 AD12/A11 41 AD9/A10 41 AD14/A9 41 CBE1#/A8 41 AD18/A7 41 AD20/A6 41 AD21/A5 41 AD22/A4 41 AD23/A3 41 AD24/A2 41 AD25/A1 41 AD26/A0 41

AD8/D15 41 RFU/D14 41,43 AD6/D13 41 AD4/D12 41 AD2/D11 41 AD31/D10 41 AD30/D9 41 AD28/D8 41 AD7/D7 41 AD5/D6 41 AD3/D5 41 AD1/D4 41 AD0/D3 41 RFU/D2 41,43 AD29/D1 41 AD27/D0 41

AD11/OE# 41 CGNT#/WE# 41 AD10/CE2# 41 CBE0#/CE1# 41 CBE3#/REG# 41

CSERR#/WAIT# 41,43 CCLKRUN#/IOIS16# 41,43 CINT#/IREQ# 41 CAUDIO/SPKR_IN#/BVD2 41,43 CSTSCHG/STSCHG#/BVD1 41,43 CVS2 41 CVS1 41 CCD2# 41 CCD1# 41,43 CREQ#/INPACK# 41

AD13/IORD# 41 AD15/IOWR# 41

Zdiff= 90ohm

USB_PN4 23 USB_PP4 23

Zdiff= 90ohm

1 2

R460 100KOhm /*

AVPP1 41 AVPP0 41 AVCC3# 41 AVCC5# 41

12

R461 100KOhm

DESIGN ENGINEER :SCHEMATIC FILE NAME :

E

R437 22Ohm

1 2

C393 0.01UF /*

+3V

+VCCCB

UDIO03 H : Enable SD UDIO04 H : Enable MS VPPEN0 H : Enable xD

Alice Shih

E

CCLK/A16 41

12

C406

SHIELD GND

5PF

/*

1 2

CRST#/RESET 41

R414 100KOhm

/*

CCLKRUN#/IOIS16#

1 2

5

4

3

2

1

+3V

R389 0Ohm

1 2

C364 0.01UF

1 2

R408 10KOhm

1 2

C385 0.01UF

place close to ASIC

bom

CPS

X2_1394

X1_1394

1394_FIL

1394_REF

D D

C C

B B

A A

U31C

D11

CPS

A16

XI

B16

XO

A14

FIL0

B14

REXT

1%

D13

VREF

E12

NC9

R5C841

X2_1394 X1_1394

C355 20P

1 2

PROJECT:

5

X5

12

24.576MHZ

W3V

AVCC_PHY_1 AVCC_PHY_2 AVCC_PHY_3 AVCC_PHY_4

TPBIAS0

TPBN0 TPBP0

TPAN0 TPAP0

TPBIAS1

TPBN1 TPBP1

TPAN1 TPAP1

C360 20P

1 2

37mA

12

C373 10UF/10V

E10 E11 A17 B17

TPBIAS0

D12

TPB0-_1

A13

TPB0+_1

B13

Layout: SHIELD GND

TPA0-_1

A12

TPA0+_1

B12

TPBIAS1

D10

TPB1-_1

A11

TPB1+_1

B11

TPA1-_1

A10

TPA1+_1

B10

R1.1#17

REVISION

2.1

12

C383

0.1UF

TPBIAS0 42

TPB0-_1 42 TPB0+_1 42

TPA0-_1 42 TPA0+_1 42

1

T353

12

R395 0Ohm

12

R394 0Ohm

1

T176

1

T177

DATE: SHEET OF

4

AVCC_PHY_CB

12

C369

C379 1000PF

C370

0.1UF

1000PF

CINT#/IREQ# CSERR#/WAIT# CREQ#/INPACK# CAUDIO/SPKR_IN#/BVD2

CSTOP#/A20 CDEVSEL#/A21 CTRDY#/A22 CIRDY#/A15

CSTSCHG/STSCHG#/BVD1 CBLOCK#/A19 CPERR#/A14 CCLKRUN#/IOIS16#

Monday, January 17, 2005

41 63

+3V

L56

21

120Ohm/100Mhz

1 1 1 1

CBDEBUGEN#_Q43

T187 T383 T334 T331

T339 T186 T362 T368

T381 T380 T382 T161

DESCRIPTION:

1

Q166

G

2N7002

3

2

D

AVCC5#40

AVCC3#40

+VPPCB

12

C326 10UF/10V

AD0/D340 AD1/D440 AD3/D540 AD5/D640 AD7/D740 RFU/D14 40,43 CBE0#/CE1#40 AD9/A1040 AD11/OE#40 AD12/A1140 AD14/A940 CBE1#/A840 CPAR/A1340 CPERR#/A1440,43 CGNT#/WE#40 CINT#/IREQ#40

CCLK/A1640 CIRDY#/A1540 CBE2#/A1240 AD18/A740 AD20/A640 AD21/A540 AD22/A440

AD23/A340 AD24/A240 AD25/A140 AD26/A040 AD27/D040 AD29/D140 RFU/D240,43

CCLKRUN#/IOIS16#40,43

CCD1# CCD2#

L L 16bit Other 32bit

S

12

R915 10KOhm

12

D62 1SS355

C340

0.1UF

AVPP040 AVPP140

+VPPCB

CN12

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

PCMCIA Slot

CARDBUS SOCKET

3

+3V

12

R914 10KOhm

12

C890

0.1UF

6970

7172

7374

7576

35

SIDE1SIDE2

RELEASE DATE :

36 37

NP_NC1NP_NC2

P_GND1P_GND2

P_GND3P_GND4

38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

BtoB_CON_68

2

U66

1

VCC5_EN

2

VCC3_EN

3

EN0

4

EN1

5

FLG

6

NC1

7

NC2

8 9

VPPOUT VCCOUT1

35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

GND

VCC5IN2

VCCOUT3

VCC5IN1

VCCOUT2

VCC3IN

NC3

R5531V002

12

C381 270P

+5V

12

16 15 14 13 12 11 10

12

C881

0.1UF

+VCCCB

12

C352

C343

10UF/10V

0.1UF

AD2/D11 40 AD4/D12 40 AD6/D13 40

AD8/D15 40 AD10/CE2# 40 CVS1 40 AD13/IORD# 40 AD15/IOWR# 40 AD16/A17 40 RFU/A18 40,43 CBLOCK#/A19 40,43 CSTOP#/A20 40 CDEVSEL#/A21 40

CTRDY#/A22 40 CFRAME#/A23 40 AD17/A24 40 AD19/A25 40 CVS2 40 CRST#/RESET 40 CSERR#/WAIT# 40,43 CREQ#/INPACK# 40 CBE3#/REG# 40 CAUDIO/SPKR_IN#/BVD2 40,43 CSTSCHG/STSCHG#/BVD1 40,43 AD28/D8 40 AD30/D9 40 AD31/D10 40 CCD2# 40

C868 10UF/10V

/*

12

C891

0.1UF

DESIGN ENGINEER :SCHEMATIC FILE NAME :

12

C875

0.1UF

+VCCCB

12

C772 270P

+3V

12

C867 10UF/10V

/*

CCD1# 40,43

Alice Shih

1

12

C884

0.1UF

5

D D

1394A CON

R2.1

CN26

SIDE_G2

SIDE_G1

IEEE_1394_4P

5 6

C C

LTPA0+

4

TPXA1+

LTPA0-

3

TPXA1-

LTPB0+

2

TPXB1+

LTPB0-

1

TPXB1-

R768 0Ohm R771 0Ohm R773 0Ohm R776 0Ohm

LTPA0+

1 4

LTPA0LTPB0-

14

LTPB0+

2 3

23

12 12 12 12

L107 200Ohm

/*

L108 200Ohm

/*

TPA0+_1

TPA0-_1

TPB0-_1

TPB0+_1

CO-LAYOUT

4

12

R404 56Ohm

1%

12

R403 56Ohm

1%

12

R405 56Ohm

1%

12

R406 56Ohm

1%

1. Close to R5C841

2. The area is as compact as possibl e,le ng th < 1 0 mm

3. TPA Pair and TPB pair mismatch < 2.5mm

4. No via recommend, maxmium is one.

5. Total length < 50 mm

6. Differential impedance is 110+/- 6 ohm

7. TPA Pair trace or TPB pair trace mismatch < 1.25mm

1 2

C363 0.01UF

1 2

C361 0.33U

12

R392 5.11KOhm

1%

1 2

C362 270P

3

+3V

12

C889

0.1UF

TPBIAS0 41 TPA0+_1 41 TPA0-_1 41 TPB0+_1 41 TPB0-_1 41

To solve MS-Duo short with SD card

U65

1 2 3 4

AT24C02N

SDD1_MSD140

SDD2_MSD240

A0 A1 A2 GND

VCC

SDA

SCL

2

R911

R910

10KOhm

8 7

WP

6 5

SDCD#

10KOhm

1 2

Q143

1

2N7002

G

3

2

D

S

6 1

R818 0Ohm /*

1 2

2

Q138A UM6K1N

12

3 4

R816 0Ohm /*

+12V

R817 100KOhm

1 2

5

Q138B UM6K1N

12

1394_SCL 40 1394_SDA 40

SD_DAT1

SD_DAT2

1

Layout: SHIELD GND

1

Q141 2N7002

W3V

+3V

23

2

S

Q142 SI2301DS

1

G

+MC_VCC

D

3

12

C820

C798

0.1UF

REVISION

2.1

Place as close to card reader socket as possible

DATE: SHEET OF

4

Monday, January 17, 2005

42 63

SDCMD_MSBS40

SDD3_MSD340

+MC_VCC

DESCRIPTION:

+MC_VCC

CN30

24 25

NP_NC1 NP_NC2

23

SD_DAT2

GND

9

1

2

3

4

CARD_READER_19P

IEEE1394A / 3in1 CONN

3

B B

R820 10KOhm

1 2

3

D

SDPWR_MSPWR40

A A

bom

1

G

S

2

PROJECT:

5

SDD0_MSD0

SDCLK_MSCLK

SDD3_MSD3

SDD2_MSD2

SDCMD_MSBS

SDD1_MSD1

19

101112131415161718

21

22

20

SDCD#

21

22

SD_DAT1

8

7

6

5

20

RELEASE DATE :

MSCD#

C821 270P

1 2

SDD0_MSD0 40 SDCLK_MSCLK 40

2

MSCD# 40

C805 270P

1 2

+MC_VCC

12

R819 10KOhm

/*

12

C802 270P

/*

SDCD# 40

SDWP 40

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

1

A

U69

LPC_FRAME#21,22,30,31,32

R932 0Ohm

+3V

CLK_DBPCI12

LPC_AD021,22,30,31,32 LPC_AD121,22,30,31,32 LPC_AD221,22,30,31,32

LPC_AD321,22,30,31,32 DIS_FWH31

1 2 3 4

74LVC1G00GV

T97

1

3

D

S

2

3

D

S

2

3

D

S

2

REVISION

CSTSCHG/STSCHG#/BVD140,41

1 1

2 2

3 3

+5VLCM

TS1#54,55,56,58 TS2#54,55,56,58

R929 100KOhm

4 4

5 5

bom

CCD1#40,41

R927 1MOhm

1 2

3

D

Q175 2N7002

5

Q174 2N7002

1

G

1

G

+5VLCM

W3V

S

2

3

D

S

2

12

AC_APR_UC54,55,56 BAT_LOW#_OC 54

1 2

CHG_EN_OC54

U63

1

A

VCC

2

B

3 4

GND Y

SN74LVC1G08

PROJECT:

A

INB

VCC INA GND OUTY

R938

100KOhm

CBDEBUGEN#

Q176 2N7002

1

G

Q177 2N7002

1

G

Q173 2N7002

1

G

2.1

5

12

T385

CHG_LED#

ICH6_1HZ

PM_SUSC#

B

+3V

C882

1 2

0.1UF

PCMCIA DEBUG CARD MUX

U64

3

A0

7

A1

11

A2

17

A3

21

A4

4

B0

8

B1

1

14

B2

18

B3

22

B4

1

BE#

13

BX

74CBT3383

+5VLCM

12

R913

100KOhm

3

D

Q172

2N7002

DATE: SHEET OF

G

S

2

3

D

Q171

G

S

2

ICH6_1HZ22,25

PM_SUSB47 DJ_LED_EN 32,44

PM_SUSC#22,44,47,48,57

Monday, January 17, 2005

B

+3VALWAYS

13

U67B

CLR CK D

PR

10

2

C0

6

C1

10

C2

16

C3

20

C4

5

D0

9

D1

15

D2

19

D3

23

D4

24 12

R995 100KOhm

/*

1 2

R924 1MOhm

Q129 2N7002

ICH6_1HZ

Q133 2N7002

PM_SUSB

Q131 2N7002

PM_SUSC#

VCCGND

Q#

Q

SN74LVC74APWR

+5V

+5VLCM

12

1

G

1

G

1

G

11 12

VCC GND

12

1

43 63

147 8 9

R996 1MOhm

+5VLCM

3

D

S

2

3

D

S

2 3

D

S

2

+3V+3V

1 2

R994 100KOhm

PM_SUSB

Q170 2N7002

DESCRIPTION:

C

C870

+3V

0.1UF

1 2

CCLKRUN#/IOIS16# 40,41 CAUDIO/SPKR_IN#/BVD2 40,41 CPERR#/A14 40,41 RFU/D2 40,41 RFU/D14 40,41

RFU/A18 40,41 CSERR#/WAIT# 40,41 CBLOCK#/A19 40,41

3

D

3

D

G

S

2

12

D63 1SS355

1

3

D

R993 0Ohm /*

+5VLCM

1

G

2

S

R1.1#19

T299

PWR_LED#

1

Q128 2N7002

1

1 2

R749 100KOhm

3

D

Q127 2N7002

1

G

S

2

12

R926 100KOhm

CBDEBUGEN#

CBDEBUGEN#_Q 41

Q194

G

2N7002

2

S

12

R928 100KOhm

LEDs & DEBUG PORT

C

R2.1

BAT_LOW#_KBC 32

PWR_LED# 45

PM_SUSB# 22,33,34,40,47,54,57

R2.0#3

WIRELESS_LED#32

D

12

R726

CHG_LED#

PWR_LED#

HDD_LED_EN28

R1.1#29

BT_LED#32,38,45

1 2

R970 0Ohm /*

RELEASE DATE :

D

R725

10KOhm

D67 DAP202K

1 2

802_ON39

12

3

D

1

3

G

S

2

1 2

R724 10KOhm /*

R730 100KOhm

Q122 2N7002

100KOhm

+5V +5V

12

R176 100KOhm

12

R572 100KOhm

3

D

Q91

1

2N7002

G

S

2

12

R728 100KOhm

3

D

1

G

S

2

Q121 2N7002

DESIGN ENGINEER :SCHEMATIC FILE NAME :

E

+5VLCM+5VLCM

23

2

S

Q115

1

TP0610T

1

G

D

3

R711

R1.1#39

470Ohm

1 2

23

2

S

1

G

D

3

R180 475Ohm

1%

1 2

+5VS+5VS

23

2

S

1

G

D

3

R601 470Ohm

1 2

+5VS+5VS+3VS

23

2

S

1

G

D

3

1 2

E

1

Q41 TP0610T

1

Q89 TP0610T

Q120 TP0610T

R727 470Ohm

M.Y.

CHG_LED 44

T398

R1.1#39

PWR_LED 44

T397

R1.1#39

HDD_LED 44

R1.1#39

WIRELESS_LED 44

A

+3V

1

Q104

G

2N7002

3

2

D

MSK_INSTKEY#32

R2.1

1 1

2 2

3 3

DJ_LED_EN

4 4

5 5

12

R634 100KOhm

DJKEY_EN30

DJ_LED_EN32,43

R633 1MOhm

1 2

LID_SW#20,45,47

PM_SUSC#22,43,47,48,57

+5V +5V

12

R629 100KOhm

3

D

Q103

1

2N7002

G

S

2

+3VALWAYS

2

1

G

3

DJ_LED_EN

C518 1UF/10V

23

S

D

R43 475Ohm

1%

1 2

S

1 2

R612 10KOhm

SWDJ_SW#_Q

Q102 TP0610T

R1.1#39

DJ_LED 45

R611 0Ohm

R635 0Ohm /*

KSO332

KSI532 KSI632 KSI432 KSI332

12

R586 1MOhm

12

D41

1 2

RB717F

+3V

R610 10KOhm

/*

1 2

Q96

1

2N7002

G

3

2

D

S

LN1

7 8 5 6 3 4 1 2

120Ohm/100MHz

For EMI

3

U39B

11

CK

12

D

+3V

R609 1MOhm

1 2

KSI5_DJ_BWARD KSI6_DJ_STOP_EJECT KSI4_DJ_PLAY_PAUSE KSI3_DJ_FFWARD

12

13

147

CLR

VCCGND

8

Q#

9

Q

PR

SN74LVC74APWR

10

3

Q110

D

2N7002

1

G

S

2

SWDJ_SW#_Q

B

R587 100KOhm

C521

0.01UF

/*

12

R683 1MOhm

3

D

S

2

L20 120Ohm/100Mhz L15 120Ohm/100Mhz

12

+3VALWAYS

D45

1SS355

1

G

Q106 2N7002

1

R657 10KOhm

G

21 21

12

3

D

S

2

+3VALWAYS

+3V

+3VALWAYS

12

R630 100KOhm

Q105 2N7002

12

+3V

DJ SW

BWARD

Stop/Eject

Play / Pulse

FFWARD

C61 100PF

1 2

C62 100PF

12

R637 1MOhm

12

1 2

SWDJ_EN# 32

SWDJ_SW# 47

AUDIO_DJ FPC

1

AUDIO DJ CONN

KSO3_DJ

12

C63

C60

100PF

C59

C58

100PF

1 2

C

8

AUDIO_DJ CONN.

CN5

1

2

3

4

5

6

7

78SIDE1

8

SIDE2

FPC_CON_8P_DJ

WIRELESS_LED43

+12VS

PWR_LED43

CHG_LED43

HDD_LED43

INTDATA_5S32

INTCLK_5S32

T406

1

+5VS_TPD

+5V

12

R171 220KOhm

D

C184 100PF /*

1 2

C183 100PF /*

1 2

C182 100PF /*

1 2

C181 100PF /*

1 2

LN2 120Ohm/100MHz

7 8 5 6 3 4 1 2

L45 120Ohm/100Mhz

21

L47 1KOhm/100MHz

21

L46 1KOhm/100MHz

21

+5VS_TPD

Q38 2N7002

S

D

3

2

G

1

C188

0.1UF

1 2

For EMI

TOUCHPAD/LED CON.

12

C180

0.1UF

C179 82PF/50V

/*

C178 82PF/50V

/*

E

14 13 12 11 10

9 8 7 6 5 4 3 2 1

CN8

14

GND2 13 12 11 10 9 8 7 6 5 4 3 2 1

GND1

FPC_CON_14P

16

15

MARATHON

Hotkey FPC

1

8

HOTKEY CONN

HOTKEY CONN.

CN10

1

2

3

4

5

6

SIDE2

7

78SIDE1

8

9

10

FPC_CON_8P_HOTKEY

9 10

Bluetooth

INTERNET

WIRELESS

PANLOCK

R1.1#21,29 R2.1

PANLOCK#_J WIRELESS#_J INTERNET#_J BT#_J

MARATHON#_J

For EMI

CP10B

CP10A

56

34

12

100PF

LN4 1KOhm/100MHz

L48 120Ohm/100Mhz

CP10C

CP10D

C1940.1UF

12

78

100PF

1 3 5 7 8

2 4 6

21

+3V

RN26A

RN26B

RN26C

RN26D

R18310KOhm

12

10KOhm

5 6

7 8

1 2

3 4

R1.1#21,29

PANLOCK_# 32 WIRELESS_# 32 INTERNET_# 32 BT_# 32

MARATHON_# 32

For EMI

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 17, 2005

DATE: SHEET OF

B

44 63

DESCRIPTION:

AUDIO DJ/ HOTKEY/ TP+LEDs

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

E

A

B

C

D

E

+3VALWAYS

1 1

PWR_LED#43

POWER SWITCH CON

T399

CN7

5

NC1

6

NC2

WTOB_CON_10P_2HOLD

2 2

1

2

3

4

1

T400

R1.1_No28

3 3

VRM_PWRGD8,12,48,49,54

R1.1#39

1 2

R134 470Ohm L33 1KOhm/100MHz

12

C892 330pF

For EMI

+3VS

12

R513 10KOhm

21

12

R1.1#3

C512

0.47U

/*

12

R596 10KOhm

12

R512 220KOhm

/*

12

C129 100PF

/*

R1.1#2

+3VS+5VS

12

R527 220KOhm

3

D

Q68

1

2N7002

G

S

2

3

D

Q69

1

2N7002

G

S

2

1

G

3

D

R666 0Ohm /*

C130

0.01UF

23

2

S

1

G

D

3

12

C503

0.1UF

/*

Q108 TP0610T

2

23

S

12

PWR_SW#_Q 47

Q75 TP0610T

R969 0Ohm Q189

3

VCC

R665 0Ohm

R664 0Ohm

1 2

12

/*

12

/*

RESET#

GND

+5VS +5V

2

1

RESET BUTTON

T336

1

SW1

1

2

1

2

3 4

34

50mA/12V

T112

1

ICH6_PWROK 22

R567 100KOhm

1 2

R827

100Ohm

LID_SW#20,44,47

DJ_LED44

R831 100KOhm

1 2

12

RESET_BTN# RESET

12

C806

4.7U

BT_LED NUM_LED CAP_LED

+3VALWAYS

12

C807 1UF/10V

147

VCC

1 2

GND

LN3 120Ohm/100MHz

1 2 3 4 5 6 7 8

21

L27 120Ohm/100Mhz

U56A 74HC14

+3VSUS

12

C809

0.1UF

R833 47KOhm

T347

1

3

1

G

2

3

1

G

2

12

D

S

D

S

Q148 2N7002

Q149 2N7002

R834 330KOhm

12

R838 330KOhm

/*

R839 0Ohm

R837 0Ohm

12

C810 1UF/10V

R1.1#7

1 2

/*

1 2

ADD FOR RC-RESET

SYS_RESET# 22

PM_RSMRST# 22

RST_BTN# 54

KB COVER CON

+3VALWAYS

12

C545

0.1U

CP6B

CP6A

CP6C

CP6D

C860.1UF

56

34

12

78

100PF

1 2

CN6

1

2

3

4

5

6

7

8

9

FPC_CON_9P

SIDE1

SIDE2

Keyboard Cover FPC

DJ_LED Bluetooth NUM CAP Magnet Switch

10

1

9

11

KB Cover CON

4 4

For EMI

12

R713 100KOhm

D

S

+5VS

23

2

S

Q116

1

TP0610T

1

G

D

3

R712

Q117

470Ohm

2N7002

1 2

DATE: SHEET OF

Monday, January 17, 2005

B

45 63

+3VS

12

R553

3

100KOhm

1

G

NUM_LED#32 CAP_LED#32

DESCRIPTION:

PWR SW / RESET / KBC LEDs

2

C

+5VS

+3VS

12

R714

3

100KOhm

1

G

5 5

bom

PROJECT:

A

BT_LED#32,38,43

W3V

2

REVISION

2.1

12

R568 100KOhm

D

S

Q76 2N7002

+5VS+5VS

23

2

S

Q85

1

TP0610T

1

G

D

3

R1.1#39 R1.1#39R1.1#39

R583 470Ohm

1 2

NUM_LED

RELEASE DATE :

D

+3VS

12

R514 100KOhm

1

G

3

2

12

R588 100KOhm

D

S

Q71 2N7002

+5VS+5VS

23

2

S

Q70

1

TP0610T

1

G

D

3

R535 470Ohm

1 2

CAP_LEDBT_LED

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

E

A

B

C

D

E

1 1

+5VS

12

C197

0.1UF

FAN_FB

FAN_DA32

R184

2 2

100KOhm

/*

1 2

FAN_DA

U15

A+

3

8

VCC

+

1

A-

AO

2

-

B+

5

+

BO

7

B-

4

6

-

GND

LM358DR

1 2

R185 100KOhm /*

FAN_ON_R#

12

C196

0.1UF

/*

+5VS

1 2

R186 1KOhm

WATCHDOG32

1 2

R1.1#40

3

R188 2KOhm

Q43 2SB1132

C

E12

B

R187 1KOhm

FAN_ON#

12

C195 22P

12

C199 1UF/10V

1

G

+5VS_FAN

3

2

T401

1

R2.1

12

R182

5.11KOhm

1 2

D

S

Q44 2N7002

R181 10KOhm

1 2

C193 10UF/10V

12

C700

0.1UF

C192 100PF

1 2

R1.1#40

FAN CON.

12

C190

0.01UF

/*

For EMI

FAN_TACH

CN24

1

2

3

4

H1

5

H2

WTOB_CON_3P_FAN

+5VS

12

R178 10KOhm

/*

2

1

G

3

D

S

Q42 2N7002

CPUFAN_SPD_A 32

FAN CONTROL

3 3

A/D_VIN_P

TPC32t

4 4

5 5

bom

PROJECT:

RTC BAT CON.

3 4

1 2

RTC Battery P/N=07-016322032

W3V

A

CN13 WtoB_3P

12

C388

0.1U

REVISION

2.1

RTC_BAT 22

DATE: SHEET OF

B

Monday, January 17, 2005

46 63

DESCRIPTION:

CN2

11

SIDE2

10

SIDE1

WtoB_CON_9P_DC

FAN / RTC / DC_IN

C

DC-IN CONN.

TPC32t

T17

T18

1

9

8

7

6

5

4

3

2

1

T195 TPC32t

1

T100 TPC32t

TPC32t

T23

T22

1

T102

T101

TPC32t

RELEASE DATE :

L14 680 Ohm/ 100MHz

4532

12

C40

0.1U

D

12

C42

0.1U

C12 1UF/50V

A/D_DOCK_IN 55,56

12

C17

0.1U

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

E

A

R2.0#10

1 2

12

+3VALWAYS

1 1

ACIN#

D73 RB751V_40

2 2

3 3

4 4

5 5

bom

12

C907 0.1UF

R986 100KOhm

PM_SUSB#22,33,34,40,43,54,57

OS#_OC6

PROJECT:

A

R638 100KOhm

U39A

4

SN74LVC74APWR

PR

7 14

GND VCC

2

D CK

Q#

CLR

1

R987 10KOhm

1 2

R7 1MOhm

/*

D7 1SS355

/*

D56 1SS355

1 2

D24 1SS355

Q

12

3

W3V

5 6

12

T169

+3VALWAYS

R1010 10KOhm

12

C57 1UF/10V

+3VS

R829 100KOhm

1 2

C808 1000PF

1 2

/*

S

2

G

Q49

1

2N7002

1

R352 10KOhm

12

J2

12

1MM_OPEN_5MIL

/*

REVISION

2.1

12

D

3

1 2

B

VSUS_OFF#54

3

D

Q191

1

2N7002

G

S

2

PM_SUSC#

R2.1

C919 100PF

1 2

U4

1

A

2

B

3 4

GND Y

SN74LVC1G08

/*

1 2

R10 0Ohm

1 2

R985 100KOhm

VCC

ACIN#56

R2.1

+3VSUS+3VSUS

5

R1008 10KOhm

PM_SUSC#22,43,44,48,57

(+3VALWAYS)

147

U56B

VCC

74HC14

3 4

GND

147

U56E

VCC

74HC14

1110

GND

+3VS

Monday, January 17, 2005

DATE: SHEET OF

B

47 63

ACIN#

C918 100PF

1 2

/*

12

/*

PM_SUSC#

147

VCC

5 6

GND

147

VCC

GND

U56C 74HC14

U56F 74HC14

1312

3

1

3

1

G

2

3

1

G

2

D8 RB717F

2

D

Q12

S

2N7002

D

Q6

S

2N7002

OTP_RESET#6,53

SHUT_DOWN#56

DESCRIPTION:

VSUS_OFF#

+5VLCM

CPU_VRON 49,51

PM_SUSB 43

3

D

1

G

S

2

Q48 2N7002

C

PWR_ON

3

CK

2

D

7 14

GND VCC

12

R934 10KOhm

/*

12

R939 470KOhm

T403

1

3

2

D64 RB717F

R2.1

R1009 100Ohm

12

R916 150KOhm

/*

1 2

R1.1#27

PWR_ON

+3VSUS

12

R28 100KOhm

PWR_ON#

12

C32

2.2uF/6.3V

R301 100KOhm

C307

0.33U

R1.1#16

T165

1

12

J1

12

1MM_OPEN_5MIL

/*

+3V

12

POWER ON SEQUENCE

C

+3VALWAYS

1 2

R305 1KOhm

3

At boot, KBCRSM need to be set low for normal operation

+3VALWAYS

12

1

CLR

PR

4

12

T404

1

1 2

R830 10KOhm

D22 DAP202K

R824 100KOhm

U67A SN74LVC74APWR

6

Q#

5

Q

1 2

R825 10KOhm

1 2

C885

D61 1SS355

2.2uF/6.3V

R2.1

U56D

GND

74HC14

98

VCC

14 7

D6 RB751V_40

R1.1#2

PM_SUSC#

1 2

RELEASE DATE :

D

+3VALWAYS

R940 100Ohm

1 2

KBCRSM 32

D

R2.1

R1.1#3

+3VALWAYS

12

R823 100KOhm

3

D

Q167

1

2N7002

G

S

2

D

3

+3VALWAYS

E

R1.1#8

1 2

C804

0.1UF

T402

1

VSUS_ON 50,57

74HC74 TRUTH TABLE

PRE# CLR# CLK D Q Q'

L H X X H L

H L X X L H L L X X float float H H T H H L

H H T L L H H H L X Qo Qo'

T36

1

T53

1

S

2

G

1

+3VSUS

12

R31 10KOhm

12

D5 1SS355

12

C47

0.1UF

DESIGN ENGINEER :SCHEMATIC FILE NAME :

E

1

12

S

2

Q16

G

2N7002

R38 1MOhm

3

D

Q15 2N7002

SWDJ_SW# 44

PWR_SW#_Q 45PM_PWRBTN#22

LID_ICH#_3A 22

LID_SW# 20,44,45

M.Y.

A

E E

D D

R1.1#1

+VCCP

12

CPU_BSEL04,12

R861 330Ohm

R858 100KOhm

/*

1 2

C823 0.01UF

/*

B

C

E12

3

Q152 PMBS3904 C822

S

2

Q153 2N7002

G

1

+3VALWAYS

D

3

12

R873 100KOhm

Q161 2N7002

D

3

B

+3VALWAYS

12

R871 100KOhm

1 2 3 4

S

2

12

G

1

R869 1MOhm

S

2

G

0.01U

1 2

U58

A

VCC B GND Y

SN74LVC1G08

D

3

Q158

1

2N7002

+3VALWAYS

5

SELECT_VCCA

D

3

G

1

S

2

Q156 2N7002

C

1 2

R862 100KOhm

12

R859 100KOhm

12

D72 1SS355

D

+1.8VS VCCA_+1.5VS_+1.8VS+1.5VS

S

D

3

2

Q135

+5VS

12

R780 10KOhm

3

D

Q157

1

2N7002

G

S

2

12

R962 10KOhm

3

D

1

G

S

2

Q186 2N7002

1 2

R950 10Ohm

/*

D

3

1 2

D65 F01J4L

S

2

Q136

G

1

SI2302DS

/*

G

1

SI2302DS

+1.8VS_VCCA+1.8VS

S

D

3

2

Q185

G

1

SI2302DS

1

T405

E

12

C897

C896

0.1UF/25V

1UF/10V

R2.0#11

CPU Type VCCA Voltage

+5VALWAYS

12

R870 100KOhm

+5VALWAYS

12

R878 100KOhm

12

R961 100KOhm

Celeron (Dothan) FSB400 1.8v Dothan FSB533 1.5v

3

D

Q155

C C

MDC NUT *2

(DIP BOM => SMT)

B B

CPU screw hole *4

A A

bom

H22 CT197CB87D47

H3 C276D87

H9 C276D87

H18 C276D87

AGND_A

H10 C276D142

PROJECT:

A

H21 CT197CB87D47

1

H7 C276D87

/*

1

H16 C276D87

/*

1

H2 C276D87

/*

1

H13 C276D142

/*

1

W3V

R2.0#2

H4 C276D87

/*

1

H20 C276D87

/*

1

H12 C276D87

/*

1

H11 C276D142

/*

1

H5 C276D87

/*

1

H1 C276D87

/*

1

H15 C276D87

/*

1

H14 C276D142

/*

1

REVISION

2.1

2N7002

H6 C276D98

/*

1

H19 C276D87

/*

1

H23

H24

c158d158n

/*

1

DATE: SHEET OF

B

1

G

S

2

/*

H25 c158d158n

/*

1

R2.1

For Daughter Board hole *3

H8 C276D98

H17 C276D87

/*

1

Monday, January 17, 2005

48 63

Q154 2N7002

R2.0#19

3

D

1

G

S

2

DESCRIPTION:

3

D

Q184 2N7002

G

S

2

Discharge

1

VRM_PWRGD 8,12,45,49,54

SUSC_DIS

PM_SUSC#22,43,44,47,57

DISCHARGE & EMI

C

12

3

D

1

G

S

2

R14 330Ohm

/*

Q4 2N7002

2

/*

+3VALWAYS

12

R1 47KOhm

/*

3

D

Q2

1

2N7002

G

/*

S

2

RELEASE DATE :

+1.5VS+5VS+3VS +1.8VS

12

61

R863 330Ohm

/*

Q151A UM6K1N

/*

12

SUSC_DIS

C1 1000P

/*

12

R864 330Ohm

/*

34

Q151B UM6K1N

5

/*

2

12

61

R27 330Ohm

/*

Q14A UM6K1N

/*

12

61

R854 330Ohm

/*

Q150A UM6K1N

/*

D

+2.5VS

12

R866 330Ohm

/*

34

Q150B UM6K1N

5

/*

+5V+3V

12

R39 330Ohm

/*

34

Q14B UM6K1N

5

/*

DESIGN ENGINEER :SCHEMATIC FILE NAME :

M.Y.

E

A

VR_VID0

VID 0 1 2 3 4 5

1 1

1.468V 1 1 1 1 0 0

0.956V 1 1 1 1 0 1

TPC32t

1

TPC32t

1

TPC32t

1

VR_VID04 VR_VID14 VR_VID24 VR_VID34 VR_VID44 VR_VID54

CPU_VRON47,51

CLK_EN#

PM_PSI#4

R777

100KOhm

STPCPU#

DPRSLPVR

+3VS

R226 100KOhm

1 2

R201 100KOhm

/*

1 2

0Ohm

12

PSI#

R942 100KOhm

1 2

R233 100KOhm

1 2

R774

R779

1 2

0Ohm

T137 T324

T325

2 2

1.8_2.5_1.5_1_PWRGD51,54

VRM_PWRGD8,12,45,48,54

3 3

PM_DPRSLPVR22

STP_CPU#12,22

+3VO

4 4

DPRSLPVR

+3VS

CLK_EN#

5 5

VR_VID1 VR_VID2 VR_VID3 VR_VID4 VR_VID5

/*

1 2

R224 0Ohm

10/11

1 2

R200 0Ohm

1 2

R199 1KOhm

1 2

R227 1KOhm

/*

R203

1 2

100KOhm

GND

/*

R202 0Ohm

1 2

T128

T129

T127

T130

TPC32t

1

R978

100KOhm

1 2

TPC32t

T142

1

U19

NC

1

A

2 3 4

GND

U21

NC

1

A

2 3 4

GND

NC7ST04M5

VCC

Y

VCC

Y

R209 0Ohm

T133

1

/*

1 2

TPC32t

5

/*

R218 0Ohm

1 2

T131

TPC32t

1

12

C238

0.01uF/25V

+5VO

/*

R217 0Ohm

R215 0Ohm

1 2

GND

T147

1

2

5

for C4 fast exit event

bom

PROJECT:

A

W3V

REVISION

2.1

B

+3VO

1 2

R208 47KOhm

/*

1 2

R211 47KOhm

/*

1 2

R213 47KOhm

/*

1 2

R214 47KOhm

/*

1 2

R216 47KOhm

/*

1 2

R220 47KOhm

/*

R221 0Ohm

1 2

GND

12

T333

T149

TPC32t

1

C248

TPC32t

0.1UF

MCH_OK

1

CLK_EN# VR_PWRGD

VR_VID0 VR_VID1 VR_VID2 VR_VID3 VR_VID4 VR_VID5

GND

DPRSLPVR

STPCPU#

12

R207

C249 47P

C240 0.47U

12

R196

GND

01/04

1 2

R770 15KOhm

61

Q130A

UM6K1N

1 2

R764 36.5KOhm

34

Q130B

UM6K1N

Monday, January 24, 2005

DATE: SHEET OF

B

12

22 24 23

30 29 28 27 26 25

43

TIME

C246 100P

TIME

44 21

14 10

11

31

PSI#

VRON

100KOhm

12

75KOhm

OCP : 34A

12

R765 121KOhm

GNDGND

49 63

12

GND

U17

VCC

SYSOK CLKEN# IMVPOK

D0 D1 D2 D3 D4 D5

6

S0

7

S1

8

S2

3

B0

4

B1

5

B2 SUS

DPSLP# PSI#

9

SHDN#

2

TON CCV REF

ILIM

1

TIME DD0#

MAX1987ETM

1 2

GND

R197 10Ohm

C250

4.7u

BSTM

PGND GND1 GND2

OAIN+

OAIN-

R229

100KOhm

12

36

VDD

42

V+

32 34

DHM

33

LXM

35

DLM

37 13 49 46

CMN

45

CMP

20 19

18

FB

16

NEG

17

CCI

15

POS

48

CSP

47

CSN

41

BSTS

39

DHS

40

LXS

38

DLS

1 2

1.21KOhm

DESCRIPTION:

R222

+5VO

1 2

C247 470PF

1 2

R198 2.7Ohm

R225 360Ohm

1 2

4.7KOhm

C

1 2

R206 2.7Ohm

3

GND

R230

C

12

C220

GND

C251

1 2

4700P

4.7u

12

2 1

D19RB717F

1 2

R223 1MOhm

VCORE

C236

0.1UF

1 2

R219 511Ohm

1 2

R228 511Ohm

C232

1 2

0.1UF

R241 1KOhm

1 2

R244 1KOhm

1 2

CSP

567

8

G

SD

123

4

567

8

G

SD

123

4

PCPU_GND

567

8

G

SD

123

4

567

8

G

SD

123

4

PCPU_GND

RELEASE DATE :

Q126

IRF7413Z

Q125

IRF7831

Q139

IRF7413Z

Q137

IRF7831

D

1

1 2

1

1 2

D

CE33

T313

TPC32t

D18 EC31QS04

CE32

T139

TPC32t

D55 EC31QS04

12

+

5.6UF/25V

12

+

5.6UF/25V

11/26

12

+

CE35

5.6UF/25V

PCPU_GND

L106

0.56UH

CMP

AC_BAT_SYS

11/26

12

+

CE34

5.6UF/25V

PCPU_GND

L109

0.56UH

AC_BAT_SYS

12

C716 1000P

C714 1U

R755

21

1 2

3mOhm

12

C794 1000P

C795 1U

R778

21

1 2

3mOhm

T335

1

T260

1

TPC32t

T314

1

12

TPC32t

+

AC_BAT_SYS

+VCORE

C727

220UF/2V

T329

TPC32t

1

T136

TPC32t

1

CE31 220UF/2V

T317

TPC32t

1

DESIGN ENGINEER :SCHEMATIC FILE NAME :

E

T315

TPC32t

1

T318

TPC32t

1

T138

TPC32t

1

T143

TPC32t

1

T301

TPC32t

1

Amos Yu

E

T316

TPC32t

1

GND

T141

TPC32t

T271

TPC32t

1

GND

T319

TPC32t

1

T148

TPC32t

1

+VCORE

(25A)

12

C766

0.1UF/25V

GND

T295

TPC32t

1

T144

TPC32t

c0603

T291

T320

TPC32t

1

TPC32t

1

A

+5VAO

01/03

R147

10KOhm

1 1

+5VO

2 2

3 3

4 4

5 5

3V_5V_PWRGD54

12

R720 107KOhm

12

R715 20KOhm

1 2

PLLFLTR

R151

1 2

GND

100KOhm /*

12

C690

4700P

PLLFLTR

R718 0Ohm /*

GND

VSUS_ON47,57

3V_5V_PRWGD

GND

1 2 3 4 5 6 7 8

33

1 2

20KOhm

VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND

3.3VOUT ITH2

SIDE1

12

C689

5600P

R716

R723

100KOhm

/*

+5VAO

C670 1000P

R709 150KOhm

01/03

R717

100KOhm

1 2

12

C676 220P

12

C682 180P

12

C671 1000P

12

C677 220P

12

R710 150KOhm

+3VO

12

R729 100KOhm

B

12

C686

1000P

3V_5V_PRWGD

RUN_5VO

32

NC

TG1

NC_3

PGOOD

SENSE1-

RUN/SS1

SENSE1+

BOOST1

EXTVCC

INTVCC

PGND

BOOST2

SW2

TG2

RUN/SS2

SENSE2+

SENSE2-

NC_1

VOSENSE2

9

RUN_3VO

12

C685

1000P

C683 180P

12

R721

1 2

64.9KOhm

Vref = 0.8 V

+3VALWAYS

5

12

GND

C698

25262728293031

VIN

BG1

BG2

16151413121110

12

34

SW1

NC_2

1UF

U50

LTC3728LX

24 23 22 21 20 19 18 17

R719 100KOhm

2

Q118B

UM6K1N

C

12

+

CE38

5.6UF/25V

01/03

SI4800BDY

SI4894DY-TI

12

+

5.6UF/25V

AC_BAT_SYS

PSYS_GND

T122 TPC32t

1

1 2

6/14

AC_BAT_SYS

CE36

5.6UF/25V

T119 TPC32t

1

D16 FS1J4TP

1 2

6/14

11/26

12

C187

0.1UF/25V

D15 FS1J4TP

11/26

12

+

PSYS_GND

DCR =13 mOHM

PSYS_GND

c0603

L44

3.8UH

567

G

4

567

G

4

8

SD

123

8

SD

123

AC_BAT_SYS

8

SD

123

8

SD

123

CE37

Q32

SI4800BDY

01/03

Q36

SI4894DY-TI

Q40

Q37

1 2

12

R732 10Ohm

GND

C695

0.1UF/25V

1 2

+5VAO

2 1

3

RB717F

RUN_3VO RUN_5VO

D54

1 2

C693 0.1UF/25V

1 2

T408 TPC32t

1

T409 TPC32t

567

G

4

567

G

4

+3VO

12

GND

61

+5VAO

PSYS_GND

T285 TPC32t

1

C696

4.7u

3

Q118A

UM6K1N

+5VO

D53 RB715F

D

L39

3.8UH

DCR =13 mOHM

PSYS_GND

12

C172

1U

GND

21

01/03

R159

1 2

10mOhm

01/03

R174

1 2

10mOhm

100UF/6.3V

CE10

+3VO

(5A)

E

1

IN:

OUT:

T297 TPC32t

1

T166 TPC32t

1

T379 TPC32t

1

T114 TPC32t

1

SUSC#_PWR VSUS_ON

AC_BAT_SYS

+3VO +5VO

T168 TPC32t

SIGNAL

POWER

(5A)

+5VO

12

+

12

C177 1UF/10V

GND

T196

T287

TPC32t

1

12

+

CE7

12

120UF/4V

GND

1

C161

T293 TPC32t

1

T146 TPC32t

1

T281 TPC32t

1UF/10V

1

T115 TPC32t

T294 TPC32t

1

T145 TPC32t

1

T280 TPC32t

1

T117 TPC32t

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 24, 2005

DATE: SHEET OF

B

50 63

DESCRIPTION:

C

SYSTEM

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Amos Yu

E

A

VREF5

100KOhm

Q165A

UM6K1N

Q165B UM6K1N

12

C846

8200PF

R972

100KOhm

2

12

100KOhm

UM6K1N

34

2

09/23

12

/*

ON_2.5

61

Q178A

2

+5VALWAYS

+3VALWAYS

ON_1.8

61

GND

1.8_2.5_1.5_1_PWRGD49,54

61

12

1 2

GND

VREF5

1 2

ON_1.05

12

GND

T212 TPC32t

T205 TPC32t

REVISION

C848

2700P

12/28

12.4KOhm

R490

0Ohm

/*

R489 0Ohm

C873

2200P

1

2.1

+1.5VO

R904

1 2

R901

12

C450 47pF/50V

TPC32t

T93

12

RB520S_30

/*

VREF5

R899

11KOhm

Q164B

1 2

UM6K1N

12

C845

0.47U

RB520S_30

R974 0Ohm

10/11

D71

RB520S_30

10/11

12

C442

0.047U

T193

TPC32t

T203

TPC32t

R905

5

D70

09/23

1

SUSC#_PWR

D68

1 2

SUSC#_PWR52,57

1 1

SUSB#_PWR

10/11

D69

2 2

RB520S_30

1 2

SUSB#_PWR52,53,57

3 3

ON_2.5

CPU_VRON47,49

4 4

VREF5

5 5

VREF3

bom

PROJECT:

1

R906

R900

0Ohm

34

1 2

5

12

C847

0.01U

/*

100KOhm

Q164A

UM6K1N

2

10/11

R453

470KOhm

1 2

Q190B UM6K1N

/*

5

VREF5

R923

11KOhm

Q178B

1 2

UM6K1N

5

12

C872

0.47U

JP12

12

1MM_OPEN_5MIL

JP18

12

1MM_OPEN_5MIL

ON_1.5

61

GND

12

R973

UM6K1N

/*

34

R936

VREF5

/*

100KOhm

Q190A

12

34

1 2

12

GND GNDGND

1 2

W3V

A

B

12

C864

6800P

12/28

12

10KOhm

R909

330Ohm

R925

1 2

10.2KOhm

C850

5600P

R895

1.8KOhm

2.7KOhm

ON_1.8

ON_1.5

1 2

12

R483100KOhm

1 2

R484100KOhm

AC_BAT_SYS

C445 0.1U

GND

12

R454

R874 2.7KOhm

100KOhm

+3VO

Monday, January 24, 2005

DATE: SHEET OF

B

+1.8VO

12

C862

3300P

11.8KOhm

C828 0.01U

C414

6800P

1 2

12

1 2

10 11 12

C861

3300P

1

FB1

2

SS_STBY1

3

INV2

4

FB2

5

SS_STBY2

6

PWM_SEL

7

CT

8

GND

9

REF STBY_VREF5 STBY_VREF3.3 STBY_LDO

12/28

12

R875

12.4KOhm

12

R903

U60

ON_1.05

12

GND

R912

R902

ON_2.5

1 2 12

R444 680Ohm

1 2 12

+1.05VO

51 63

09/23

330Ohm

1 2

C855 0.01uF/25V

48

LL1

FLT

LH1

INV1

OUT1_u

TPS5130

SS_STBY3

FB3

INV3

PGOUT

PG_DELAY

1314151617181920212223

12

c0603

C831 0.1UF/25V

C417 0.1UF

1 2

R867

49.9KOhm

1 2

GND

C856

R908 12.7KOhm

C853

+1.8VGND +1.5VGND

3738394041424344454647

TRIP2

TRIP1

OUT2_d

OUT1_d

OUTGND1

TRIP3

VIN_SENSE3

01/03

R872

6.81KOhm

DESCRIPTION:

OUT2_u

OUTGND2

VIN_SENSE12

VREF3.3

REG5V_IN

LDO_IN

LDO_CUR

LDO_GATE

LDO_OUT

INV_LDO

LH3

OUT3_u

LL3

OUT3_d

OUTGND3

24

+1.05VGND

C829

1 2

0.1UF/25V

c0603

2.5V/1.5V/1.8V/1.05V

C

TPC32t

01/03

R907

1 2

10.2KOhm

0.1UF/25V

1 2

12

0.1UF/25V

LL2

LH2

VIN

VREF5

C

T210

1

12

36 35 34 33

VREF3

32

VREF5

31 30 29 28 27 26 25

12

D30

1SS355

TPC32t

1 2

R876 0Ohm

T189

C446 4.7uF/25V

12

C837

0.1U

1

D

AC_BAT_SYS

12

0.1UF

/*

R882

567

G

4

567

G

4

8/16

01/03

8

Q66

SI4800BDY

SD

123

8

Q63

SI4894DY-TI

SD

so8

123

8/16

+1.8VGND

2 3 4

+1.5VGND

678

D

S

G

1

2

3

4 5

11/26

12

+

C909

0.1UF/25V

CE42

c0603

5.6UF/25V L72

1.8UH

T37

T38

TPC32t

1

JP21

1 2

SHORT_PIN

RELEASE DATE :

D

D33

1 2

Q65

D1_1

D1_2

G2

S2 S1/D2_1

SI4814DY

1 2

R472 20mOHM

Q61

RSS090N03

1

C859

12

0.1UF/25V

D34

1SS355

1 2

12

VREF5

R897 2.7Ohm

12

GND

12

C458 4.7uF/25V

R880

1 2

10KOhm

GND

D32

1 2

1SS355

+5VO

C836 0.1UF

12

567

G

4

567

G

4

12

C851 0.1UF/25V

/*

C834

1 2

19.6KOhm

AC_BAT_SYS

01/03

8

Q64

SI4800BDY

SD

123

8

Q67

SI4894DY-TI

SD

so8

123

+1.05VGND

CE40

L69

1.8UH

FS1J4TP

S1/D2_3

S1/D2_2

+2.5VO

T201 TPC32t

21

GND

12

+

CE41

5.6UF/25V

TPC32t

AC_BAT_SYS

81

G1

7 6 5

+2.5VO

T199 TPC32t

1

12

+

CE17

330UF/2V

GND

11/26

12

+

12

C911

0.1UF/25V

5.6UF/25V

c0603

+1.8VGND

+1.8VO

+1.8 VO

21

T154

T98

TPC32t

1

AC_BAT_SYS

T211TPC32t

1

12

+

CE39

5.6UF/25V

1 2

T192 TPC32t

1

12

10UF/6.3V

C447

GND

1

1 2

T151

TPC32t

1

11/26

12

C908

0.1UF/25V

c0603

L71

4.7UH

JP20

SHORT_PIN

+3VO

12

GND

01/03

(5A)

+1.05VO

JP19 SHORT_PIN

T204

TPC32t

1

01/03

12

+

CE20

120UF/4V

/*

GND

TPC32t T384

GND

(0.5A)

1 2

C415

0.1UF/25V

c0603

+1.05VO

SIGNAL

POWER IN:

T208

1

12

+

CE18

330UF/2V

TPC32t T209

1

12

+

T200 TPC32t

1

GND

JP13

12

1MM_OPEN_5MIL

DESIGN ENGINEER :SCHEMATIC FILE NAME :

E

OUT:

GND

T207

TPC32t

1

12

GND

+1.5VO

CE19

330UF/2V

1

Amos Yu

E

SUSB#_PWR

IN:

SUSC#_PWR

AC_BAT_SYS +3VO

+1.8V +1.5V +2.5V +VCC_GMCH_CORE +5VALWAYS +3VALWAYS

01/03

(7A)

JP17

1 2

12

3MM_OPEN_5MIL

01/04

10UF/6.3V

JP32

C460

1 2

12

3MM_OPEN_5MIL

(4A)

JP15

1 2

12

3MM_OPEN_5MIL

C910

12

0.1UF/25V

c0603

TPC32t T226

+2.5VS

+1.8V

T198 TPC32t

T118 TPC32t

1

+1.5VS

1

5

01/03

1844VCC

R1001

R997

0Ohm

/*

GND

1

REF

/*

1 2

1844_OVP

R1000

0Ohm

1 2

12/28

1 2

R145 13KOhm

D14 1SS355

SOD323 /*

1 2

R1014 13KOhm

01/06

+3VS

R1004 100KOhm

/*

1 2

3

C

B

E 2

Q196 PMBS3904

/*

GND

11/26

R952

64.9KOhm

1 2

/*

12/28

C898

0.1UF/25V

/*

+3VS

1 2

12/28

3

1

G

2

+2.5VREF

12/28

107KOhm

/*

1 2

12

R128

10KOhm

01/03

R998

1 2

0Ohm

C121 1UF/10V

c0603

PWR_OK_VGA

D

Q195

S

2N7002

/*

R955

100KOhm

1 2

GND

R954

GND

1 2

R144

150KOhm

T410 TPC32t

1

4.7UF/6.3V

c0805

C95

R143

100KOhm

+12VO

10/11

12

1844_UVP

D D

C C

1 2

R999

1 2

PWR_OK_VGA16,54

SUSC#_PWR51,57

SUSB#_PWR51,53,57

01/03

+ATI_VCORE

R1007 20KOhm

/*

1 2

B B

A A

C916 1UF/10V

c0603 /*

165KOhm

/*

1 2

R1006

4

+5VO

01/07

12

R84

20Ohm

1844VCC

1 2

0Ohm

C122

1UF/10V

c0603

ATI_PERF#16

12

R956

10Ohm

U71

1

VOUT1

2

VIN1-

3

VIN1+

4 5

GND VIN2+

LM358ADR

GND

1 2

R957

4.75KOhm

ILIM

REF

R83

VOUT2

12

GND

VCC

VIN2-

C81

0.1UF/25V

C0603

GND

C900

1UF/16V

8 7 6

12

C72

4.7UF/6.3V

c0805

MAX1844EEP

U9

13

VDD

14

VCC

17

SKIP

10

PGOOD

3

SHDN

7

ILIM

2

LATCH

8

REF

15

TON

11

GND

soic_20p_25_344x237

H:1.0V L:1.2V

T411 TPC32t

1

+1.8VS

567

G

4

BST

DH

CS

DL OVP UVP OUT

FB

01/07

R114 100KOhm

8

SI4800DY

SD

123

V+

LX

Q183

T91 TPC32t

12

16 18 20 19 1 12 4 9 6 5

+5VO

3

1

G

2

12

GND

10/11

1

C901

22UF/6.3V

1 2

DH

CS

DL 1844_OVP 1844_UVP

T412 TPC32t

1 2

D

Q113 2N7002

S

C902

4.7U

R82

0Ohm

01/03

R121

1 2

3

D

1

G

S

2

GND

JP7

1 2

12

1MM_OPEN_5MIL

12

R133

D13

SS0540

sod123

C79

01/03

200Ohm

1KOhm

Q112 2N7002

3

12

0.1U

C917

0.1UF/25V

c0603

12

T89 TPC32t

1

C135

0.1UF/25V

c0603

/*

+1.2VSP+1.2VO

12

GND

8/16

C80

2200P

G

567

4

567

4

8

SD

123

8

SD

123

VGAGND

2

11/26

12

+

CE44

5.6UF/25V

JP3

1 2

SHORT_PIN

T276

T52

T60

TPC32t

1

12

GND GND GND

CE4220UF/2V

+

330UF/2V

8/30

CE43

5.6UF/25V

21

12

+

VGAGND

T273

TPC32t

CE2

12

C39

0.1UF/25V

c0603

8/30

Q10

IRF7413Z

T413 TPC32t

Q17

IRF7831

L13

1

0.56UH

D12

EC31QS04

1 2

AC_BAT_SYS

GND

T414 TPC32t

1

12

C75

0.1UF/25V

T111

TPC32t

1

c0603

T113

TPC32t

1 2

T135

T110

TPC32t

1

MAX:15A

1.2V +/30mV

3MM_OPEN_5MIL

JP4

12

01/04

3MM_OPEN_5MIL

JP33

12

1

GND

1

+ATI_VCORE

Option 1 : remove R54 LVDDR=2.5V Option 2 : remove R149 add R55 LVDDR=2.8V

R102

SUSB#_PWR

R52 100KOhm

1 2

0.1UF/25V

c0603

T46

TPC32t

R89

1

1 2

12

T30 TPC32t

1

12

C53

/*

R73

127KOhm

12

/*

R58

100KOhm

1 2

0Ohmr0603

+3VS

12

C56

C55

10UF/6.3V

GND

+2.5VS

0Ohmr0603

/*

T66 TPC32t

1

LVDDR

(100mA)

U3

1

VIN

2

VSS

3

ON/OFF

S_1111B28MC_NYN_TF

T132 TPC32t

1

VOUT

11/26

NC

5 4

bom

PROJECT:

5

GND

W3V

+1.2VO

REVISION

2.1

Monday, January 24, 2005

DATE: SHEET OF

4

52 63

GND

DESCRIPTION:

VGA VCORE

3

RELEASE DATE :

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Amos Yu

1

A

TPC32t T202

1

12

RT1

100KOhm

C421

0.1UF/25V

GND

TPC32t T197

1

12

C470

0.1UF/25V

GND

11/26

12

+5VALWAYS

12

R921 10KOhm

1 1

+1.05VO +VCC_GMCH_CORE

2 2

+1.8VS

3 3

+5VALWAYS

4 4

5 5

0.01U

1

NC

2

SUB

3 4

GND VOUT

PST9013

GND

C871

U68

12

VCC

TPC32t T140

1

TPC32t T387

5

JP26

1 2

12

3MM_OPEN_5MIL

1

R922

23.2KOhm

1 2

TPC32t T206

1

JP11

1 2

12

2MM_OPEN_5MIL

JP14

1 2

12

2MM_OPEN_5MIL

T26

T6

TPC32t

1

95 DEGREE C

THERMAL PROTECTION PLACE UNDER CPU

GND

01/04

B

+ATI_MEM

OTP_RESET# 6,47

TPC32t T283

1

6/14

TPC32t T95

1

6/14

C

1

T150 TPC32t

TPC32t

+0.9VS

12

JP8

12

GND

T344

12

+

CE15 100U/2V

T346

1

IN

2

GND

3 4

EN ADJ

SI9183DT

/*

GND

T164

+1.8V

TPC32t

1

12

JP9

T2 TPC32t

+0.9VO

12

C299 10UF/6.3V

3MM_OPEN_5MIL

1

+1.5VAO

U57

5

OUT

T163 TPC32t

1

1 2 3 4

T64

TPC32t

1

+0.9VO

R2

20KOhm

1 2

R6

165KOhm

1 2

Vref=1.215V

+1.5VAO

R842

2.4KOhm

/*

1 2

R843 10KOhm

/*

1 2

U22

VIN

VCNTL2

GND

VOUT

VCNTL1 REFEN

RT9173ACL5

100KOhm

1 2

3

C

B

1

E 2

Q1 PMBS3904

GND

TPC32t

R12

1

6 5

+3VS

+3VSUS

+VCCP+1.05VO

12

C815

4.7u

/*

1

G

D

JP31

12

1MM_OPEN_5MIL

N/A

+3V

12

C298 10UF/6.3V

R3

100KOhm

1 2

3

D

Q3

S

2

2N7002

+1.5VSUS

+1.8V

T415 TPC32t

12

R268100KOhm

12

R262100KOhm

1

T156 TPC32t

1

3

D

1

G

S

2

VTT_PWRGD 54

Q45

2N7002

+3V

D

S

12

100KOhm

3

2

R281

G

Q46

1

2N7002

R290

0Ohm

POWER

12

E

SUSB#_PWR

IN:SIGNAL

CPU_VRON

+3VALWAYS

IN:

+3V +1.8V +VCC_GMCH_CORE

+0.9VS

OUT:

+1.5VSUS +VCCP

SUSB#_PWR 51,52,57

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 24, 2005

DATE: SHEET OF

B

53 63

DESCRIPTION:

0.9VS/1.05VS/1.5VSUS

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Amos Yu

E

A

B

C

D

E

BAT_LLOW#_OC 32

T418 TPC32t

1

3

D

Q87

2N7002

1

G

S

2

GND

U35C

POWERGD

8

+5VLCM

BAT_CTRL2 56

CHG_CTRL 55 CHG_EN# 23,55

RST_BTN# 45

3

D

1

G

S

2

GND

T417 TPC32t

1

Q100

2N7002

BAT_LOW#_OC 43

POWERGD 22

CHG_EN_OC 43

U40

SOT23_S5_NB

R620

C530

1U

T43

T1

TPC32t

T215

TPC32t

T214

TPC32t

T194

TPC32t

Q72B UM6K1N

TPC32t

5

PST9142

T259

1

34

R581

1 2

1MOhm

X6

1 3

GND

2

GND

12

GND

4MHZ

T247

T228

T230

TPC32t

1 1

AC_APR_UC43,55,56

BAT_1P55

2 2

PULL UP TO 3VA

3 3

4 4

5 5

BAT_LOW BAT_LLOW

TS1#43,55,56,58 TS2#43,55,56,58

12

C536 100P

SMDATA_BAT232,58 SMDATA_BAT132,58

SMCLK_BAT232,58 SMCLK_BAT132,58

12

11/26

+5VLCM

C125

0.1uF/10V

8/5

BAT_CTRL1

BAT_CTRL2

1

C542

100P

BAT_CTRL1

12

1 2

10KOhm

TS1#

1 2

10KOhm

TS2#

TPC32t

1

1 2

D44 V0402MHS03

GND

1234567

S

I0A

I1AYAI0B

I0DE#VCC

GND

R87

1

R57

1

T223

T272 TPC32t

1

1 2

YB

I1B

I1C

I0CYDI1D

10111213141516

3

D

G

S

2

GND

3

D

G

S

2

GND

D47 V0402MHS03

89

GNDYC

Q25 2N7002

Q21 2N7002

TPC32t

U12

QS3257

1

GND

Q24

B

1

TPC32t

SMC_BAT_PW

SMD_BAT_PW

3 C

E 2

Q20

B

1

PMBS3904

3 C

E 2

PMBS3904

GND

U38

1

RA2

2

RA3

3

T0CKL

4

MCLR#/Vpp

5

Vss

6

RB0

7

RB1

8

RB2

9 10

RB3 RB4

PIC16C54C

GND

BAT1_OFF# 58

3

1

G

2

R86

1MOhm

1 2

OSC1/CLKIN

OSC2/CLKOUT

D

Q23

2N7002

S

GNDGND

RA1 RA0

RB7 RB6 RB5

Vdd

18 17 16 15 14 13 12 11

T242 TPC32t

1

BAT2_OFF# 58

C535

1U

T219 TPC32t

R621

47KOhm

100KOhm

1 2

1

12

GND

VTT_PWRGD53 PWR_OK_VGA16,52

3V_5V_PWRGD50

1.8_2.5_1.5_1_PWRGD49,51

PM_SUSB#22,33,34,40,43,47,57

TPC32t T3

POWERGD

1

VCC

D1

1SS355

TPC32t

1

T257

12 13

1

NC

2

SUB

34

GNDVOUT

TPC32t

T39

TPC32t

1

147

VCC

1 2

GND

147

VCC

GND

R525 1MOhm

1 2

12

C489

GND

1

LV08A

T419 TPC32t

1

1UF/10V

U35A

U35D

2

T35

T225

TPC32t

1

BAT_LLOW

3

11

61

TPC32t

1

VRM_PWRGD8,12,45,48,49

T216

TPC32t

1

Q72A UM6K1N

TPC32t

T220

1

+3VS

147

VCC

4 5

GND

LV08A

GND

T337

TPC32t

R524

0Ohm

1 2

3

1

G

2

U35B

6

1

VSUS_OFF# 47

1 2

D

S

GND

BAT_LOW

R551 0Ohm

R536 0Ohm

Q101 2N7002

6/14

9

10

1

T416 TPC32t

SMD_BAT_PW

SMC_BAT_PW

BAT_CTRL2 BAT_CTRL1

CHG_EN#

147

VCC

GND

LV08A

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 24, 2005

DATE: SHEET OF

B

54 63

DESCRIPTION:

PIC16C54/BATCON/PWOK

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Amos Yu

E

A

A/D_VIN

1 1

2 2

3 3

4 4

5 5

A/D_VIN_O

MAX1909_PDS56

AC_APR_UC43,54,56

A/D_VIN_O

AC_IN Threshold 2.089Vmax A/D_DOCK_IN > 9.913V active

R570

100KOhm

1 2

R569

26.7KOhm

1 2

GND

R603

6/18

T254

1

TPC32t

Adapter Iin(max) = [0.075V/Rsense(ADin)]*[VCLS/VREF] Rsense(ADin)=0.02 ohm VCLS=3.685V => Iin(max)=3.27A => Constant Power = 19 * 3.27 = 62.13W

Charge Current Ichg = [0.075V/Rsense(CHG)]*[ICTL/3.6V] Rsense(CHG)=0.015 ohm VICTL= 1.8Vor 0.9 => Ichg = 2.5A or 1.25A

Vbatt = Cell * { Vref +[ (VCTL- 1.8V) / 9.52 ] } VCTL= 1.576V => Vbatt = 4.2V

Mode pin : Vmode > 2.8V (trie to LDO pin) ----> 4 Cells

VICTL< 0.8V or DCIN < 7V -->Charger Disable

Pre_CHG_V = 3.1mV Pre_CHG_I = 300mA

20KOhm

1 2

R592

TPC32t

137KOhm

1 2

GND

BAT_1P54

2.0 > Vmode > 1.6V (floating) ----> 3 Cells

0.8 > Vmode (trie to GND) ----> Learning mode

T224

LDO : 5.4V REF : 4.2235V

1

3

G

2

6/18

T229 TPC32t

1

10.5KOhm

D

Q77 2N7002

S

GND

Hi = 1P (1.25A), Low = 2P (2.5A)

R566

12

For 1P/2P 6/14

6/14

T252 TPC32t

1

1909_REF

R605

19.6KOhm

1 2

R591

R619

1 2

GND

R604

14.7KOhm

CHG_EN#23,54 TS1#43,54,56,58

A/D_DOCK_IN

D38 1SS400

53.6KOhm

1 2

36.5KOhm

1 2

GND

MAX1909_LDO

B

12

MAX1909_LDO

12

C504 1U

C497 1U

GND

T255 TPC32t

1

6/14

R552 100KOhm

MAX1909_LDO

12

C517 1U

GND

3

1

G

2

C492

100KOhm

1 2

PKPRES#

T253 TPC32t

D

S

GND

12

0.1UF/25V

GND

CHG_GND

R590

6/16

1 2 3 4 5 6 7

MODE

1

R598

Q78 2N7002

C491

DCIN LDO ACIN REF PKPRES# ACOK MODE

6/14

20KOhm

1 2

12

0.1UF/25V

GND

28272625242322

29

PDL

GND2

IINP

891011121314

IINP

12

PDS

CLS

CSSP

ICTL

C528

C529

0.1UF/25V

A/D_DOCK_IN

12

DHI

SRC

DHIV

CSSN

DLOV

PGND

GND1

VCTL

CCI

CCV

CCS

12

0.01U

DLO

CSIP CSIN BATT

C493 0.1UF/25V

R589

C524

12

C490

MAX1909_LDO

GND

21 20 19 18 17 16 15

U36 MAX1909

10KOhm

1 2

CHG_CCV

12

0.1UF/25V

GND

1U

12

C

R526 33Ohm

1 2

C507 0.1UF/25V

1 2

C516

0.047UF/16V

8/16

CHG_CTRL54

BAT_LEARN32

T236 TPC32t

1

6/14

T217

TPC32t

R989

100KOhm

1

11/26

1 2

4

G

567

G

4

MAX1909_LDO

R577

100KOhm

3

D

1

G

S

2

3

D

1

G

S

2

GND

123

S D

Q8

SI4835BDY

8

Q13

SI4800BDY

SD

123

01/04

Q94 IRLML2402

Q93

2N7002

T33 TPC32t

1

1 2

T420 TPC32t

1

12

+

CE46

5.6UF/25V

D9 EC31QS04

CHG_GND

MODE

CHG_GND

L5

10UH

D

T44 TPC32t

T48 TPC32t

T15 TPC32t

7343

5750

Q74

2N7002

1

BAT

12

+

C31 15UF/25V

GND

12

AC_BAT_SYS

C510

0.1UF/25V

1

12

11/26

+

12

CE45

C912

0.1UF/25V

5.6UF/25V

c0603

JP2

1 2

SHORT_PIN

R26

1 2

21

15mOhm

TS2#43,54,56,58

MAX1909_LDO

R576

100KOhm

1

5

G

T123 TPC32t

GND

T232 TPC32t

1

1 2

3

D

S

2

34

GND

1

Q79B UM6K1N

E

BAT

T234 TPC32t

PKPRES#

1

61

Q79A

2

UM6K1N

6/18

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 24, 2005

DATE: SHEET OF

B

55 63

DESCRIPTION:

C

CHARGER

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Amos Yu

E

A

T21

T25

TPC32t

A/D_DOCK_IN46,55

1 1

A/D_DOCK_IN

2 2

3 3

TPC32t

1

MAIN BATTERY SHUNT

1

1 2

T20 TPC32t

C494

1U

1

T5 TPC32t

1 2 3 4

Q11

S D

G

TPC8107

D39 1SS355

1 2

R523 10KOhm

DOWN=11.53V SECOND BATTERY SHUNT DOWN=8.575V

BAT

R584

243KOhm

3

2

12

R599 205KOhm

D

S

Q95 2N7002

1 2

12

R578

100KOhm

W3V

+2.5VREF

12

GND

4 4

D46

12

1SS355 R624

100KOhm

1 2

0.1UF/25V

5 5

BAT_CTRL254

bom

C553

1

G

12

PROJECT:

A

+5VLCM

52

V+

1

+

3

GND

12

C511 0.1UF

C519 0.1UF

REVISION

01/03

U37

4

LMV331

2.1

B

T16 TPC32t

1

8 7 6 5

R34

1 2

20mOhm

6/14

12

AC_APR_UC

1

+5VCHG

1 2

GND

2

3

R618

4.7KOhm

3

D

1

G

S

2

Q97

2N7002

R1005

15KOhm

Monday, January 24, 2005

DATE: SHEET OF

B

T31 TPC32t

12/28

D10

1

1 3

EA60QC04_TE16F

MAX1909_PDS 55

+5V

R663

10KOhm

1 2

34

5

UM6K1N

+5VLCM

12

R585

470KOhm

12

D42

RB715F

10KOhm

R565

12

R615

100KOhm

GND

56 63

C

A/D_VIN A/D_VIN_O

T9

T10

2

Q99B

T11 TPC32t

22KOhm

Q99A

1 2 3 4

1

Q86

S D

G

TPC8107

2

12

R642

R643

30KOhm

1 2 61

UM6K1N

GND

TPC32t

1

8 7 6 5

AC_BAT_SYS

BAT

AC_BAT_SYS, BATTERY LEARN CIRCUIT

AC_BAT_SYS

0923

1

B

1

R59747KOhm

1 2

12

TPC32t T213

R594 100KOhm

1

3

C

E 2

Q180

PMBS3904

AC_APR_UC 43,54,55

(11.6V)

SHUT_DOWN# 47

12

R606 47KOhm

2 E

C543

0.1UF/25V

C

3

PMBS3906

B

Q98

D43 1SS355

1 2

12

C551 4.7u

BATTERY SHUT_DOWN

DESCRIPTION:

BATLOW#/SD#

C

TS1#43,54,55,58

+5VCHG

U45

1 3

OUT IN

GND

L78L05ACUTR

2

+5VLCM

12

T96

R676 100KOhm

TPC32t

1

2

12

C595

1000PF/16V

RELEASE DATE :

D

A/D_VIN

12

C594

U42

12

OUTIN GND

3

LM3480

/*

1U

GND

T421

TPC32t

+5VCHG

C608 1U

+5VO

1

12

1 2

TPC32t

1

T50

R641 1KOhm

1 2

D51

F02JK2E

+2.5VREF

12

1UF/10V

E

3

C560

GND

T279 TPC32t

+5VLCM

1

R662

4.7KOhm

1 2

12

C546

3

2 1

1U

U41 LM4040BIM3X

+5VCHG, +5VLCM, +2.5VREF

AC_BAT_SYS

T32 TPC32t

ACIN_OC32

ACIN#47

1

Q19

3

2N7002

D

1

G

S

2

3 C

E

2

A/D_DOCK_IN

12

R74 100KOhm

TPC32t T28

1

R-1

B1

47K

R-2 47K

Q22 DTC144EK

01/14

12

R50 68KOhm

T34 TPC32t

1

12

R49 10KOhm

C48 0.1UF/25V

GND

ADAPTER IN CIRCUIT

T41 TPC32t

1

+5VLCM

12

R681

12

1000PF/16V

GND

T72 TPC32t

1

12

R687

100KOhm

5

34

5

Q111B UM6K1N

C590

34

Q109B UM6K1N

BAT2_IN#_OC 32

12

61

GND

R669 100KOhm

2

Q111A UM6K1N

1

61

T59 TPC32t

Q109A UM6K1N

BAT1_IN#_OC 32

TS2#43,54,55,58

BATTERY IN CIRCUIT

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Amos Yu

E

A

+1.8VO

1 1

TPC32t

T84

T86

1

TPC32t T121

TPC32t T94

PM_SUSB#22,33,34,40,43,47,54

SUSB#_PWR51,52,53

TPC32t T90

1

TPC32t T134

1

TPC32t T107

1

PM_SUSC#22,43,44,47,48

1

TPC32t T289

1

+3VALWAYS

TPC32t T88

1

TPC32t T54

1

+3VALWAYS

T4

T218

TPC32t

1

TPC32t

1

T92

TPC32t

1

R977 100KOhm

T288

TPC32t

1

R976 100KOhm

R179 0Ohm

12

/*

R155 0Ohm

12

/*

12

+3VO

2 2

3 3

4 4

5 5

+5VO

+12VO

+3VO

+5VO

SUSC#_PWR51,52

01/03

B

01/03

Q62

SD

1

8

2

7

3

6 5

4

G

SI4800BDY

12/28

R462

24KOhm

01/03

Q114

SD

1

8

2

7

3

6 5

4

G

R175 100KOhm

/*

1 2

GND

8 7 6 5

Q39 UMC4N

47K

12 3

SI4800BDY Q123

SI4800BDY

C

BB

47K

E

SD

1 2 3 4

G

SUSB#_PWR_ON

E

10K

C

R990 0Ohm

r0603

46

01/03

Q27

SD

1

8

2

7

3

6 5

4

G

SI4800BDY Q119

SD

1

8

2

7

3

6 5

4

G

SI4800BDY

SUSC#_PWR_ON

R177 0Ohm

/*

12

8/16

Q29 UMC4N

C

46

E

47K

BB

47K

10K

47K

12 3

R154 100KOhm

1 2

E

C

GNDGND GND

12

12/28

C440

0.022U

GND

1 2

11/26

C913

0.1UF/25V

1 2

/*

GND

1 2

12/28

1 2

C705 0.1UF/25V

D75

RB520S_30

/*

1 2

R167

10KOhm

TPC32t T81

TPC32t T296

01/14

1 2

C680 0.1UF/25V

12

R149 10KOhm

TPC32t T277

1

TPC32t T306

/*

12

1

TPC32t T278

1

1 2

GNDGND

TPC32t T73

1

TPC32t T292

1

GND

TPC32t T282

R146 100KOhm

1 2

1

TPC32t T307

1

GND

R170 100KOhm

1

C

12

GND

12

GND

12

C114

0.1UF/25V

GND

12

C679

0.1UF/25V

GND

T422 TPC32t

1

1 2

C636

0.1UF/25V

C712

0.1UF/25V

JP5

1 2

12

3MM_OPEN_5MIL

JP27

1 2

12

3MM_OPEN_5MIL

JP16

12

2MM_OPEN_5MIL

JP24

1 2

12

3MM_OPEN_5MIL

JP30

1 2

12

3MM_OPEN_5MIL

TPC32t T82

1

TPC32t T56

1

T290

TPC32t

T284 TPC32t

T311 TPC32t

TPC32t T235

1

D

+3VO

1

+1.8VS

+5VO

1

+3VS

AC_BAT_SYS

C191

1

+5VS

01/03

SUSC#_PWR

VSUS_ON47,50

+12VS

+3V

+5V

+12V+12VO

0.1U

1 2

GND

R1003 0Ohm /*

12

R1002 0Ohm

12

SUSB#_PWR

U14

1

IN

2

GND

3 4

EN ADJ

MIC5233BM5

SUSC#_PWR

OUT

LEAA

+3VALWAYS

R157 100KOhm

1 2

34

5

GND

+3VALWAYS

1 2

34

5

GND

5

Q31B UM6K1N

R158 100KOhm

Q30B UM6K1N

JP6

1 2

12

1MM_OPEN_5MIL

JP10

1 2

12

1MM_OPEN_5MIL

61

2

Q31A UM6K1N

61

T19

TPC32t

1

T188

TPC32t

1

R168

845KOhm

1 2

R173

95.3KOhm

1 2

GND

SUSB#_PWR_ON

12

C162

SUSC#_PWR_ON

Q30A

12

UM6K1N

E

T120

TPC32t

0.47U

01/04

C160

1UF/16V

+3VSUS

+5VSUS

1

12

C185 1U

+12VO

8/3

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 24, 2005

DATE: SHEET OF

B

57 63

DESCRIPTION:

LOAD SWITCH

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Amos Yu

E

A

TPC32t

T12

1

1 1

CN18

1

2

3

4

5

6

7

8

BATT_CON_8P

2 2

T116

T323

TPC32t

TPC32t T386 TPC32t

1

3 3

T322 TPC32t

1

12

T221 TPC32t

1

C496

0.1UF/25V

T222 TPC32t

1

T14

T13

T8

GND

T227 TPC32t

1

TPC32t

1

TPC32t

1

TPC32t

1

12

C502

0.1UF/25V

T231 TPC32t

1

12

GND

L78

21

150Ohm/100Mhz

12

C500

100P

C498

100P

12

C499

100P

B

R546 0Ohm

1 2

12

C501

100P

R548

1 2

0Ohm

R547

1 2

0Ohm R549

1 2

0Ohm

12

C506 100P

BAT1_OFF# 54

SMCLK_BAT1 32,54

SMDATA_BAT1 32,54

TS1# 43,54,55,56

C

8/16

Change to new

T321

TPC32t

CN31

BATT_CON_6P

T309 TPC32t

1

T310

TPC32t

1

6 5 4 3 2

1

T308

TPC32t

1

T338

TPC32t

12

C351

0.1UF/25V

1

T173 TPC32t

T172

TPC32t

1

T174

T179

T180

1

T340 TPC32t

12

C341

0.1UF/25V

1

TPC32t

1

TPC32t

1

TPC32t

1

T343 TPC32t

1

D

R840 0Ohm

1 2

12

C816

100P

GND

21

L110

150Ohm/100Mhz

R848 0Ohm

1 2

R851 0Ohm

1 2

R853 0Ohm

1 2

12

C817

100P

12

C819

C818

100P

12

GNDGNDGND

C814

BAT2_OFF# 54

BATBAT

100P

E

SMCLK_BAT2 32,54

SMDATA_BAT2 32,54

TS2# 43,54,55,56

4 4

5 5

bom

PROJECT:

A

W3V

REVISION

2.1

Monday, January 24, 2005

DATE: SHEET OF

B

58 63

DESCRIPTION:

PIC16C54/BATCON/PWOK

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Amos Yu

E

A

B

C

D

E

A/D_DOCK_IN

1 1

AC_BAT_SYS

L78L05

(Regulator)

VSUSON

LTC3728LX

+5VCHG +5VLCM

(20mA)

+3VO

+12VO

SWITCH (F02JK2E)

(6A)

(100mA)

+3VSUS

LM4040BIM

(Regulator)

SI9183DP

(Regulator)

+2.5VREF

+1.5VSUS

(Controllor)

+5VO

(4.2A)

+5VSUS

SUSC#_PWR

2 2

(UMC4N)

(SI4800DY)

SUSC#_PWR

+1.8VO

(7A) +0.9VS

+12V

+5V

+3V

SUSB#_PWR

RT9173ACL5+1.8V

(Regulator)

+1.5V+1.5VO (4A)

+5VO

3 3

TPS5130

(Controllor)

VREF3 VREF5

+3VA +5VA

+2.5V(3A)+2.5VO

CPU_VRON

+VCCP

SWITCH+1.05VO(6A)

(PMN45EN)

+VCC_GMCH_CORE

SUSB#_PWR

(UMC4N)

4 4

+12VS

+5VS +3VS

+1.5VS

(SI4800DY)

+2.5VS

CPU_VRON

+5VO

5 5

A

MAX1987

(Controllor)

VRM_PWRGD, CLK_EN#

VR_VID0 - VR_VID5, STP_CPU#, PM_DPRSLPVR, PM_PSI#

B

C

+VCORE

bom

ASUSTeK COMPUTER INC

Size Project Name

Custom

D

Date: Sheet

W3V

(27A)

Title :

Engineer:

E

POWER FLOWCHART

59 63Wednesday, January 26, 2005

2.1

of

Rev

A

B

C

D

E

Revision History

1 1

2 2

3 3

4 4

5 5

bom

R1.1

SYSTEM

1. (p48) Modify CPU +VC C A

2. (p45,47) Fix auto power o n wh e n A C in in AC m od e

3. (p45,57) Solve U 56 ea s il y da m a ge d

4. (p8) Add R941 for BIOS internal VGA st ra p pi n g

5. (p8) U48, D30 change from ICH6_PW RO K to VR M_P WR GD (p 12) R 363 chang e to10K, C893=0.47uF

6. (p20) Fix PID 1 c an ' t s t ra p pe d lo w

7. (p45) Modify power sequence of +3VSUS -> PM_RSMRST#

8. (p47) Fix that +3VSUS/+5VSUS may be turn ed on for a wh ile whe n th e p ower com es in at th e firs t ti me

9. (p16) Fix TV out can't work

10. Add Bluetooth support

11. (p24) DEL rese r ve d V 5R E F_S U S c ir c ui t

12. (p12) ADD net " C PU S EL 0/ 1" fo r l a yo u t

13. (p37) Change X7 part

14. (p23) Add R949 to reduce overshoot

15. (p34) Solve pop noise in Windows boot

16. (p47) Power button debounce

17. Tune X'tal freq. (p22) C353/C356 (p26) C350/C354 (p32) C78/C93 (p41) C355/C360

18. (p27) Change CN32 part

19. (p43) Change R924 to +5VLCM to solve +5V le ak a g e i n p owe r off .

20. (p20) Tune LCD_VCC ti m in g

21. (p44) Modify CN10 p in d efi n e fo r I D ch a ng e

22. (p23,34) Add ALC861VS PC -B eep su pp or t

23. (p33) ADD T388, U61.3 ADD "AUD_GPIO0" (p34) DEL R482, ADD U72

24. (p34,35) DEL net "MIC _AG N D_ A"

25. (p39) ADD voltage div i de r f or Mi c V R EF

26. (p34) for EMI request

27. (p47) VSUS_OFF#

28. (p45) Modify power on sequence

29. (p43,p32) Reserved for bluetooth LED

30. (p39) Reserved PCI_INTC# for M I NI-PCI.

31. (p29) Solve USB pow er s ur ge war ni ng whe n U SB H DD pl ug -i n

32. (p28) Support CSEL+ ODD

33. (p6) GMCH_THRMTRI P# n o fun cti on in hig h t emp e ra tu r e

34. (p10) unstuff for W3 V

35. (p17) Adjust ATI 27MHz V hi gh

36. (p23) Aviod logic output unstab le

37. (p4) Fix BT_VCC unsta bl e

38. (p40) Tune clock timing

39. (p43) Tune LED current for LED spec

40. (p46) Adjust for +5VS_FAN stable

41. (p47) Fix can't power on in batttery mode

POWER

1 (p49) Add R942, MCH_OK connect to 1.8_2.5_1.5_1_P WR GD , C 248, R233 un stuff

R2.0

SYSTEM

1. (p20) Adjust BA CK _E N Vh ig h

2. (p48) Chang e M D C n u t

3. (p22,38,43) DEL BT_ON#, control BT_VCC by BT_LED#

4. (p29) Adjust for US B-I F s pec

5. (p32) Solve SMBus loss pull-high power in power-off.

6. (p23) Reduce PCI_RSTNS # o ve r sh oo t

7. (p23) Reduce 2V step o n P C I _R S T#

8. (p12) Tune W3V clock

9. (p25) Update PC B_ VI D

10. (p47) Solve system can' t pow er on i n b at t er y m o de

11. (p48) Modify +1.8VS_V CCA ga te ck t

12. (p20) Avoid U28 damage

13. (p34) Remove reserved Wind ow s d e- po p C k t

14. (p16) Tune W3A HSYNC/VSYNC timing

15. (p21) Tune W3V HSYNC/VSYNC timing

16. (p28) Modify for swap bay d etec tio n.

17. (p34) For EM I

18. (p20) For EM I

19. (p48) For PD4

20. (p21) For ME

21. (p33) DEL net "AUD_GP IO 0 "

PROJECT:

A

W3V

REVISION

2.1

Wednesday, January 26, 2005

DATE: SHEET OF

B

60 63

DESCRIPTION:

History

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Alice Shih

E

5

D D

4

3

2

1

DC IN

C C

CONDC1

GND

JDC1

P_GND1

4

NP_NC

5

P_GND

6

DC_PWR_JACK_3P

9

8 1 2 3

GND

7

6

5

4

3

2

1 10

WTOB_CON_9P

9

GND2 8 7 6 5 4 3 2 1GND1

11

GND

HDC1 C197D87

1

GND

B B

A A

bom

PROJECT:

5

W3V

REVISION

2.1

Wednesday, January 26, 2005

DATE: SHEET OF

4

61 63

DESCRIPTION:

DC_IN CONNECTOR

3

RELEASE DATE :

2

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Renyu Wang

1

A

B

C

D

E

W3V ODD Board

1 1

Block Diagram

ODD Board Connector

2 2

ODD BOARD CONN.

+5VDOCK_ODD

CONODD2

61

IDE_PDD1_ODD IDE_PDDREQ_ODD

3 3

4 4

IDE_PDD0_ODD IDE_PDIOR#_ODD IDE_PDIOW#_ODD IDE_PDDACK#_ODD IDE_PIORDY_ODD IDE_PDIAG_ODD INT_IRQ14_ODD IDE_PDA2_ODD

IDE_PDCS3#_ODD IDE_PDA1_ODD

IDE_PDA0_ODD IDE_PDCS1#_ODD IDE_PDASP#_ODD

BAY_IN0_ODD IDE_PCSEL_ODD PIN22_+5V_PH_ODD

BAY_IN1_ODD

NP_NC1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

62 64

NP_NC2 SIDE2

BtoB_CON_60P

SIDE1

63 31

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

SATA_DET_#2_ODD BAYDOCK_IN#_ODD SATA_SWAP_TXN2_ODD

SATA_SWAP_TXP2_ODD SATA_SWAP_RXN2_ODD

SATA_SWAP_RXP2_ODD IDE_PDD15_ODD

IDE_PDD2_ODD IDE_PDD14_ODD IDE_PDD3_ODD IDE_PDD13_ODD IDE_PDD4_ODD IDE_PDD12_ODD IDE_PDD5_ODD IDE_PDD11_ODD IDE_PDD6_ODD IDE_PDD10_ODD IDE_PDD7_ODD IDE_PDD9_ODD IDERST#_5S_ODD IDE_PDD8_ODD CD_GND_A_ODD CD_GND_A_ODD CD_L_A_ODD CD_R_A_ODD

ODD CONN.

+5VDOCK_ODD

12

CODD4

0.1U

ODD CONN.

IDE_PDD1_ODD IDE_PDDREQ_ODD IDE_PDD0_ODD IDE_PDIOR#_ODD IDE_PDIOW#_ODD IDE_PDDACK#_ODD IDE_PIORDY_ODD IDE_PDIAG_ODD INT_IRQ14_ODD IDE_PDA2_ODD

IDE_PDCS3#_ODD IDE_PDA1_ODD

IDE_PDA0_ODD IDE_PDCS1#_ODD IDE_PDASP#_ODD

BAY_IN0_ODD IDE_PCSEL_ODD PIN22_+5V_PH_ODD

BAY_IN1_ODD SATA_DET_#2_ODD

12

CODD5

CODD2

0.1U

/*

CODD3

0.1U

/*

12

CODD1

0.1U

/*

CONODD1

1

NP_NC4

2

NP_NC3

3

NP_NC2

4

NP_NC1

5

SIDE_L

6

SIDE_R

7

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

BtoB_60P

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35

CD_R_A_ODD CD_L_A_ODD CD_GND_A_ODD CD_GND_A_ODD IDE_PDD8_ODD IDERST#_5S_ODD IDE_PDD9_ODD IDE_PDD7_ODD IDE_PDD10_ODD IDE_PDD6_ODD IDE_PDD11_ODD IDE_PDD5_ODD IDE_PDD12_ODD IDE_PDD4_ODD IDE_PDD13_ODD IDE_PDD3_ODD IDE_PDD14_ODD IDE_PDD2_ODD IDE_PDD15_ODD

SATA_SWAP_RXP2_ODD SATA_SWAP_RXN2_ODD

SATA_SWAP_TXP2_ODD SATA_SWAP_TXN2_ODD

BAYDOCK_IN#_ODD

5 5

bom

PROJECT:

A

W3V

REVISION

2.1

Wednesday, January 26, 2005

DATE: SHEET OF

B

62 63

DESCRIPTION:

ODD BOARD

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Joe Wu

E

A

B

C

D

E

W3V TP & LED Board

1 1

Block Diagram

2 2

TP Board Connector

TP CONN.

TP Button

TOUCHPAD & LED BOARD CONN.

CONTP3

GND1

GND2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

INTCLK_5S_TP INTDATA_5S_TP

+5VS_TPD_TP

WIRELESS_LED_TP HDD_LED_TP CHG_LED_TP PWR_LED_TP

15

16

FPC_CON_14P_TP&LED

RIGHT_TP

LEFT_TP

INTCLK_5S_TP INTDATA_5S_TP +5VS_TPD_TP

TP CONN.

CONTP2

1

2

3

4

5

6

7

8

9

10

11

12

13

NC1

14

NC2

FPC_CON_12P

LED CONN.

3 3

TOUCHPAD BUTTON

4 4

LEFT RIGHT

SWTP1

5 6 1 2

3 4

1mA/5V

LEFT_TP RIGHT_TP

12

CTP1

0.1U

/*

SWTP2

5 6 1 2

3 4

1mA/5V

12

CTP2

0.1U

/*

LED CONN.

CONTP1

7

SIDE1

8

SIDE2

FPC_CON_6P

1

2

3

4

5

6

PWR_LED_TP CHG_LED_TP

HDD_LED_TP WIRELESS_LED_TP

HTP1 C91D91N

/*

1

HTP2 C91D91N

/*

1

R2.1

5 5

bom

PROJECT:

A

W3V

REVISION

2.1

Wednesday, January 26, 2005

DATE: SHEET OF

B

63 63

DESCRIPTION:

TP&LED BOARD

C

RELEASE DATE :

D

DESIGN ENGINEER :SCHEMATIC FILE NAME :

Joe Wu

E

Asus W3V-A Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual