![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg1.png)
A
B
T13Fv SCHEMATIC R1.11
C
D
E
PAGE
1 1
2 2
3 3
4 4
5 5
SYSTEM PAGE REF.
4
YONAH CPU (1)
5
YONAH CPU (2)
6
FAN CTRL&Thernal protection
7
CLK GEN-ICS954310
8
Calistoga--CPU
Calistoga--PCIE
9
Calistoga--DDR2
10
Calistoga--POWER
11
Calistoga--GND
12
13
Calistoga--Strap
DDR2 SO-DIMM_0
14
15
DDR2 SO-DIMM_1
DDR2 ADDRESS TERMINATION
16
LVDS & INVERTER CONN
17
18
VGA CONN
ICH7M--CPU,IDE,AUDIO
19
ICH7M--GPIO
20
ICH7M--PCI,PCI-E,USB
21
ICH7M--VCC,GND
22
23
HDD & CD-ROM CONN
USB PORT
24
B/T & F/P
25
B TO B CONN(M)
26
CARDBUS R5C841
27
PCMCIA SOCKET
28
PCI-E--LAN_RTL8101E
29
30
AZALIA - ALC660-GR
31
AUDIO_AMPLIFIER
32
MICROPHONE
NEWCARD
33
EC-IT8510E
34
35
ISA ROM & Touch Pad & KB& FP
Card Reader GL817E
36
37
DISCHARGE
38
Instant Key & FFC CONN
39
LEDs
EMPTY
40
41
EMPTY
42
EMPTY
43
EMPTY
EMPTY
44
45
SREW HOLE
46
DC & BAT IN
A
Content
PAGE
47
EMPTY
48
History(1)
49
History(2)
POWER PAGE REF.
50
POWER_VCORE
51
POWER_SYSTEM
52
POWER_I/O_1.8V & 1.05VS
53
POWER_I/O_DDR & VTT
54
POWER_I/O_VTT & +2.5VS
55
POWER_VGA_CORE(Empty)
56
POWER_VGA_RAM(Empty)
57
POWER_CHARGER
58
POWER_PIC(Empty)
59
POWER_DETECT
60
POWER_PROTECT
61
POWER_LOAD SWITCH
62
POWER_FLOWCHART
63
POWER_SIGNAL
B
Content
<Variant Name>
Title :
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
C
D
T13Fv
Engineer:
E
PAGE REF.
Marco Chen
163Monday, August 28, 2006
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg2.png)
A
B
C
D
E
1 1
T13F BLOCK DIAGRAM
BATTERY
TYPE
Internal IO CON with Cable
3S1P
3S2P
SPKR
CON
Int. MIC.
CON
CCD
CON
DEBUG
CON
BT CONTP CON INVERTER
CON
LVDS
CON
Yonah
2 2
CLOCK
GEN.
ICS954310
7
LVDS & INV
CON
17
479
AGTL
1.468V,167MHZ
HOST BUS
....
4
DDR2 SDRAM 533/667MHz
945GMZ
CRT CON
18
3 3
USB x3
24
USB2.0
PATA BUS
SATA BUS
B/T
25
Camera
17
4 4
Finger
Print
25
ODD
Slave
23 23
HDD Master
EC(IT8510E)
GL817E
36
T13Fv
5 5
+SI
3IN1 CARD
READER
A
ISA
ROM
35 39
36
INTERNAL
KEYBOARD
19, 20, 21, 22
LPC, 33MHz
B
8, 9, 10, 11, 12
X4 DMI
ICH7-M
652
BGA
34
HP
31
MIC_IN
32
CPU
CAP
PCI BUS
ACZ BUS
Azalia
ALC660
AUDIO AMP
G1420
C
5
DDR2 533/667
SODIMM X2
+1.8V
+0.9VS
14, 15
PCI EXPRESS X1
30
31
SPKR
31
POWER
SEQENCE
....
R5C841
T13Fg
34 16
LAN 10/100
27
PCMCIA
28
D
DDR
CAP/RES
RTL8101E
SMBUSRESET
16
+ USB2.0
NEWCARD
29
33
SI
AC & BAT CON
FAN CTRL
<Variant Name>
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
45
6
T13Fv
THERMAL
SENSOR
(MAX6657)
Title :
Engineer:
E
6
BLOCK DIAGRAM
Marco Chen
263Monday, August 28, 2006
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg3.png)
A
B
C
D
E
EC GPIO SETTING
Pin
32
1 1
2 2
3 3
4 4
5 5
33
36
37
38
39
40
43
153
154
164
5
6
165
47
169
170
171
172 ACIN_OC#
175
176
1
26
29
30
31
41
42
62
63
87
88
89
90
2
44
24
25
110
111
114
115
116
118
119
113
112
104
103
3
4
27
28
Pin Name
PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
PWM6/GPA6
PWM7/GPA7
RXD/GPB0
TXD/GPB1
GPB2
SMCLK0/GPB3
SMDAT0GPB4
GA20/GPB5
KBRST#/GPB6
GPB7
CLKOUT/GPC0
SMCLK1/GPC1
SMDAT1/GPC2
GPC3
TMRI0/WUI2/GPC4
GPC5
TMRI1/WUI3/GPC6
CK32KOUT/GPC7
RI1#/WUI0/GPD0
RI2#/WUI1/GPD1
LPCRST#/WUI4//GPD2
ECSCI#/GPD3
GPD4
GINT/GPD5
TACH0/GPD6
TACH1/GPD7
ADC4/GPE0
ADC5/GPE1
ADC6/GPE2
ADC7/GPE3
PWRSW/GPE4
WUI5/GPE5
LPCPD#/WUI6/GPE6
CLKRUN#/WUI7/GPE7
PS2CLK0/GPF0
PS2DAT0/GPF1
PS2CLK1/GPF2
PS2DAT1/GPF3
PS2CLK2/GPF4 I/0
PS2DAT2/GPF5117
PS2CLK3/GPF6
PS2DAT3/GPF7
FA16/GPG0
FA17/GPG1
FA18/GPG2
FA19/GPG3
FA20/GPG4
FA21/GPG5
LPC80HL/GPG6
LPC80LL/GPG7
A
Signal Name
N/A
FAN_PWM
N/A
N/A
CHG_LED_UP#
PWR_LED_UP#
BATSEL_3S#
LCD_BACKOFF#
NUM_LED
CAP_LED
N/A162
SMB0_CLK
SMB0_DAT
A20GATE
RCIN#
THRO_CPU
PWRGEAR_LED
SMB1_CLK
SMB1_DAT
CR_DRIVER#
OP_SD#
BAT_IN_OC#
EC_IDE_RST#
SUSB#
SUSC#
PCI_RST#
EXT_SCI#
CR_POWER#
N/A
FAN0_TACH
N/A
WLAN_BTN#
N/A
MARATHON#
N/A
PWR_SW#
N/A
LID_EC#
N/A
/
/
/
/
TP_CLK
TP_DAT
PWRLMT_EC#
/
FA16
FA17
FA18
/
THRM_CPU#
N/A
PMTHERM#
AC_APR_UC#
Type
O
O
O
O
O
O
O
I/0163
I/0
O
O
O
O
I/0
I/0
O
I
O
I
O
I
I
I
O
O
I
I
I
I
I
I
I/0
I
I
I
O
I
GPH0
GPH1
GPH2
GPH3
GPH4
GPH5
GPH6
GPH7
GPI0
GPI1
GPI2
GPI3
GPI4
GPI6
ADC1
ADC2
ADC3
ADC8
ADC9
DAC0
DAC1
DAC3
Pin Name
Signal Name
VSUS_ON O
VSUS_GD#
PM_PWRBTN#
SUSC_ON
SUSB_ON
CPU_VRON
PM_RSMRST#
ICH7_PWROK
WATCH_DOG#149
N/A
CHG_EN#
PRECHG
BAT_LL#
BAT_LEARN O
N/A
N/A
N/A
SYS_TEMP
KID0
KID1
N/A
N/A
INVTER_DADAC2
BATSEL_2P#
Pin
48
54
55 CPUPWR_GD#
69
70
76
105
148
152
155
156
16875GPI5
174
81 ADC0
82
83
84
93
94
99
100
101
102
ICH7M_PCI EXPRESS:
PCI-E Device PAIR
1RTL8101E
2GOLAN
NEWCARD 3
ICH7M_SMBUS ADDRESS :
SM-Bus Device
Clock Generator
SO-DIMM 0
SO-DIMM 1
Thermal Sensor( MAX6657)
SM-Bus Address
1101001x ( D2 )
1010000x ( A0 )
1010001x ( A4 )
1001100x ( 98 )
ICH7M_PCI_DEVICE:
PCI Device
B
IDSEL# Interrupts
AD17
Type
REQ/GNT#
1
O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
B, DR5C841
C
ICH7M_GPIO
Pin
GPIO 00
GPIO 01
GPIO [5:2]
GPIO 06
GPIO 07
GPIO 08
GPIO 09
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
GPIO 19 1
GPIO 20
GPIO 21
GPIO 22
GPIO 23 N/A
GPIO 24
GPIO 26
GPIO 27
GPIO 28
GPIO 29
GPIO 30
GPIO 31ii
GPIO 32
GPIO 33
GPIO 34
GPIO 35
GPIO 36
GPIO 37
GPIO 38
GPIO 39
GPIO [40:47] NA
GPIO 48
GPIO 49 Native
Use As
i
GPI
GPI
i
GPI
i
GPO
GPI
i
GPI
i
GPI
i
i
GPI
Native
i
GPI
i
i
GPI
i
GPI
GPO
i
0
O
GPO
O
GPO
1
GPO
O
1
iGPI
GPO
O
1
GPO
i
1
Native
1
i
Native
1
O
GPO
0
OGPIO 25
GPO
1
O
GPO
0
GPO
O
0
O
GPO
0
Native
i
0
i
Native
0
Native
0
GPO
O
1
O
GPO
1
GPO
O
0
GPO
O
0
GPO
i
0
GPI
i
0
GPI
i
0
GPI
NA
D
Signal Name
PM_BMBUSY#
PCI_REQ#5
PCI_INT[E:H]#
BT_LED_EN
N/A
EXTSMI#
N/A
N/A
SMB_ALERT#
KBC_SCI#
N/A
N/A
802_LED_EN
PM_DPRSLPVR
PCI_GNT#5
STP_PCI#
N/A
STP_CPU#
N/A
PCI_REQ#4
MSK_PCIRST
CB_SD#
BT_ON#
WLAN_ON#
MEMROM/YONAH#
USB_OC#5
USB_OC#6
USB_OC#7
PM_CLKRUN#
N/A
CPU_Select
N/A
N/A
PCB_ID0
PCB_ID1
PCB_ID2i0
PCI_GNT#4
H_PWRGD
<Variant Name>
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet
T13Fv
Power
+3VS
+3VS
+3VS
+3VSi
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VSUS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
NA
+3VSNative
+VCORE
Title :
Engineer:
E
Schematic data
Marco Chen
363Monday, August 28, 2006
of
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg4.png)
5
D D
H_A#[16:3]8
H_ADSTB#08
H_REQ#[4:0]8
C C
B B
H_A#[31:17]8
H_ADSTB#18
H_A20M#19
H_FERR#19
H_IGNNE#19
H_STPCLK#19
H_INTR19
H_NMI19
H_SMI#19
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
L2
K3
H2
K2
J3
L5
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
V4
A6
A5
C4
D5
C6
B4
A3
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
B25
U401A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
RSVD[10]
RSVD[11]
SOCKET479P
4
ADS#
BNR#
BPRI#
ADDR GROUP 0
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
ADDR GROUP 1
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
XDP/ITP SIGNALS
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
THERMHCLKRESERVED
BCLK[0]
BCLK[1]
RSVD[12]
RSVD[A2]
RSVD[13]
RSVD[14]
RSVD[15]
RSVD[16]
RSVD[17]
RSVD[18]
RSVD[19]
RSVD[20]
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
B1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
A25
C7
A22
A21
T22
A2
D2
F6
D3
C1
AF1
D22
C23
C24
H_IERR#H_A#13
T401
T411
TPC28T
TPC28T
1
1
R401 56Ohm
H_RS#0
H_RS#1
H_RS#2
R402 56Ohm@
R403 56Ohm
R404 56Ohm
R405 56Ohm@
R406 56Ohm
R407 56Ohm
T407
TPC28T
H_PROCHOT_S#
R408 56Ohm
H_ADS# 8
H_BNR# 8
H_BPRI# 8
H_DEFER# 8
H_DRDY# 8
H_DBSY# 8
H_BR0# 8
+VCCP_AGTL+
H_INIT# 19
H_LOCK# 8
H_CPURST# 8
H_RS#0 8
H_RS#1 8
H_RS#2 8
H_TRDY# 8
H_HIT# 8
H_HITM# 8
T402 TPC28T
1
T403 TPC28T
1
T404 TPC28T
1
T405 TPC28T
1
T406 TPC28T
1
+VCCP_AGTL+
GND
1
R417
0Ohm
H_THERMDA 6
H_THERMDC 6
+VCCP_AGTL+
H_THRMTRIP# 6
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
3
PWRLMT# 34,35,57
+VCCP_AGTL+
R409
1KOhm
1%
R415
2KOhm
1%
GND
133
166
H_DSTBN#08
H_DSTBP#08
H_DINV#08
GTLREF0
<500 mil (55 Ohm)
T/B trace 5.5 ,
Space 25
H_DSTBN#18
H_DSTBP#18
H_DINV#18
CPU_BSEL07
CPU_BSEL27
BSEL2BCLK
FSB
533
L
667
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
GTLREF0
R416 1KOhm@
R414 51Ohm
GND
BSEL0
BSEL1
H
LL
H
H
AD26
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
H23
G22
J26
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
M24
N25
M26
C26
D25
B22
B23
C21
2
U401B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
BSEL[0]
BSEL[1]
BSEL[2]
SOCKET479P
DATA GRP 0
DATA GRP 2DATA GRP 3
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DATA GRP 1
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
MISC
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
PWRGOOD
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DPWR#
SLP#
PSI#
H_D#[63:0]
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
R26
U26
U1
V1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_COMP0
H_COMP1
H_COMP2
H_COMP3
POWER
1
H_D#[63:0] 8
H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8
H_DSTBN#3 8
H_DSTBP#3 8
H_DINV#3 8
R410 27.4Ohm 1%
R411 54.9Ohm 1%
R412 27.4Ohm 1%
R413 54.9Ohm 1%
H_DPRSTP# 19,50
H_DPSLP# 19
H_DPWR# 8
H_PWRGD 19
H_CPUSLP# 8,19CPU_BSEL17
PM_PSI# 50
GND
P/N:12G04600479A
A A
<Variant Name>
Title :
YONAH CPU (1)
1
Marco Chen
463Monday, August 28, 2006
of
Rev
1.11
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet
5
4
3
2
T13Fv
Engineer:
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg5.png)
5
4
3
2
1
A11
A14
A16
A19
A23
A26
B11
B13
B16
B19
B21
B24
C11
C14
C16
C19
C22
C25
D11
D13
D16
D19
D23
D26
E11
E14
E16
E19
E21
E24
F11
F13
F16
F19
F22
F25
G23
G26
H21
H24
K23
K26
L21
L24
M22
M25
N23
N26
A4
A8
B6
B8
C5
C8
C2
D1
D4
D8
E3
E6
E8
F5
F8
F2
G4
G1
H3
H6
J2
J5
J22
J25
K1
K4
L3
L6
M2
M5
N1
N4
P3
U401D
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
SOCKET479P
T13Fv
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
Title :
Engineer:
1
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
YONAH CPU (2)
Marco Chen
563Monday, August 28, 2006
Rev
1.11
+VCORE
C507
C508
D D
C C
B B
A A
+VCORE
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A10
A12
A13
A15
A17
A18
A20
B10
B12
B14
B15
B17
B18
B20
C10
C12
C13
C15
C17
C18
D10
D12
D14
D15
D17
D18
E10
E12
E13
E15
E17
E18
E20
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AB9
A7
A9
B7
B9
C9
D9
E7
E9
F7
F9
U401C
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[65]
VCC[66]
VCC[67]
SOCKET479P
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
VCC[77]
VCC[78]
VCC[79]
VCC[80]
VCC[81]
VCC[82]
VCC[83]
VCC[84]
VCC[85]
VCC[86]
VCC[87]
VCC[88]
VCC[89]
VCC[90]
VCC[91]
VCC[92]
VCC[93]
VCC[94]
VCC[95]
VCC[96]
VCC[97]
VCC[98]
VCC[99]
VCC[100]
VCCP[1]
VCCP[2]
VCCP[3]
VCCP[4]
VCCP[5]
VCCP[6]
VCCP[7]
VCCP[8]
VCCP[9]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
AD6
AF5
AE5
AF4
AE3
AF2
AE2
AF7
AE7
+VCORE
VR_VID0
VR_VID1
VR_VID2
VR_VID3
VR_VID4
VR_VID5
VR_VID6
+VCCP_AGTL+
+1.5VS
12
R502
100Ohm
GND
+1.5VS
12
C501
0.01UF/16V
GND
VR_VID[0..6] 50
R501
12
100Ohm
CPU +VCCA
Decoupling
Capacitors
C528
10UF/6.3V
Please close to CPU.
POWER
+VCORE
VCCSENSE 50
VSSSENSE 50
POWER
POWER
CPU +VCORE
Mid-Frequency
Capacitors
Intel:22UF*32
T13F:10UF*26
CPU +VCORE
Bulk-Decoupling
Capacitors
CPU +VCCP
Decoupling
Capacitors
Intel:270UF*1,
0.1UF*6
T13F:150UF*1,
0.1UF*10
10UF/6.3V
+VCORE
10UF/6.3V
+VCORE
12
10UF/6.3V
+VCCP_AGTL+
C502
C512
C538
c0805_h37
@
+VCORE
C503
10UF/6.3V
C513
10UF/6.3V
12
10UF/6.3V
12
+
CE501
330UF/2.5V
12
+
CE503
150UF/4V
10UF/6.3V
10UF/6.3V
C534
c0805_h37
@
C504
C514
12
+
CE502
330UF/2.5V
GND
C522
0.1UF/10V
C529
0.1UF/10V
1 2
12
10UF/6.3V
JP501
SHORT_PIN
@
C505
10UF/6.3V
C515
10UF/6.3V
C533
c0805_h37
@
10UF/6.3V
10UF/6.3V
12
+
CE504
@
330UF/2.5V
C523
0.1UF/10V
C530
0.1UF/10V
C506
C516
12
C537
c0805_h37
10UF/6.3V
@
+VCCP+VCCP_AGTL+
10UF/6.3V
C517
10UF/6.3V
C524
0.1UF/10V
C531
0.1UF/10V
12
C535
c0805_h37
10UF/6.3V
GND
10UF/6.3V
C518
10UF/6.3V
@
C525
0.1UF/10V
C532
0.1UF/10V
10UF/6.3V
10UF/6.3V
12
10UF/6.3V
GND
C509
C519
C536
c0805_h37
@
C526
0.1UF/10V
C510
10UF/6.3V
C520
10UF/6.3V
C527
0.1UF/10V
GND
C511
10UF/6.3V
GND
C521
10UF/6.3V
GND
GND GND
<Variant Name>
4.0A
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
5
4
3
2
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg6.png)
5
4
3
2
1
PWM FAN
Control
5
FAN0_TACH34
R1.1
Item 11
L601
80Ohm/100Mhz
10mils
+3VS
12
34
GND
21
D D
OS#_OC
R1.1
Item 24
2
FAN_PWM34
C C
CPU FAN will be forced on:
1) Thermal Sensor Over-temperture
2) WATCHDOG asserted by EC
B B
WATCH_DOG#34
SYS_TEMP34
R1.1
Item 1
+3VS
R612
100KOhm
1 2
61
Q601A
UM6K1N
GND
D603
1N4148W
12
@
D604
1N4148W
12
@
+5V
+3VA
3
BAT54C
D606
1
2
Place L601, R615, C610, C3413
and D606 near IT8510E
R611
10KOhm
r0603_h24
@
Q601B
UM6K1N
12
GND
C610
1UF/10V
c0603
+5VS_FAN
12
+5V_TEMP
R601
10KOhm
r0603_h24
@
+3VS
GND
R615
4.7KOhm
1%
1 2
1 2
12
R603
10KOhm
12
C601
0.1UF/16V
@
R616
0Ohm
@
GND
GND
12
C604
0.1UF/25V
c0603
@
D602
1 2
1N4148W
C603
0.1U
@
1
2
3 4
U602
NC
SUB
GND VOUT
PST9013NR
@
(94~98'C protect)
VCC
+5VS
3
1
2
+5VA
R602
22.1K
1%
@
RT601
100K 1%
5
Enable: Turn OFF system
OPEN Collect
D601
BAT54C
@
+5VS_FAN
GND
GND
FORCE_OFF# 34,51,60
CON601
4
3
2
1 5
4
SIDE2
3
2
1 SIDE1
WtoB_CON_4P_1
6
P/N:12G17000004B
GND
R1.1
Item 25
GND
H_THERMDC4
12
C609
1UF/10V
c0603
@
H_THERMDC
H_THERMDA
+5VS +5VS_FAN
R614 0Ohm
1 2
12
C607
0.1UF/10V
12
GND
C608
22UF/10V
12
+
GNDGND
CE601
@
100uF/6.3V
CO-LAYOUT
Thermal Sensor
GND
+3VS_THM
C606
0.1U
C605
Enable: Turn OFF system
1000P
Slave address: 98h
Max: 1mA
U601
1
VCC
2
DXP
3
DXN
4
OVERT#
R610
200Ohm
OD
12
MAX6657MSA
SCLK
SDA
ALERT#
GND
+3VS
SMB1_CLK
8
SMB1_DAT
7
6
5
GND
OS#_OC 34
OD
Close to Pin A24
& A25 of CPU
D605
1N4148W
@
1 2
GND
SMB1_CLK 34
SMB1_DAT 34H_THERMDA4
THRM_ALERT# 34
R613 0Ohm
@
+VCCP_AGTL+
A A
H_THRMTRIP#4
GMCH_THRMTRIP#9
PLT_RST#9,21,23,25
5
4
R605
56Ohm
R607 0Ohm
+VCCP_AGTL+
B
E12
Q603
PMBS3904
R604
330
C602 0.1U
C
+3VS
R606
GND
10KOhm
S
3
3
2
ICH_THRMTRIP# 19
Enable: Turn OFF system
To EC(Internal Pull Hi)
Q602
H2N7002
D
3
G
1
THRMTRIP# 34
<Variant Name>
Title :
FAN_CTRL&Thernal
1
Marco Chen
663Monday, August 28, 2006
of
Rev
1.11
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet
2
T13Fv
Engineer:
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg7.png)
5
4
3
2
1
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
D D
POWERSAVE#
Q701A
61
UM6K1N
2
Q701B
34
UM6K1N
5
GND
C C
B B
A A
DREFSSCLKIN9
DREFSSCLKIN#9
CLK_USB4820
CLK_DBGPCI35
CLK_ECPCI34
CLK_DEBUG233
CLK_CBPCI27
CLK_ICHPCI21
R701 1KOhm
R702 1KOhm
R705 1KOhm
CPU_Select 20
ACIN_OC# 34,35,59
T705
TPC28T
SCL_3S14,15,20,33
SDA_3S14,15,20,33
5
MCH_BSEL0 9
MCH_BSEL1 9
MCH_BSEL2 9
GND
12
C712
27PF/50V
GND
CPU_BSEL04
CPU_BSEL14
1
C715 10PF/50V
C716 10PF/50V
C717 10PF/50V
@
@
@
BCLK
C701
10UF/6.3V
X701
12
14.318Mhz
R725 0Ohm
C718 10PF/50V
@
12
GND
1 2
C714 10PF/50V
C719 10PF/50V
@
@
GND
C709
0.1UF/16V
C713
27PF/50V
R733 2.2KOhm
C720 10PF/50V
@
Latched Input Select
/ PIN9 PIN5 PIN 17 PIN 18
* 0 X 27FIX 27SS
1 0 96MSS_T 96 MSS_ C
1 1 PCIEX0_T PCIEX0_C
FSLC FSLB FSLA
BSEL1
BSEL2FSB
533 L
L133
L
R714 2.2Ohm
POWERSAVE#
+3VS_VDDA
GND
R727 33Ohm
R729 33Ohm
R732 33Ohm
R738 33Ohm@
GND
+3VS
+3VS
R740 10KOhm
R742 33Ohm
R743 33Ohm
R745 33Ohm@
R747 10KOhm@
R749 33Ohm@
R752 33Ohm R753 33Ohm
R754 10KOhm
R756 0Ohm
1 2
R758 0Ohm
1 2
4
GND
H166 667
R762
475Ohm
1%
BSEL0
H
H
+3VS_CLK
XOUT_CLK
PCIE0
FSA
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
GND
+3VS
C706
10UF/6.3V
GND GND
12
R716
10KOhm
U701
21
VDDPCIEX1
28
VDDPCIEX2
42
VDDPCIEX3
34
PWRSAVE#
50
VDDCPU
45
VDDA
46
GNDA
58
X1
57
X2
17
27FIX/LCD_SSCGT/PCIEX0T
18
27SS/LCD_SSCGC/PCIEX0C
12
FSLA/USB_48MHz
16
FSLB/TEST_MODE
5
SELPCIEX0_LCD#PCICLK5
4
PCICLK4
3
PCICLK3
64
PCICLK2/REQ_SEL
9
SELLCD_27#/PCICLK_F1
8
ITP_EN/PCICLK_F0
54
SCLK
55
SDATA
47
IREF
2
GND1
6
GND2
13
GND3
29
GND4
37
GND5
53
GND6
59
GND7
ICS954310CGLFT
Int. PU: PIN5, PIN9, PIN32, PIN33, PIN34
Int. PD: PIN64
21
L702
120Ohm/100Mhz
1
7
VDDPCI1
VDDPCI2
CPUCLKT2_ITP/PCIEXT8
CPUCLKC2_ITP/PCIEXC8
REF1/FSLC/TEST_SEL
3
21
L701
120Ohm/100Mhz
+3VS_VDDPCI
VDD48
VDDREF
PCI/PCIEX_STOP#
CPU_STOP#
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
PEREQ1#/PCIEXT7
PEREQ2#/PCIEXC7
PCIEXT6
PCIEXC6
PCIEXT5
PCIEXC5
PCIEXT4
PCIEXC4
PCIEXT3
PCIEXC3
PCIEXT2
PCIEXC2
PCIEXT1
PCIEXC1
SATACLKT
SATACLKC
DOTT_96MHz
DOTC_96MHz
PEREQ3#
PEREQ4#
Vtt_PwrGd#/PD
REF0
C707
0.1UF/16V
GND
11
56
63
62
49
48
52
51
44
43
41
40
39
38
36
35
30
31
24
25
22
23
19
20
26
27
14
15
32
33
10
61
60
+3VS_CLK
C702
0.1UF/16V
C708
0.1UF/16V
+3VS_VDDREF
CLK_MCH
CLK_MCH#
CLK_CPUXIN_CLK
CLK_CPU#
PCIE8
PCIE#8
PEREQ#1PCIE#0
PEREQ#2
PCIE6
PCIE#6
PCIE5
PCIE#5
PCIE4
PCIE#4
PCIE3
PCIE#3
PCIE2
PCIE#2
PCIE1
PCIE#1
SATACLKT
SATACLKC
DOT96
DOT96#
REF1
REF0
C704
C703
0.1UF/16V
0.1UF/16V
R711
+3VS_VDD48
2.2Ohm
STP_PCI# 20
STP_CPU# 20
R721 33Ohm
R722 33Ohm
R723 33Ohm
R724 33Ohm
1
1
R730 10KOhm@
R731 10KOhm@
R734 33Ohm
R735 33Ohm
R736 33Ohm
R739 33Ohm
1
1
R771 33Ohm
R768 33Ohm
R751 33Ohm@
R764 33Ohm@
R755 33Ohm
R757 33Ohm
R759 33Ohm
R760 33Ohm
R761 33Ohm
T707
TPC28T
1
T706
1
TPC28T
R765
+3VS
10KOhm
R766 2.2KOhm
R767 33Ohm
GND
+3VS_CLK
C705
0.1UF/16V
R712
1Ohm
C710
0.1UF/16V
GND
C711 0.1UF/16V
CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8
CLK_CPU_BCLK 4
T701 TPC28T
T702 TPC28T
T703 TPC28T
T704 TPC28T
CLK_CPU_BCLK# 4
GND
GND
CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9
CLK_PCIE_MINICARD 26
CLK_PCIE_MINICARD# 26
CLK_PCIE_LAN 29
CLK_PCIE_LAN# 29
CLK_PCIE_NEWCARD 33
CLK_PCIE_NEWCARD# 33
CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21
CLK_SATA_ICH 19
CLK_SATA_ICH# 19
DREFCLKIN 9
DREFCLKIN# 9
CLK_REQ_NEWCARD# 33
CLK_REQ_MINICARD# 26
CLK_EN# 50
From Power
CPU_BSEL2 4
CLK_ICH14 20
C721
@
10PF/50V
2
PLACE termination close to source IC
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_PCIE_MINICARD
CLK_PCIE_MINICARD#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
GND
ITP_EN/PCICLK_F0
(PIN8)
SELPCIE0_LCD#/PCI_CLK5
(PIN5)
PCI_CLK2/REQ_SEL
(PIN64)
SELLCD_27#/PCICLK_F1
<Variant Name>
(PIN9)
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_NEWCARD
CLK_PCIE_NEWCARD#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_SATA_ICH
CLK_SATA_ICH#
DREFCLKIN
DREFCLKIN#
DREFSSCLKIN
DREFSSCLKIN#
PEREQ#1: PCIEX0, PCIEX6
PEREQ#2: PCIEX1, PCIEX8
PEREQ#3: PCIEX2, PCIEX4
PEREQ#4: PCIEX3, PCIEX5, PCIEX7
R703 49.9Ohm 1%
R704 49.9Ohm 1%
R706 49.9Ohm 1%
R708 49.9Ohm 1%
R709 49.9Ohm 1%
R710 49.9Ohm 1%
R713 49.9Ohm 1%
R715 49.9Ohm 1%
R717 49.9Ohm 1%
R718 49.9Ohm 1%
R763 49.9Ohm 1%@
R750 49.9Ohm 1%@
R769 49.9Ohm 1%
R770 49.9Ohm 1%
R726 49.9Ohm 1%
R728 49.9Ohm 1%
R737 49.9Ohm 1%
R741 49.9Ohm 1%
R744 49.9Ohm 1%
R746 49.9Ohm 1%
0 = SRC Pair
1 = CPU_ITP Pair
0 = LCD Clock (96MHz)
1 = PCI Express (100MHz) (D)
0 = PCICLK(D)
1 = PEREQ#
0 = 27MHzSS/27MHzSS# Pa i r
1 = LCD_CLK Pair (D)
Title :
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
T13Fv
Engineer:
1
ICS954310
Marco Chen
763Monday, August 28, 2006
GND
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg8.png)
5
4
3
2
1
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
J7
W8
U3
AB10
K4
T7
Y5
AC4
K3
T6
AA5
AC5
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
E3
E7
H_A#[3..31]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_RS#0
H_RS#1
H_RS#2
R810 0Ohm
H_A#[3..31] 4
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_CPURST# 4
H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
H_DRDY# 4
H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4
H_DSTBN#0 4
H_DSTBN#1 4
H_DSTBN#2 4
H_DSTBN#3 4
H_DSTBP#0 4
H_DSTBP#1 4
H_DSTBP#2 4
H_DSTBP#3 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_VREF
H_CPURST#
H_REQ#[4..0] 4
H_RS#[0..2] 4
H_CPUSLP# 4,19
H_TRDY# 4
AGTL+ I/O Voltage
Reference
+VCCP_AGTL+
R803
100Ohm
<500 mil (55 Ohm)
1%
T/B trace 5.5 ,
Space 25
R806
200Ohm
1%
T801
TPC28T
1
C802
0.1UF/16V
GNDGND
H_D#[0..63]4
D D
RCOMP
For Calibrating FSB I/O Buffer
H_XRCOMP
R801
24.9Ohm
1%
GND GND
10/20mils
H_YRCOMP
R802
24.9Ohm
1%
10/20mils
SCOMP
For Slew Rate Compensation on the FSB
+VCCP_AGTL+
C C
R804
54.9Ohm
1%
H_XSCOMP
+VCCP_AGTL+
R805
54.9Ohm
1%
H_YSCOMP
5.5/20 mils5.5/20 mils
Voltage Swing
For Providing a Reference Voltage to The FSB RCOMP Circuit
+VCCP_AGTL+
R807
221Ohm
1%
1 2
B B
R808
100Ohm
1%
+VCCP_AGTL+
R809
221Ohm
1%
1 2
R811
100Ohm
1%
GNDGND
H_XSWING
C801
0.1UF/16V
H_YSWING
C803
0.1UF/16V
12/20mils
12/20mils
CLK_MCH_BCLK7
CLK_MCH_BCLK#7
H_D#[0..63]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP H_REQ#4
H_YSWING
W11
AB7
AA9
Y10
AB8
AA4
AA7
AA2
AA6
AA10
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
AG2
AG1
K11
T10
U11
T11
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
G4
T3
U7
U9
W9
T1
T8
T4
W7
U5
T9
W6
T5
W4
W3
Y3
Y7
W5
W2
Y8
E1
E2
E4
Y1
U1
W1
U801A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
H_CLKIN
H_CLKIN#
HOST
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_AVREF
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_DVREF
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
GNDGND
A A
<Variant Name>
Title :
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
5
4
3
2
T13Fv
Engineer:
1
Calistoga--CPU
Marco Chen
863Monday, August 28, 2006
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg9.png)
5
D D
U801B
T32
RSVD_1
R32
RSVD_2
F3
RSVD_3
F7
RSVD_4
AG11
RSVD_5
AF11
RSVD_6
H7
RSVD_7
J19
RSVD_8
K30
TV_DCONSEL_0
J29
TV_DCONSEL_1
A41
RSVD_11
A35
RSVD_12
A34
RSVD_13
AH33
AH34
BA41
BA40
BA39
AY41
AW41
AW1
D28
D27
K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26
G28
F25
H26
H28
H27
K28
H32
C41
BA3
BA2
BA1
B41
AY1
A40
A39
G6
D1
C1
B2
A4
A3
RSVD_14
RSVD_15
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
PWROK
RSTIN#
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC#
CLK_REQ#
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
011=667MHz
001=533MHz
MCH_BSEL07
MCH_BSEL17
MCH_BSEL27
C C
B B
GMCH_THRMTRIP#6
ICH7_PWROK20,27,34
PLT_RST#6,21,23,25
MCH_ICH_SYNC#21
+3VS
MCH_CFG_513
MCH_CFG_713
MCH_CFG_913
MCH_CFG_1013
MCH_CFG_1113
MCH_CFG_1213
MCH_CFG_1313
MCH_CFG_1513
MCH_CFG_1613
MCH_CFG_1813
MCH_CFG_1913
PM_BMBUSY#20
R911 10KOhm
R912 10KOhm
T901
1
TPC28T
R901 100Ohm
T906TPC28T
1
T907TPC28T
1
T908
1
TPC28T
PM_EXTTS#0
PM_EXTTS#1
PM_EXTTS#0
PM_EXTTS#1
RSVD
CFG
PM
MISC NC
DDR MUXINGCLK
DMI
4
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_OCDCOMP_0
SM_OCDCOMP_1
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP#
SM_RCOMP
SM_VREF_0
SM_VREF_1
G_CLKIN#
G_CLKIN
D_REFCLKIN#
D_REFCLKIN
D_REFSSCLKIN#
D_REFSSCLKIN
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AY35
AR1
AW7
AW40
AW35
AT1
AY7
AY40
AU20
AT20
BA29
AY29
AW13
AW12
AY21
AW21
AL20
AF10
BA13
BA12
AY20
AU21
AV9
AT9
AK1
AK41
AF33
AG33
A27
A26
C40
D41
AE35
AF39
AG35
AH39
AC35
AE39
AF35
AG39
AE37
AF41
AG37
AH41
AC37
AE41
AF37
AG41
M_CKE0
M_CKE1
M_CKE2
M_CKE3
M_CS#0
M_CS#1
M_CS#2
M_CS#3
M_OCDCOMP0
M_OCDCOMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
M_RCOMP#
M_RCOMP
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
VTT_REF
M_CLK_DDR0 14
M_CLK_DDR1 14
M_CLK_DDR2 15
M_CLK_DDR3 15
M_CLK_DDR#0 14
M_CLK_DDR#1 14
M_CLK_DDR#2 15
M_CLK_DDR#3 15
M_CKE[0..3] 14,15,16
M_CS#[0..3] 14,15,16
Layout Note: Route as
R906 40.2Ohm 1%@
R907 40.2Ohm 1%@
R908 80.6Ohm 1%
R909 80.6Ohm 1%
short as possible.
M_ODT[0..3] 14,15,16
+1.8V
VTT_REF
CLK_MCH_3GPLL# 7
CLK_MCH_3GPLL 7
DREFCLKIN# 7
DREFCLKIN 7
DREFSSCLKIN# 7
DREFSSCLKIN 7
DMI_TXN[0..3] 21
DMI_TXP[0..3] 21
DMI_RXN[0..3] 21
DMI_RXP[0..3] 21
GND
EDID_CLK17
EDID_DAT17
GND
GND
3
+3VS
10KOhm
10KOhm
10KOhm
10KOhm
RN903C
RN903B
RN903D
RN903A
5 6
3 4
7 8
R905
1.5KOhm
1%
GND
R910
255Ohm
L_IBG
12
1 2
L_BKLTEN_V17
L_VDD_EN17
LVDS_LCLKN17
LVDS_LCLKP17
LVDS_L0N17
LVDS_L1N17
LVDS_L2N17
LVDS_L0P17
LVDS_L1P17
LVDS_L2P17
CRT_BLUE18
CRT_GREEN18
CRT_RED18
CRT_DDC_CLK18
CRT_DDC_DATA18
CRT_HSYNC18
CRT_VSYNC18
GND
T902
TPC28T
T905
TPC28T
+1.5VS
CRT_IREF
1
1
GND
D32
H30
H29
G26
G25
B38
C35
F32
C33
C32
A33
A32
E27
E26
C37
B35
A37
B37
B34
A36
G30
D30
F29
F30
D29
F28
A16
C18
A19
B16
B18
B19
E23
D23
C22
B22
A21
B21
C26
C25
G23
H23
U801C
J30
J20
J22
2
L_BKLTCTL
L_BKLTEN
L_CLK_CTLA
L_DATA_CTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL
LA_CLK#
LA_CLK
LB_CLK#
LB_CLK
LA_DATA#_0
LA_DATA#_1
LA_DATA#_2
LA_DATA_0
LA_DATA_1
LA_DATA_2
LB_DATA#_0
LB_DATA#_1
LB_DATA#_2
LB_DATA_0
LB_DATA_1
LB_DATA_2
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC
LVDS
TV
VGA
PEG_COMP
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
PCI-EXPRESS GRAPHICS
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
D40
D38
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
1
R904 24.9Ohm
1%
+1.5VS_PCIE
C901
A A
5
4
1UF/6.3V
GND
C902
0.1UF/16V
GND
3
CRT_BLUE
CRT_GREEN
CRT_RED
R1.1
Item 27
12
C905
33PF/50V
c0402
GND GND GND
12
C904
33PF/50V
c0402
12
Place C903, C904, C905 near NB
C903
33PF/50V
c0402
+VCCP_GMCH
GND
2
C906
0.1UF/16V
1 2
c0402
@
<Variant Name>
Title :
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
T13Fv
Engineer:
Calistoga--PCIE
Marco Chen
963Monday, August 28, 2006
1
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bga.png)
5
D D
M_A_DQ[0..63]14
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
C C
B B
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
U801D
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
DDR SYSTEM MEMORY A
SA_RCVENOUT#
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVENIN#
SA_WE#
4
AU12
AV14
BA20
AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
AW14
AK23
AK24
AY14
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_BS#0 14,16
M_A_BS#1 14,16
M_A_BS#2 14,16
M_A_CAS# 14,16
M_A_RAS# 14,16
M_A_WE# 14,16
M_A_DM[0..7] 14
M_A_DQS[0..7] 14
M_A_DQS#[0..7] 14
M_A_A[0..13] 14,16
3
M_B_DQ[0..63]15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AN10
AK13
AH11
AK10
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
U801E
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
AJ9
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
AJ8
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
AJ5
SB_DQ62
AJ3
SB_DQ63
2
AT24
SB_BS_0
AV23
SB_BS_1
AY28
SB_BS_2
AR24
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
DDR SYSTEM MEMORY B
SB_MA_13
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
AU23
AK16
AK18
AR27
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_BS#0 15,16
M_B_BS#1 15,16
M_B_BS#2 15,16
M_B_CAS# 15,16
M_B_DM[0..7] 15
M_B_DQS[0..7] 15
M_B_DQS#[0..7] 15
M_B_A[0..13] 15,16
M_B_RAS# 15,16
M_B_WE# 15,16
1
A A
<Variant Name>
Title :
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
5
4
3
2
T13Fv
Engineer:
1
Calistoga--DDR2
Marco Chen
10 63Monday, August 28, 2006
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bgb.png)
5
+2.5VS
C1101
10UF/6.3V
D D
+1.5VS
+3VS +VCCA_TVBG
C C
+1.5VS
B B
A A
C1103
C1104
0.1UF/16V
0.022UF/16V
L1102
120Ohm/100Mhz
L1105
120Ohm/100Mhz
+1.5VS_3GPLL
21
C1111
10UF/6.3V
C1121
0.022UF/16V
NOTE:0.1uF caps in
1.5SxPLL need to be
located as edge caps
within 200 mils.
L1106
120Ohm/100Mhz
21
L1108
120Ohm/100Mhz
21
L1109
120Ohm/100Mhz
21
L1110
120Ohm/100Mhz
21
GND
GND
C1125
10UF/10V
1 2
C1130
10UF/10V
1 2
C1138
10UF/10V
1 2
C1140
10UF/10V
1 2
5
C1112
0.1UF/16V
C1122
0.1UF/16V
+1.5VS
L1101 80Ohm/100Mhz
C1105
0.1UF/16V
GND GND
+2.5VS +VCCA_CRTDAC
+1.5VS_DPLLA
C1126
0.1UF/16V
GND
+1.5VS_DPLLB
C1131
0.1UF/16V
GND
+1.5VS_HPLL
C1139
0.1UF/16V
GND
+1.5VS_MPLL
C1141
0.1UF/16V
GND
12
+
CE1102
220UF/2V
L1103
120Ohm/100Mhz
C1113
0.022UF/16V
+2.5VS
R1101
1 2
10Ohm
R1102
1 2
10Ohm
1.425V~1.575V
Max: 40mA
1.425V~1.575V
Max: 40mA
1.425V~1.575V
Max: 45mA
1.425V~1.575V
Max: 45mA
C1106
10UF/6.3V
4
+1.5VS_PCIE
C1107
0.1UF/16V
C1114
0.1UF/16V
GND
2
1
2
1
+3VS
C1132
10UF/6.3V
NOTE:0.1UF CAPS USED IN
+1.5VS, +3VS
+2.5VS should be placed within
200 mils of edge.
D1101
RB717F
D1102
RB717F
4
+1.5VS
C1118
0.1UF/16V
GND
+VCCP_AGTL+
3
+1.5VS+3VS
3
+1.5VS
C1133
0.1UF/16V
12
+
CE1101
@
220UF/2V
R1.1
Item 27
+2.5VS
+1.5VS_PCIE
1.425V~1.575V
Max: 1.5A
+1.5VS_3GPLL
+2.5VS
+VCCA_CRTDAC
R1103 0Ohm
GND
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+2.5VS
+1.5VS_MPLL
+1.5VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
+1.5VS
C1134
10UF/6.3V
GNDGND
1 2
+3VS
C1135
0.1UF/16V
GND
GND
GND
GND
+2.5VS
C1102
0.1UF/16V
3
3
H22
C30
B30
A30
AJ41
AB41
Y41
V41
R41
N41
AC33
G41
H41
E21
G21
B26
C39
AF1
A38
B39
AF2
H20
G20
E19
C20
D20
E20
AH1
AH2
A28
B28
C28
D21
A23
B23
B25
H19
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12
L41
F21
F19
F20
U801H
VCCSYNC
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VSSA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCD_TVDAC
VCC_HV0
VCC_HV1
VCC_HV2
VCCD_QTVDAC
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
POWER
VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76
2
AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1
2
+VCCP_AGTL+
VTTLF_CAP3
VTTLF_CAP2
VTTLF_CAP1
1
0.9475V~1.1025V
Max: 1.4A
PLACE IN CAVITY
C1108
0.47UF/16V
GND GND
C1129
0.47UF/16V
GND
C1136
0.47UF/16V
1 2
GND GND
<Variant Name>
10UF/6.3V
C1137
0.1UF/16V
PLACE ON THE EDGE
C1109
C1110
0.1UF/16V
1 2
Title :
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
T13Fv
Engineer:
1
+VCCP_AGTL+
12
+
CE1103
220UF/2V
Calistoga--POWER
Marco Chen
11 63Monday, August 28, 2006
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bgc.png)
+VCCP_GMCH
D D
C C
B B
A A
AA33
W33
AA32
W32
M32
AA31
W31
V31
R31
P31
N31
M31
AA30
W30
V30
U30
R30
P30
N30
M30
AA29
W29
V29
U29
R29
P29
M29
AB28
AA28
V28
U28
R28
P28
N28
M28
P27
N27
M27
P26
N26
N25
M25
P24
N24
M24
AB23
AA23
P23
N23
M23
AC22
AB22
W22
P22
N22
M22
AC21
AA21
W21
N21
M21
AC20
AB20
W20
P20
N20
M20
AB19
AA19
N19
M19
N18
M18
P17
N17
M17
N16
M16
P33
N33
L33
J33
Y32
V32
P32
N32
L32
J32
T31
Y30
T30
L30
Y29
L29
Y28
T28
L28
L27
L26
L25
Y23
L23
Y22
L22
L21
Y20
L20
Y19
L19
L18
L16
U801F
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
5
+1.8V
AU41
VCC_SM_0
AT41
VCC_SM_1
AM41
VCC_SM_2
AU40
VCC_SM_3
BA34
VCC_SM_4
AY34
VCC_SM_5
AW34
VCC_SM_6
AV34
VCC_SM_7
AU34
VCC_SM_8
AT34
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC
5
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99
VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
4
VCCSM_LF4
VCCSM_LF5
C1201
0.47UF/16V
GND GND
C1203
0.47UF/16V
GND
C1206
0.47UF/16V
GND
VCCSM_LF2
VCCSM_LF1
C1211
0.47UF/16V
GND GND
4
+VCCP_GMCH
C1202
0.47UF/16V
C1212
0.47UF/16V
+1.8V
AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18
C1204
10UF/6.3V
U801G
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
JP1201
1 2
SHORT_PIN
@
C1205
10UF/6.3V
NCTF
C1216
0.1UF/16V
+VCCP+VCCP_GMCH
C1215
0.1UF/16V
3
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
C1213
0.1UF/16V
GND
3
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
+1.5VS
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
C1214
0.1UF/16V
GND
GND
+VCCP_GMCH
AV10
AP10
AL10
AJ10
AG10
AC10
W10
AW9
AG8
AG6
AW3
AG3
12
+
CE1201
220UF/2V
D11
B11
U10
BA9
AR9
AH9
AB9
AD8
AA8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
AD6
AB6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
AY3
AV3
AL3
AH3
AF3
AD3
AC3
AA3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
AL1
2
U801J
J11
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
Y9
VSS_289
R9
VSS_290
G9
VSS_291
E9
VSS_292
A9
VSS_293
VSS_294
VSS_295
VSS_296
U8
VSS_297
K8
VSS_298
C8
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
R7
VSS_308
G7
VSS_309
D7
VSS_310
VSS_311
VSS_312
VSS_313
Y6
VSS_314
U6
VSS_315
N6
VSS_316
K6
VSS_317
H6
VSS_318
B6
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
Y4
VSS_328
U4
VSS_329
R4
VSS_330
J4
VSS_331
F4
VSS_332
C4
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
G3
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
Y2
VSS_352
U2
VSS_353
T2
VSS_354
N2
VSS_355
J2
VSS_356
H2
VSS_357
F2
VSS_358
C2
VSS_359
VSS_360
C1207
10UF/6.3V
VSS
C1208
0.1UF/16V
C1209
10UF/6.3V
2
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
GND
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
C1210
0.1UF/16V
GND
U801I
AK34
VSS_97
AG34
VSS_98
AF34
VSS_99
AE34
VSS_100
AC34
VSS_101
C34
VSS_102
AW33
VSS_103
AV33
VSS_104
AR33
VSS_105
AE33
VSS_106
AB33
VSS_107
Y33
VSS_108
V33
VSS_109
T33
VSS_110
R33
VSS_111
M33
VSS_112
H33
VSS_113
G33
VSS_114
F33
VSS_115
D33
VSS_116
B33
VSS_117
AH32
VSS_118
AG32
VSS_119
AF32
VSS_120
AE32
VSS_121
AC32
VSS_122
AB32
VSS_123
G32
VSS_124
B32
VSS_125
AY31
VSS_126
AV31
VSS_127
AN31
VSS_128
AJ31
VSS_129
AG31
VSS_130
AB31
VSS_131
Y31
VSS_132
AB30
VSS_133
E30
VSS_134
AT29
VSS_135
AN29
VSS_136
AB29
VSS_137
T29
VSS_138
N29
VSS_139
K29
VSS_140
G29
VSS_141
E29
VSS_142
C29
VSS_143
B29
VSS_144
A29
VSS_145
BA28
VSS_146
AW28
VSS_147
AU28
VSS_148
AP28
VSS_149
AM28
VSS_150
AD28
VSS_151
AC28
VSS_152
W28
VSS_153
J28
VSS_154
E28
VSS_155
AP27
VSS_156
AM27
VSS_157
AK27
VSS_158
J27
VSS_159
G27
VSS_160
F27
VSS_161
C27
VSS_162
B27
VSS_163
AN26
VSS_164
M26
VSS_165
K26
VSS_166
F26
VSS_167
D26
VSS_168
AK25
VSS_169
P25
VSS_170
K25
VSS_171
H25
VSS_172
E25
VSS_173
D25
VSS_174
A25
VSS_175
BA24
VSS_176
AU24
VSS_177
AL24
VSS_178
AW23
VSS_179
<Variant Name>
GND GND
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
T13Fv
1
VSS
Title :
Engineer:
1
AC41
VSS_0
AA41
VSS_1
W41
VSS_2
T41
VSS_3
P41
VSS_4
M41
VSS_5
J41
VSS_6
F41
VSS_7
AV40
VSS_8
AP40
VSS_9
AN40
VSS_10
AK40
VSS_11
AJ40
VSS_12
AH40
VSS_13
AG40
VSS_14
AF40
VSS_15
AE40
VSS_16
B40
VSS_17
AY39
VSS_18
AW39
VSS_19
AV39
VSS_20
AR39
VSS_21
AN39
VSS_22
AJ39
VSS_23
AC39
VSS_24
AB39
VSS_25
AA39
VSS_26
Y39
VSS_27
W39
VSS_28
V39
VSS_29
T39
VSS_30
R39
VSS_31
P39
VSS_32
N39
VSS_33
M39
VSS_34
L39
VSS_35
J39
VSS_36
H39
VSS_37
G39
VSS_38
F39
VSS_39
D39
VSS_40
AT38
VSS_41
AM38
VSS_42
AH38
VSS_43
AG38
VSS_44
AF38
VSS_45
AE38
VSS_46
C38
VSS_47
AK37
VSS_48
AH37
VSS_49
AB37
VSS_50
AA37
VSS_51
Y37
VSS_52
W37
VSS_53
V37
VSS_54
T37
VSS_55
R37
VSS_56
P37
VSS_57
N37
VSS_58
M37
VSS_59
L37
VSS_60
J37
VSS_61
H37
VSS_62
G37
VSS_63
F37
VSS_64
D37
VSS_65
AY36
VSS_66
AW36
VSS_67
AN36
VSS_68
AH36
VSS_69
AG36
VSS_70
AF36
VSS_71
AE36
VSS_72
AC36
VSS_73
C36
VSS_74
B36
VSS_75
BA35
VSS_76
AV35
VSS_77
AR35
VSS_78
AH35
VSS_79
AB35
VSS_80
AA35
VSS_81
Y35
VSS_82
W35
VSS_83
V35
VSS_84
T35
VSS_85
R35
VSS_86
P35
VSS_87
N35
VSS_88
M35
VSS_89
L35
VSS_90
J35
VSS_91
H35
VSS_92
G35
VSS_93
F35
VSS_94
D35
VSS_95
AN34
VSS_96
Calistoga--GND
Marco Chen
12 63Monday, August 28, 2006
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bgd.png)
5
4
3
2
1
MCH_CFG_59
GND
R1301
2.2KOhm
@
D D
CFG5 : DMI STRAP
LOW = DMI X 2
HIGH = DMI X 4 (Default)
MCH_CFG_129
R1302
2.2KOhm
@
GND
CFG[13:12] : GMCH TEST MODE SELECT
00 = Partial CLK gating disable
01 = XOR Mode Enable
10 = ALL Z Mode Enable
MCH_CFG_79 MCH_CFG_139
R1303
2.2KOhm
@
GND
C C
MCH_CFG_99
R1305
2.2KOhm
@
GND
MCH_CFG_109
R1308
2.2KOhm
@
GND
CFG7 : CPU STRAP
LOW = RESERVED
HIGH = Mobile Yonah CPU (Default)
CFG9 : PCIE GRAPHIC LANE
LOW = REVERSE LANE
HIGH = NORMAL OPERATION (Default)
CFG10 : HOST PLL VCO SELECT
LOW = RESERVED
HIGH = MOBILITY (Default)
R1304
2.2KOhm
@
GND
MCH_CFG_159
R1306
2.2KOhm
@
GND
MCH_CFG_169
R1307
2.2KOhm
@
GND
11 = NORMAL OPERATION (D efa u lt )
CFG15 : ICH RESET Disable
LOW = ICH RESET Disabled
HIGH = Normal Operation (Default)
CFG16 : FSB Dynamic ODT
LOW = Dynamic ODT Disabled
HIGH = Dynamic ODT Enabled (Defa ult )
B B
MCH_CFG_119
R1310
2.2KOhm
@
GND
CFG[17..3] have internal pullup resistors.
CFG[19..18] have internal pulldown resistors.
SDVOCRTL_DATA has internal pulldown resistors.
A A
5
CFG11 : PSB 4x CLK ENABLE
LOW = 4X ENABLED
HIGH = 8X ENABLED (Default)
4
MCH_CFG_189
MCH_CFG_199
3
+3VS
+3VS
R1309
1KOhm
@
R1311
1KOhm
@
CFG18 : GMCH Core Voltage Level
LOW = 1.05V (Default)
HIGH = 1.5V
CFG19 : DMI LANE REVERSAL
LOW = NORMAL (Default)
HIGH = LANES REVERSED
<Variant Name>
Date: Sheet of
2
ASUSTeK COMPUTER INC
Size Project Name
Custom
T13Fv
Title :
Engineer:
1
Calistoga--Strap
Marco Chen
13 63Monday, August 28, 2006
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bge.png)
5
4
3
2
1
DDR2 HAD SWAPED.
D D
SMBus Slave Address:A0H
M_CLK_DDR0
C1401
@
10PF/50V
1 2
M_CLK_DDR#0
M_CLK_DDR1
C1402
@
10PF/50V
1 2
M_CLK_DDR#1
C C
GND
B B
PLACE NEAR SO-DIMM_0
PLACE NEAR SO-DIMM_0
RN1401A
RN1401B
1 2
10KOhm
3 4
10KOhm
M_A_A[0..13]10,16
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_BS#210,16
M_A_BS#010,16
M_A_BS#110,16
M_CS#09,16
M_CS#19,16
M_CLK_DDR09
M_CLK_DDR#09
M_CLK_DDR19
M_CLK_DDR#19
M_CKE09,16
M_CKE19,16
M_A_CAS#10,16
M_A_RAS#10,16
M_A_WE#10,16
SCL_3S7,15,20,33
SDA_3S7,15,20,33
M_ODT09,16
M_ODT19,16
M_A_DM[0..7]10
M_A_DQS[0..7]10
M_A_DQS#[0..7]10
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
CON141A
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16_BA2
107
BA0
106
BA1
110
S0#
115
S1#
30
CK0
32
CK0#
164
CK1
166
CK1#
79
CKE0
80
CKE1
113
CAS#
108
RAS#
109
WE#
198
SA0
200
SA1
197
SCL
195
SDA
114
ODT0
119
ODT1
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
11
DQS#0
29
DQS#1
49
DQS#2
68
DQS#3
129
DQS#4
146
DQS#5
167
DQS#6
186
DQS#7
DDR2_DIMM_200P
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ9
M_A_DQ12
M_A_DQ14
M_A_DQ15
M_A_DQ8
M_A_DQ13
M_A_DQ11
M_A_DQ10
M_A_DQ20
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ16
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ46
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ42
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ60
M_A_DQ63
M_A_DQ59
M_A_DQ57
M_A_DQ61
M_A_DQ58
M_A_DQ62
M_A_DQ[0..63] 10
0
1
12
C1403
2.2UF/6.3V
c0603
@
2
3
4
5
6
Layout Note: Place these Caps near SO DIMM 0
7
+1.8V
12
C1407
0.1UF/16V
12
C1408
0.1UF/16V
12
C1409
0.1UF/16V
+3VS
GND
12
C1404
0.1UF/16V
12
C1405
2.2UF/6.3V
c0603
12
C1410
0.1UF/16V
VTT_REF
12
GND
C1406
0.1UF/16V
+1.8V
CON141B
112
VDD1
111
VDD2
117
VDD3
96
VDD4
95
VDD5
118
VDD6
81
VDD7
82
VDD8
87
VDD9
103
VDD10
88
VDD11
104
VDD12
199
VDDSPD
83
NC1
120
NC2
50
NC3
69
NC4
163
NCTEST
1
VREF
201
GND0
202
GND1
203
NP_NC1
204
NP_NC2
47
VSS1
133
VSS2
183
VSS3
77
VSS4
12
VSS5
48
VSS6
184
VSS7
78
VSS8
71
VSS9
72
VSS10
121
VSS11
122
VSS12
196
VSS13
193
VSS14
8
VSS15
DDR2_DIMM_200P
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
GNDGND
Hight: 4.0 mm
P/N:12G025022004
+1.8V
12
C1411
1UF/10V
A A
5
4
3
c0603
12
C1412
1UF/10V
c0603
12
C1413
1UF/10V
c0603
12
GND
C1414
1UF/10V
c0603
12
C1415
1UF/10V
c0603
<Variant Name>
GND
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
2
T13Fv
Title :
Engineer:
1
DDR2 SO-DIMM_0
Marco Chen
14 63Monday, August 28, 2006
Rev
1.11
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bgf.png)
5
4
3
2
1
DDR2 HAD SWAPED.
GND
12
C1505
0.1UF/16V
+1.8V
CON151B
112
VDD1
111
VDD2
117
VDD3
96
VDD4
95
VDD5
118
VDD6
81
VDD7
82
VDD8
87
VDD9
103
VDD10
88
VDD11
104
VDD12
199
VDDSPD
83
NC1
120
NC2
50
NC3
69
NC4
163
NCTEST
1
VREF
201
GND0
202
GND1
203
NP_NC1
204
NP_NC2
47
VSS1
133
VSS2
183
VSS3
77
VSS4
12
VSS5
48
VSS6
184
VSS7
78
VSS8
71
VSS9
72
VSS10
121
VSS11
122
VSS12
196
VSS13
193
VSS14
8
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
DDR2_DIMM_200P
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
GNDGND
Layout Note: Place these Caps near SO DIMM 1
+1.8V
12
+1.8V
12
C1513
1UF/10V
c0603
<Variant Name>
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
2
C1506
0.1UF/16V
12
12
C1514
1UF/10V
c0603
T13Fv
C1507
0.1UF/16V
12
C1515
1UF/10V
c0603
Engineer:
12
C1508
0.1UF/16V
12
Title :
1
12
C1509
0.1UF/16V
GND
12
C1516
1UF/10V
c0603
GND
C1517
1UF/10V
c0603
DDR2 SO-DIMM_1
Marco Chen
15 63Monday, August 28, 2006
Rev
1.11
M_CLK_DDR2
@
M_CLK_DDR#2
@
M_CLK_DDR#3
+3VS
RN1401C
RN1401D
GND
PLACE NEAR SO-DIMM_1
PLACE NEAR SO-DIMM_1
5 6
10KOhm
7 8
10KOhm
C1501
D D
C C
B B
10PF/50V
1 2
C1502
10PF/50V
1 2
M_B_A[0..13]10,16
M_B_BS#210,16
M_B_BS#010,16
M_B_BS#110,16
M_CS#29,16
M_CS#39,16
M_CLK_DDR39
M_CLK_DDR#39
M_CLK_DDR29
M_CLK_DDR#29
M_CKE29,16
M_CKE39,16
M_B_CAS#10,16
M_B_RAS#10,16
M_B_WE#10,16
SCL_3S7,14,20,33
SDA_3S7,14,20,33
M_ODT29,16
M_ODT39,16
M_B_DM[0..7]10
M_B_DQS[0..7]10
M_B_DQS#[0..7]10
SMBus Slave Address:A4H
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7M_CLK_DDR3
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM6
M_B_DM7
M_B_DM5
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS6
M_B_DQS7
M_B_DQS5
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#6
M_B_DQS#7
M_B_DQS#5
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
107
106
110
115
30
32
164
166
79
80
113
108
109
198
200
197
195
114
119
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
CON151A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
BA0
BA1
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DDR2_DIMM_200P
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_B_DQ[0..63] 10
M_B_DQ0
5
M_B_DQ1
7
M_B_DQ2
17
M_B_DQ3
19
M_B_DQ4
4
M_B_DQ5
6
M_B_DQ6
14
M_B_DQ7
16
M_B_DQ8
23
M_B_DQ10
25
M_B_DQ9
35
M_B_DQ11
37
M_B_DQ12
20
M_B_DQ13
22
M_B_DQ14
36
M_B_DQ15
38
M_B_DQ21
43
M_B_DQ17
45
M_B_DQ20
55
M_B_DQ18
57
M_B_DQ19
44
M_B_DQ16
46
M_B_DQ22
56
M_B_DQ23
58
M_B_DQ24
61
M_B_DQ25
63
M_B_DQ29
73
M_B_DQ27
75
M_B_DQ28
62
M_B_DQ26
64
M_B_DQ30
74
M_B_DQ31
76
M_B_DQ32
123
M_B_DQ33
125
M_B_DQ34
135
M_B_DQ35
137
M_B_DQ36
124
M_B_DQ38
126
M_B_DQ37
134
M_B_DQ39
136
M_B_DQ48
141
M_B_DQ52
143
M_B_DQ55
151
M_B_DQ50
153
M_B_DQ49
140
M_B_DQ53
142
M_B_DQ54
152
M_B_DQ51
154
M_B_DQ60
157
M_B_DQ62
159
M_B_DQ61
173
M_B_DQ63
175
M_B_DQ57
158
M_B_DQ56
160
M_B_DQ58
174
M_B_DQ59
176
M_B_DQ43
179
M_B_DQ46
181
M_B_DQ45
189
M_B_DQ44
191
M_B_DQ47
180
M_B_DQ42
182
M_B_DQ41
192
M_B_DQ40
194
0
1
2
+3VS
12
GND
VTT_REF
12
C1503
0.1UF/16V
C1504
2.2UF/6.3V
c0603
3
4
6
7
5
Hight: 9.2 mm
P/N:12G025C22004
+0.9V
R1.1
Item 2
+1.8V
12
R1502
1KOhm
1%
GND
@
R1501
1KOhm
1%
@
4
12
A A
5
C1518
0.1UF/10V
c0402
@
C1520
0.1UF/10V
c0402
@
L1501
2 1
120Ohm/100Mhz
L1502
2 1
120Ohm/100Mhz
@
VTT_REF
GND
C1512
10UF/6.3V
3
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg10.png)
5
4
3
2
1
+0.9VS
D D
C C
B B
A A
GND
GND
GND
GND
GND
GND
GND
1 2
0.1UF/25V
3 4
0.1UF/25V
5 6
0.1UF/25V
7 8
0.1UF/25V
1 2
0.1UF/25V
3 4
0.1UF/25V
5 6
0.1UF/25V
7 8
0.1UF/25V
1 2
0.1UF/25V
3 4
0.1UF/25V
5 6
0.1UF/25V
7 8
0.1UF/25V
1 2
0.1UF/25V
3 4
0.1UF/25V
5 6
0.1UF/25V
7 8
0.1UF/25V
1 2
0.1UF/25V
3 4
0.1UF/25V
5 6
0.1UF/25V
7 8
0.1UF/25V
1 2
0.1UF/25V
3 4
0.1UF/25V
5 6
0.1UF/25V
7 8
0.1UF/25V
1 2
1 2
CN1601A
CN1601B
CN1601C
CN1601D
CN1602A
CN1602B
CN1602C
CN1602D
CN1603A
CN1603B
CN1603C
CN1603D
CN1604A
CN1604B
CN1604C
CN1604D
C16010.1UF/10V
C16020.1UF/10V
CN1605A
CN1605B
CN1605C
CN1605D
CN1606A
CN1606B
CN1606C
CN1606D
Layout note: Place array cap close to each pullup resistors terminated to +0.9VS
5
4
DDR2 HAD SWAPED.
3
RN1601A
RN1601B
RN1601C
RN1601D
RN1601E
RN1601F
RN1601G
RN1601H
RN1602A
RN1602B
RN1602C
RN1602D
RN1602E
RN1602F
RN1602G
RN1602H
RN1603A
RN1603B
RN1603C
RN1603D
RN1603E
RN1603F
RN1603G
RN1603H
RN1604A
RN1604B
RN1604C
RN1604D
RN1604E
RN1604F
RN1604G
RN1604H
RN1605A
RN1605B
RN1605C
RN1605D
RN1605E
RN1605F
RN1605G
RN1605H
RN1606A
RN1606B
RN1606C
RN1606D
RN1606E
RN1606F
RN1606G
RN1606H
RN1607A
RN1607B
RN1607C
RN1607D
RN1607E
RN1607F
RN1607G
RN1607H
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
1 16
56Ohm
2 15
56Ohm
3 14
56Ohm
4 13
56Ohm
5 12
56Ohm
6 11
56Ohm
7 10
56Ohm
8 9
56Ohm
R1601 56Ohm
R1602 56Ohm
R1603 56Ohm
M_CKE3 9,15
M_CKE2 9,15
M_B_A11 10,15
M_B_A7 10,15
M_B_BS#2 10,15
M_B_A6 10,15
M_B_A4 10,15
M_A_A12 10,14
M_A_A9 10,14
M_A_A8 10,14
M_A_A6 10,14
M_A_A7 10,14
M_A_A11 10,14
M_A_A4 10,14
M_A_A5 10,14
M_B_CAS# 10,15
M_ODT2 9,15
M_CS#2 9,15
M_CS#3 9,15
M_ODT3 9,15
M_A_WE# 10,14
M_A_A13 10,14
M_A_CAS# 10,14
M_ODT0 9,14
M_CS#0 9,14
M_CS#1 9,14
M_ODT1 9,14
M_B_A3 10,15
M_B_A1 10,15
M_B_BS#1 10,15
M_B_A10 10,15
M_B_BS#0 10,15
M_B_WE# 10,15
M_B_RAS# 10,15
M_B_A13 10,15
M_B_A2 10,15
M_B_A12 10,15
M_B_A9 10,15
M_B_A8 10,15
M_B_A0 10,15
M_B_A5 10,15
M_A_A3 10,14
M_A_A2 10,14
M_A_A0 10,14
M_A_BS#1 10,14
M_A_RAS# 10,14
M_A_A10 10,14
M_A_A1 10,14
M_A_BS#0 10,14
M_CKE0 9,14
M_CKE1 9,14
M_A_BS#2 10,14
<Variant Name>
Title :
DDR2 TERMINATION
1
Marco Chen
16 63Monday, August 28, 2006
Rev
1.11
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
2
T13Fv
Engineer:
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg11.png)
5
4
3
2
1
LCD Backlight Control
D1704
1N4148W
D D
+3VS_LCD_DISCHRG
12
LCD Power
+3VSUS
R1701
100KOhm
r0402
1 2
Q1701A
61
UM6K1N
L_VDD_EN9
C C
2
R1704
100KOhm
r0402
1 2
GND
PR_NOTE: Change R1703 to 200K ohm, C1701 to 0.1uF/25V, D1704 to
BAT54C and R1705 to 100ohm
+12VS
R1703
200KOhm
1 2
Q1701B
34
UM6K1N
5
R1.1
Item 17
12
GNDGND
C1701
0.1UF/25V
c0603
Q1702
1
2
3
G
SI3456BDV
6
D
5
S
4
+3VSLCD
GND
12
C1704
0.1UF/16V
c0402
12
C1702
0.1UF/16V
c0402
L1701
80Ohm/100Mhz
R1705
1 2
100Ohm
12
C1703
0.01UF/16V
GND
21
GND GNDGNDGND
+3VS
Cable Requirement:
Impedence: 100 ohm +/- 10%
Length Mismatch <= 10 mils
Twisted Pair(Not Ribbon)
Maximum Length <= 16"
C1705
10UF/10V
c0805
12
C1706
0.1UF/16V
c0402
12
+3VS_LCD
EDID_DAT9
EDID_CLK9
LCD LVDS Interface
LVDS_LCLKP9
LVDS_LCLKN9
LVDS_L2P9
LVDS_L2N9
LVDS_L1P9
LVDS_L1N9
LVDS_L0P9
LVDS_L0N9
GND
L1702
12
C1707
0.1UF/16V
c0402
80Ohm/100Mhz
21
12
C1708
100PF/50V
@
+3VS
+3VS_LCD
12
C1709
100PF/50V
@
CON171
22
NP_NC2
20
20
SIDE2
19
19
18
18
GND2
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
GND1
2
2
1
1
SIDE1
21
NP_NC1
WTOB_CON_20P
P/N:12G170040204
AC_BAT_SYS
26
25
24
23
GNDGND GND GND
21
21
L1703
80Ohm/100Mhz
2A
+VIN_INV
LID_EC#_CON
21
BL_DA_CON
21
BL_EN_CON
21
+3VA_CON
C1712
100PF/50V
@
T13Fv
Use F3's
inverter
12
P/N:12G171010104
GND
Title :
Engineer:
CON172
12
SIDE2
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
11
SIDE1
WTOB_CON_10P
LVDS & INVERTER
Marco Chen
1
GND
Rev
17 63Monday, August 28, 2006
1.11
of
CCD connecter
B B
+5V
L1704
2 1
80Ohm/100Mhz
R1.1
Item 3
F1701
1 2
0.2A/9V
12
+
CE1701
47UF/6.3V
@
Co-layout
12
C1713
10UF/10V
c0805
12
C1710
0.1UF/16V
c0402
GND GND
R1710
0Ohm
r0603_h24
1 2
USBP2+
USBP2-
CON173
1
2
3
4
5
P/N:12G171010050
1
SIDE1
2
3
4
5
SIDE2
WTOB_CON_5P
6
7
GND
PLT_RST#_BUF21,26,33
To EC Lid Switch
L_BKLTEN_V9
LCD_BACKOFF#34
From EC
BIOS
LID#
D1702
RB717F
1
2
1
2
D1703
RB717F
+3VS
12
3
3
From EC brightness control
Inverter connecter
R1707
10KOhm
r0402
LID_EC#34
BL_EN
1 2
D1701 1N4148W
INVTER_DA34
+3VA
LID#
L17081KOhm/100Mhz
C1711
1UF/25V
12
GND
L17051KOhm/100Mhz
L17071KOhm/100Mhz
L17061KOhm/100Mhz
BACK_OFF#:When user push "Fn+F7"
FOR EMI
A A
USB_PN221
USB_PP221
5
Co-layout
1 4
3 4
0OHM
1 2
0OHM
@
90Ohm/100Mhz
L1709
2 3
RN1701B
RN1701A
USBP2+
4
button, BIOS active this pin to
turn off back light.
3
L_BKLTEN_VUSBP2-
R1709
100KOhm
r0402
1 2
GND
2
<Variant Name>
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg12.png)
CRT
A
B
C
D
E
1 1
2 2
3 3
4 4
5 5
PLACE NEAR CON181.
+3VS
D1801 BAV99
1
3
2
D1802 BAV99
1
3
2
D1803 BAV99
1
3
2
D1804 BAV99
1
2
1
2
GND
A
D1805 BAV99
HSYNC_CRT
3
VSYNC_CRT
3
RED
GREEN
BLUE
R1.1
Item 22
JP1801
5
5
RN1801B
4.7KOHM
1 2
SHORT_PIN
@
JP1802
1 2
SHORT_PIN
@
JP1803
1 2
SHORT_PIN
@
HSYNC_CRT
VSYNC_CRT
+5VS
2
61
CRT_RED9
CRT_GREEN9
CRT_BLUE9
CRT_HSYNC9
CRT_VSYNC9
GND
RN1801A
4.7KOHM
CRT_DDC_DATA9
CRT_DDC_CLK9
37.5 ohm
37.5 ohm
37.5 ohm 55 ohm
U1802
3 4
GND Y
2
A
1
OE#
VCC
74LVC1G125GV
U1801
1
OE#
VCC
2
A
3 4
GND Y
74LVC1G125GV
+3VS +3VS
1 2
3 4
B
0Ohm
R1811
D1806
1 2
1N4148W
Q1803A
UM6K1N
12
+3VS
RED
GND
GREEN
GND
BLUE
GND
RN1801C
4.7KOHM
5
55 ohm 55 ohm
R1801
75Ohm
1%
1 2
55 ohm
R1802
75Ohm
1%
1 2
R1803
75Ohm
1%
1 2
R1804
1 2
0Ohm
R1805
1 2
0Ohm
RN1801D
4.7KOHM
5 6
7 8
34
Q1803B
UM6K1N
C
L1801
21
82NH
12
C1801
12PF/50V
c0402
@
GND GND
L1802
21
82NH
12
C1803
12PF/50V
c0402
@
GND GND
L1803
82NH
12
C1805
12PF/50V
c0402
@
DDC2BD_CRT
DDC2BC_CRT
55 ohm
21
55 ohm
C1807
47PF/50V
c0402
1 2
@
GND
C1808
47PF/50V
c0402
1 2
@
GND
R1806
1 2
0Ohm
R1807
1 2
0Ohm
GNDGND
12
C1802
22PF/25V
c0402
12
C1804
22PF/25V
c0402
12
C1806
22PF/25V
c0402
RED_CON
GREEN_CON
BLUE_CON
CON181
1617
6
1
7
2
8
3
9
4
10
5
11
12
13
14
15
D_SUB_15P3R
P/N:12G101102155
GND
HSYNC
VSYNC
DDC2BD
DDC2BC
<Variant Name>
Title :
CRT CONN
E
Marco Chen
18 63Monday, August 28, 2006
of
Rev
1.11
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet
D
T13Fv
Engineer:
![](/html/c7/c7fe/c7fee62597f9c8749a0d64b82bb952735698470be8bd6de8c93cef8a9a133cda/bg13.png)
5
4
3
2
1
Request of CSC for CMOS
clear function
R1.1
Item 29
D D
+VCC_RTC
R1.1
Item 22
C C
B B
ACZ_BCLK_AUD30
ACZ_BCLK_MDC26
ACZ_SYNC_AUD30
ACZ_SYNC_MDC26
ACZ_RST#_AUD30,31
ACZ_RST#_MDC26
ACZ_SDOUT_AUD30
ACZ_SDOUT_MDC26
R1911 39Ohm
R1912 33Ohm@
R1913 39Ohm
R1914 33Ohm@
R1915 39Ohm
R1916 33Ohm@
R1918 39Ohm
R1920 33Ohm@
12
12
12
12
R1904 20KOhm
RTCRST# RC
delay should be
18ms~25ms
C1901
12PF/50V
C1903
12PF/50V
GND
1%
GND
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
12
3
2
12
C1904
1UF/X7R
X1901
32.768Khz
1 4
12
JRST1
RTC_RST#
@
ACZ_SDIN0_AUD30
+VCC_RTC
T1901
TPC28T
SATA_LED#39
SATA_ICH_RXN023
SATA_ICH_RXP023
CLK_SATA_ICH#7
CLK_SATA_ICH7
GND
IDE_PDIOR#23
IDE_PDIOW#23
IDE_PDDACK#23
INT_IRQ1423
IDE_PIORDY23
IDE_PDDREQ23
12
R1901
10MOhm
R1903
0Ohm
1
Int.PD
Int.PD
R1923 0Ohm
T1908 TPC28T
T1909 TPC28T
GND
R1924
24.9Ohm 1%
1 2
RTC_X1
RTC_X2
R1905 1M
R1906 330K
R1907
@
1K
GND
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
SATA_ICH_RXN0
SATA_ICH_RXP0
SATA_ICH_TXN0
SATA_ICH_TXP0
1
1
12
INT_IRQ14
Int.PD
Int.PU
Int.PU
Int.PD
Int.PU
Int.PU
Int.PU
Int.PD
Int.PD
Int.PD
Int.PD
Int.PU
Int.PD
U1901A ICH7M
AB1
RTCX1
AB2
RTCX2
AA3
AF18
AF3
AE3
AG2
AH2
AF7
AE7
AG6
AH6
AF1
AE1
AH10
AG10
AF15
AH15
AF16
AH16
AG16
AE15
Y5
W4
W1
Y1
Y2
W3
V3
U3
U5
V4
T5
U7
V6
V7
U1
R6
R5
T2
T3
T1
T4
RTCRST#
INTRUDER#
INTVRMEN
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
RTCLAN
CPU LPC
GPIO49/CPUPWRGD
AC-97/AZALIASATA
IDE
LAD0
LAD1
LAD2
LAD3
LDRQ0#
LDRQ1#/GPIO23
LFRAME#
A20GATE
A20M#
CPUSLP#
TP1/DPRSTP#
TP2/DPSLP#
FERR#
IGNNE#
INIT3_3V#
INIT#
INTR
RCIN#
SMI#
STPCLK#
THERMTRIP#
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DCS1#
DCS3#
NMI
DA0
DA1
DA2
AA6
AB5
AC4
Y6
AC3
AA5
AB3
AE22
AH28
AG27
AF24
AH25
AG26
AG24
AG22
AG21
AF22
AF25
AG23
AH24
AF23
AH22
AF26
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AH17
AE17
AF17
AE16
AD16
Int.PU
Int.PU
Int.PU
Int.PU
Int.PU
Int.PU
R1908 0Ohm@
R1910 0Ohm
FWH_INIT#
+RTCBAT +3VA +VCC_RTC
R1902 1K
BAT191
12
34
Socket P/N:12G17100002C
Battary P/N:07G016412032
GND GND
LPC_AD0 33,34,35
LPC_AD1 33,34,35
LPC_AD2 33,34,35
LPC_AD3 33,34,35
T1902 TPC28T
1
T1903 TPC28T
1
1
1
1
T1904
TPC28T
T1905
TPC28T
T1907
TPC28T
R1919
24.9Ohm
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
LPC_FRAME# 33,34,35
A20GATE 34
H_A20M# 4
H_CPUSLP# 4,8
H_DPRSTP# 4,50
H_DPSLP# 4
H_PWRGD 4
H_IGNNE# 4
H_INIT# 4
H_INTR 4
RCIN# 34
H_NMI 4
H_SMI# 4ACZ_SDIN1_MDC26
H_STPCLK# 4
12
IDE_PDA0 23
IDE_PDA1 23
IDE_PDA2 23
IDE_PDCS1# 23
IDE_PDCS3# 23
+VCCP_ICH
T1906
TPC28T
1
+VCCP_ICH
ALL Int.PD
IDE_PDD[15:0] 23
D1901
2
1
BAT54C
12
R1909
56Ohm
12
R1917
56Ohm
3
C1902
1UF/X7R
H_FERR# 4
ICH_THRMTRIP# 6
Differential
Pair
3900P
C1905
SATA_ICH_TXP0
A A
5
4
C1906
SATA_HDD_RXP0
SATA_HDD_RXN0SATA_ICH_TXN0
3900P
SATA_HDD_RXP0 23
SATA_HDD_RXN0 23
<Variant Name>
Title :
ASUSTeK COMPUTER INC
Size Project Name
Custom
Date: Sheet of
3
2
T13Fv
Engineer:
1
ICH7M (1)
Marco Chen
19 63Monday, August 28, 2006
Rev
1.11