Asus t12fv Schematics

DC/BATT

www.bufanxiu.com

IN

5

T12F Block Diagram

D D

LVDS &

PAGE 12

CRT & TV OUT

PAGE 13

C C

KEYP

AD

MA

TRIX

PAGE 29

INST

ANT KEY

PAGE 38

LED

Control

PAGE

B B

30,38

T/P

PAGE 30

PAGE 24

EC I

T8511E

PAGE 29,30

ISA
ROM

Azalia Codec

AD1986A

PAGE 21,22,23

4

INV

LPC
33M

Hz

Azalia

PAGE 28

PAGE 28

YONAH-

PAGE 2,3

B0:02G010009121

PAGE 6,7,8,9,10,11

PAGE
17,18,19,20

(PATA,SATA)

B0:02G010008811

SATA2

HD

D

OD

D

3

CPU

2M

FSB
66

7MHz

MCH-M

Calistoga
945GM

DMI interface

ICH7-M

IDE

USB

PAGE 36

PAGE 27

PAGE 12

US
CON

Bl

uetooth

Cam

B 2.0

X4

era

PCIE *1

PCIE *1

DDR2-667

PCI
33MH

z

2

Dual Channel DDR2

SO-DIMM X 2

PAGE 14,15,16

MINI

CARD

WLA

N

PAGE 26

NEW
CARD

PAGE 25

10/100 LAN
RTL8100CL

PAGE 34,35

CardBus

R5C832

PAGE 31,32

CardBus

R5C841

PAGE
43,44

FAN

+ SENSOR

MAX6657MSA

PAGE 4

CLOCK

ICS9

PAGE 5

DISCHARGE
CIRCUI

PAGE 37

Powe

r On Sequence

PAGE 40

DC/BATT

PAGE 41

CPU V

PAGE 50

SYS

TEM PWR

PAGE 51

BAT &

CHARGER

PAGE 57

13

94

PAGE 32

CARD READER

PAGE 33

1

GEN

54310

T

CORE

R

IN

A A

5

4

3

FingerPri

PAGE 39

TP

PAGE 42

nt

M

PAGE 32

PC

MCIA

2

<Variant Name>

ASUSTeK COMPUTER INC

Size

Project Name

Custom

Wednesday, April 19, 2006

Date:

T12F

Title :

Engineer:

Sheet

1

BLOCK DIAGRAM

Leon and George

1

Rev

1.1

61

of

H_A#[16..3]

www.bufanxiu.com

6

H_REQ#[4..0]

6

H_A#[31..17]

6

5

4

3

2

1

T202

H_A#3

D D

H_ADSTB#0

6

C C

H_ADSTB#1

6

H_A20M#

17

H_FERR#

17

H_IGNNE#

17

H_STPCLK#

17

H_INTR

17

H_NMI

17

H_SMI#

17

B B

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

U201A

J4

A[3]#

L4

A[4]#

M3

A[5]#

K5

A[6]#

M1
N2

J1
N3
P5
P2

L1
P4
P1
R1

L2
K3

H2
K2

J3

L5
Y2

U5
R3

W6

U4
Y5
U2
R4

T5

T3
W3
W5

Y4

W2

Y1
V4

A6
A5
C4

D5
C6
B4
A3

AA1
AA4
AB2
AA3

M4
N5

T2

V3
B2
C3

B25

A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
RSVD[10]

RSVD[11]

ADDR GROUP 0

ADDR GROUP 1

THERMHCLKRESERVED

THERMTRIP#

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

XDP/ITP SIGNALS

DBR#

PROCHOT#

THERMDA

THERMDC

BCLK[0]
BCLK[1]

RSVD[12]
RSVD[A2]

RSVD[13]
RSVD[14]
RSVD[15]
RSVD[16]
RSVD[17]
RSVD[18]
RSVD[19]
RSVD[20]

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
B1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6

TDI

AB3
AB5
AB6
C20

D21
A24
A25

C7

A22
A21

T22
A2

D2
F6
D3
C1
AF1
D22
C23
C24

12G04600479A

1

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_CPURST#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

PRDY#
H_PREQ#
H_TCK
H_TDI
H_TDO
H_T

MS
H_TRST#
CPU_DBR#

H_PROCHOT_S#
CPU_THRM_DA
CPU_THRM_DC

PM_THRMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#

6

H_BNR#

6

H_BPRI#

6

H_DEFER#

6

H_DRDY#

6

H_DBSY#

6

H_BR0#

6

H_INIT#

17
H_LOCK# 6
H_CPURST#

H_RS#0

6
H_RS#1

6
H_RS#2

6
H_TRDY#

6

H_HIT# 6
H_HITM#

6

+VCCP_AGTL+

T203

1

R203

56Ohm
56Ohm
56Ohm
56Ohm
56Ohm
56Ohm

CPU_THRM_DA
CPU_THRM_DC

PM_THRMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

@

@

R204

1 2

R205

1 2

R206
R207

1 2

R208

1 2

68 ¡Ó 5% pull-up to Vcc1_0
If PROCHOT# is not u
56 pull-up resistor to VCCP.
If PROCHOT# is routed between CPU, IMVP and MCH,
pull-up resistor has to be 75 Ohm ¡Ó 5

R201
56Ohm

1

6

R202

54.9Ohm

T201

GND

1

TP

C28T

4
4

4,7,17

5

5

sed, then it must be terminated with a

T204

12

@

+VCCP_AGTL+

+VCCP_AGTL+

C201

0.1UF/10V

@

GND

+VCCP_AGTL+

12

R213

2KOhm

1%

R209

1KOhm

1%

1 2

<500 mil (55 Ohm)
T/B trace 5
Space 25

1 2

GND

6
6
6

6
6
6

GND

CPU_BSEL0

5

CPU_BSEL1

5

CPU_BSEL2

5

BCLK

133
166L667

H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_DSTBN#1
H_DSTBP#1
H_DINV#1

R214

@

1KOhm

R216

51Ohm

1 2
1 2

FSB
533

BSEL2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

GTL_REF

AD26

TEST1
TEST2

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

BSEL1HBSEL0

L

HL

H

U201B

E22

D[0]#

F24

D[1]#

E26

D[2]#

H22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H26

D[12]#

F26

D[13]#

K22

D[14]#

H25

D[15]#

H23

DSTBN[0]#

G22

DSTBP[0]#

J26

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L25

D[20]#

L22

D[21]#

L23

D[22]#

M23

D[23]#

P25

D[24]#

P22

D[25]#

P23

D[26]#

T24

D[27]#

R24

D[28]#

L26

D[29]#

T25

D[30]#

N24

D[31]#

M24

DSTBN[1]#

N25

DSTBP[1]#

M26

DINV[1]#
GTLREF

C26

TEST1

D25

TEST2

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

12G011204792

12G04600479A

DATA GRP 0

DATA GRP 1

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#

DATA GRP 2DATA GRP 3

D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23

AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20

R26
U26
U1
V1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

H_COMP0
H_COMP1
H_COMP2
H_COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD

H_CPUSLP#
PM_PSI#

H_D#[0..63]

R210
R211
R212
R215

1

6

H_DSTBN#2
H_DSTBP#2
H_DINV#2

6

Layout Note:
Comp0,2 connect with Z0=27.4 ohm,
make trace length shorter than 0.5".
Comp1,3 connect with Z0=54.9 ohm,
make trace length shorter than 0.5".
Comp[3:0] at least 25 mils a
any other toggling signa

27.4 ohm connects with an ~18mil
wide trace to comp0.

54.9 ohm connect with 5mil-wide
to comp1

H_DSTBN#3
H_DSTBP#3
H_DINV#3

6

27.4Ohm

1 2

54.9Ohm

1 2

27.4Ohm

1 2

54.9Ohm

1 2

H_DPRSTP#
H_DPSLP#

17

H_DPWR#

6

H_PWRGD

T205

H_CPUSLP#
PM_PSI#

6
6

way from

l.

6
6

1%

GND

1%
1%
1%

17,50

17

6,17

50

+VCCP_AGTL+

JP201

1 2

SHORT_PIN

2.5A

+VCCP

+VCCP_AGTL+

A A

5

+VCCP

@

+VCCP

6,9,20,52

+VCCP_AGTL+

3,5,6,9

H_PROCHOT_S#

29

4

H_PROCHOT_S#

+VCCP_AGTL+

R217

56Ohm

H_PWRGD

3

+VCCP_AGTL+

R218

56Ohm

@

<Variant Name>

Title :

YONAH CPU (1)

Sheet

1

Leon and George

2

61

of

Rev

1.0

ASUSTeK COMPUTER INC

Size

Project Name

Custom

2

Date:

T12F

Wednesday, April 26, 2006

Engineer:

5

www.bufanxiu.com

4

3

2

1

YUNAH FSB667

LFM TYP HFM
VCC 1.14V 1.2V 1.356V
C4 C3 C0
ICC 0.9A 7.59A 27A

D D

+VCORE

U201C

A7

VCC[1]

A9

VCC[2]

A10

VCC[3]

A12

VCC[4]

A13

VCC[5]

A15

VCC[6]

A17

VCC[7]

A18

VCC[8]

A20

VCC[9]

B7

VCC[10]

B9

VCC[11]

B10

VCC[12]

B12

VCC[13]

B14

VCC[14]

B15

VCC[15]

B17

VCC[16]

B18

VCC[17]

B20

VCC[18]

C9

VCC[19]

C10

VCC[20]

C12

VCC[21]

C13

VCC[22]

C15

VCC[23]

C17

VCC[24]

C18

C C

B B

D10

D12

D14

D15

D17

D18

E10

E12

E13

E15

E17

E18

E20

F10

F12

F14

F15

F17

F18

F20

AA7

AA9

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9

AC10
AB10
AB12
AB14
AB15
AB17
AB18

VCC[25]

D9

VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]

E7

VCC[33]

E9

VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]

F7

VCC[42]

F9

VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[65]
VCC[66]
VCC[67]

VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
VCC[77]
VCC[78]
VCC[79]
VCC[80]
VCC[81]
VCC[82]
VCC[83]
VCC[84]
VCC[85]
VCC[86]
VCC[87]
VCC[88]
VCC[89]
VCC[90]
VCC[91]
VCC[92]
VCC[93]
VCC[94]
VCC[95]
VCC[96]
VCC[97]
VCC[98]
VCC[99]

VCC[100]

VCCP[1]
VCCP[2]
VCCP[3]
VCCP[4]
VCCP[5]
VCCP[6]
VCCP[7]
VCCP[8]

VCCP[9]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26

AD6
AF5
AE5
AF4
AE3
AF2
AE2

AF7

AE7

12G04600479A

YUNAH FSB667

Min Typ Max

VCCP 0.997V 1.05V 1.102V

Min Typ Max

ICCP

+VCORE

+VCCA

+VCCP_A

GTL+

+VCCA

120mA / 20mil
Close to Pin B26

12

10UF/10V

H_VID0

1 2

H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

VCCSENSE

VSSSENSE

0Ohm

3 4

0Ohm

5 6

0Ohm

7 8

0Ohm

1 2

0Ohm

3 4

0Ohm

5 6

0Ohm

12

R302
100Ohm

2.5A

JP301

1 2

1 2

1MM_

@

7 8

C301

GND

RN302A
RN302B
RN302C
RN302D
RN303A
RN303B
RN303C

R301

1 2

100Ohm

OPEN_5MIL

RN303D

0Ohm

12

C318

0.01UF/25V

checklist suggests
10uF POSCAP

VR_VID0
VR_VID1
VR_VID2
VR_VID3
VR_VID4
VR_VID5
VR_VID6

+VCORE
VCCSENSE

VSSSENSE

U201D

A4

VSS[1]

A8

VSS[2]

A11

VSS[3]

A14

VSS[4]

A16

VSS[5]

A19

VSS[6]

A23

VSS[7]

A26

VSS[8]

B6

VSS[9]

B8

VSS[10]

B11

VSS[11]

B13

VSS[12]

B16

VSS[13]

B19

VSS[14]

B21

VSS[15]

B24

VSS[16]

C5

VSS[17]

C8

VSS[18]

C11

VSS[19]

C14

VSS[20]

C16

VSS[21]

C19

VSS[22]

C2

VSS[23]

C22

VSS[24]

C25

VSS[25]

D1

VSS[26]

D4

VSS[27]

D8

VSS[28]

D11

M22
M25

N23
N26

D13
D16
D19
D23
D26

E11
E14
E16
E19
E21
E24

F11
F13
F16
F19

F22
F25

G23
G26

H21
H24

K23
K26

L21
L24

VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]

E3

VSS[35]

E6

VSS[36]

E8

VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]

F5

VSS[44]

F8

VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]

F2

VSS[50]
VSS[51]
VSS[52]

G4

VSS[53]

G1

VSS[54]
VSS[55]
VSS[56]

H3

VSS[57]

H6

VSS[58]
VSS[59]
VSS[60]

J2

VSS[61]

J5

VSS[62]

J22

VSS[63]

J25

VSS[64]

K1

VSS[65]

K4

VSS[66]
VSS[67]
VSS[68]

L3

VSS[69]

L6

VSS[70]
VSS[71]
VSS[72]

M2

VSS[73]

M5

VSS[74]
VSS[75]
VSS[76]

N1

VSS[77]

N4

VSS[78]
VSS[79]
VSS[80]

P3

VSS[81]

+1

.5VO

50
50
50
50
50
50
50

50

50

12G04600479A

VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24

+VCORE

1215---PWR comp

12

+

GND

Place these

12

C302

22UF/6.3V

GND GND

Place these lower s

12

C308

22UF/6.3V

@

GND GND

Place these

12

C314

22UF/6.3V

GND

Place these lower s

12

C319

22UF/6.3V

@

GND

GNDGND

Place the cap on North

CE301

of Secondary side

220UF/4V

@

upper side inside socket cavity on L1

12

22UF/6.3V

C303

12

C304

22UF/6.3V

GND

ide inside socket cavity on L1

12

22UF/6.3V

@

C309

12

C310

22UF/6.3V

@

GND

upper side inside socket cavity on L6

12

22UF/6.3V

GND

C315

12

C316

22UF/6.3V

N/A

GND

ide inside socket cavity on L6

C320

12

C321

22UF/6.3V

@

GNDGND

12

22UF/6.3V

@

GND GND

GND

GND

GND

+VCCP_A

GTL+

+VCORE

+1.5VS

Vcc Core Decoup
Primary side => Bot
Secondar

C305

C311

C317

C322

12

22UF/6.3V

12

22UF/6.3V

@

GND

C306

C312

12

22UF/6.3V

12

22UF/6.3V

@

12

22UF/6.3V

N/A

12

22UF/6.3V

@

+VCCP_A

GTL+

+VCORE
+1.5VS 9,10,20,25,26,37,52

2,5,6,9

50

ling Caps

tom side

y side => Top side

12

C307

22UF/6.3V

GND

12

C313

22UF/6.3V

@

GND

+VCCP_A

GTL+

+1.05V Decoupling Capacitor
Place near CPU

12

12

C323

C324

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C325

c0402

0.1UF/10V

12

C326

c0402

0.1UF/10V

12

C327

c0402

0.1UF/10V

12

C328

c0402

0.1UF/10V

12

GND

+

CE302
100UF/2.5V

GND

Layout Note:
VCCSENSE/VSSSENSE lines between the
CPU and the VR should have a trace width of

A A

5

18 mils on 7 mils spacing, with trace
impedance of Zo=27.4 Ohm.
The VCCSENSE/VSSSENSE should be
length matched to within 25 mils.
These resistors should be placed within 2
inch of the CPU.

<Variant Name>

Title :

ASUSTeK COMPUTER INC

SizeProject Name

A3

4

3

2

Date:

T12F

Wednesday, April 26, 2006

Engineer:

Yonah CPU (2)

Leon and George

3

Sheet of

1

Rev

1.0

61

5

www.bufanxiu.com

4

3

2

1

+5VS
+3VS

C402

0.1UF/10V

C406

2200PF/50V

N/A

+3VA

4
3
2
1 5

R407

1 2

330Ohm

CPU_THRM_DA

CPU_THRM_DC

29,38

CON401

4
3
2
1

WtoB_4P

Fan Speed Control

D D

+5VS

KBC will issue a
analog ( a voltage
level ) signal.

SW: FAN_DA1 must
be low du

C C

B B

Route H_THERMDA and H_THERMDC
on the same layer

------------------OTHER
12 mils
===============GND
10 mils
=========H_THERMDA(10 mils)
10 mils

A A

=========H_THERMDC(10 mils)
10 mils
=========GND
12 mils

---------------------OT

SIGNALS

HER SIGNALS

FAN_PWM

29

FAN0_TACH

29

ring S3

R1.2

THRM_CPU#

29

FAN_PWM

FAN0_TACH

C407

12

0.01UF/50V

1

NC

2

SUB

3 4

GND

PST9013NR

GND

U402

VCC

VOUT

+3VA

T4

02

TPC28

1

R409
10KOhm

r040

2

T

5

+3VA_EC

1 2

T4

03

TPC28

T

1

R411

7.68KOhm

1 2

Q40

3

3 2

3

D

2N7002

R412
100KOhm

T4
TPC28

1

+5VS

1

1

+3VS

R403

10KOhm

r0402_h

16

1 2

12

C401

2200PF/50V

N/A

GND

THERMAL PROTECT
PLACE

UNDER CPU

ION

(105 DEGREE C)

12

12

GN

D

01

T

FORCE_OFF#

SMB1_

29

G

SMB1_DAT

29

2

S

+3VS

29,41,51,60

CLK

1 2

R410

4.7KOhm

+3VS

SMB1_
SMB1_DAT
SM

R408

1 2

0Ohm

r040

CLK

BALERT#

12

2

8
7
6
5

r0402_h

+3VS_T

C405

0.1UF/10V

c0402

U401

SCLK
SDA
ALERT#
GND

MAX6657MS

R402

10KOhm

+3VS_TH

HM

+3VS

16

OVERT#

A

1 2

M

VCC
DXP
DXN

12

+

CE401

100UF/10V

GND

Sta

ndby Mode: 3uA(Max. 10uA)

Full Active: 0.5 mA(Max. 1m

+3VS_T

1

CPU_THRM_DA

2

CPU_THRM_DC

3
4

GND GND

12

C403
100PF/50V

@

GND

2,7,17

HM

EC_RST_SW#

1 2

PM_THRMT

D1
1N4148W

A)

12

GND

RIP#

4"-8"

12

4"-8"

EC_RST_SW#

Avoid BPSB,Power

5

4

3

2

SIDE2

SIDE1

TRIP_R

+5VS

13,19,20,21,22,28,29,30,37,38,50,61

+3VS

5,7,9,11,12,13,14,15,19,20,21,22,23,25,26,27,28,29,30,31,32,33,37,39,40,42,43,50,52,60,61

+3VA

12,20,22,29,37,38,40,54,59,63

6

GND

+3

VA

11/29

12

1

1

G

GND

T12F

3

2

32

D

S

R405
10KOhm

r040

2

@

VSUS_ON

Q40
2N7002

1

Engineer:

VSUS_ON

Title :

THER-SENSOR,FAN

Leon and George

Sheet

1

PM

Q40

B

1

BS3904

2

2

+3VS

12

R406
1MOh

m

VSUS_ON_G

3

2

C

E
2

GND

GND

<Variant Name>

ASUSTeK COMPUTER INC

SizeProject Name

A3

Date:

12

C404

0.22UF/6.3V

Wednesday, April 26, 2006

25,29,51

Rev

4

1.0

61

of

5

www.bufanxiu.com

+VCCP_AGTL+

Control ne

Request

PCIE_REQ1#PCIE0(#),PCIE6(

PCIE_REQ2

#

PCIE_REQ3

PCIE_REQ4

#

#

14,15,19,25,26
14,15,19,25,26

D D

C C

B B

SELPCIE0_LCD#:
0-->pin17,pin18=LCDCLK(96MHz) or
27M/27M_SS

A A

SELLCD_27#/PCICLK_F1:
1-->pin17,pin18=LCDCLK(96MHz)

PCICLK2/REQ_SEL:
1-->pin40,pin41=PREQ1#,PREQ2#

ITP_EN/PCICLK_F0:
1-->CPU_ITP pair

t

PCIE1(#),PCIE8(

PCIE2(#),PCIE4(

PCIE3(#),PCIE5(
PCIE7(#

)

CLK_LCD_SSCG

7

CLK_LCD_SSCG#

7

CLK_USB48

19

CPU_BSEL0

2

CPU_BSEL1

2

CLK_LAN_PCI

34

CLK_CBPCI

31,43

CLK_FWHPCI

26

CLK_TPMPCI

42

CLK_ECPCI

29

CLK_ICHPCI

18

SMB_CLK_S
SMB_DA

5

#)

#)

#)

#),

GND

T_S

Net nam

e

None

None

CLK_PCIE_MINICARD

CLK_MCH_3GPLL(

+/-30ppm/20PF

X5

01

14.318Mh

1 2

12

C516
22PF/25V

z

@

12

C517
22PF/25V

C524 10PF/50V

@

1 2

GND

(#)

#)

GND

12

12

C514

C515

10UF/10V

0.1UF/10V

GND

GND

+3VS_CLK
+3VS_CLK

+3VS_CLK

C519 10PF/50V

C520 10PF/50V

C522 10PF/50V

C521 10PF/50V

C523 10PF/50V

C518 10PF/50V

@

@

@

@

@

1 2

1 2

1 2

1 2

1 2

1 2

Realtek:Mount R519,Remove R550 R534

R530
R532
R535

R539
R541
R544

R565
R546

R552

R536

R540

R548
R550

R553

4

R501
1KOhm

R503
1KOhm

R504
1KOhm

R506
1KOhm

R517

2.2Ohm

1 2
1 2
1 2

1 2

1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2

4

@

12

@

12

@

12

@

12

+3VS_CLK

12

GND

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

33Ohm
33Ohm
33Ohm

2.2KOhm

33Ohm
10KOhm
33Ohm

33Ohm
33Ohm
33Ohm
10KOhm

10KOhm
33Ohm

10KOhm

R558
475Ohm

GND

+3VS_VDDA

ICS_X1
ICS_X2
LCD_SSCG
LCD_SSCG#
FSA

PCICLK5
PCICLK4
PCICLK3
PCICLK2

PCICLK_F0

ICS_IREF

1 2

R502

1 2

R505

1 2

R507

1 2

GND

0Ohm

0Ohm

0Ohm

+3V

S

12

0.1UF/10V

GND

C501

MCH_BSEL0

MCH_BSEL1

MCH_BSEL2

12

C502

0.1UF/10V

Pin34 is PWRSAVE#

U501

21

VDDPCIEX1

28

VDDPCIEX2

42

VDDPCIEX3

34

VDD

50

VDDCPU

45

VDDA

46

GNDA

58

X1

57

X2

17

27FIX/LCD_SSCGT/PCIEX0T

18

27SS/LCD_SSCGC/PCIEX0C

12

FSLA/USB_48MHz

16

FSLB/TEST_MODE

5

SELPCIEX0_LCD#PCICLK5

4

PCICLK4

3

PCICLK3

64

PCICLK2/REQ_SEL

9

SELLCD_27#/PCICLK_F1

8

ITP_EN/PCICLK_F0

54

SCLK

55

SDATA

47

IREF

2

GND1

6

GND2

13

GND3

29

GND4

37

GND5

53

GND6

59

GND7

ICS954310CGLFT

Internal Pull-Up Resistor

Internal Pull-Down Resistor

3

7

7

7

120Ohm/100Mhz

21

L502
120Ohm/100Mhz

+3VS_VDDPCI

1

7

VDDPCI1

VDDPCI2

CPUCLKT2_ITP/PCIEXT8

CPUCLKC2_ITP/PCIEXC8

intern

al

pull hi

REF1/FSLC/TEST_SEL

3

Bclk

FS

B

133

533
667

166

L501

21

12

12

C508

0.1UF/10V

0.1UF/10V

VDD48

VDDREF

PCI/PCIEX_STOP#

CPU_STOP#

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

PEREQ1#/PCIEXT7
PEREQ2#/PCIEXC7

PCIEXT6
PCIEXC6

PCIEXT5
PCIEXC5

PCIEXT4
PCIEXC4

PCIEXT3
PCIEXC3

PCIEXT2
PCIEXC2

PCIEXT1
PCIEXC1

SATACLKT

SATACLKC

DOTT_96MHz
DOTC_96MHz

PEREQ3#

gh

PEREQ4#

Vtt_PwrGd#/PD

FSLC FSL

BSE

L2

L
L H

+3VS_CLK

12

C503

10UF/10V

C509

GND

11
56
63
62

49
48

52
51

44
43

41
40

39
38

36
35

30
31

24
25

22
23

19
20

26
27

14
15

32
33

10

61
60

REF0

BSE

12

C504

0.1UF/10V

12

C510

10UF/10V

+3VS_VDD48
+3VS_VDDREF
STP_PCI#
STP_CPU#

CLK_CPU
CLK_CPU#

CLK_MCH
CLK_MCH#

PEREQ#1
PEREQ#2

PCIE6
PCIE#6

PCIE4
PCIE#4

PCIE3
PCIE#3

PCIE2
PCIE#2

CLK_SATA
CLK_SATA#

DOT96
DOT96#

REF1
REF0

B FSLA

L1

12

0.1UF/10V

R513

2.2Ohm

R526
R527

R523
R524

R537
R538

R542
R543

R545
R547

R549
R551

R556
R557

R563

R564

BSE

HL
H

C505

1 2

1 2
1 2

1 2
1 2

R531
R533

R534

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

R554
R555

1 2
1 2

R561

1 2
1 2

L0

+3VS_CLK

12

C506

0.1UF/10V

12

C511

0.1UF/10V

STP_PCI#
STP_CPU#

1 2

10KOhm

12

33Ohm

@

33Ohm

@

33Ohm
33Ohm

33Ohm
33Ohm

33Ohm
33Ohm

1 2
1 2

33Ohm
33Ohm

0Ohm

12

2.2KOhm
33Ohm

12

0.1UF/10V

GND

12

10UF/10V

GND

33Ohm
33Ohm

33Ohm
33Ohm

12

C507

C512

10KOhm
0Ohm

33Ohm
33Ohm

@
@

2

+VCCP_AGTL+

+3

19

19,50

GND

CLK_PCIE_NEWCARD
CLK_PCIE_NEWCARD#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_MINICARD
CLK_PCIE_MINICARD#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_UMA_96M
CLK_UMA_96M#

MCH_CLK_REQ#
CLK_MINICARD_REQ#

CPU_BSEL2
CLK_ICH14

2

VS

R514
1Ohm

1 2

C513

1 2

0.1UF/10V

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

+3

VS

CLK_NEWCARD_REQ#

CLK_PCIE_SATA
CLK_PCIE_SATA#

2

19

1

+VCCP_AGTL+
+3VS4,7,9,11,12,13,14,15,19,20,21,22,23,25,26,27,28,29,30,31,32,33,37,39,40,42,43,50,52,60,61

25

7

7

26

18

18

GND

2

6

25

26

2,3,6,9

Layout N

ote:

Plac

e termination close to source IC

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_LCD_SSCG
CLK_LCD_SSCG#

CLK_UMA_96M

25

CLK_UMA_96M#

CLK_PCIE_MINICARD
CLK_PCIE_MINICARD#

CLK_PCIE_NEWCARD
CLK_PCIE_NEWCARD#

CLK_PCIE_SATA
CLK_PCIE_SATA#

R1.

1

2

6

R508
R509

R510
R511

R512
R515

R516
R518

R519
R521

R522
R525

R528
R529

R566
R567

R568
R569

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402

49.9Ohm

r0402
@

49.9Ohm

r0402
@

49.9Ohm

r0402
@

49.9Ohm

r0402
@

PREQ#1
0=PCIEX 6/0 Not Controlled
1=PCIEX 6/0 Controlled

PREQ#2

17

7

7

7

26

0=PCIEX 8/1 Not Controlled

17

1=PCIEX 8/1 Controlled
PREQ#3

+3VS_CLK

0=PCIEX 4/2 Not Controlled
1=PCIEX 4/2 Controlled

12

R560
10KOhm

@

CLK_EN#

50

PREQ#4
0=PCIEX 7/5/3 Not Controlled
1=PCIEX 7/5/3 Controlled

<Variant Name>

Title :

CLOCK GEN

Sheet

1

Leon and George

5

of

ASUSTeK COMPUTER INC

Size

Project Name

Custom

Wednesday, April 26, 2006

Date:

Engineer:

T12F

GND

Rev

1.0

61

5

www.bufanxiu.com

H_D#[0..63]

2

K11
T10

W11

U11
T11

AB7
AA9

Y10
AB8

AA4
AA7
AA2
AA6

AA10

AA1
AB4

AC9
AB11
AC11

AB3

AC2

AD1

AD9

AC1

AD7

AC6

AB5
AD10

AD4

AC8

AG2
AG1

F1

J1

H1

J6
H3
K2

G1
G2

K9
K1
K7

J8
H4

J3

G4

T3
U7
U9

W9

T1
T8
T4

W7

U5
T9

W6

T5

W4
W3

Y3
Y7

W5

W2

Y8

E1
E2
E4

Y1
U1

W1

U601A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_XRCOMP
H_XSCOMP
H_XSWING

H_YRCOMP
H_YSCOMP
H_YSWING

H_CLKIN
H_CLKIN#

CALIST

OGA_Q137

H_D#0
H_D#1
H_D#2
H_D#3

5

H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOM

P

H_X

SCOMP

H_XSWING
H_YRCOMP

H_YSCOMP
H_YSWING

CLK_MCH_BCLK
CLK_MCH_BCLK#

D D

C C

B B

CLK_MCH_BCLK

5

CLK_MCH_BCLK#

A A

5

4

H_A#[31..3]

H_A#3

H9

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_AVREF

H_BNR#

H_BPRI#

H_BREQ#0

H_CPURST#

HOST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_SLPCPU#

4

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#
H_DVREF

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_TRDY#

C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13

J7
W8
U3
AB10

K4
T7
Y5
AC4

K3
T6
AA5
AC5

D3
D4
B3

D8
G8
B8
F8
A8

B4
E6
D6

E3
E7

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_ADS#
H_ADST

B#0

H_ADST

B#1

H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_CPURST#

H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTB

P#0

H_DSTB

P#1

H_DSTB

P#2

H_DSTB

P#3

H_HIT#
H_HITM

#

H_LOCK#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

N_CPUSLP#
H_TRDY#

H_ADS#
H_ADST
H_ADST

H_BNR#
H_BPRI#
H_BR0#
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTB
H_DSTB
H_DSTB
H_DSTB

H_HIT#
H_HITM#
H_LOCK#

R611
0Ohm

12

2

2

B#0

2

B#1

2

2

2

2

2

2

2
2
2

2
2
2
2

2
2
2
2

P#0

2

P#1

2

P#2

2

P#3

2

2

2

2
H_REQ#[4..0]

H_RS#[0..2]

+V

3

CCP_AGTL+

R601
100Oh

m

1%

1 2

R606
200Oh

m

1%

1 2

GND

Layou

GND

t Note:

0.1uF should be
less

from GMCH pin.

2

2

H_CPUSLP#
H_TRDY#

3

2,17

2

<500 mil (55 Ohm)
T/B trace 5.5 ,
Space 25

12

C601

0.1UF/10V

placed 100mils or

+VCCP

GND

+VCCP

GND

+VCCP

GND

2

R602

54.9Ohm

1%

H_X

1 2

H_XRCOMP

R604

24.9Ohm

1%

1 2

R607
221Oh

1%

1 2

R608
100Oh

1%

1 2

R609
221Oh

1%

1 2

R610
100Oh

1%

1 2

2

SCOMP

m

m

m

m

12

GND

12

GND

5.5/20 mils

10/20mils

H_XSWING

C602

0.1UF/10V

H_YSWING

C603

0.1UF/10V

<Variant Name>

ASUSTeK COMPUTER INC

SizeProject Name

B

Date:

+VCCP

+V

CCP_AGTL+

+VCCP

R603

54.9Ohm

1%

H_YSCOMP

1 2

H_YRCOMP

R605

24.9Ohm

1%

1 2

GND

10/20mils

Signal vol

tage level =

0.3125

*VCCP
Trace should be 10 mil w
with 20 mil spac

Wednesday, April 26, 2006

ing

T12F

1

+VCCP
+V

CCP_AGTL+

ide

Title :

Engineer:

Sheet

1

2,9,20,52

2,3,5,9

Calistoga MCH (1)

Leon and George

6

Rev

1.0

61

of

5

4,5,9,11,12,13,14,15,19,20,21,22,23,25,26,27,28,29,30,31,32,33,37,39,40,42,43,50,52,60,61

www.bufanxiu.com

4

3

2

1

+1.5VS_PCIE

+3VS

L_

BKLTCTL

12

R703 10KOhm

1 2

R704 10KOhm

1 2

R705 10KOhm

1 2

R706 10KOhm

D D

1 2

GND

C C

B B

A A

DAC_HSYNC_GM
DAC_VSYNC_GM

R707

1.5KOhm

1%

L_BKL

TEN

R710
100KOhm

R715 150Ohm
R716 150Ohm
R717 150Ohm

GND

GND

R720 150Ohm
R721 150Ohm
R722 150Ohm

GND

LVDS_L0N
LVDS_L2N
LVDS_L0P

LVDS_L1P
LVDS_L2P

LVDS_U0N
LVDS_U1N
LVDS_U2N

LVDS_U0P
LVDS_U1P
LVDS_U2P

1 2

12

GND

1 2
1 2

T7

02

GND

R701

4.99KOhm

1%

R723
39Ohm

R724
39Ohm

5

L_

BKLTCTL
L_BKLT
L_CTLA_CLK
L_CTLB_
EDID_CLK
EDID_DAT
L_IBG
L_VB

1

L_VDDEN
L_VREFH
L_VREFL

LVDS_LCLKN
LVDS_LCLKP
LVDS_UCLKN
LVDS_UCLKP

LVDS_L0N
LVDS_L1N
LVDS_L2N

LVDS_L0P
LVDS_L1P
LVDS_L2P

LVDS_U0N
LVDS_U1N
LVDS_U2N

LVDS_U0P
LVDS_U1P
LVDS_U2P

TV_CV

12

TV_Y

12

TV_

12

1%

TV_IREF

12

CRT_BLUE

12

1%

CRT_GREEN

12

1%

CRT_RED

12

1%

CRT_DDC_CLK
CRT_DDC_DATA

N_HSYNC
N_VSYNC

R725

255Ohm

1%

LVDS_L0N
LVDS_L1N
LVDS_L2N

LVDS_L0P
LVDS_L1P
LVDS_L2P

LVDS_U0N
LVDS_U1N
LVDS_U2N

LVDS_U0P
LVDS_U1P
LVDS_U2P

G

C

EN

BS

12
12
12

DATA

GND

GND

12
12
12

12
12
12

12
12
12

D32
J30
H30

H29
G26
G25
B38
C35

F32
C33
C32

A33
A32
E27
E26

C37
B35
A37

B37
B34
A36

G30
D30

F29

F30
D29

F28

A16
C18
A19

J20
B16
B18
B19

E23
D23
C22
B22
A21
B21

GND

C26
C25
G23

J22
H23

CRT_IREF

12

U601C

L_BKLTCTL
L_BKLTEN
L_CLK_CTLA
L_DATA_CTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL

LA_CLK#
LA_CLK
LB_CLK#
LB_CLK

LA_DATA#_0
LA_DATA#_1
LA_DATA#_2

LA_DATA_0
LA_DATA_1
LA_DATA_2

LB_DATA#_0
LB_DATA#_1
LB_DATA#_2

LB_DATA_0
LB_DATA_1
LB_DATA_2

TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC

CALISTOGA_Q13

LVDS_LCLKN
LVDS_LCLKPLVDS_L1N
LVDS_UCLKN
LVDS_UCLKP

L_BKLT

EN

EDID_CLK
EDID_DAT

L_VDDEN

EXP_A_C

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8

EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13

PCI-EXPRESS GRAPHICS

12
12

12

EXP_A_RXN_14
EXP_A_RXN_15

EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8

EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15

EXP_A_TXN_0

EXP_A_TXN_1

EXP_A_TXN_2

EXP_A_TXN_3

EXP_A_TXN_4

EXP_A_TXN_5

EXP_A_TXN_6

EXP_A_TXN_7

EXP_A_TXN_8

EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15

EXP_A_TXP_0

EXP_A_TXP_1

EXP_A_TXP_2

EXP_A_TXP_3

EXP_A_TXP_4

EXP_A_TXP_5

EXP_A_TXP_6

EXP_A_TXP_7

EXP_A_TXP_8

EXP_A_TXP_9

EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15

12

12

12

12

4

LVDS

TV

VGA

7

LVDS_LCLKN
LVDS_LCLKP
LVDS_UCLKN
LVDS_UCLKP

L_BKLTEN12
EDID_CLK

EDID_DAT
L_VDDEN

D40
D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

TV_C

VBS
TV_Y
TV_

C

CRT_RED
CRT_GREEN
CRT_BLUE

DAC_HSYNC_GM
DAC_VSYNC_GM

CRT_DDC_CLK
CRT_DDC_DATA

OMP

19,50

R702

1 2

24.9Ohm

1%

PM_DPRSLPVR

2,4,17

19,29

18,19,25,28,29,42

18

TV_C
TV_Y
TV_C13

CRT_RED
CRT_GREEN
CRT_BLUE

CRT_DDC_CLK
CRT_DDC_DATA

+3

VS

MCH_BSEL0

5

MCH_BSEL1

5

MCH_BSEL2

5

MCH_CFG_5

11

MCH_CFG_7

11

MCH_CFG_9

11

MCH_CFG_11

11

MCH_CFG_16

11

MCH_CFG_18

11

MCH_CFG_19

11

PM_BMBUSY#

19

PM_THRMT
ICH_PWROK

PLT_RST#

MCH_ICH_SYNC#
MCH_CLK_REQ#

5

VBS

13

13

13

13

13

R708

1 2

10KOhm
R709

1 2

10KOhm

R718

RIP#

13

13

PM_E

PM_E

T7
T7

T7
T7
T7
T7

T7
T7
T7

T7

T7

0Ohm

1 2

@

DAC_VSYNC_GM

DAC_HSYNC_GM

3

XTTS#0

XTTS#1

MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
MCH_CFG_3

03

1

MCH_CFG_4

01

1

MCH_CFG_5
MCH_CFG_6

04

1

MCH_CFG_7
MCH_CFG_8

05

1

MCH_CFG_9
MCH_CFG_10

06

1

MCH_CFG_11
MCH_CFG_12

07

1

MCH_CFG_13

08

1

MCH_CFG_14

09

1

MCH_CFG_15

10

1

MCH_CFG_16
MCH_CFG_17

11

1

MCH_CFG_18
MCH_CFG_19
MCH_CFG_20

12

1

PM_BMBUSY#
PM_EX
PM_EX
PM_THRM
ICH_PWROK

RST_IN#_MCH

MCH_ICH_SYNC#
MCH_CLK_REQ#

TTS#0
TTS#1

TRIP#

U601B

T32

RSVD_1

R32

RSVD_2

F3

RSVD_3

F7

RSVD_4

AG11

RSVD_5

AF11

RSVD_6

H7

RSVD_7

J19

RSVD_8

K30

TV_DCONSEL_0

J29

TV_DCONSEL_1

A41

RSVD_11

A35

RSVD_12

A34

RSVD_13

D28

RSVD_14

D27

RSVD_15

K16

CFG_0

K18

CFG_1

J18

CFG_2

F18

CFG_3

E15

CFG_4

F15

CFG_5

E18

CFG_6

D19

CFG_7

D16

CFG_8

G16

CFG_9

E16

CFG_10

D15

CFG_11

G15

CFG_12

K15

CFG_13

C15

CFG_14

H16

CFG_15

G18

CFG_16

H15

CFG_17

J25

CFG_18

K27

CFG_19

J26

CFG_20

G28

PM_BMBUSY#

F25

PM_EXTTS#_0

H26

PM_EXTTS#_1

G6

PM_THRMTRIP#

AH33

PWROK

AH34

RSTIN#

H28

SDVO_CTRLCLK

H27

SDVO_CTRLDATA

K28

ICH_SYNC#

H32

CLK_REQ#

D1

NC0

C41

NC1

C1

NC2

BA41

NC3

BA40

NC4

BA39

NC5

BA3

NC6

BA2

NC7

BA1

NC8

B41

NC9

B2

NC10

AY41

NC11

AY1

NC12

AW41

NC13

AW1

NC14

A40

NC15

A4

NC16

A39

NC17

A3

NC18

CALISTOGA_Q13

DAC_VSYNC_GM

DAC_HSYNC_GM

RSVD

DDR MUXINGCLK

CFG

PM

MISC NC

DMI

7

18

18

2

+3VS

M_VREF_MCH

+1.5VS

+1.5VS_PCIE

+1.8V

SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3

SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3

SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_OCDCOMP_0
SM_OCDCOMP_1

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP#

SM_RCOMP
SM_VREF_0

SM_VREF_1

G_CLKIN#

G_CLKIN

D_REFCLKIN#

D_REFCLKIN

D_REFSSCLKIN#

D_REFSSCLKIN

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

+3VS
M_VREF_MCH
+1.5VS

+1.5VS_PCIE
+1.8V 10,14,15,37,53

M_CLK_DDR0

AY35

M_CLK_DDR1

AR1

M_CLK_DDR2

AW7

M_CLK_DDR3

AW40

M_CLK_DDR#0

AW35

M_CLK_DDR#1

AT1

M_CLK_DDR#2

AY7

M_CLK_DDR#3

AY40

M_CK

E0

AU20

M_CK

E1

AT20

M_CK

E2

BA29

M_CK

E3

AY29

M_CS

#0

AW13

M_CS

#1

AW12

M_CS

#2

AY21

M_CS

#3

AW21

M_OCDCOMP0

AL20

M_OCDCOMP1

AF10

M_ODT

BA13
BA12
AY20
AU21

AV9
AT9

AK1
AK41

AF33
AG33
A27
A26
C40
D41

AE35
AF39
AG35
AH39

AC35
AE39
AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

0

M_ODT

1

M_ODT

2

M_ODT

3

M_RCO
M_RC

OMP

M_VREF_MCH

CLK_MCH_3GPLL#
CLK_MCH_3GPLL
CLK_UMA
CLK_UMA
CLK_LCD_SSCG#
CLK_LCD_SSCG

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_

TXP0

DMI_

TXP1

DMI_

TXP2

DMI_

TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_R

XP0

DMI_R

XP1

DMI_R

XP2

DMI_R

XP3

<Variant Name>

ASUSTeK COMPUTER INC

SizeProject Name

A3

Wednesday, April 26, 2006

Date:

14,15,16

9,10,20,25,26,37,52

9

Layout Note:
Route as short as possible

R711 40.2Ohm

R712 40.2Ohm

R713 80.6Ohm 1%

MP#

1 2
1 2

R714 80.6Ohm 1%

_96M#
_96M

T12F

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

12
12

CLK_MCH_3GPLL#
CLK_MCH_3GPLL
CLK_UMA_
CLK_UMA
CLK_LCD_SSCG#
CLK_LCD_SSCG

DMI_TXN[0..3]

DMI_TXP[0..3]

DMI_RXN[0..3]

DMI_RXP[0..3]

Title :

Engineer:

14
14
15
15

14
14
15
15

M_CKE[0..3]
M_CS#[0..3]
M_ODT[0..3]

@

@

GND

+1.8V

GND

5

5

96M#

5

_96M

5

5

5
18

18

18

18

Calistoga PCI-E (2)

Leon and George

Sheet

1

7

14,15,16
14,15,16
14,15,16

of

Rev

1.0

61

www.bufanxiu.com

D D

C C

B B

5

M_A_D
M_A_D
M_A_D
M_A_D
M_A_D
M_A_D
M_A_D
M_A_D
M_A_D
M_A_D
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ
M_A_DQ

U601D

Q0

AJ35

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

AJ34
AM31
AM33

AJ36

AK35

AJ32
AH31
AN35

AP33

AR31

AP31
AN38
AM36
AM34
AN33

AK26

AL27
AM26
AN24

AK28

AL28
AM24

AP26

AP23

AL22

AP21
AN20

AL23

AP24

AP20

AT21
AR12
AR14

AP13

AP12

AT13

AT12

AL14

AL12

AK9
AN7
AK8
AK7
AP9
AN9
AT5

AY2

AW2

AP1
AN2
AV2
AT3
AN1

AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

AL5

AL2

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

CALISTOGA_Q13

SYSTEM MEMORY A

DDR

7

Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9

4

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

SA_WE#

AU12
AV14
BA20

AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

AW14
AK23
AK24
AY14

M_

A_BS#0

M_

A_BS#1

M_

A_BS#2

M_A_CA

S#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQ

S0
M_A_DQ

S1
M_A_DQ

S2
M_A_DQ

S3
M_A_DQ

S4
M_A_DQ

S5
M_A_DQ

S6
M_A_DQ

S7
M_A_DQ

S#0
M_A_DQ

S#1
M_A_DQ

S#2
M_A_DQ

S#3
M_A_DQ

S#4
M_A_DQ

S#5
M_A_DQ

S#6
M_A_DQ

S#7
M_A_A0

M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_RA

S#
M_A_RCVENIN#
M_A_RCVENOUT#
M_A_W

E#

M_A_DM[0..7]
M_A_DQS[0..7]
M_A_DQS#[0..7]
M_A_A[0..13]
M_A_DQ[0..63]

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CAS#14,16

T8

1

T8

1

14

14,16

M_A_R

02
01

M_A_

14

14

14

WE#

AS#

14,16
14,16
14,16

14,16

14,16

3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
Q33
Q34
Q35
Q36
Q37
Q38
Q39
Q40
Q41
Q42
Q43
Q44
Q45
Q46
Q47
Q48
Q49
Q50
Q51
Q52
Q53
Q54
Q55
Q56
Q57
Q58
Q59
Q60
Q61
Q62
Q63

AK39

AJ37
AP39
AR41

AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40

AW38

AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31

AW31

AV29

AW29
AM19

AL19
AP14
AN14
AN17

AM16

AP15
AL15

AJ11
AH10

AN10
AK13
AH11
AK10

BA10

AW10

BA4

AW4
AY10

AY9

AW5

AY5
AV4
AR5
AK4
AK3

AK5

AJ9

AJ8

AT4
AJ5

AJ3

U601E

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

CALISTOGA_Q13

M_B_
M_B_
M_B_
M_B_
M_B_
M_B_
M_B_
M_B_
M_B_
M_B_
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D
M_B_D

2

M_B_BS#0

AT24

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7

SYSTEM MEMORY B

SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11

DDR

SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVENIN#

SB_RCVENOUT#

SB_WE#

7

AV23
AY28

AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

AU23
AK16
AK18
AR27

M_B_BS#1
M_B_BS#2

M_B_C

AS#

M_B_DM

0

M_B_DM

1

M_B_DM

2

M_B_DM

3

M_B_DM

4

M_B_DM

5

M_B_DM

6

M_B_DM

7

M_B_D

QS0

M_B_D

QS1

M_B_D

QS2

M_B_D

QS3

M_B_D

QS4

M_B_D

QS5

M_B_D

QS6

M_B_D

QS7

M_B_D

QS#0

M_B_D

QS#1

M_B_D

QS#2

M_B_D

QS#3

M_B_D

QS#4

M_B_D

QS#5

M_B_D

QS#6

M_B_D

QS#7

M_B_A

0

M_B_A

1

M_B_A

2

M_B_A

3

M_B_A

4

M_B_A

5

M_B_A

6

M_B_A

7

M_B_A

8

M_B_A

9

M_B_A1

0

M_B_A1

1

M_B_A1

2

M_B_A1

3

M_B_R

AS#
M_B_RCVENIN#
M_B_RCVENOUT#
M_B_

WE#

M_B_BS0
M_B_BS1
M_B_BS2

M_B_C

T8

1

T8

1

M_B_DM[0..7]
M_B_DQS[0..7]
M_B_DQS#[0..7]
M_B_A[0..13]
M_B_DQ[0..63]

15,16
15,16
15,16

AS#

15,16

M_B_R

AS#

03
04

M_B_WE#15,16

15

15

15

15,16

15

1

15,16

A A

<Variant Name>

Title :

Calistoga DDR2 (3)

ASUSTeK COMPUTER INC

SizeProject Name

A3

5

4

3

2

Date:

T12F

Wednesday, April 26, 2006

Engineer:

Leon and George

Sheet

1

Rev

8

1.0

61

of

5

4,5,7,11,12,13,14,15,19,20,21,22,23,25,26,27,28,29,30,31,32,33,37,39,40,42,43,50,52,60,61

www.bufanxiu.com

Layout Note:
Place filter components

+1.5VS

close to GMCH

L90

2

120Ohm/10

D D

L90

1

30Ohm/10

L903
80Ohm/10

L90

4

30Ohm/10

C C

L90

6

30Ohm/10

L90

7

120Ohm/10

L90

8

120Ohm/10

B B

+2.5VS

VCC_SYNC
Pin H22

12

C932

0.1UF/10V

R905

10Ohm

A A

70 mA

L90

9

120Ohm/10

Layout Note:
Caps should be on Top layer

21

12

0Mhz

+

CE902
150UF/4V

@

GND

21

12

0Mhz

C904

0.1UF/10V

GND

0Mhz

21

12

+

CE903

470UF/2.5V

GND

21

12

0Mhz

+

CE904

470UF/2.5V

GND

21

12

0Mhz

+

CE905

470UF/2.5V

GND

21

12

0Mhz

C923

22UF/6.3V

GND

21

12

C927

0Mhz

22UF/6.3V

GND

VCCA_LVDS
Pin A38 10 mA

12

0.01UF/25V

GND GNDGND

+VCCP_GMCH_R

12

VCCA_CRTDAC
Pin E21 F21

21

12

0Mhz

C901

0.022UF/25V

GND GND

5

12

C902
10UF/10V

GND

12

C905

10UF/10V

GND

12

C909

0.1UF/10V

GND

12

@

C912

0.1UF/10V

GND

12

@

C918

0.1UF/10V

GND

12

C924

0.1UF/10V

GND

12

C928

0.1UF/10V

GND

C933

GND GND

3

12

C946

0.1UF/10V

GND

VCCA_3GPLL

+1.5VS_VCCAUX

VCCAUX
1900 mA

+1.5VS_DPLLA

VCCA_DPLLA
50 mA

+1.5VS_DPLLB

VCCA_DPLLB
50 mA

+1.5VS_HPLL

VCCA_HPLL
45 mA

VCCA_MPLL
45 mA

12

C934

0.1UF/10V

D902

BAT5

4C

+1.5VS_PCIE

VCC3G

12

C903
10UF/10V

+1.5VS_3GP

LL

1500

+1.5VS

_MPLL

Layout Note:

0.1uF caps in 1.5VS_xPLL
need to be located as
edge caps within 200 mils.

VCCA_3GBG
Pin G41 2 mA

12

C935

0.1UF/10V

GND

1

+VCCP_GMCH

2

+2.5VS_CRTDAC

Layout Note:
These Caps should
be within 250 mils of
edge of GMCH

+VCCP

+VCCP

mA

+1.5VS

VCCD_LVDS 20 mA
Pin A28 B28 C28

12

C910

0.1UF/10V

GND

+1.5VS

VCCD_TVDAC
Pin D21

12

C913

0.022UF/25V

GND

+1.5VS

VCCD_QTVDAC
H19 C28

12

C919

0.022UF/25V

GND

Layout Note:
These Caps should be within
250 mils of edge of GMCH

VCCTX_LVDS 60 mA
Pin A30 B30 C30

12

C936

0.1UF/10V

4

GMCH VCORE

+1.

05VS

JP902

3500

mA

1 2

SHORT_PIN

@

JP901

1 2

SHORT_PIN

@

12

C911
10UF/10V

GND

12

C914

0.1UF/10V

GND

24 mA

12

C920

0.1UF/10V

GND

Layout Note:
These 0.1uF caps should
be placed within 200 mils
of edge

12

C937

4.7UF/10V

+3VS

VCC_HV 40 mA
Pin A23 B23 B25

12

C944
10UF/10V

GND

4

+VCCP_GMCH

+2.5VS_CRTDAC

GND

+3VS_TVDA
+3VS_TVDA
+3VS_TVDACC

+1.5VS_VCCAUX

12

C945

0.1UF/10V

GND

+1.5VS_3GP

+2.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL

+2.5VS

+1.5VS

_MPLL

+3VS_TVB

+1.5VS

+1.5VS

+1.5VS

+3VS

+1.5VS

+1.5VS_PCIE

GND

G

CA
CB

+2.5VS

GND

LL

GND

AJ41

AB41

AC33

AK31
AF31
AE31

AC31

AL30
AK30

AJ30
AH30
AG30

AF30

AE30
AD30
AC30
AG29

AF29

AE29
AD29
AC29
AG28

AF28

AE28
AH22

AJ21

AH21

AJ20
AH20
AH19

AH15
AH14

AG14

AF14
AE14

AF13
AE13
AF12
AE12

AD12

H22
C30

B30
A30

Y41
V41
R41
N41

G41
H41

F21
E21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
A23

B23
B25

H19

P19
P16

P15

Y14

L41

U601H

VCCSYNC
VCC_TXLVDS0

VCC_TXLVDS1
VCC_TXLVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC
VCC_HV0

VCC_HV1
VCC_HV2

VCCD_QTVDAC
VCCAUX0

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

CALISTOGA_Q1

3

+VCCP_A

AC14

VTT_0

AB14

VTT_1

W14

VTT_2

V14

VTT_3

T14

VTT_4

R14

VTT_5

P14

VTT_6

N14

VTT_7

M14

VTT_8

L14

VTT_9

AD13

VTT_10

AC13

VTT_11

AB13

VTT_12

AA13

VTT_13

Y13

VTT_14

W13

VTT_15

V13

VTT_16

U13

VTT_17

T13

VTT_18

R13

VTT_19

N13

VTT_20

M13

VTT_21

L13

VTT_22

AB12

VTT_23

AA12

VTT_24

Y12

VTT_25

W12

VTT_26

V12

VTT_27

U12

VTT_28

T12

VTT_29

R12

VTT_30

P12

VTT_31

N12

VTT_32

M12

VTT_33

L12

VTT_34

R11

VTT_35

P11

VTT_36

N11

VTT_37

M11

VTT_38

R10

VTT_39

P10

VTT_40

N10

VTT_41

M10

VTT_42

P9

VTT_43

POWER

37

3

VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76

N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

NOTE:0.1UF CAPS USED IN +1.5VS,
+3.3VS
+2.5VS should be placed within
200 mils of edge.

2

+VCCP_A

GTL+

+VCCP_GMCH

+1.5VS_PCIE

+3VS

GTL+

VTTLF_

C929

0.47UF/16V

VTTLF_
VTTLF_

C938

0.47UF/16V

+2.5VS
+1.5VS

+VCCP_A

GTL+

12

12

C906

4.7UF/10V

2.2UF/6.3V

Layout Note:
Place in cavity

+3VS_DAC

+3

VS

R903
0Ohm

@

1 2

Layout Note:
These Caps used in +3VS_TVDACx
should be within 250 mils of edge of
GMCH

CAP3

12

GND

CAP2
CAP1

0.22UF/6.3V

12

12

C939

+3VS

12

GND

3VS_DAC_EN

12

GND

R904

10KOhm

C940

0.1UF/50V

GND

2

800

mA

C907

R902
10Ohm

L90

5

180Ohm/1

00Mhz

21

C915
10UF/10V

+5V

12

C941

4.7UF/16V

GND GND

<Variant Name>

ASUSTeK COMPUTER INC

SizeProject Name

A3

Date:

+VCCP_

AGTL+

37,54
10,20,25,26,37,52

C908

+1.5VS_DAC

2,3,5,6

10

7

Layout Note:
Place on the edge

12

+

CE901
330UF/2V

11G08D23372

GND

D901

3

BAT5

+VCCP_GMCH
+1.5VS_PCIE

+3VS
+2.5VS
+1.5VS

12

0.22UF/6.3V

12

Total Power Consumption 120 m

12

12

C916

0.022UF/25V

GNDGND GND

12

C921

0.022UF/25V

GNDGND

12

C925

0.022UF/25V

GNDGND

12

C930

0.022UF/25V

GND GND

U901

1

VIN

5

VOUT

2

GND

4

FB

3

SD#

SI9183DT

T12F

Wednesday, April 26, 2006

1

2

+1.5VS

1
2

4C

A

+3VS_TVB

12

C917

0.1UF/10V

12

C922

0.1UF/10V

12

C926

0.1UF/10V

12

C931

0.1UF/10V

0.1UF/50V

GND GND GND

Title :

Engineer:

G

VCCA_TVBG
Pin H20

+3VS_TVDA

CA

VCCA_TVDACA
Pin E19 F19

+3VS_TVDA

CB

VCCA_TVDACB
Pin C20 D20

+3VS_TVDACC

VCCA_TVDACC
Pin E20 F20

3VS_DAC_ADJ

12

1 2

35.7KOhm

20KOhm

C942

R906

@

1 2

Calistoga Power (4)

Leon and George

9

Sheet

1

R901

•

of

+3VS_DAC

12

Rev

1.0

61

C943

4.7UF/16V

5

www.bufanxiu.com

4

3

2

1

+VCCP_GMCH

C1014

4

+VCCP_GMCH+VCCP_GMCH

12

+

CE1001

220uF/4V

U601G

AD27
AC27
AB27
AA27

Y27

W27

V27
U27
T27

R27
AD26
AC26
AB26
AA26

Y26

W26

V26

U26

T26

R26
AD25
AC25
AB25
AA25

Y25

W25

V25

U25

T25

R25
AD24
AC24
AB24
AA24

Y24

W24

V24

U24

T24

R24
AD23

V23

U23

T23

R23
AD22

V22

U22

T22

R22
AD21

V21

U21

T21

R21
AD20

V20

U20

T20

R20
AD19

V19

U19

T19
AD18
AC18
AB18
AA18

Y18

W18

V18

U18

T18

CALISTOGA_Q137

VCC(GMCH Core)

+1.5VS (5500 mA) or +1.05

121

4

12

CE1002

+

220uF/4V

@

+1.8V

12

10UF/10V

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

12

C1006

10UF/10V

C1012

12

C1007

10UF/10V

Layout Note:
Place in cavity

12

C1001

10UF/10V

NCTF

VS (3500 mA)

12

C1008

1UF/10V

12

+

CE1003

330UF/2.5V

@

12

C1009

0.22UF/6.3V

3200 mA

12

+

CE1004

330UF/2.5V

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

12

C1010

0.22UF/6.3V

121

12

+

CE1005

@

330UF/2.5V

@

GND

3

12

C1011

0.22UF/6.3V

GND

4

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

GND

+1.5VS

U601F

AA33

VCC_0

W33

VCC_1

P33

VCC_2

N33

VCC_3

L33

VCC_4

J33

VCC_5

AA32

VCC_6

Y32

VCC_7

W32

VCC_8

V32

D D

C C

B B

A A

P32
N32
M32
L32
J32

AA31

W31

V31
T31
R31
P31
N31
M31

AA30

Y30

W30

V30
U30
T30
R30
P30
N30
M30
L30

AA29

Y29

W29

V29
U29
R29
P29
M29

L29
AB28
AA28

Y28

V28

U28

T28

R28

P28

N28

M28

L28

P27

N27

M27

L27

P26

N26

L26

N25

M25

L25

P24

N24

M24
AB23
AA23

Y23

P23

N23

M23

L23
AC22
AB22

Y22

W22

P22

N22

M22

L22
AC21
AA21

W21

N21

M21

L21
AC20
AB20

Y20

W20

P20

N20

M20

L20
AB19
AA19

Y19

N19

M19

L19

N18

M18

L18

P17

N17

M17

N16

M16

L16

CALISTOGA_Q137

VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110

VCC

VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107

5

VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8

VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

VCC_SM_1
VCC_SM_2

C1002

0.47UF/16V

VCC_SM_3

VCC_SM_4

VCC_SM_5
VCC_SM_6

0.47UF/16V

12

GND GND

R1.2

12

GND

12

GND

+1.8V

C1013

12

C1003

0.47UF/16V

C1004

0.47UF/16V

C1005

0.47UF/16V

12

12

0.47UF/16V

GNDGND

GND

U601J

J11
D11
B11

AV10
AP10
AL10
AJ10
AG10
AC10

W10

U10
BA9

AW9

AR9
AH9
AB9

Y9
R9
G9
E9

A9
AG8
AD8
AA8

U8

K8

C8
BA7
AV7
AP7
AL7

AJ7
AH7
AF7
AC7

R7
G7

D7
AG6
AD6
AB6

Y6

U6

N6

K6

H6

B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4

AJ4

Y4

U4

R4

J4
F4
C4

AY3

AW3

AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3

G3

AT2
AR2
AP2
AK2

AJ2
AD2
AB2

Y2
U2
T2
N2

J2
H2
F2
C2

AL1

CALISTOGA_Q137

+VCCP_GMCH

VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

+1.5VS

+1.8V

VSS

+1.5VS

9,20,25,26,37,52

+1.8V

7,14,15,37,53

+VCCP_GMCH

2

VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272

9

AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11

GND

U601I

AK34

VSS_97

AG34

VSS_98

AF34

VSS_99

AE34

VSS_100

AC34

VSS_101

C34

VSS_102

AW33

VSS_103

AV33

VSS_104

AR33

VSS_105

AE33

VSS_106

AB33

VSS_107

Y33

VSS_108

V33

VSS_109

T33

VSS_110

R33

VSS_111

M33

VSS_112

H33

VSS_113

G33

VSS_114

F33

VSS_115

D33

VSS_116

B33

VSS_117

AH32

VSS_118

AG32

VSS_119

AF32

VSS_120

AE32

VSS_121

AC32

VSS_122

AB32

VSS_123

G32

VSS_124

B32

VSS_125

AY31

VSS_126

AV31

VSS_127

AN31

VSS_128

AJ31

VSS_129

AG31

VSS_130

AB31

VSS_131

Y31

VSS_132

AB30

VSS_133

E30

VSS_134

AT29

VSS_135

AN29

VSS_136

AB29

VSS_137

T29

VSS_138

N29

VSS_139

K29

VSS_140

G29

VSS_141

E29

VSS_142

C29

VSS_143

B29

VSS_144

A29

VSS_145

BA28

VSS_146

AW28

VSS_147

AU28

VSS_148

AP28

VSS_149

AM28

VSS_150

AD28

VSS_151

AC28

VSS_152

W28

VSS_153

J28

VSS_154

E28

VSS_155

AP27

VSS_156

AM27

VSS_157

AK27

VSS_158

J27

VSS_159

G27

VSS_160

F27

VSS_161

C27

VSS_162

B27

VSS_163

AN26

VSS_164

M26

VSS_165

K26

VSS_166

F26

VSS_167

D26

VSS_168

AK25

VSS_169

P25

VSS_170

K25

VSS_171

H25

VSS_172

E25

VSS_173

D25

VSS_174

A25

VSS_175

BA24

VSS_176

AU24

VSS_177

AL24

VSS_178

AW23

VSS_179

GND

CALISTOGA_Q137

<Variant Name>

ASUSTeK COMPUTER INC

SizeProject Name

Custom

Wednesday, April 26, 2006

Date:

T12F

VSS

Title :

Engineer:

Sheet

1

AC41

VSS_0

AA41

VSS_1

W41

VSS_2

T41

VSS_3

P41

VSS_4

M41

VSS_5

J41

VSS_6

F41

VSS_7

AV40

VSS_8

AP40

VSS_9

AN40

VSS_10

AK40

VSS_11

AJ40

VSS_12

AH40

VSS_13

AG40

VSS_14

AF40

VSS_15

AE40

VSS_16

B40

VSS_17

AY39

VSS_18

AW39

VSS_19

AV39

VSS_20

AR39

VSS_21

AN39

VSS_22

AJ39

VSS_23

AC39

VSS_24

AB39

VSS_25

AA39

VSS_26

Y39

VSS_27

W39

VSS_28

V39

VSS_29

T39

VSS_30

R39

VSS_31

P39

VSS_32

N39

VSS_33

M39

VSS_34

L39

VSS_35

J39

VSS_36

H39

VSS_37

G39

VSS_38

F39

VSS_39

D39

VSS_40

AT38

VSS_41

AM38

VSS_42

AH38

VSS_43

AG38

VSS_44

AF38

VSS_45

AE38

VSS_46

C38

VSS_47

AK37

VSS_48

AH37

VSS_49

AB37

VSS_50

AA37

VSS_51

Y37

VSS_52

W37

VSS_53

V37

VSS_54

T37

VSS_55

R37

VSS_56

P37

VSS_57

N37

VSS_58

M37

VSS_59

L37

VSS_60

J37

VSS_61

H37

VSS_62

G37

VSS_63

F37

VSS_64

D37

VSS_65

AY36

VSS_66

AW36

VSS_67

AN36

VSS_68

AH36

VSS_69

AG36

VSS_70

AF36

VSS_71

AE36

VSS_72

AC36

VSS_73

C36

VSS_74

B36

VSS_75

BA35

VSS_76

AV35

VSS_77

AR35

VSS_78

AH35

VSS_79

AB35

VSS_80

AA35

VSS_81

Y35

VSS_82

W35

VSS_83

V35

VSS_84

T35

VSS_85

R35

VSS_86

P35

VSS_87

N35

VSS_88

M35

VSS_89

L35

VSS_90

J35

VSS_91

H35

VSS_92

G35

VSS_93

F35

VSS_94

D35

VSS_95

AN34

VSS_96

GND

Clistoga GND (5)

Leon and George

10 61

Rev

1.0

of

5

www.bufanxiu.com

MCH_CFG_5

7

12

R1101

2.2KOhm

GND

GND

GND

GND

r0402_h16

12

R1104

2.2KOhm

r0402_h16

12

R1105

2.2KOhm

r0402_h16

12

R1107

2.2KOhm

r0402_h16

D D

MCH_CFG_7

7

MCH_CFG_9

C C

B B

7

MCH_CFG_11

7

CFG5 : DMI

LOW =

@

HIGH = DMI X 4 (Defa

CFG7

LOW = Rese

@

HIGH = Mobility

CFG9 : PCIE GRAP

LOW = RE

@

HIGH = NORMAL OPERATION (De

X2 Select

DMI X 2

: CPU STRAP

rved

CPU (Default)

HIC LANE

VERSE LANES

CFG11 : Reserved but need to

@

ult)

4

fault)

be pull low

MCH_CFG_16

7

MCH_CFG_18

7

MCH_CFG_19

7

+3V

12

GND

12

+3V

R1102

2.2KOhm

r0402_h16

S

R1103
1KOhm

r0402

S

12

3

CFG16 : FSB

LOW = Dynamic

@

HIGH = Dynamic ODT Enabled (Default

DYNAMIC ODT

ODT Disabled

CFG18 : GMCH Core Vol

LOW

= 1.05V

HIGH = 1.5V (default)

@

CFG19

: DMI LANE REVERSAL

LOW = NOR

HIGH = LANES REVER

R1106

@

1KOhm

r0402

MAL

tage Level

SED

)

CFG

2:0
4:3

5
6

7
8

9
11:10

13:12

15:14

16
17

SDVO_C
TRLDATA

18

19

20

2

CFG[17..3] have internal

pullup resistors.
CFG[19..18] have internal pulld
SDVO

CRTL_DATA has internal pulldown

resistor

s.

All are sampled with respect to the
leading edge of the GMCH PWROK

FSB Freq select

DMI X 2 Select

CPU Strap

PCIE Graphics
Lane Reversal

XOR/ALLZ

FSB Dynamic ODT

SDVO Present

VCC select
DMI Lane

Reversal
SDVO/PCIE

concurrent

001 = FSB533
011 = FSB667

0 = DMI X 2
1 = DMI X 4 (Default)

0 = Reserved
1 = Mobile CPU (Default)

0 = Reverse Lanes
1 = Normal (Default)

00 = Partial Clock Gating Disable
01 = XOR Mode Enabled
10 = All-Z Mode Enabled
11 = Normal operation (Default)

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = No SDVO Card Present (Default)
1 = SDVO Card Present

0 = 1.05V (Default)
1 = 1.5V

0 = Normal (Default)
1 = Reverse Lanes

0 = Only SDVO or PCIE x1 is
operational(Default)
1 = SDVO and PCIE x1 are operating
simultaneously via the PEG port

1

own resistors.

A A

5

4

+2.5VS

3

+2.5VS

9,37,54

<Variant Name>

Title :

Calistoga Strapping

ASUSTeK COMPUTER INC

SizeProject Name

Custom

2

Date:

T12F

Wednesday, April 26, 2006

Engineer:

Leon and George

11 61

Sheet

1

Rev

1.0

of

5

www.bufanxiu.com

LCD Panel

SI3865: US$0.22

+1

12

R1204
100KOhm

GND

5

+3V

Q12

02

2N7002

1

1

G

GND

ton

oltage level) to

LCD_BACKOFF#
PCI_RST#
L_BKL

TEN

LID_SW#

L120

9

120Ohm/1

L121

1

120Ohm/1

L121

3

120Ohm/1

12

C1213

c0402

1000PF/50V

N/A

12

32

3

D

S

2

21

00Mhz

@

21

00Mhz

@

21

00Mhz

L121

GND

R1202
100KOhm

12

1000PF/50V

N/A

D D

L_VDDEN

7

GND

C C

LC

D Backlight Control

BI

OS

LCD_

BACKOFF#
When user push "Fn+F7" but
BIOS active this pin to turn On/Off backlig

EC
INVTER_DA:
EC output D/A signal ( adjust v
adjust ba

LCD_BACKOFF#

29

PCI_RST#
L_BKL

7

LID_SW#

29

L_

BKLTCTL

7

INVTER_DA

29

BRIGHT_PWM

29

23
23

cklight

TEN

INTMIC_N
INTMIC_P

B B

A A

1

1

G

ht

4

L1215120Ohm/10
C1221

c0402

3

2

GND

N/A

N/A

2VS

21
21

12

32

D

S

R1203
22kOhm

+3VSLCD_G

Q12

03

2N7002

+3VSLCD_DG

D1204

RB717F

1
2
1
2

D1201

RB717F

L121

120Ohm/1

120Ohm/10

2

0Mhz

GND

00Mhz

0Mhz

12

C1204

1UF/25V

BL_EN_L

3

3

21

12

C1214

c0402

1000PF/50V

4

Power

Q120

1

1

6

D

2

5

+3VSLCD

S

3

4

G

SI3456BDV

Q120

4

2N7002

S

3 2

D

3

2

G

1

1

Inverter Boar
built in 14.1
LCD Panel

+3VS +3VA

12

2 1

INTMIC_N_GND_CON
INTMIC_P_CON

12

1000PF/50V

R1205
10KOhm

r040

2

L121

0

120Ohm/10

C1215

c0402

4

AC_BAT_SYS

0Mhz

12

C1216

0.1UF/25V

L120

l0805_h

80Ohm/10

2 1

12

C1217
1UF/25V

12

0.1UF/10V

GND

7

43

0Mhz

L120
80Ohm/10

C1201

12

C1218

c0402

1000PF/50V

3~3.6V
Full Active: 410 mA(Max. 500

3~3.6V
S0-S1 M: 410 mA(Max. 500 mA)

2

21

0Mhz

12

C1202

0.1UF/10V

12

C1205

10UF/10V

+3

VS

12

C1203

0.01UF/25V

GND

12

C1206

1UF/10V

+3VS_LCD

12

0.1UF/10V

GND

d
W

L120

8

l0805_h

43

80Ohm/10

0Mhz

2 1

INVERTER

AC_INV

LID_SW#_CON

GND

ADJ_BL_CON
BL_EN_CON

+3VA_CON

12

C1219

0.1UF/10V

c0402

GND

700V rms@5
(Min.
rms(Max.
rm

10

3 mA rms)6 mA

s)

3

mA)

C1207

Interface

2122

12

GND1GND2

34
56
78
9

10

1112
1314
1516
1718
1920

mA rms

6.5 mA

3

CON1201

WTOB_CON_20P

12
34
56
78
9
1112

USB_P4-

1314

USB_P4+

1516
1718
1920

GND

+3

VS

+5V_USB

80Ohm/1

LVDS_U1N

7

LVDS_U1P

7

LVDS_U0N

7

LVDS_U0P

7

LVDS_U2N

7

LVDS_U2P

7

LVDS_UCLKN

7

LVDS_UCLKP

7

L120

3

00Mhz

+3VS_LCD

USB4
For
CMOS
Camera

4

2

LCD LVDS Inter

3132

CON1202

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

S

USB_PN4

USB_PP4

21

23

23

25

25

27

27

29

29

WTOB_CON_30P

2

GND

+3VS_LVD

12

C1208

0.1UF

c0402

GND

18

18

21

2

2

4

SIDE1SIDE2

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

+5

V

L120

6

2 1

80Ohm/1

00Mhz

l0805_

h43

face

EDID_CLK_LCD
EDID_DAT_LCD

+3VS_LCD

GND

+5V_USB

4

12

CE1201
22UF/6.3V

c0805

L120

90Ohm/10

@

1 4

2 3

RN1202A

1 2

0OH

M

3 4

0OH

M

RN1202B

<Variant Name>

ASUSTeK COMPUTER INC

SizeProject Name

A3

Thursday, April 27, 2006

Date:

LVDS_L0N
LVDS_L0P

LVDS_L1N
LVDS_L1P

LVDS_L2N
LVDS_L2P

LVDS_LCLKN
LVDS_LCLKP

GND

GND

12

C1211

c0402

0.1UF/10V

1

0Mhz

T12F

12

12

7

7

7

7

7

7

7

7

C1209

0.1UF

c0402
@

120Ohm/10

C1210

0.1UF

c0402
@

12

1000PF/50V

GND

L120

4

120Ohm/1

L120

C1212

c0402

12

D1202

EGA10603

Title :

Engineer:

1

5

0Mhz

@

21

V05A1

21

00Mhz

GND

USB_P4-

USB_P4+

12

D1203

EGA10603

EDID_CLK

EDID_DAT

@

V05A1

ESD G
Cl

ose to

US

B Port

LVDS & INVERTER

Leon and George

12 61

Sheet

1

of

uard

7

7

Rev

1.0

5

www.bufanxiu.com

TV OUT

D D

TV_CV

TV_Y
TV_

BS

C

TV_CVBS7

TV_Y

7

TV_C

7

37.5ohm

12

R1302

150Ohm

@

C C

B B

A A

+3VS

GND

R1303

150Ohm

150Ohm

@

@

1 2

1 2

D1302

2
1

BAV

N/A

TV_C

VBS

3

99

5

R1304

1 2

+3VS

+5VS_CR

+3

C1302
82PF/50V

c0402
@

+5VS

T

R1309
R1310

VS

R1311
R1312

2
1

GND

1 2
1 2

1 2
1 2

D1303

BAV9

N/A

6.8KOhm

6.8KOhm

2.2KOhm

2.2KOhm

12

C1303
82PF/50V

c0402
@

9

D1306

1 2

1N4148W

L130

L130
L130

12

TV_Y

3

PLACE ESD
Diodes near
TV port

DDC2BD_5
DDC2BC_5

CRT_DDC_DATA
CRT_DDC_CLK

2

1
3

C1304
82PF/50V

c0402
@

+5VS_CR

4

21

21
21

4

120Ohm/10

@

120Ohm/10

@

120Ohm/10

@

12

+3VS

T

DDC2BD_5
DDC2BC_5

C1305
82PF/50V

c0402
@

GND

0Mhz

0Mhz
0Mhz

2
1

55ohm

12

C1306
82PF/50V

c0402
@

D1304

BAV

99

N/A

TV_CVBS_CON

TV_Y_CON
TV_C_CON

12

C1307
82PF/50V

c0402
@

GNDGND GND GNDGND GNDGND GNDGND

TV_

3

+3

+3

C

+3VS

+3VS

+3VS

VS

VS

GND

GND

GND

GND

GND

D1309

2
1

BAV

99

D1307

2
1

BAV

99

D1308

2
1

BAV

99

D1305

2
1

BAV

99

D1301

2
1

BAV

99

3

CON1301

MINI_DIN_7P

@

8 9

P_GND1 P_GND2

GND2YC

CVBS1

CVBS2

NC

TV_GND

CRT_RED

3

CRT_GREEN

3

CRT_BLUE

3

HSYNC_5

3

VSYNC_5

3

3

2

CRT OUT

L130

12

C1309
10PF/50V

c0402

12

C1311
10PF/50V

c0402

12

C1301
10PF/50V

c0402

4

150NH

L130

5

150NH

L130

6

150NH

R1307
39Ohm

1 2

R1308
39Ohm

1 2

R1313

1 2

0Ohm

R1314

1 2

0Ohm

+5VS

+5VS

CRT_RED

CRT_GREEN

CRT_BLUE

2

5

2

5

R1301
150Ohm

r040

1 2

R1305
150Ohm

r040

1 2

R1306
150Ohm

r040

1 2

61

Q130
UM6K1N

Q130
UM6K1N

34

61

Q130
UM6K1N

Q130
UM6K1N

34

2

GND

2

GND

2

HSYNC_5

2A

2B

VSYNC_5

DDC2BD_5

1A

1B

DDC2BC_5

2

CRT_RED

CRT_HSYNC

18

CRT_VSYNC

18

CRT_DDC_DATA

7

CRT_DDC_CLK

7

7

CRT_GREEN

7

CRT_BLUE

7

GND1

1234567

GND

R1.2

checklist suggests 47ohm/100MHz

CRT_R_CON

21

12

C1308
10PF/50V

c0402

GND

R1.2

CRT_G_CON

21

12

C1310
10PF/50V

c0402

GND

R1.2

CRT_B_CON

21

12

C1312
10PF/50V

c0402

GND

HSYNC_CON

C1313
47PF/50V

c0402

1 2

GND

VSYNC_CON

C1314
47PF/50V

c0402

1 2

GND

DDC_DAT_CON

C1315
47PF/50V

c0402

1 2

GND

DDC_CLK_CON

C1316
47PF/50V

c0402

1 2

GND

<Variant Name>

ASUSTeK COMPUTER INC

SizeProject Name

A3

Wednesday, April 26, 2006

Date:

13

@

14

@

12

15

D_SUB_15P3R

12G101102152

T12F

1

2

3

CON1302

RED

GREEN

BLUE

HSYNC

VSYNC

DATA

DCLK

Engineer:

1

CRT

SIDE_G16
SIDE_G17

GND3

GND4

GND5

7

8

10

Title :

Sheet

1

9

VCC

4

NC1

11

NC2

15

PI

N

1

16
17

GND

GND2

GND1

6

5

GND

CRT & TV OUT

Leon and George

13 61

Rev

1.0

of

5

www.bufanxiu.com

4

3

2

1

C1405

0.1UF/16V

GND

M_VREF_MCH

C1410

0.1UF/16V

GND

12

+

CE1402
150UF/4V

@

C1412
1UF/6.3V

+1.8V

GND

C1401
1UF/6.3V

Layout Note: Place these Caps nea

C1403

M_CLK_DDR0

C1406

D D

SMBus Slave A

C C

B B

PLACE NEAR SO-DIMM_1

10PF/50V

@

M_CLK_DDR#0

M_CLK_DDR1

C1408

PLACE NEAR SO-DIMM_1

10PF/50V

@

M_CLK_DDR#1

ddress:A0H

5,15,19,25,26
5,15,19,25,26

M_A_A[0..13]

8,16

M_A_B

8,16

M_A_B

8,16

M_A_B

8,16

7,16
7,16

M_CLK_DDR0

7

M_CLK_DDR#0

7

M_CLK_DDR1

7

M_CLK_DDR#1

7

7,16
7,16

M_A_CAS#

8,16

M_A_RAS#

8,16

M_A_W

8,16

SMB_CLK_S
SMB_DA

7,16
7,16

M_A_DM[0..7]

8

M_A_DQS[0..7]

8

M_A_DQS#[0..7]

8

S2
S0

S1
M_CS#0
M_CS#1

M_CKE0
M_CKE1

T_S

M_OD
M_OD

10
11
12
13

CON1401A

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

DDR2_DIMM_200P

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_A_

A0

M_A_

A1

M_A_

A2

M_A_

A3

M_A_

A4

M_A_

A5

M_A_

A6

M_A_

A7

M_A_

A8

M_A_

A9
M_A_A
M_A_A
M_A_A
M_A_A

E#

T0
T1

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

M_A_DQ0

5

M_A_DQ4

7

M_A_DQ2

17

M_A_DQ3

19

M_A_DQ1

4

M_A_DQ6

6

M_A_DQ5

14

M_A_DQ7

16

M_A_DQ12

23

M_A_DQ8

25

M_A_DQ9

35

M_A_DQ10

37

M_A_DQ13

20

M_A_DQ14

22

M_A_DQ11

36

M_A_DQ15

38

M_A_DQ16

43

M_A_DQ17

45

M_A_DQ18

55

M_A_DQ19

57

M_A_DQ20

44

M_A_DQ21

46

M_A_DQ22

56

M_A_DQ23

58

M_A_DQ24

61

M_A_DQ25

63

M_A_DQ26

73

M_A_DQ27

75

M_A_DQ28

62

M_A_DQ29

64

M_A_DQ30

74

M_A_DQ31

76

M_A_DQ37

123

M_A_DQ36

125

M_A_DQ34

135

M_A_DQ35

137

M_A_DQ33

124

M_A_DQ32

126

M_A_DQ38

134

M_A_DQ39

136

M_A_DQ40

141

M_A_DQ41

143

M_A_DQ42

151

M_A_DQ43

153

M_A_DQ45

140

M_A_DQ44

142

M_A_DQ46

152

M_A_DQ47

154

M_A_DQ48

157

M_A_DQ49

159

M_A_DQ50

173

M_A_DQ54

175

M_A_DQ52

158

M_A_DQ53

160

M_A_DQ51

174

M_A_DQ55

176

M_A_DQ60

179

M_A_DQ56

181

M_A_DQ57

189

M_A_DQ58

191

M_A_DQ61

180

M_A_DQ63

182

M_A_DQ62

192

M_A_DQ59

194

M_A_DQ[0..63]

SWAP

SWAP

SWAP

SWAP

SWAP

SWAP

8

C1402

0.1UF/16V

0.1UF/16V

2.2UF/6.3V

VREF -> 10/10 mils

+1.8V +1.8V

GND

+3V

GND

C1409

12

+

CE1401
150UF/4V

@

+1.8V

r SO DIMM 0

C1404

0.1UF/16V

S

C1407

0.1UF/16V

12

GND

GND

C1411
1UF/6.3V

CON1401B

112
111
117

96
95

118

81
82
87

103

88

104
199

83

120

50
69

163

1

201
202

203
204

47
133
183

77

12

48
184

78

71

72
121
122
196
193

8

DDR2_DIMM_200P

C1413
1UF/6.3V

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12

VDDSPD
NC1

NC2
NC3
NC4
NCTEST

VREF
GND0

GND1
NP_NC1

NP_NC2
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

C1414
1UF/6.3V

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162

GND

+1.8V

Layout Note: Place these Caps nea

12

GND

A A

5

4

3

SO-DIMM 0 is placed farther from the
GMCH than SO-DIMM 1

C1419

2.2UF/6.3V

12

2

C1420

2.2UF/6.3V

12

GND

r SO DIMM 0

C1421

2.2UF/6.3V

12

C1422

2.2UF/6.3V

GND GNDGND

<Variant Name>

ASUSTeK COMPUTER INC

Size

Project Name

Custom

Wednesday, April 26, 2006

Date:

12

C1423

2.2UF/6.3V

T12F

Title :

Engineer:

Sheet

1

DDR2 SO-DIMM0

Leon and George

14 61

Rev

1.0

of

5

www.bufanxiu.com

4

3

2

1

12

M_VREF_MCH

12

C1514

0.1UF/16V

c0402

12

C1519

2.2UF/6.3V

GND

+1.8V

C1505

0.1UF/16V

c0402

C1501

0.1UF/16V

C1512

0.1UF/16V

12

CON1501B

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

NC3

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

203

NP_NC1

204

NP_NC2

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

DDR_DIMM_200P

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162

r SO DIMM 0

C1513

0.1UF/16V

-Freq decoupling Caps near the GMCH

12

12

C1516

0.1UF/16V

c0402

GND

C1517

0.1UF/16V

c0402

C1515

0.1UF/16V

c0402

GNDGND

he GMCH

GND

12

C1520

2.2UF/6.3V

12

C1521

2.2UF/6.3V

GNDGND

12

C1522

2.2UF/6.3V

Address reference +1.8V, add four

0.1uF decoupling CAP.

12

C1502

GND

0.1UF/16V

c0402

+1.8V

VREF -> 10/10 mils

+1.8V

+1.8V

D D

SMBus Slave A

M_CLK_DDR2

C1507
10PF/50V

@

M_CLK_DDR#2

M_CLK_DDR3

C1509
10PF/50V

@

C C

B B

M_CLK_DDR#3

+3V

S

ddress:A4H

PLACE NEAR SO-DIMM_0

PLACE NEAR SO-DIMM_0

R1501

1 2

10KOhm

5,14,19,25,26
5,14,19,25,26

M_B_A[0..13]

8,16

M_B_B

8,16

M_B_B

8,16

M_B_B

8,16

7,16
7,16

M_CLK_DDR3

7

M_CLK_DDR#3

7

M_CLK_DDR2

7

M_CLK_DDR#2

7

7,16
7,16

M_B_CAS#

8,16

M_B_RAS#

8,16

M_B_W

8,16

SMB_CLK_S
SMB_DA

7,16
7,16
M_B_DM[0..7]

8

M_B_DQS[0..7]

8

M_B_DQS#[0..7]

8

M_CS#2
M_CS#3

M_CKE2
M_CKE3

T_S

M_OD
M_OD

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

M_B_DQ[0..63]

M_B_DQ5
M_B_DQ0
M_B_DQ7
M_B_DQ3
M_B_DQ4
M_B_DQ1
M_B_DQ6

M_B_DQ2
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15

M_B_DQ16

M_B_DQ17

M_B_DQ18

M_B_DQ19

M_B_DQ20

M_B_DQ21

M_B_DQ22

M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31

M_B_DQ36

M_B_DQ32

M_B_DQ34

M_B_DQ35

M_B_DQ33

M_B_DQ37

M_B_DQ38

M_B_DQ39
M_B_DQ49
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ48
M_B_DQ52
M_B_DQ51
M_B_DQ50

M_B_DQ62

M_B_DQ57

M_B_DQ59

M_B_DQ58

M_B_DQ56

M_B_DQ60

M_B_DQ61

M_B_DQ63

M_B_DQ42
M_B_DQ47
M_B_DQ40
M_B_DQ45
M_B_DQ43
M_B_DQ46
M_B_DQ41
M_B_DQ44

SWAP

Layout Note: Place these Caps nea

SWAP

SWAP

M_B_DQ[0..63]

8

M_B_

A0

M_B_

A1

M_B_

A2

M_B_

A3

M_B_

A4

M_B_

A5

M_B_

A6

M_B_

A7

M_B_

A8

M_B_

A9
M_B_A
M_B_A
M_B_A
M_B_A

S2
S0

S1

E#

+3

VS_SET

T2
T3

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM6
M_B_DM7
M_B_DM5

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS6
M_B_DQS7
M_B_DQS5
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#6
M_B_DQS#7
M_B_DQS#5

CON1501A

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

10
11
12
13

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

DDR_DIMM_200P

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

12

12

C1504

C1503

0.1UF/16V

0.1UF/16V

c0402

c0402

GND GND GND

+3V

S

C1506

0.1UF/16V

C1508
1UF/6.3V

r SO DIMM 0

Layout Note: Place these Caps nea

C1510

C1511

0.1UF/16V

0.1UF/16V

Layout Note: Place these High

GND

Layout Note: Place these CAPs near t

12

C1518

2.2UF/6.3V

GND

A A

<Variant Name>

Title :

DDR2 SO-DIMM1

Sheet

1

Leon and George

15 61

of

Rev

1.0

ASUSTeK COMPUTER INC

Size

Project Name

Custom

5

4

3

2

Date:

T12F

Wednesday, April 26, 2006

Engineer:

5

www.bufanxiu.com

+0.9

VS

M_CKE

1

56Ohm

2

56Ohm

3

56Ohm

4

D D

C C

B B

A A

56Ohm

5

56Ohm

6

56Ohm

7

56Ohm

8 9

56Ohm

1

56Ohm

2

56Ohm

3

56Ohm

4

56Ohm

5

56Ohm

6

56Ohm

7

56Ohm

8 9

56Ohm

1

56Ohm

2

56Ohm

3

56Ohm

4

56Ohm

5

56Ohm

6

56Ohm

7

56Ohm

8 9

56Ohm

1 2

56Ohm

3 4

56Ohm

5 6

56Ohm

7 8

56Ohm

1

56Ohm

2

56Ohm

3

56Ohm

4

56Ohm

5

56Ohm

6

56Ohm

7

56Ohm

8 9

56Ohm

1

56Ohm

2

56Ohm

3

56Ohm

4

56Ohm

5

56Ohm

6

56Ohm

7

56Ohm

8 9

56Ohm

1

56Ohm

2

56Ohm

3

56Ohm

4

56Ohm

5

56Ohm

6

56Ohm

7

56Ohm

8 9

56Ohm

1 2

56Ohm

3 4

56Ohm

5 6

56Ohm

7 8

56Ohm

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

16
15
14
13
12
11
10

RN1602A
RN1602B
RN1602C
RN1602D
RN1602E
RN1602F
RN1602G
RN1602H

RN1603A
RN1603B
RN1603C
RN1603D
RN1603E
RN1603F
RN1603G
RN1603H

RN1604A
RN1604B
RN1604C
RN1604D
RN1604E
RN1604F
RN1604G
RN1604H

RN1605A
RN1605B
RN1605C
RN1605D

RN1606A
RN1606B
RN1606C
RN1606D
RN1606E
RN1606F
RN1606G
RN1606H

RN1607A
RN1607B
RN1607C
RN1607D
RN1607E
RN1607F
RN1607G
RN1607H

RN1608A
RN1608B
RN1608C
RN1608D
RN1608E
RN1608F
RN1608G
RN1608H

RN1609A
RN1609B
RN1609C
RN1609D

M_CKE
M_B_BS2
M_B_A

9
M_B_A12
M_B_A

8
M_B_A11
M_B_A

6
M_B_A

7
M_B_A

5
M_B_A

3
M_B_A

4
M_B_A

2
M_B_A

1
M_B_A

0
M_B_WE

M_B_BS1
M_B_A10
M_B_RAS
M_B_BS0
M_B_A13
M_B_CAS
M_ODT
M_CS#

2

M_CS#

3

M_ODT
M_A_A12

M_A_BS2
M_A_A11
M_A_A

7
M_A_A

6
M_CKE
M_CKE
M_A_A

9

M_A_A

5
M_A_A

4
M_A_A

3
M_A_A

0
M_A_A

2
M_A_A

8

M_A_A10
M_A_BS1
M_A_RAS
M_A_BS0
M_A_A

1
M_A_A13
M_A_CAS
M_A_WE

M_ODT
M_CS#

0

M_CS#

1

M_ODT

2
3

#

#

#

2

3

1
0

#

#

#

0

1

+0.9

+0.9

4

VS

12

C1602

c0402

0.1UF/10V

VS

12

C1614

c0402

0.1UF/10V

3

12

C1603

c0402

0.1UF/10V

12

C1604

c0402

0.1UF/10V

M_A_A[0..13]
M_A_BS[0..2]
M_A_CAS#8,14

M_A_RAS#8,14
M_A_WE#8,14

M_B_A[0..13]
M_B_BS[0..2]
M_B_CAS#8,15

M_B_RAS#8,15
M_B_WE#8,15

M_CS#[0..3]
M_ODT[0..3]
M_CKE[0..3]

12

C1605

c0402

0.1UF/10V

8,14

8,14

8,15

8,15

7,14,15

7,14,15
7,14,15

12

C1606

c0402

0.1UF/10V

Layout note:
Place one cap close to eve

12

C1615

c0402

0.1UF/10V

12

C1616

c0402

0.1UF/10V

12

C1617

c0402

0.1UF/10V

12

C1618

c0402

0.1UF/10V

2

M_VREF_MCH

+0.9

VS

+0.9

VS

L160

1

12

C1607

c0402

0.1UF/10V

12

C1608

c0402

0.1UF/10V

21

120Ohm/100Mh

12

C1609

c0402

0.1UF/10V

z

12

C1610

c0402

0.1UF/10V

M_VREF_MCH

12

C1611

c0402

0.1UF/10V

12

ry 2 pull-up resistors terminated to +0.9VS

12

C1619

c0402

0.1UF/10V

12

C1620

c0402

0.1UF/10V

12

C1621

c0402

0.1UF/10V

12

C1622

c0402

0.1UF/10V

<Variant Name>

12

C1623

c0402

0.1UF/10V

12

C1612

c0402

0.1UF/10V

C1624

c0402

0.1UF/10V

1

M_VREF_MCH
+0.9VS37,53

12

C1601

c0402

0.1UF/10V

12

C1625

c0402

0.1UF/10V

7,14,15

12

GND

12

GND

C1613

c0402

0.1UF/10V

C1626

c0402

0.1UF/10V

Title :

ASUSTeK COMPUTER INC

SizeProject Name

A4

Wednesday, April 26, 2006

5

4

3

Date:

2

T12F

Engineer:

DDR2 TERM

Leon and George

Sheet

16

1

Rev

1.0

61

of

5

www.bufanxiu.com

+VCC_RTC

R1701

20KOhm

C1704

1UF/16V

D D

R1718

LPC_AD0_ICH

LPC_AD1_ICH

LPC_AD2_ICH

LPC_AD3_ICH

LPC_FRAME#_ICH

close to

ACZ_BCLK_AUD

21

C C

ACZ_BCLK_MDC

35

ACZ_SYNC_AUD

21

ACZ_SYNC_MDC

35

ACZ_RST#_AUD

21,22

ACZ_RST#_MDC

35

ACZ_SDOUT_AUD

21

ACZ_SDOUT_MDC

35

B B

IDE_PDIOR#

28

IDE_PDD1

28

IDE_PDD2

28

IDE_PDD9

28

IDE_PDD10

28

A A

R1728

R1720
R1721

R1722
R1723

R1724
R1725

R1726
R1727

ICH7

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

R1731

R1714

1 2

R1729

1 2

1 2

1 2

R1733

1 2

R1734

1 2

R1735

1 2

R1736

1 2

R1737

1 2

5

12

GND

R1708
39Ohm

R1732
R1710

39Ohm

R1717
39Ohm

R1730
39Ohm

@

12

33Ohm

@

33Ohm

33Ohm

33Ohm

33Ohm

39Ohm

@

RTCRST#

JRST1701

1 2

1 2

N/A

33Ohm

33Ohm

@

33Ohm

@

33Ohm

@

33Ohm

@

39Ohm

@

39Ohm

39Ohm

@

0Ohm

0Ohm

0Ohm

0Ohm

0Ohm

@

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

ACZ_BCLK

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

IDE_PDIOR#_ICH

IDE_PDD1_ICH

IDE_PDD2_ICH

IDE_PDD9_ICH

IDE_PDD10_ICH

LPC_AD0_TPM42
LPC_AD0

LPC_AD1
LPC_AD1_TPM42

LPC_AD2
LPC_AD2_TPM42

LPC_AD3
LPC_AD3_TPM42

LPC_FRAME#
LPC_FRAME#_TPM

SATA

_RXN0

28

SATA_RXP

28

SATA

_TXN0

28

SATA_TXP

28

R1.

1

0

0

CLK_PCIE_SATA#

5

CLK_PCIE_SATA

5

26,29

26,29

26,29

26,29

30

26,29

42

SATA_LED

4

#

1 2

1 2

4

ACZ_SDIN0

21

ACZ_SDIN1

35

C1705

28
28
28
28
28

GND

+VCC_RTC

1000PF/50V

C1701

1000PF/50V

@

@

GND

R1719

GND

IDE_PDIOW#
IDE_PDDACK#
INT_IRQ14
IDE_PIORDY
IDE_PDDREQ

C1702

C1703

R1703

1MOhm

1 2
1 2

R1704

330KOhm

T170

3

R1716

1 2

0Ohm

T170

4

T170

5

ACZ_SD

ACZ_SY

EE_C

S

EE_DO

GNT2

#

#

GNT5#/GPI
GNT4#/GPI

12

20PF/50V
X170

1

3

SIDE

32.768KHZ

12

20PF/50V

1

SATA_TXN0_I
SATA_TX

1
1

12

24.9Ohm

IDE_PDIOR#_ICH

IDE_PDIOW#
IDE_PDDACK#
INT_IRQ14
IDE_PIORDY
IDE_PDDREQ

OUT

NC

UT

O17#
O48

2

2

1

1

RTC_X

1

RTC_X

2
RTCRST#
INTRUNDER#

INTVRMEN

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

CH

P0_ICH

SATA2_

R

SAT

A2_TN

SATA2_

TP

SATA2_RBIAS

1%

PWROK ri

PWROK ri

PWROK ri

PWROK ri

3

RTC_X

1

R1702
10MOh

m

RTC_X

2

1 2

U1701A

AB1

RTCX1

AB2

RTCX2

AA3

RTCRST#

Y5

INTRUDER#

W4

INTVRMEN

W1

EE_CS

Y1

EE_SHCLK

Y2

EE_DOUT

W3

EE_DIN

V3

LAN_CLK

U3

LAN_RSTSYNC

U5

LAN_RXD0

V4

LAN_RXD1

T5

LAN_RXD2

U7

LAN_TXD0

V6

LAN_TXD1

V7

LAN_TXD2

U1

ACZ_BCLK

R6

ACZ_SYNC

R5

ACZ_RST#

T2

ACZ_SDIN0

T3

ACZ_SDIN1

T1

ACZ_SDIN2

T4

ACZ_SDOUT

AF18

SATALED#

AF3

SATA0RXN

AE3

SATA0RXP

AG2

SATA0TXN

AH2

SATA0TXP

AF7

SATA2RXN

AE7

SATA2RXP

AG6

SATA2TXN

AH6

SATA2TXP

AF1

SATA_CLKN

AE1

SATA_CLKP

AH10

SATARBIASN

AG10

SATARBIASP

AF15

DIOR#

AH15

DIOW#

AF16

DDACK#

AH16

IDEIRQ

AG16

IORDY

AE15

DDREQ

ICH7M

TP3 pull low: allow entrance t

sing

TP3 not pull low: sets b

sing

sing

sing

sets bit 0 of

should not be pu

should not be pu

should not be pu

low: "top-block s

GNT5# G
0 1
1 0
1 1

NT4#

3

RPC.PC

SPI
PCI
LPC

RTCLAN

AC-97/AZALIASATA

IDE

lled high

lled low

lled low

wap" mode

CPU LPC

GPIO49/CPUPWRGD

it 1 of RPC.PC

+1.5VS_PCIE_ICH

+VCCP_ICH

+VCC_RTC

AA6

LAD0

AB5

LAD1

AC4

LAD2

Y6

LAD3

AC3

LDRQ0#

LFRAME#
A20GATE

A20M#

CPUSLP#

FERR#

IGNNE#

INIT3_3V#

INIT#

INTR

RCIN#

SMI#

STPCLK#

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DA0
DA1
DA2

DCS1#
DCS3#

NMI

AA5
AB3
AE22

AH28
AG27
AF24

AH25
AG26
AG24

AG22
AG21
AF22
AF25

AG23
AH24

AF23
AH22
AF26

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AH17
AE17
AF17

AE16
AD16

LDRQ1#/GPIO23

TP1/DPRSTP#

TP2/DPSLP#

THERMTRIP#

o XOR Chain testing

+VCCP

+1.5VS

+5

VS

+3

VS

+3

VA

LPC_AD0_ICH
LPC_AD1_ICH
LPC_AD2_ICH
LPC_AD3_ICH

LPC_DRQ#0
LPC_DRQ#1

LPC_FRAME#_ICH
A20

GATE

H_A20M#
S_CPUSLP#
S_DPRSTP#

H_DPSLP#
H_FERR#
H_PWRGD

H_IGNNE#
INIT3_3V#
H_INIT#
H_INTR

RCIN#
H_NMI

H_SMI#
H_STPCLK#
S_THRMTRIP#

IDE_PDD0
IDE_PDD1_ICH
IDE_PDD2_ICH
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9_ICH
IDE_PDD10_ICH
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_PDA0
IDE_PDA1
IDE_PDA2

IDE_PDCS1#
IDE_PDCS3#

PD

PD

PD

PU

PU

PUGNT3

PU

1 2
1 2

GPIO

16

/DPRS
GPIO

25

INTVRM

LINKALE

REQ[4:

SATALE

SPK

R

TP

3

2

+1.5VS_PCIE_ICH
+VCCP_ICH
+VCC_RTC
+VCCP
+1.5VS
+5VS4,13,19,20,21,22,28,29,30,37,38,50,61
+3VS4,5,7,9,11,12,13,14,15,19,20,21,22,23,25,26,27,28,29,30,31,32,33,37,39,40,42,43,50,52,60,61
+3VA4,12,20,22,29,37,38,40,54,59,63

LPC_DRQ#0

1

T170

2

A20

GATE

H_A20M#

R1705
0Ohm
R1707
0Ohm

H_PWRGD

H_IGNNE#
H_INIT#

H_INTR
RCIN#

29

H_NMI

2

H_SMI#
H_STPCLK#

R1713

12

24.9Ohm

1%

IDE_PDD0

28

IDE_PDD3

28

IDE_PDD4

28

IDE_PDD5

28

IDE_PDD6

28

IDE_PDD7

28

IDE_PDD8

28

IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_PDA0
IDE_PDA1
IDE_PDA2

IDE_PDCS1#
IDE_PDCS3#

LPVR

RSMRST# r

ALWAY

S

EN

RT#

PWROK ri

1]#

D#

PWROK ri

PWROK ri

2

18,20

20

20
2,6,9,20,52
9,10,20,25,26,37,52

19

29
2

@
@

2

2

1

2

2

+VCCP_ICH

2

2

28
28
28
28
28

28
28
28

28
28

should not be p

should not be p

ising

high: Enable integrated

REQUIRE an extenal

sing

should not be p

high: "No rebo

sing

sing

should not be pulle
using XOR Chain

<Variant Name>

ASUSTeK COMPUTER INC

Size

Custom

Friday, April 28, 2006

Date:

+VCCP_ICH

H_CPUSLP#
H_DPRSTP#

H_DPSLP#

2,6
2,50

2

DPRSTP# routing from Intel 82801GBM to
Yonah processor is required. Routing to VR

T170

1

must be done
filtering to handle daisy chain topology.

R1711
56Ohm

PM_THRMTRIP#

24 ¡Ó 5% series termination resisto
placed within 2" from Intel 82801GBM,
56 ¡Ó 5% pull-up resistor has to b
within 2" from the series resistor

ulled high

ulled low

pull-up R

ulled low

ot" mode

d low unless

testing

Project Name

T12F

1

R1706
56Ohm

H_FERR#

2

last and must have de-bounce

2,4,7

PD

PU

VccSus1_05 VRM

Nee
PU

Conditi
PU

PD

PU

Title :

Engineer:

ICH7-M (1/4)

Leon and George

Sheet

1

d

onal

17 61

of

Rev

1.0

5

www.bufanxiu.com

4

3

2

1

3
4
5
6

0.1UF/10V

c0402

0.1UF/10V

c0402

7

@

8
9
0

1
2
1
3

4
5
6
7

8
9
0

1
2

U1701B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD_1

AD5

RSVD_2

AG4

RSVD_3

AH4

RSVD_4

AD9

RSVD_5

ICH7M

PE_RN1

1

PE_RP1

1

PE_TN1

1

PE

_TP1

1

0.1UF/10V

0.1UF/10V

@

PE_RN4

1

PE_RP4

1

PE_TN4

1

PE

_TP4

1

PE_RN5

1

PE_RP5

1

PE_TN5

1

PE

_TP5

1

PE_RN6

1

PE_RP6

1

PE_TN6

1

PE

_TP6

1

SPI_CLK

1

SPI_CS#

1

SPI_ARB

1

SPI_MOSI

1

SPI_MISO

1

USB_CON_OC01#
USB_CON_OC23#

USB_OC_4#
USB_OC_5#

NEWCARD_OC#

USB_OC_7#

PCI

Interrupt

MISC

U1701D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

_TP3

2

G28
G27

3

M26
M25

N28
N27

R28
R27

K26
K25
J28
J27

L28
L27

P26
P25

T25
T24

R2

P6
P1

P5
P2

D3
C4
D5
D4

E5

C3

A2
B3

PERp2
PETn2
PETp2

PERn3
PERp3
PETn3
PETp3

PERn4
PERp4
PETn4
PETp4

PERn5
PERp5
PETn5
PETp5

PERn6
PERp6
PETn6
PETp6

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

ICH7M

PE_TN
PE_TP2

PE_TN
PE

REQ4#/GPIO22
GNT4#/GPIO48

GPIO1/REQ5#

GPIO17/GNT5#

I/F

GPIO2/PIRQE#
GPIO3/PIRQF#

GPIO4/PIRQG#

GPIO5/PIRQH#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD_6
RSVD_7
RSVD_8
RSVD_9

MCH_SYNC#

PCI-ExpressSPI

Direct Media Interface

USB

PCI_REQ#0

D7

PCI_GNT#0

E7

PCI_REQ#1

C16

PCI_GNT#1

D16

PCI_REQ#2

C17

PCI_GNT#2

D17

PCI_REQ#3

E13

PCI_GNT#3

F13

PCI_REQ#4

A13

PCI_GNT#4

A14

PCI_REQ#5

C8

PCI_GNT#5

D8

PCI_C/BE#0

B15

PCI_C/BE#1

C12

PCI_C/BE#2

D12

PCI_C/BE#3

C15

PCI_IRDY#

A7

PCI_PAR

E10

PCI_RST#_ICH

B18

PCI_DEVSEL#

A12

PCI_PERR#

C9

PCI_LOCK#

E11

PCI_SERR#

B10

PCI_STOP#

F15

PCI_TRDY#

F14

PCI_FRAME#

F16

PLT_R

C26

CLK_ICHPCI

A9

PCI_PME#

B19

PCI_INTE#

G8

PCI_INTF#

F7

PCI_INTG#

F8

PCI_INTH#

G7

S_RSVD6

AE9

S_RSVD7

AG8

S_RSVD8

AH8

S_RSVD9

F21

MCH_ICH_SYNC#

AH20

DMI0RXN

DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN

DMI1RXP
DMI1TXN
DMI1TXP

DMI2RXN

DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN

DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN

DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

3

ST#_SB

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

T180

5

1

T180

7

1

T180

9

1

T181

1

1

DMI_RXN0
DMI_RXP0
DMI_

TXN0

DMI_TXP
DMI_RXN1

DMI_RXP1
DMI_

TXN1

DMI_TXP
DMI_RXN2

DMI_RXP2
DMI_

TXN2

DMI_TXP
DMI_RXN3

DMI_RXP3
DMI_

TXN3

DMI_TXP
CLK_PCIE_ICH#

CLK_PCIE_ICH

DMI_COMP

USB_PN0_B
USB_PP0_B
USB_PN1_B
USB_PP1_B
USB_PN2_B
USB_PP2_B
USB_PN3_B
USB_PP3_B
USB_PN4_B
USB_PP4_B
USB_PN5_B
USB_PP5_B
USB_PN6_B
USB_PP6_B
USB_PN7_B
USB_PP7_B

USBRBIAS_PN

PCI_REQ#0

1

PCI_REQ#1
PCI_GNT#1

31,43
PCI_REQ#2
PCI_GNT#2

34
PCI_REQ#3

1
PCI_REQ#4

PCI_REQ#5

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_IRDY#

19,31,34,43
PCI_PAR

31,34,43

PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
PCI_SERR#
PCI_STOP#

19,31,34,43
PCI_TRDY#
PCI_FRAME#

CLK_ICHPCI
PCI_PME#

19,31,34,43

PCI_INTE#

19

PCI_INTF#

19

PCI_INTG#

19
PCI_INTH#

19

MCH_ICH_SYNC#

0

1

2

3

R1804

1 2

R1805

1 2

22.6Ohm

19

T180

2

19,31,43
19,34
19

T180

3

19
19

31,34,43
31,34,43
31,34,43
31,34,43

19,31,34,43
19,31,34,43
19
19,31,34,43

19,31,34,43

19,31,34,43

5

7

DMI_RXN0
DMI_RXP0
DMI_

TXN0

DMI_TXP
DMI_RXN1

DMI_RXP1
DMI_

TXN1

DMI_TXP
DMI_RXN2

DMI_RXP2
DMI_

TXN2

DMI_TXP
DMI_RXN3

DMI_RXP3
DMI_

TXN3

DMI_TXP
CLK_PCIE_ICH#

CLK_PCIE_ICH

24.9Ohm

USB_PN0
USB_PP0
USB_PN1
USB_PP1
USB_PN2
USB_PP2
USB_PN3
USB_PP3
USB_PN4
USB_PP4
USB_PN5
USB_PP5
USB_PN6
USB_PP6
USB_PN7
USB_PP7

1%

GND

R1802
1KOhm

@

1 2
1 2

R1803
1KOhm

@

7
7
7

0 7

7
7
7

1 7

7
7
7

2 7

7
7
7

3 7

5

5

1%

+1.5VS_PCIE_ICH

36
36
36
36
36
36
36
36
12
12
27
27
25
25
39
39

LPC
PCI

GND

PCI_RST#_ICH

PLT_RST#_S

C1802

0.01UF/10V

PLT_R

ST#_SB

DAC_HSYNC_GM

7

DAC_VSYNC_GM

7

Layout Note:
Pull-ups must be placed within 500
mils from Intel 82801GBM pins

2

B_R

@

GNT#
11
10
01SPI

12

R1801

1 2

0Ohm

<Variant Name>

Date:

GNT#

4

5

1

(defau

lt)

1
0

1
0

1

+3V

147

U1801B

VCC

4
5

GND

2
1

14 7

+3V

ASUSTeK COMPUTER INC

Size

Custom

Wednesday, April 26, 2006

6

SN74LV08APWR

U1801A

GND

3

VCC

SN74LV08APWR

PLT_RST#_S

+3V

147

U1801C

VCC

9

10

GND

SN74LV08APWR

+3V

147

U1801D

VCC

12
13

GND

SN74LV08APWR

Project Name

T12F

PCI_RST#

12,26,31,34,43

Do not connect to reset on PCI
down devices.

PLT

_RST#

7,19,25,28,29,42

+3V

C1803

0.1UF/10V

B_R

1 2

8

11

CRT_HSYNC

CRT_VSYNC

USB Devices

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7

CON3602
CON3603
CON3601
CON3601
CMOS Camara
BlueTooth
NewCard
FingerPrint

Title :

Engineer:

Sheet

1

ICH7-M (2/4)

Leon and George

13

13

18 61

of

Rev

1.0

PCI_AD[31:0]

31,34,43

PCI Device

D D

Devic

e

IDSEL#REQ#/G

CardB

us

AD17

LAN

AD23

Mini-PCIAD19 REQ3#/G

C C

B B

A A

+3VSUS

RN1802A
RN1802B
RN1802C
RN1802D
RN1803A
RN1803B
RN1803C
RN1803D

1 2

10KOhm

3 4

10KOhm

5 6

10KOhm

7 8

10KOhm

1 2

10KOhm

3 4

10KOhm

5 6

10KOhm

7 8

10KOhm

5

REQ1#/G
REQ2#/G

NT#

Interrup

NT1#AB, C,
NT2#
NT3#

E,

26
26
26
26

25
25
25
25

USB_CON_OC01#
USB_CON_OC23#
USB_OC_7#
NEWCARD_OC#
USB_OC_5#
USB_OC_4#
SYS_RST#
PM_RI#

ts

D

F

PCI_INTA#

19,34

PCI_INTB#

19,31,43

PCI_INTC#

19,31,43

PCI_INTD#

19,43

PCIE_RXN2_MINICARD
PCIE_RXP2_MINICARD
PCIE_TXN2_MINICARD
PCIE_TXP2_MINICARD

PCIE_RXN3_NEWCARD
PCIE_RXP3_NEWCARD
PCIE_TXN3_NEWCARD
PCIE_TXP3_NEWCARD

36
36

25

SYS_RST#
PM_RI#

19

T180
T180
T180
T181
T181

USB_CON_OC01#
USB_CON_OC23#

NEWCARD_OC#

19

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#

S_RSVD1

4

1

S_RSVD2

6

1

S_RSVD3

8

1

S_RSVD4

0

1

S_RSVD5

2

1

T181
T181
T181
T181

C1801

1 2

C1806

1 2

C1804

1 2

C1805

1 2

T181
T181
T181
T182

T182
T182
T180
T182

T182
T182
T182
T182

T182
T182
T183

T183
T183

4

5

www.bufanxiu.com

4

3

2

1

SMB_

CLK

SMB_DA

T
LINKALERT#
SM_LINK0
SM_LINK1

T#

5
6

T191

@

1
1

0Ohm

1

PM_RI#
SB_SPKR

PM_SUS_STA
SYS_RST#

PM_BMBUSY#
SM

B_ALERT#

STP_PCI#
STP_CPU#

BT_DET

#

PM_CLKRUN#
GPIO33

GPIO34
PCIE_WAKE#

INT_SERIRQ
PM_THERM#

VRMPWRGD
BT_L

ED

GPIO7

1

EXTSM

I#

PM_RI#

5,50

25,26

29

18

SB_SPKR

21

PM_SUS_STA

42

SYS_RST#

18

PM_BMBUSY#

7

STP_PCI#

5

STP_CPU#

27

PM_CLKRUN#

PCIE_WAKE#
INT_SERIRQ
PM_THERM#

BT_LED38

EXTSM

29

BT_DET#

1 2

R1907

T190
T190

I#

D D

31,34,42,43

29,31,42,43

IMVPOK40

C C

U1701C

C22
B22
A26
B25
A25

A28
A19

T#

A27
A22

AB18

B23

AC20

AF21

A21
B21

E23

AG18
AC19

U2

F20

AH21

AF20
AD22
AC21

AC18

E21

ICH7M

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RI#
SPKR

SUS_STAT#
SYS_RST#

GPIO0/BM_BUSY#
SMBALERT#/GPIO11
GPIO18/STPPCI#

GPIO20/STPCPU#
GPIO26
GPIO27

GPIO28
GPIO32/CLKRUN#
GPIO33/AZ_DOCK_EN#

GPIO34/AZ_DOCK_RST#
WAKE#

SERIRQ
THRM#

VRMPWRGD
GPIO6

GPIO7
GPIO8

SATA

SMB

GPIO16/DPRSLPVR

SYS GPIO

Power MGT

GPIO

GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP

GPIO

GPIO37/SATA3GP

CLK14
CLK48

SUSCLK

Clocks

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

TP0/BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39

AF19
AH18
AH19
AE19

AC1
B2

C20
B24

D23
F22

AA4
AC22
C21
C23

C19
Y4
E20

A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

GPIO21
GPIO19

PCB_ID0
CLK_ICH14

CLK_USB48
SUSCLK
SLP_S

3#

SLP_S

4#

SLP_S

5#
ICH_PWROK
PM_DPRSLPVR
PM

_BATLOW#

PM_PWRBTN#

PLT_RST#
PM

_RSMRST#

SAT

A_DET#0
GPIO10
KB_SCI#
GPIO13
GPIO14
WLAN_LED#
P4G_LED#
CB_SD#
GPIO35
PCB_ID1
PCB_ID2

R1902

100Ohm

12

T190

2

1

CLK_ICH14

SUSCLK

R1903

0Ohm

12

R1904

0Ohm

12

1

T190

PM_DPRSLPVR

PM_PWRBTN#

PM

_RSMRST#

T190

7

1
1

1

1

T190
T190

1
8

T191

KB_SCI#

WLAN_LED#
P4G_LED#
CB_SD#

2

PM

GPIO Power Plane

CPU V

core

GPIO[

5V Cor

e

3.3V C

ore

3.3V Resume

PCB_ID0
PCB_ID1
PCB_ID2

SMB_CL

SM

B_DAT_S

+3

5,14,15,25,26

B B

5,14,15,25,26

A A

49]

GP

IO[5:1]

GPI

O[0][7:6][23:16][39:32][48]

GPIO[15:8

K_S

VS

+3

VS

12

12

R1929

R1930

8.2KOhm

8.2KOhm

@

@

r0402_

h16

r0402_

12

12

5

R1934

8.2KOhm

r0402_

R1935

8.2KOhm

r0402_

h16

GND

][31:24]

Q19032N7002

S

2

G

1

1

1

1

G

2

S

Q19012N7002

+3VS

12

h16

12

h16

D

32

3

+5VS

3

32

D

R1931

8.2KOhm

@
r0402_

R1936

8.2KOhm

r0402_

SMB_

CLK

SMB_DA

T

PCB_VID3 : PROJECT

h16

PCB_VID
MB V1.

h16

+5VS

Q190

2

1

2N7002

1

ICH_PWROK

3 2

3

D

G

S

2

GND

VRMPWRGD

R1914
10KOhm

1 2

CODE

0 1

2

0 0

0

0

4

D

PRSLPVR contains same information

as DPRSTP#.

GND

DPRSLPVR is preferred over DPRSTP#
if only one signal will be used.

5

42

PM_SUSB#29
PM_SUSC#

4

29

38

43

29

7,50

R1905
10KOhm

29

1 2

GND

29

R1906
10KOhm

1 2

30

GND

Internal pull high

_BATLOW#

1 2

18,31,34,43

3

D1901

1N4148W

checklist suggests
+3Vsus

PCI_PME#

C1901

@

10PF/50V

1 2

GND

ICH_PWROK

PL

T_RST#

If ICH7M embedded Lan
controller was used
"LAN_RST#" should be
connected to "RSMRST#"

CLK_USB48

7,29

7,18,25,28,29,42

BAT_LL#

29

KB_SCI#

SM

B_ALERT#

PM

_BATLOW#

SAT

A_DET#0

BT_DET#

WLAN_LED#
P4G_LED#

SMB_C

LK
SMB_DAT
PCIE_WAKE#

SM_LINK1
LINKALERT#
SM_LINK0

PM_SUS_STA

PCI_PME#

Internal pull up

5

T#

CLK_ICH14

R1908

1 2

R1910

1 2

R1915
R1917

1 2

R1919

1 2

R1923

1 2

R1939

1 2

R1926

1 2

R1927

1 2

R1928

1 2

RN1902A
RN1902B
RN1902C
RN1902D

R1937

1 2

R1938

1 2

C1902
10PF/50V

1 2

GND

10KOhm

10KOhm

8.2KOhm

12

8.2KOhm

8.2KOhm

8.2KOhm

8.2KOhm

2.2KOhm

2.2KOhm
1KOhm

1 2

10KOhm

3 4

10KOhm

5 6

10KOhm

7 8

10KOhm

4.7KOhm

@

10KOhm

@

@

+3VSUS

+3VSUS

2

18,31,34,43

18,31,34,43
18,31,34,43

18,31,34,43
18,31,34,43

18,31,43

18,31,43

18,31,43

18,31,34,43
18,31,34,43

PCI_TRDY#
PCI_LOCK#

18

PCI_SERR#

PCI_PERR#
18
18

PCI_IRDY#

PCI_DEVSEL#

18,34

18,43

18
18
18
18

18

18,34

18

PCI_FRAME#

PCI_STOP#

LPC_DRQ#0

17

PCI_REQ#5
PCI_REQ#0

PCI_INTB#
PCI_INTA#
PCI_INTC#
PCI_INTD#
PCI_INTG#
PCI_INTF#
PCI_INTH#
PCI_INTE#

PCI_REQ#4
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

PCI_TRDY#
PCI_LOCK#
PCI_SERR#
PCI_PERR#
PCI_REQ#5
PCI_REQ#0
PCI_IRDY#
PCI_DEVSEL#

PCI_INTB#
PCI_INTA#
PCI_INTC#
PCI_INTD#
PCI_INTG#
PCI_INTF#
PCI_INTH#
PCI_INTE#

PCI_REQ#4
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PM_CLKRUN#
PM
PCI_FRAME#
PCI_STOP#

SMB_CL
SM

INT_SERIRQ
STP_PCI#
STP_CPU#

GPIO19

LPC_DRQ#0

Internal pull up

PM

PM_DPRSLPVR

Internal pull down

<Variant Name>

ASUSTeK COMPUTER INC

SizeProject Name

A3

Wednesday, April 26, 2006

Date:

_THERM#

B_DAT_S

_RSMRST#

T12F

K_S

RP1902A
RP1902B
RP1902C
RP1902D
RP1902E
RP1902F
RP1902G
RP1902H

RP1903A
RP1903B
RP1903C
RP1903D
RP1903E
RP1903F
RP1903G
RP1903H

RP1904A
RP1904B
RP1904C
RP1904D
RP1904E
RP1904F
RP1904G
RP1904H

R1911
R1912

R1916

1 2

R1918

1 2

R1901

1 2

R1922

R1925

R1932

1 2

R1933

1 2

Title :

Engineer:

1 5

8.2KOHM

2 5

8.2KOHM

3 5

8.2KOHM

4 5

8.2KOHM

6 5

8.2KOHM

7 5

8.2KOHM

8 5

8.2KOHM

9 5

8.2KOHM

1 5

8.2KOHM

2 5

8.2KOHM

3 5

8.2KOHM

4 5

8.2KOHM

6 5

8.2KOHM

7 5

8.2KOHM

8 5

8.2KOHM

9 5

8.2KOHM

1 5

8.2KOHM

2 5

8.2KOHM

3 5

8.2KOHM

4 5

8.2KOHM

6 5

8.2KOHM

7 5

8.2KOHM

8 5

8.2KOHM

9 5

8.2KOHM

12
12

12

12

Sheet

1

+3VS

10
10
10
10
10
10
10
10

10
10
10
10
10
10
10
10

10
10
10
10
10
10
10
10

2.2KOhm

2.2KOhm

10KOhm
10KOhm

@

10KOhm

@

8.2KOhm

8.2KOhm

@

10KOhm

100KOhm

@

GND

ICH7-M (3/4)

Leon and George

19 61

of

Rev

1.0