Asus D1T Service Manual Chapter 07-v1.0

Software Specifications

T

Get to know more about the D1000 Series Portable Desktop with a
detailed look at the software specifications.

he information contained in the chapter can be quite useful when you are
troubleshooting the system’s hardware. Each item has its individual usage for you to
understand the software side of the Portable Desktop’s architecture.
Th is chapter includes specifications about:

• System features

• BIOS Specifications

Chapter

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SOFTWARE SPECIFICATIONS

1. General Description

The specification is a guideline for bios development on D1 platform. It is for internal use only. Anyone
who need the system bios information can check this document for reference.

The general device specification, hardware block diagram, SMBUS, PCI Devices IRQ Routing Table,
GPIO definition and so on are subjected to be depicted in this document. Hotkeys implementation and
other bios features are also included in the document.

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SOFTWARE SPECIFICATIONS

1. 2. CPU, Chipsets & Main Devices

Item

CPU
North Bridge
South Bridge
VGA
Audio Codec
Modem Codec
USB
Lan
Cardbus
IEEE1394
AC97 Controller
MC97 Controller
Glock Gen.
SIO

Vendor

Intel

Specification Part’s Name Revision

Northwood B0/C1
SiS 650M
SiS 962
SiS 650M
Realtekl ALC650
Lucent
SiS 962
Broadcom BCM4401KFB
ENE CB710
SiS 962
SiS 7012
SiS 7013
ICS 952003AF
ITE IT8705F

Table 2-1

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SOFTWARE SPECIFICATIONS

3. PCI Devices & Interrupt Routing Table

Table 3-1

Device Vendor Bus # Device # Function # INTA INTB INTC INTD INTE INTF INTG INTH

Host bridge
PCI2PCI

SiS 0 0 0 N/A N/A N/A N/A N/A N/A N/A N/A
SiS 0 1 0 N/A N/A N/A N/A N/A N/A N/A N/A

Bridge
USB
USB
USB
USB
LPC Bridge
IDE
SMBus1
Audio
Modem
IEEE 1394
VGA
Lan
Cardbus slot

SiS 0 3 0 N/A N/A N/A N/A *PIRQA N/A N/A N/A
SiS 0 3 1 N/A N/A N/A N/A N/A *PIRQB N/A N/A
SiS 0 3 2 N/A N/A N/A N/A N/A N/A *PIRQC N/A
SiS 0 3 3 N/A N/A N/A N/A N/A N/A N/A *PIRQD
SiS 0 2 0 N/A N/A N/A N/A N/A N/A N/A N/A
SiS 0 2 5 N/A N/A N/A N/A N/A N/A N/A N/A
SiS 0 2 1 N/A N/A N/A N/A N/A N/A N/A N/A
SiS 0 2 7 N/A N/A *PIRQC N/A N/A N/A N/A N/A
SiS 0 2 6 N/A N/A *PIRQC N/A N/A N/A N/A N/A
SiS 0 2 3 N/A *PIRQB N/A N/A N/A N/A N/A N/A
SiS 1 0 0 PIRQA N/A N/A N/A N/A N/A N/A N/A
Broadcom 0 15 0 PIRQC N/A N/A N/A N/A N/A N/A N/A
ENE 0 16 0 PIRQA PIRQD N/A N/A N/A N/A N/A N/A

* : DEVICE INTERNAL ROUTING

1

: Device Hidden

4. GPIO Definition Tables

The following tables are the definition of GPIO pins which included of south bridge(SIS962),
KBC(KB3886) and super IO(IT8705F). Some of GPIO pins need to be initialized by system BIOS and
some of them need the driver to support. Please check the Description column for reference.

Table 4-1. SIS962 GPIO Definition

GPIO Type Multi-function Definition Activated

Level

GPIO0/SPDIF

O

0

O GPIO1/LDRQ1# BIT1 N/A CPU Vcore over-voltage BIT1

1

I GPIO2/THERM# THERM# Low

2

I GPIO3/EXTSMI# EXTSMI# Low From KBC, notify system the SMI

3

O GPIO4/CLKRUN# GPO4 N/A N/A

4

O GPIO5/PREQ5# POW High Disable auto power off function

5

O GPIO6/PGNT5# GP6 High Enable KBC SCI

6

I GPIO7 GPWAKE Low Audio DJ power button

7

I GPIO8/RING LID# Low LID switch off

8

GPIO9/AC_SDIN2

O

9

BIT0 N/A CPU Vcore over-voltage BIT0

KBC SCI High From KBC, notify system the SCI

NOTIFY SYSTEM
THE THERMAL
EVENT

event

Description

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SOFTWARE SPECIFICATIONS

N/A GPIO10/AC_SDIN3 N/A N/A N/A

10
11
12

13

14
15
16
17
18

O GPIO11 BACK_OFF# Low Turn off the LCD back light

I GPIO12/CPUSTP# CPUCD# Low A preliminary control signal

GPIO13/DPRSLPVR

I

GPIO14

I

VCORECD# Low

BATIN# Low High/Low: AC adapter/Battery

O GPIO15 N/A N/A N/A

GPIO16

O

N/A N/A N/A
O GPIO17 N/A N/A N/A
O GPIO18 N/A N/A N/A

* : PU -> Pull Up, PD -> Pull Down, NC -> Not Connected

1

: powered in resume well.

event

intends to put CPU into low
frequency mode

A PRELIMINARY
CONTROL SIGNAL
INTENDS TO PUT
CPU INTO LOW
FREQUENCY
MODE

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SOFTWARE SPECIFICATIONS

5. Devices

5.0 – CPU

Intel P4 is designed in the D1 system.

5.1 - NORTH BRIDGE (SIS650M)

5.1.1 – Function & Feature

The device is one of key part of system. It provides the interface control of Processor, Memory, AGP
and SiS962. In power management, it is in compliance with ACPI2.0 and APM1.2.

In memory system, it supports 266MHz DDR devices and 64Mb, 128Mb, 256Mb and 512Mb
technologies for x16 devices and x8 devices. By using 512Mb technology, the largest memory
capacity possible is 1.0GB

In AGP interface, it uses the internal VGA Controller.

In SiS962 interface, it supports high throughput SiS MuTIOL connection to SiS962 MuTIOL Media
I/O.

a. Bi-directional 16 bit data bus.
b. Perform 533MB/s bandwidth in 66MHz x 4 mode
c. Distributed arbitration strategy with enhanced mode of contiguous DMA data streaming
d. Packet based, pipelining, and split transaction scheme

5.1.2 – PCI Address

The device is internally located on PCI address 0x80000000.(Bus 0, Device 0, Function 0). Please
check Table 3-1

for reference.

5.1.3 – Sub-system & Sub-vendor ID

Subsystem ID : 0x8081
SubVendor ID : 0x1043

5.1.4 – DRAM TYPE Registers

The DRAM Type Register defines the type (NBA*NRA*NCA) and side of each pair of DRAM rows.
The offset of these registers are 60h~62h. The following is the mapping of the registers.

DRT0(row 0) : 60h
DRT1(row 1) : 61h
DRT2(row 2) : 62h

The supported DDR type
Bank x Row x Column Bank x Row x Column

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