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This book is written for system designers, system integrators, and programmers who are
designing or programming a System-on-Chip (SoC) that uses the AMBA Network Interconnect.
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for a high-level view of the AMBA Network Interconnect and a
description of its features.
Conventions
Chapter 2 Functional Description
Read this for a description of the major interfaces and components of the AMBA
Network Interconnect. The chapter also describes how they operate.
Chapter 3 Programmers Model
Read this for a description the address map and registers of the AMBA Network
Interconnect.
Appendix A Revisions
Read this for a description of the technical changes between released issues of this
book.
Glossary Read this for definitions of terms used in this book.
Conventions that this book can use are described in:
•Typographical.
•Signals on page viii.
Typographical
The typographical conventions are:
italicHighlights important notes, introduces special terminology, denotes
internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal
names. Also used for terms in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file
The AMBA Network Interconnect is a highly configurable component that enables you to create
a complete high performance, optimized AMBA-compliant network infrastructure. The
possible configurations for the AMBA Network Interconnect can range from a single bridge
component, for example an AHB to AXI protocol bridge, to a complex infrastructure that
consists of up to 128 masters and 64 slaves of a combination of different AMBA protocols.
An AMBA Network Interconnect configuration can consist of multiple switches with many
topology options. Figure 1-1 shows a top-level block diagram of the AMBA Network
Interconnect that contains:
The AMBA Network Interconnect is a highly configurable infrastructure component that
supports:
•1-128 AXI or AHB-Lite slave interfaces.
•1-64 master interfaces that can be AXI, AHB-Lite, APB2, or APB3.
•Configuration of:
—an APB port to support 1-16 slaves
—an AXI port to support four region control bits.
•Single-cycle arbitration.
•Full pipelining to prevent master stalls.
•Programmable control for FIFO transaction release.
•Multiple switch networks.
•Complex topologies, including Network On Chip (NOC) loop-back connections between
switches.
•Up to five cascaded switch networks between any master and slave interface pair.
•AXI or AHB-Lite masters and slaves with:
—an address width of 32-64 bits
—a data width of 32, 64, 128, or 256 bits.
•Non-contiguous APB slave address map for a single master interface.
•Independent widths of user-defined sideband signals for each channel.
•Global Programmers View (GPV) for the entire infrastructure that you can configure so
that any master, or a discrete configuration slave interface, can access it. See Chapter 3
Programmers Model.
1.3Relationship between AMBA Network Interconnect and AMBA Designer
AMBA Designer is a configuration tool that generates a specific implementation of an AMBA
Network Interconnect. AMBA Designer drives the AMBA Network Interconnect generation
engine to provide the following for a set of configuration parameters and implementation
scripts:
•Verilog Register Transfer Level (RTL)
•testbench and stimulus synthesis scripts.
The documentation suites and implementation scripts for the AMBA Network Interconnect and
AMBA Designer are designed to be used together to describe the principles of the AMBA
Network Interconnect and the actual configuration options. There is no duplication between the
two sets of documentation. The following sections describe the information that each
documentation suite provides:
•AMBA Network Interconnect documentation
•AMBA Designer documentation.
1.3.1AMBA Network Interconnect documentation
The AMBA Network Interconnect documentation consists of:
TRM The Technical Reference Manual (TRM) describes how to create the transfer
function and possible capabilities of the network component and how to
dynamically change it using the programmers model.
Introduction
IG The Implementation Guide (IG) describes how to set up the network environment
and how to use it to run RTL simulations or implementation scripts.
IM The Integration Manual (IM) describes how to integrate a configured network
into a larger subsystem.
1.3.2AMBA Designer documentation
The AMBA Designer (FD001) User Guide describes how to:
•Install AMBA Designer.
•Generate and verify RTL sub-systems of ARM IP.
•Stitch ARM components together. ARM components conform to the IP-XACT
from the SPIRIT Consortium
The AMBA Network Interconnect (NIC-301) Supplement to AMBA Designer (ADR-301) User Guide describes how to produce a customized infrastructure.
•use of an AHB to AXI bridge optimized for accessing memory where
appropriate.
•Separation of arbitration of AW and AR channels so that a slave can accept
transactions from two different masters simultaneously.
•Changes to the way that the AMBA Network Interconnect handles
LOCKed transactions.
•Configurable arbitration schemes, that can be:
—programmable Least Recently Granted (LRG), the scheme present in
r1p0
—a non-programmable Round-Robin (RR) scheme.
•You can select and configure arbitration schemes for each master interface.
•The APB programming interface enables you to program and interrogate
the new, separate arbitration schemes.
•The AHB to AXI bridge is optimized for accessing memory is updated with
performance enhancements, and to fix a defect.
•The way arbitration schemes are described has changed to enable you to
select and configure arbitration schemes.
•The Quality of Service (QoS) tidemark value now represents the maximum
permitted number of active transactions before the QoS mechanism is
activated, instead of the minimum number of unused slots before the
mechanism is activated. This means the combined acceptance capability
attribute of a master interface is no longer required.
r1p1-r1p2 Contains the following differences in functionality:
•Updates to the example synthesis scripts.
•Addition of a programmable version of the fixed round-robin arbitration
scheme.
•Shortening some long paths to improve synthesis performance.
•A change to the way register slices are instantiated. This makes it easier to
use them to resolve timing issues during synthesis.
•The choice of CDAS is independent for reads and writes.
•Additional configuration option for the single-slave-per-ID CDAS that
permits only a single data-active write transaction to be in progress.
You can consider the AMBA Network Interconnect to be built from functions that each have
their own transfer function. A transfer function can:
•a domain crossing, for example:
—clock domain crossing
—data width crossing.
•used to create timing isolation, for optimizing critical network paths for latency.
Within a domain, a switch, or multiple switches, can exist to enable routing paths between any
slave interface to any master interface.
The functions are configured into routing switches or Interface Blocks (IBs) and you can use
AMBA Designer to create highly complex topologies using these modules. For more
information, see the AMBA Designer (ADR-301) User Guide and AMBA Network Interconnect (NIC-301) Supplement to AMBA Designer (ADR-301) User Guide.