ARM CM940T User Manual

ARM Integrator/CM940T

User Guide

ARM DUI 0125A

ARM Integrator/CM940T User Guide

Release information

Change history

Description Issue Change

8 September1999 A New document

Proprietary notice

ARM, the ARM Powered logo, Thu m b and StrongARM are registered t rademarks of ARM Limited. The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, ARM7TDMI,

ARM7TDMI-S, ARM9TDMI, PrimeCell, and STRONG are trademarks of ARM Limited.

All other products or services mentioned herein may be trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may

be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product describe d in this document is subject to co nt inuous developments an d im provements. All particulars of the produc t and its use contained in this document are given by ARM Limit ed in good faith. However, all warrantie s im plied or expressed, including but not limited to impli ed warranties or merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arisi ng from the use of any informati on in this document, or any error or om ission in such information, or any incorrect use of the product.

Document confidentiality status

This document is Open Access. T his do cument has no restriction on distribution.

Product status

The information in this documents is Final (information on a developed product).

ARM web address

http://www.arm.com

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Electromagnetic conformity

This section contains electromagnetic conformity (EMC) notices.

Federal Communications Commission Notice

NOTE: This equipment has been tested and found to comply with the limits for a class A digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense.

CE Declaration of Conformity

This equipment has been tested according to ISE/IEC Guide 22 and EN 45014. It conforms to the following product EMC specifications:

The product herewith complies with the requirements of EMC Directive 89/336/EEC as amended.

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ARM Integrator/CM940T User Guide

Electromagnetic conformity............................................................................................iii

Preface

About this document....................................................................................................viii

Further reading............................................................................................................... x

Feedback .......................................................................................................................xi

Chapter 1 Introduction

1.1 About the ARM Integrator/CM940T core module..........................................1-2

1.2 ARM Integrator/CM940T overview................................................................1-4

1.3 Links and indicators......................................................................................1-8

1.4 Test points ..................................................................................................1-10

1.5 Precautions.................................................................................................1-11

Chapter 2 Getting Started

2.1 Setting up a standalone ARM Integrator/CM940 T............................. ...... .....2-2

2.2 Attaching the ARM Integrator/CM940T to a motherboard.............................2-5

Chapter 3 Hardware Description

3.1 ARM940T microprocessor core ....................................................................3-2

3.2 SSRAM controller .........................................................................................3-3

3.3 Core module FPGA.......................................... ...... .......................................3-4

3.4 SDRAM controller.........................................................................................3-6

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3.5 Reset controller............................................................................................ 3-8

3.6 System bus bridge...................................................................................... 3-11

3.7 Clock generators........................................................................................ 3-17

3.8 Multi-ICE support........................................................................................ 3-21

Chapter 4 Programmer’s Reference

4.1 Memory organization.................................................................................... 4-2

4.2 Exception vector mapping............................................................................ 4-6

4.3 Core module registers..................................................................................4-7

4.4 Interrupt registers....................................................................................... 4-19

Appendix A Signal Descriptions

A.1 HDRA ...........................................................................................................A-2

A.2 HDRB ...........................................................................................................A-4

Appendix B Specifications

B.1 Electrical specification..................................................................................B-2

B.2 Timing specification......................................................................................B-3

B.3 Mechanical details........................................................................................B-4

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Preface

This preface introduces the ARM Integrator/CM940T core module and its reference documentation. It contains the following sections :

• About this document on page viii

• Further reading on page x

• Feedback on page xi.

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vii

About this document

This document describes how to set up and use the ARM Integrator/CM940T core module.

Intended audience

This document has been written for experienced hardware and software developers to aid the development of ARM-based products using the ARM Integrator/CM940T as part of a development system.

Organization

This document is organized into the following chapters:

Chapter 1 Introduction

Chapter 2 Getting Started

Chapter 3 Hardware Description

Read this chapter for an introduction to the core module.

Read this chapter for a description of how to set up and start using the core module.

Read this chapter for a descr iption of the header’s hardwar e architecture, including clocks, resets, and debug.

viii

Chapter 4 Programmer’s Reference

Read this chapter for a description of the header memory map and registers.

Appendix A Signal Descript i ons

Refer to this appendix for a description of t he sign al s on the HDRA and HDRB connectors.

Appendix B Specifica tions

Refer to this appendix for electrical, timing, and mechanical specifications.

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Typographical conventions

The following typographical conventions are used in this document: bold Highlights ARM processor signal names within text, and interface

italic Highlights special terminology, cross-references and citations.

typewriter Denotes text that may be entered at the keyboard, such as

typewriter Denotes a permitted abbreviation for a command or option. The

typewriter italic

typewriter bold

elements such as menu names. May also be used for emphasis in descriptive lists where appropriate.

commands, file names and program names, and source code.

underlined text may be entered instead of the full comm a nd or option name.

Denotes arguments to commands or functions where the argument is to be replaced by a specific value.

Denotes language keywords when used outside example code.

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Feedback

ARM Limited welcomes feedback both on the ARM Integrator/CM940T core module and on the documentation.

Feedback on this document

If you have any comments about this document, please send email to

errata@arm.com giving:

• the document title

• the document number

• the page number(s) to which your comments refer

• an explanation of your comments. General suggestions for additions and improvements are also welcome.

Feedback on the ARM Integrator/CM940T

If you have any comments or suggestions about this product, please contact your supplier giving:

• the product name

• an explanation of your comments.

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xii

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Chapter 1

Introduction

This chapter introduces the ARM Integrator/CM940T core module. It contains the following sections:

• About the ARM Integrator/CM940 T core module on page 1-2

• ARM Integrat or/CM940T overv i ew on page 1-4

• Links and indicators on page 1-8

• Test points on page 1-10

• Precautions on page 1-1 1 .

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1-1

Introduction

1.1 About the ARM Integrator/CM940T core module

The Integrator/CM940T core module provides you with the b a sis of a flexible development system which can be used in a number of differ ent ways. Wi th power and a simple connection to a Multi-ICE debugger, the core module provides a basic development system. By mounting th e core mod ule onto a mo therboard , you can build a realistic emulation of the system being developed. Through-board connectors allow up to four core modules to be stacked on one motherboard.

The core module can be used in the following ways:

• as a standalone development system

• mounted onto an ARM Integrator/SP develo pm ent motherboard

• mounted onto an ARM Integrator/AP development motherboard

• integrated into a third-party development or ASIC prototyping system.

Figure 1-1 on page 1-3 shows the layout of the ARM Integrator/CM940T.

1-2

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Introduction

Core module/motherboard

connectors HDRB

Multi-ICE

connector

Processor

core

Power

connector

Reset button DIMM socket

SDRAM DIMM

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Core module/motherboard

connectors HDRA

Memory controller and

system bus bridge (FPGA)

Figure 1-1 Integrator/CM940T layout

1-3

Introduction

1.2 ARM Integrator/CM940T overview

The major components on the core module are as follows:

• ARM940T microprocessor core

• core module FPGA which implements: — SDRAM controller — system bus bridge — reset controller — interrupt controller — status, con f iguration, and interrupt registers.

• volatile memory comprising: — up to 256MB of SDRAM (optional) via DIMM socket — 256KB SSRAM.

• SSRAM controller

• clock generator

• system bus connectors

• Multi-ICE debug connector.

1.2.1 System architecture

1-4

Figure 1-2 illustrates the architecture of the core module.

ARM core

Multi-ICE

SSRAM

FPGA

System bus connectors

Figure 1-2 ARM Integrator/CM940T block diagram

SDRAM

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1.2.2 Core module FPGA

The FPGA provides system control functions for the core module, enabling it to operate as a standalone development system or attached to a motherboard. These functions are outlined in this section and descri bed in detail in Chapter 3 Hardware Description.

SDRAM controller

The SDRAM controller is implemented within the FPGA. This provides support for Dual In-line Memory Modules (DIMMs) with a capacity of between 16 and 256MB. See SDRAM controller on page 3-6.

Reset controller

The reset controller initializes the core and allows the core module to be reset from five sources:

• reset button

• motherboard

• other core modules

• Multi-ICE

• software.

Introduction

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For information about the reset controller, see Reset controller on page 3-8.

System bus bridge

The system bus bridge provides an interface between the memory bus on the core module and the system bus on a motherboard. It allows the local processor access to interface resources on the motherboard and to the SDRAM on other core modules. It also allows access to the local SDRAM from the PCI bridge on the motherboard and processors on other core modules (see System bus bridge on page 3-11).

1-5

Introduction

Status and configuration space

The status and configuration space contains status and configuration registers for the core module. These provide the following information and control:

• type of processor and whether it has a cache, MMU, or protection unit

• the position of the core module in a multi-module stack

• SDRAM size, address configuration, and CAS latency setup

• core module oscillator setup

• interrupt control for the processor debug communications channel.

The status and control registers can only be accessed by the local processor. For more information about the status and control registers see Chapter 4 Programmer’ s

Reference.

1.2.3 Volatile memory

The volatile memory system includes an SSRAM device, and a plug-in SDRAM memory module (referred to as local SDRAM when it is on the same core module as the processor). These areas of memory are closely coupled to the processor core to ensure high performance. Th e cor e mo dul e u ses s eparate memory and system buses to avoid memory access performance being degraded by bus loading.

The SDRAM controller is implemented within the core module controller FPGA and a separate SSRAM controller is implemented with a Programmable Logic Device (PLD).

The SDRAM can be accessed by the local processor, by processors on other core modules, and by other system bus masters.

The SSRAM can only be accessed by the local processor.

1.2.4 Clock generator

The core module uses two on-board clocks:

• CPU clock up to 160MHz

• memory bus clock up to 66MHz.

These clocks are supplied by two clock generator chips. Their frequencies are selected via the oscillator control register (CM_OSC) within the FPGA. A reference clock is supplied to the two clock generators and to the FPGA (see Clock generators on page 3-17). The memory bus and system bus are asynchro nous. This allows each bus to be run at the speed of its slowest device without compromising the performance of othe r buses in the system.

1-6

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1.2.5 Multi-ICE connector

The Multi-ICE connector enables JTAG hardware debugging equipment, such as Multi-ICE, to be connected to the core module. It is possible to bo th drive and sense the system-reset line (nSRST), and to drive JTAG reset (nTRST) to the core from the Multi-ICE connector. See Multi-ICE su pport on page 3-21.

JTAG test equipment supplied by other vendors may also be used.

Introduction

Note

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1-7

Introduction

1.3 Links and indicators

The core module provides one link and four surface-mounted LEDs. These are illustrated in Figure 1-3.

CONFIGMISCFPGA OKPOWERCFGLED

1.3.1 CONFIG link

1-8

Figure 1-3 Links and indicators

The core module has only one link, marked CONFIG. This is left open during normal operation. It is only fitted when downloading new FPGA and PLD configuration information.

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1.3.2 LED indicators

The functions of the four surface-mounted LEDs are summarized in Table 1-1.

Introduction

Table 1-1 LED functional summary

Name Color Function

MISC Green This LED is controlled via the control regi ster (see

CM_CTRL (0x1000000C) on page 4-11).

FPGA OK Green This LED illuminates when the FPGA has successfully

loaded its configuration information following power-on.

POWER Green This LED illuminates to indicate that a 3.3V supply is

present.

CFGLED Orange This LED illuminates to indicate that the CONFIG link is

fitted.

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1-9

Introduction

1.4 Test points

The core module provides two ground and five signal test points as an aid to debug. These are illustrated in Figure 1-4.

Voltage

regulator

TP1

TP3

TP5

TP4

TP6

TP7

1-10

TP2

Figure 1-4 Test points

The functions of the test points are summarized in Table 1-2.

Table 1-2 Test point functions

T est point Name Function

TP1 GND Ground TP2 GND Ground TP3 FCLKOUT Clock output from the ARM940T microprocessor core TP4 LBCLK Local memory bus clock TP5 Core clock Clock suppl ied to the ARM940T microprocessor core TP6 VDD940T Output from voltage regulator TP7 ADJ ADJ pin of voltage regulator

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1.5 Precautions

This section contains safety information and advice on how to avoid damage to the core module.

1.5.1 Ensuring safety

To avoid a safety hazard, only Safety Extra Low Voltage (SELV) equipment should be connected to the JTAG interface.

1.5.2 Preventing damage

The core module is intended for use within a laboratory or engineering development environment. It is supplied without an encl osure which leaves the board sensitive to electrostatic discharges and allows electromagnetic emissions.

To avoid damage to the board you should observe the following precautions.

Introduction

Warning

Caution

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• Never subject the board to high electrostatic potentials.

• Always wear a grounding strap when handling the board.

• Only hold the board by the edges.

• Avoid touching the component pins or any other metallic element.

• Do not use the board near equipment which could be: — sensitive to electrom a gnetic emissions (such as medical equipment) — a transmitter of electromagnetic em issions.

1-11

Introduction

1-12

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Chapter 2

Getting Started

This chapter describes how to set up and prepare the ARM Integrator/CM940T core module for use. It contains the following sections:

• Setting up a standalone ARM Integrator/CM940T on page 2-2

• Attaching the ARM Integrator/CM9 40T to a motherboard on page 2-5.

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2-1

Getting Started

2.1 Setting up a standalone ARM Integrator/CM940T

To set up the core module as a standalone development system:

1. Optionally, fit an SDRAM DIMM.

2. Supply power.

3. Connect Multi-ICE.

2.1.1 Fitting an SDRAM DIMM

You should fit the following type of SDRAM module:

• PC66- or PC100-compliant 168pin DIMM

• unbuffered

• 16MB, 32MB, 64MB, 128MB or 256MB. To install an SDRAM DIMM:

1. Ensure that the core module is powered down.

2. Op en the SDRAM retaining latches outwards.

3. Press the SDRAM module into the edge connector until the retaining latches click into place.

Note

The DIMM edge connector has polarizing notches to ensure that it is correctly oriented in the socket.

2.1.2 Using the core module without SDRAM

The core module can be operated without SDRAM because it has 256KB of SSRAM permanently fitted. However, in order to operate the core module with ARM deb uggers, you must change the internal variable 0x00080000 (= 512KB) to 0x00040000 (= 256KB) before running programs that are linked with the standard libraries.

For further information about ARM debugger internal variables, refer to the Software Development Toolkit Reference Guide.

2-2

$top_of_memory from the default setting of

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2.1.3 Supplying power

When using the core modul e as a s tandal on e de vel opm ent s yst em, y ou sho ul d conn ect a bench power supply with 3.3V and 5V outputs to the power connector, as illustrated in Figure 2-1.

Getting Started

3.3V

GND

3V3

GND

Figure 2-1 Power connector

Note

This power connection is not required when the core module is fitted to a motherboard.

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2-3

Getting Started

2.1.4 Connecting Multi-ICE

When you are using the core module as a standalone system, Multi-ICE debugging equipment can be used to download programs. The Multi-ICE setup for a standalone core module is shown in Figure 2-2.

Multi

Multi-ICE

server/debugger

Parallel

cable

ICE

2-4

Multi-ICE unit

Power supply

Core module

Figure 2-2 Multi-ICE connection to a core module

Caution

Because the core module does not provide non-volatile memory, programs are lost when the power is removed.

Multi-ICE can also be used when a core module is attached to a motherboard. If more than one core module is attached, then the Multi-ICE unit must b e connected to the module at the top of the stack. The Multi-ICE server and the debugger can be on one computer or on two networked co mputers.

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2.2 Attaching the ARM Integrator/CM940T to a motherboard

Attach the core module onto a motherboard (for example, the ARM Integrator/SP) by engaging the connectors HDRA and HDRB on the bottom of the core module with the corresponding connectors on the top of the motherboard. The lower side of the core module has sockets and the upper side of the core module has plugs to allow core modules to be mounted on t op of one anot her. A maximum of f our core module s can be stacked on a motherboard.

Figure 2-3 illustrates an example development system with four core modules attached to an ARM Integrator/SP motherboard.

Getting Started

Module 3 Module 2 Module 1 Module 0

Motherboard

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Figure 2-3 Assembled Integrator system

2-5

+ 67 hidden pages

ARM CM940T User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Electromagnetic conformity

Contents

Preface

About this document

Further reading

Feedback

Introduction

1.1 About the ARM Integrator/CM940T core module

1.2 ARM Integrator/CM940T overview

1.3 Links and indicators

1.4 Test points

1.5 Precautions

Getting Started

2.1 Setting up a standalone ARM Integrator/CM940T

2.2 Attaching the ARM Integrator/CM940T to a motherboard