OPU connector pin out
is reversed with respect
to OPU, since FFC
cable has contact
surfaces on SAME
+3V3DDGND
CD*_DVD
0=DVD,1=CDDGND
Motor driver now has its own regulator
Use +3V3D because Vc must be = VDDPW M/2
OPU_HFM
5
OPU_MD
CDLD_OUT
6
7
CD_MD
DVD_MD
8
9
10
RFE
11
+5V_OPU
12
OPU_VREF
13
14
RFF
15
RFB
16
RFA
17
RF
18
CD_DVD_SW
19
RFD
20
RFC
21
22
23
24
DGND
R313
0R0 0603
+5VD
P310
DGND
+12VD
C335
220UF
16V
YXF
+3V3D
R345
R343
100R
47K
0W063
0603
0603
NF
R346
100R
0W063
0603
DGND
R318
P343P344
10K 0603
TRACK_S
R319
10K 0603
SPINDLE_S
R312
0R0 0805
P361
P305
NF
R314
470R
0805
0W125
TR304
MMUN2211LT1
SOT-23
DVD
DGND
C334
100N
16V
0603
C310
100N
16V
0603
R351
6K8
0603
C317
47UF
35V
YK
P304
HS300A
PF752
23.7C/W
P328
0603
C325
P346
R302
10R
0W125
0805
TACTTACT+
FACT+
FACT-
C311
100N
16V
C327
4N7
50V
0603
100P
0603
TR302
BC327
TO-92
DGND
+5VD
R321
470R
0805
0W125
TR310
MMUN2211LT1
SOT-23
DGND
REG300
L7805CV
TO-220
+5
P347
C320
47P
50V
0603
FOCUS_S
P329
P348
P349P345
P350
R301
220R
0603
P306
1=CD,0=DVD
+5VM
R344
47K 0603
TR301
MMUN2111LT1
SOT-23
C326
220UF
16V
YXF
P331
C324
DVRSB*
R323
3K3
0603
100P
0603
FACT-
C312
100N
16V
0603
VC2
TACT-
DGND
P307
KTC2875
SOT-23
DGND
P332P330
R320
1K0
0603
CD
C318
47UF
35V
YK
TR308
R309
3K3
0603
C313
100N
16V
0603
26
25
24
20
23
27
28
R303
10R
0W125
0805
1
3
7
4
5
6
+5VD
TR303
BC327
TO-92
C321
47P
50V
0603
DGND
DGNDDGND
P309
9
8
VCC
VINFC
CFCERR12VOFC+
CFCERR2
VNFFC
VINSL+
VINSLVOSL
VINTK
CTKERR1
CTKERR2
VNFTK
VINLD
BIAS
STBY
PGND
PGND
PREGND
19
10
22
DGND
L302 600R@100MHz
C301
100UF
10V
YXF
C307
100N
16V
0603
C308
100N
16V
0603
TR309
KTC2875
SOT-23
MOTOR DRIVER
21
IC301
PVCC1
PVCC2
13
VOFC-
14
11
VOSL-
12
VOSL+
16
VOTK-
15
VOTK+
18
VOLD-
17
VOLD+
GNDHS29GNDHS
30
BA5954FP-E2
HSOP-28
+5VRFA
DGND
P311
P312
P313
P314
P315
P316
R3041R0 0805
R3051R0 0805 FACT-
P333
SLEDSLED+
R3061R0 0805
R3071R0 0805
P351
C304
100N
16V
0603
RFF
RFB
RFA
RF
RFD
RFC
L303 600R@100MHz
R308
10R
0W063
0603
P303
C305
100N
16V
0603
DGND
SPDLSPDL+
C302
100UF
10V
YXF
P335
FACT+
TACTTACT+
P336
DGND
DGND
P356
+5V_OPU
C306
100N
16V
0603
C319
47UF
35V
YK
P354
P355
Close to OPU
R325
33R
0603
P317
P318
P319
P320
+3V3D
R317
10K
0603
SLED & SPINDLE
C314
100N
16V
DGND
0603
DGND
CD_MD
DVD_MD
RFE
VC
CON302
6
5
4
3
2
1
JST
PH
HOME_SW
SPDL_OUT-
DGND
+12VD
C332
C329
100N
100UF
16V
25V
0603
YK
DGND
R311
15K
0W063
0603
R339
3K3
0603
NF
R340
3K3
0603
NF
IC302A
1
LM358AM
SO-8
NF
R352
120R
0W125
0805
NF
Filename:
Notes:
Contact Engineer:
5
3
6
9
4
DGND
DGND
P342
R333
1K0
0603
R324
6K8
0603
DGND
R310
2K2
0W063
0603
NF
L988C03 Front End.Sch
Mark Tweedale
markt@arcam.co.uk
CLOSE
OPEN
DZ300
BZX84C
5V6
SOT-23
OFFSET CANCELLATION CCT NOT USED
R335
220K
0603
NF
R326
TACT+
1K0 0603
NF
R327
TACT-
1K0 0603
NF
R328
FACT+
1K0 0603
NF
R329
FACT-
1K0 0603
NF
BEMF CCT 2
BEMF CCT 1 NOT USED
R330
1K0
0W063
0603
NF
C328
22N
16V
0603
NF
R334
1K0
0W063
0603
NF
IC302B
5
7
6
LM358AM
SO-8
P308
P358
DGND
DGND
R347
1R0
0805
R336
220K
0603
P321
P322
R337
220K
0603
NF
P323
P324
R338
220K
0603
NF
D300
BAT54S
SOT-23
NF
31
2
DGND
NF
57
6
R331
0R0
0603
R332
0R0
0603
DRAWING TITLE
ARCAM
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR
C333
10N 50V
0603
C331
47UF
35V
YK
DGND
+5VM
C309
P325
100N
16V
0603
R348
470K
0603
NF
P340
P326
P341
R349
470K
0603
NF
DGND
3
2
+3V3D
DGND
+5VD
DGND
R350
39R
0W125
0805
C316
100N
16V
0603
NF
NF
84
84
IC300A
LM393M
SO-8
NF
IC300B
LM393M
SO-8
NF
DGND
DV137 Front End
8
IC303
VCC17VCC2
2
OUT1
IN1
P1
IN2
P2
Vz
C315
100N
16V
0603
DGND
R342
360R
0W063
0603
NF
R341
360R
0W063
0603
10
OUT2
GND
1
LB1641
SIP-10
P327
BACK-EMF CIRCUIT
P359
SPDL_SENSE-
P360
SPDL_SENSE+
Contact Tel:
C330
100N
16V
0603
ADC_H
01223 203210 (direct)
01223 203200 (switch)
06_E093 MJT12/06/06 None to this sheet. Add heats ink to top of Vaddis3.1
06_E036 PG20/03/06 Add thermal attac h pads to IC2003.0
06_E029 PG15/03/06 Issue 2 PCB ( changes only affect DV139)2.0
05_E242 PG08/12/05 Production R elease1.0
ECO No.
TRAYTRAY+
INITIALS
Printed:
DGND
+3V3D
DGND
12-Jun-2006
R315
10K
0603
C322
1N0
50V
0603
DATE
R316
10K
0603
TRAY
CON301
1
2
3
4
5
JST
PH
C323
1N0
50V
0603
DESCRIPTION OF CHANGE
313Sheetof
IN_SW
OUT_SW
A2
DRAWING NO.
ISSUE
L988CT
A
REG400
C402
100N
16V
0603
LM1117MPX-3.3
SOT-223
+3V3
X400
27MHz
HC49
PLLSEL
+5VD
DGNDDGND
C400
27P
100V
0805
C401
DGND
27P
100V
0805
CLOCK GENERATOR
+3V3PLL
C423
100UF
10V
YXF
12
1
VDD3
VDD1
7
XTI
8
XTO
14
FSEL
16
NC
2
VSS1
IC401
SM8707E
VSOP-16
VSS3
11
C404
100N
16V
0603
DGND
C405
100N
16V
0603
5
6
VDD2
VSS2
MO1
MO2
AO1
AO2
SO1
SO2
C406
100N
16V
0603
3
4
9
10
13
15
R400
75R 0603
P402
R410
P401
100R 0603
P403
R411
100R
0603
P404
CLK27M_VADDIS
P406
STOP_DIV2*STOP_DIV8*
P405
+3V3D
P411
4
D
CLK
Q
SD*
!Q
RD*
74LVC74AD
1
S0-14
IC403A
5
P409
6
P410
100R 0603
R412
100R 0603
udio master clock frequency for differ ent sample rates
Fs Master clock frequency PLLSEL DIV0* DIV2* DIV8*
32kHz 12.288MHz (384 x Fs) 1 1 0 1
44.1kHz 11.2896MHz (256 x Fs) 0 1 0 1
48kHz 12.288MHz (256 x Fs) 1 1 0 1
88.2kHz 22.5792MHz (256 x Fs) 0 0 1 1
96kHz 24.576MHz (256 x Fs) 1 0 1 1
176.4kHz 22.5792MHz (128 x Fs) 0 0 1 1
192kHz 24.576MHz (128 x Fs) 1 0 1 1
DSD 44.1k 2.8224MHz (64 x Fs) 0 1 1 0
2
3
CLOCK DIVIDER
P412
R413
AUDIO CLOCK BUFFERS
DGND
54
RP402D
33K
R404
75R0603
R405
75R0603
R406
75R0603
R407
75R0603
MCLK_DAC0
MCLK_DAC1
MCLK_DAC2
MCLK_DAC3
Close to DACs
DGND
IC408B
19
OE*
17
A0
15
A1
13
A2
11
A3
74LVC244APW
TSSOP-20
MCLK_DACS
IC407B
19
OE*
17
A0
15
A1
13
A2
11
A3
74LVC244APW
TSSOP-20
R434
0R0
To allow testing with Vaddis PLL enabled
0603
NF
I2S_MODE*
23
IC405A
SO-14
1
74LVC125AD
SO-14
56
IC405B
4
74LVC125AD
SO-14
98
74LVC125AD
10
IC405C
R418
Option to allow 5.6448MHz clock if required
+3V3D
10
12
D
SD*
11
CLK
RD*
74LVC74AD
13
S0-14
Q
!Q
IC403B
9
P467
8
P469
P468
R408
100R 0603
100R 0603
NF
R409
100R 0603
P470
+3V3D
P473
4
2
D
3
CLK
Q
SD*
!Q
RD*
74LVC74AD
1
S0-14
IC400A
5
P471
6
P472
R427
100R 0603
R428
100R 0603
DIV2*
P474
DIV8*
DIV0*
P475
P413
P414
R436
47R 0603
R432
47R 0603
R433
47R 0603
DGND
P415
R437
10K
0603
P422
3
P424
Y0
5
Y1
7
P425
Y2
9
Y3
P423
P416P419
3
Y0
5
Y1
7
Y2
9
Y3
P417P421
P418
R401
75R0603
R402
75R0603
R403
75R0603
MCLK_HDMI
MCLK_VADDIS
RP402A
33K
18
RP402B
33K
27
63
RP402C
33K
PCM_DAC0/DSD0
R440
0R0
0603
Close to IC413
20
10
+3V3D
DGND
P407
R438
10K
0603
I2S_MODE*
TR400
MMUN2211LT1
SOT-23
DGND
P496
R441
0R0
0603
NF
IC403C
VCC
C416
100N
16V
GND
0603
74LVC74AD
S0-14
DGND
DGND
14
7
P400
I2S/DSD MUX
Close to DACs
IC411A
1
OE*
2
A0
4
A1
6
A2
8
A3
74LVC244APW
TSSOP-20
IC411B
19
OE*
17
A0
15
A1
13
A2
11
A3
74LVC244APW
TSSOP-20
PCM_DAC0
PCM_DAC2
Close to DACs
IC413A
1
OE*
2
A0
4
A1
6
A2
8
A3
74LVC244APW
TSSOP-20
IC413B
19
OE*
17
A0
15
A1
13
A2
11
A3
74LVC244APW
TSSOP-20
C417
100N
16V
0603
18
P452
Y0
16
P453
Y1
14
P454
Y2
12
P455
Y3
3
Y0
5
Y1
7
Y2
9
Y3
18
P456
Y0
16
P457
Y1
14
P458
Y2
12
P459
Y3
3
Y0
5
Y1
7
Y2
9
Y3
Could use IC408B for this - depends on layout
Setting DIRECT_MCLK* low allows
master clock to be sent direct to DAC in
DSD mode (instead of via vaddis) f or
improved jitter in DSD mode.
This may be removed from the design if it
is found to adversly affect jitter in PCM
IC412B
16
VCC
GND
74HC151D
SO-16
C418
100N
16V
8
0603
RP400A
RP400B
RP400C
RP400D
RP401A
RP401B
RP401C
RP401D
IC413C
20
VCC
10
GND
74LVC244APW
TSSOP-20
18
27
18
27
C408
100N
16V
0603
100R
100R
100R
63
100R
54
100R
100R
100R
63
100R
54
+3V3D
DGND
IC406C
20
VCC
10
GND
74LVC244APW
TSSOP-20
ALRCLK/DSD0
ALRCLK/DSD2
ALRCLK/DSD4
ALRCLK_DAC3
C403
100N
16V
0603
C409
100N
16V
0603
ABCLK_DAC0
ABCLK_DAC1
ABCLK_DAC2
ABCLK_DAC3
C419
100N
16V
0603
IC404C
14
VCC
7
GND
74LVC74AD
S0-14
DAC3 is PCM only
C420
C424
100N
100N
16V
16V
0603
0603
IC411C
VCC
C421
100N
16V
GND
0603
74LVC244APW
TSSOP-20
P460
2
3
+3V3D
20
10
D
CLK
+3V3D
4
1
C427
100N
16V
0603
C422
100N
16V
0603
P477
Q
SD*
!Q
RD*
74LVC74AD
S0-14
PSU CLOCK DIVIDER
P461
+3V3D
P462
IC404A
5
6
595_DATA
595_CLK
595_LATCH
C428
100N
16V
0603
ITEM4001Pad Dam ping 7.5x6x3MM RubberE828APFit on one side of XTAL (see assembly drawing)
ITEM4011INSULATING PAD FOR HC49 CRYSTALSF087Fit to X400 to insulate from PCB
DRAWING TITLE
ARCAM
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9QR