The SA04 is a pulse width amplifier that can supply 4000W
to the load. An internal 45kHz oscillator requires no external
components. The clock input stage divides the oscillator
frequency by two, which provides the basic switching of 22.5
kHz. External oscillators may also be used to lower the
switching frequency or to synchronize multiple amplifiers.
Current sensing is provided for each half of the bridge giving
amplitude and direction data. A shutdown input turns off all
four drivers of the H bridge output. A high side current limit and
the programmable low side current limit protect the amplifier
from shorts to supply or ground in addition to load shorts. The
H bridge output MOSFETs are protected from thermal overloads by directly sensing the temperature of the die. The 12pin hermetic MO-127 power package occupies only 3 square
inches of board space.
BLOCK DIAGRAM AND TYPICAL APPLICATION
TORQUE MOTOR DRIVER
CONTROL
SIGNAL
3/7V
Vcc
+PWM
–PWM/RAMP
CLK OUT
CLK IN
GND
10
3
4
470pF
56K
2
1
5
÷2OSC
CLK IN
CLK OUT
+PWM
–PWM/RAMP
GND
1
2
3
TOP
TOP
VIEW
VIEW
4
5
6
12
11
10
9
8
7
*
*
ILIM/SHDN
Case tied to pin 5. Allow no current in case. Bypassing of supplies
is required. Package is Apex MO-127 (STD). See Outline
Dimensions/Packages in Apex data book.
If +PWM > RAMP/–PWM then A OUT > B OUT.
*See text.
SUPPLY VOLTAGE, +V
SUPPLY VOLTAGE, V
POWER DISSIPATION, internal300W
TEMPERATURE, pin solder - 10s300°C
TEMPERATURE, junction
S
CC
2
200V
16V
150°C
TEMPERATURE, storage–65 to +150°C
OPERATING TEMPERATURE RANGE, case –55 to +125°C
INPUT VOLTAGE, +PWM0 to +11V
INPUT VOLTAGE, –PWM0 to +11V
SPECIFICATIONS
INPUT VOLTAGE, I
PARAMETERTEST CONDITIONS
LIM
2
MINTYPMAXUNITS
0 to +10V
CLOCK (CLK)
CLK OUT, high level
CLK OUT, low level
FREQUENCY44.1045.0046.90kHz
4
4
I
≤ 1mA4.85.3V
OUT
I
≤ 1mA0.4V
OUT
RAMP, center voltage5V
RAMP, P-P voltage4V
CLK IN, low level
CLK IN, high level
4
4
0.9V
3.75.4V
OUTPUT
TOTAL R
EFFICIENCY, 10A outputVS = 200V97%
SWITCHING FREQUENCYOSC in ÷ 222.0522.5022.95kHz
CURRENT, continuous
CURRENT, peak
ON
4
4
85°C case20A
30A
.22Ω
POWER SUPPLY
VOLTAGE, V
VOLTAGE, V
CURRENT, V
CURRENT, V
CURRENT, V
I
/SHUTDOWN
LIM
S
CC
CC
shutdown50mA
CC,
S
Full temperature range16
Full temperature range141516V
I
= 080mA
OUT
No Load50mA
5
120200V
TRIP POINT90110mV
INPUT CURRENT100nA
THERMAL
3
RESISTANCE, junction to caseFull temperature range, for each die.83°C/W
RESISTANCE, junction to airFull temperature range12°C/W
TEMPERATURE RANGE, caseMeets full range specifications–25+85°C
NOTES: 1.Each of the two active output transistors can dissipate 150W.
3.Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power
dissipation to achieve high MTTF. For guidance, refer to the heatsink data sheet.
4.Guaranteed but not tested.
5.If 100% duty cycle is not required V
CAUTION
The SA04 is constructed from MOSFET transistors. ESD handling procedures must be observed.
S(MIN)
= 0V.
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush,
machine, or subject to temperatures in excess of 850°C to avoid generating toxic fumes.
APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: 1 (800) 546-2739
Helpful information about power supplies, heatsinking and
mounting can be found in the “General Operating Considerations” section of the Apex data book. For information on the
package outline, heatsinks, and mounting hardware see the
“Package Outlines” and “Accessories” section of the data
book. Also see Application Note 30 on “PWM Basics.”
CLOCK CIRCUIT AND RAMP GENERATOR
The clock frequency is internally set to a frequency of
approximately 45kHz. The CLK OUT pin will normally be tied
to the CLK IN pin. The clock is divided by two and applied to an
RC network which produces a ramp signal at the –PWM/
RAMP pin. An external clock signal can be applied to the CLK
IN pin for synchronization purposes. If a clock frequency lower
than 45kHz is chosen an external capacitor must be tied to the
–PWM/RAMP pin. This capacitor, which parallels an internal
capacitor, must be selected so that the ramp oscillates 4 volts
p-p with the lower peak 3 volts above ground.
PWM INPUTS
The full bridge driver may be accessed via the pwm input
comparator. When +PWM > -PWM then A OUT > B OUT. A
motion control processor which generates the pwm signal can
drive these pins with signals referenced to GND.
PROTECTION CIRCUITS
In addition to the externally programmable current limit there
is also a fixed internal current limit which senses only the high
side current. It is nominally set to 140% of the continuous rated
output current. Should either of the outputs be shorted to
ground the high side current limit will latch off the output
transistors. Also, the temperature of the output transistors is
continually monitored. Should a fault condition occur which
raises the temperature of the output transistors to 165°C the
thermal protection circuit will activate and also latch off the
output transistors. In either case, it will be necessary to remove
the fault condition and recycle power to V
to restart the circuit.
CC
CURRENT LIMIT
There are two load current sensing pins, I SENSE A and I
SENSE B. The two pins can be shorted in the voltage mode
connection but both must be used in the current mode connection (see figures A and B). It is recommended that R
resistors be non-inductive. Load current flows in the I SENSE
pins. To avoid errors due to lead lengths connect the I LIMIT/
SHDN pin directly to
the R
resistors
LIMIT
I SENSE A
(through the filter network and shutdown divider resistor) and connect the R
LIMIT
resistors directly to the GND
pin.
Switching noise
spikes will invariably
I SENSE B
I LIMIT/SHDN
R
FILTER
C
FILTER
R
LIMIT
1K
R
SHDN
be found at the I
SENSE pins. The
FIGURE A. CURRENT LIMIT WITH
SHUTDOWN VOLTAGE MODE.
LIMIT
SHUTDOWN
SIGNAL
I SENSE A
I SENSE B
R
1K
LIMIT
noise spikes could trip the current limit threshold which is only
100 mV. R
FILTER
and C
FILTER
should be adjusted so as to
reduce the switching noise well
below 100 mV to prevent false
current limiting. The sum of the
R
LIMIT
DC level plus the noise peak
will determine the
I LIMIT/SHDN
R
FILTER
C
FILTER
SHUTDOWN
SIGNAL
R
SHDN
current limiting
value. As in most
switching circuits
it may be difficult
to determine the
FIGURE B. CURRENT LIMIT WITH
SHUTDOWN CURRENT MODE.
true noise amplitude without
careful attention
to grounding of the oscilloscope probe. Use the shortest
possible ground lead for the probe and connect exactly at the
GND terminal of the amplifier. Suggested starting values are
= .01uF, R
C
FILTER
The required value of R
FILTER
= 5k .
in voltage mode may be calcu-
LIMIT
lated by:
R
where R
= .1 V / I
LIMIT
is the required resistor value, and I
LIMIT
LIMIT
LIMIT
is the
maximum desired current. In current mode the required value
of each R
divided down by 2 (see Figure B). If R
is 2 times this value since the sense voltage is
LIMIT
is used it will further
SHDN
divide down the sense voltage. The shutdown divider network
will also have an effect on the filtering circuit.
BYPASSING
Adequate bypassing of the power supplies is required for
proper operation. Failure to do so can cause erratic and low
efficiency operation as well as excessive ringing at the outputs.
The Vs supply should be bypassed with at least a 1µF ceramic
capacitor in parallel with another low ESR capacitor of at least
10µF per amp of output current. Capacitor types rated for
switching applications are the only types that should be considered. The bypass capacitors must be physically connected
directly to the power supply pins. Even one inch of lead length
will cause excessive ringing at the outputs. This is due to the
very fast switching times and the inductance of the lead
connection. The bypassing requirements of the Vcc supply are
less stringent, but still necessary. A .1µF to .47µF ceramic
capacitor connected directly to the Vcc pin will suffice.
STARTUP CONDITIONS
The high side of the all N channel output bridge circuit is
driven by bootstrap circuit and charge pump arrangement. In
order for the circuit to produce a 100% duty cycle indefinitely
the low side of each half bridge circuit must have previously
been in the ON condition. This means, in turn, that if the input
signal to the SA04 at startup is demanding a 100% duty cycle,
the output may not follow the command and may be in a tristate condition. The ramp signal must cross the input signal at
some point to correctly determine the output state. After the
ramp crosses the input signal level one time, the output state
will be correct thereafter.
This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice.