The PA04 is a high voltage MOSFET power operational
amplifier that extends the performance limits of power amplifiers in slew rate and power bandwidth, while maintaining high
current and power dissipation ratings.
The PA04 is a highly flexible amplifier. The sleep mode
feature allows ultra-low quiescent current for standby operation or load protection by disabling the entire amplifier. Boost
voltage inputs allow the small signal portion of the amplifier to
operate at a higher voltage than the high current output stage.
The amplifier is then biased to achieve close linear swings to
the supply rails at high currents for extra efficient operation.
External compensation tailors performance to user needs. A
four wire sense technique allows precision current limiting
without the need to consider internal or external milliohm
parasitic resistance in the output line.
The JEDEC MO-127 12-pin Power Dip™ package (see
Package Outlines) is hermetically sealed and isolated from the
internal circuits. The use of compressible thermal washers will
void product warranty.
EQUIVALENT SCHEMATIC
SLEEP
12
9
+V
BOOST
Q10
D5D6
–IN
1
Q14 Q15
–V
Q21
BOOST
5
Q22
COMP
D1
Q5
D2
D3
Q12
+IN
2
4
COMP
3
Q20
Q17
D7
D8
Q19
Q26
+Vs
D4
D9
–Vs
8
Q13
Q18
6
PA04 • PA04A
TYPICAL APPLICATION
The high power bandwidth and high voltage output of the
PA04 allows driving sonar transducers via a resonant circuit
including the transducer and a matching transformer. The load
circuit appears resistive to the PA04. Control logic turns off the
amplifier in sleep mode.
SUPPLY VOLTAGE, +VS to –V
BOOST VOLTAGESUPPLY VOLTAGE +20V
S
200V
OUTPUT CURRENT, within SOA20A
POWER DISSIPATION, internal200W
INPUT VOLTAGE, differential±20V
INPUT VOLTAGE, common mode±V
TEMPERATURE, pin solder - 10s300°C
TEMPERATURE, junction
2
S
150°C
TEMPERATURE, storage–65 to +150°C
OPERATING TEMPERATURE RANGE, case –55 to +125°C
SPECIFICATIONS
PARAMETERTEST CONDITIONS
PA04
1
MINTYPMAXMINTYPMAXUNITS
PA04A
INPUT
OFFSET VOLTAGE, initial51025mV
OFFSET VOLTAGE, vs. temperatureFull temperature range30501030µV/°C
OFFSET VOLTAGE, vs. supply15*µV/V
OFFSET VOLTAGE, vs. powerFull temperature range3010µV/W
BIAS CURRENT, initial1050520pA
BIAS CURRENT, vs. supply.01*pA/V
OFFSET CURRENT, initial1050520pA
INPUT IMPEDANCE, DC10
11
*Ω
INPUT CAPACITANCE13*pF
COMMON MODE VOLTAGE RANGEFull temperature range±VB-8*V
COMMON MODE REJECTION, DCFull temp. range, VCM = ±20V8698**dB
INPUT NOISE100kHz BW, RS = 1KΩ10*µVrms
GAIN
OPEN LOOP, @ 15HzFull temperature range, CC = 100pF94102**dB
GAIN BANDWIDTH PRODUCTIO = 10A2*MHz
POWER BANDWIDTHRL = 4.5Ω, VO = 180V p-p90*kHz
CC = 100pF, RC = 120Ω
PHASE MARGINFull temperature range60*°
OUTPUT
VOLTAGE SWINGIO = 15A±VS-8.8 ±VS-7.5**V
VOLTAGE SWINGV
CURRENT, peak20*A
= Vs + 5V, IO = 20A±VS-6.8 ±VS-5.5**V
BOOST
SETTLING TIME to .1%AV = 1, 10V step, RL = 4Ω2.5*µs
SLEW RATEAV = 10, CC = 100pF, RC = 120Ω4050*V/µs
CAPACITIVE LOADFull temperature range, AV = +110*nF
RESISTANCE2*Ω
POWER SUPPLY
VOLTAGEFull temperature range±15±75±100***V
CURRENT, quiescent, boost supply3040**mA
CURRENT, quiescent, total7090**mA
CURRENT, quiescent, total, sleep mode Full temperature range35**mA
THERMAL
RESISTANCE, AC, junction to case
3
Full temperature range, F>60Hz.3.4**°C/W
RESISTANCE, DC, junction to caseFull temperature range, F<60Hz.5.6**°C/W
RESISTANCE4, junction to airFull temperature range12*°C/W
TEMPERATURE RANGE, caseMeets full range specification–2585**°C
NOTES: *The specification of PA04A is identical to the specification for PA04 in applicable column to the left.
1.Unless otherwise noted: TC = 25°C, CC = 470pF, RC = 120 ohms. DC input specifications are ± value given. Power supply
voltage is typical rating. ±V
2.Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation
BOOST
= ±VS.
to achieve high MTTF. For guidance, refer to the heatsink data sheet.
3.Rating applies if the output current alternates between both output transistors at a rate faster than 60 Hz.
4.The PA04 must be used with a heatsink or the quiescent power may drive the unit to junction temperatures higher than 150°C.
CAUTION
The PA04 is constructed from MOSFET transistors. ESD handling procedures must be observed.
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or
subject to temperatures in excess of 850°C to avoid generating toxic fumes.
APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: 1 (800) 546-2739
Please read the “General Operating Considerations” section, which covers stability, supplies, heatsinking, mounting,
current limit, SOA interpretation, and specification interpretation. Additional information can be found in the application
notes. For information on the package outline, heatsinks, and
mounting hardware, consult the “Accessory and Package
Mechanical Data” section of the handbook. The EK04 Evaluation Kit makes prototype circuits a snap by providing an
EK04PC proto circuit board, MS05 mating socket, HS11
heatsink and hardware kit.
CURRENT LIMIT
The two current limit sense lines are to be connected directly
across the current limit sense resistor. For the current limit to
work correctly pin 11 must be connected to the amplifier
output side and pin 10 connected to the load side of the
current limit resistor, R
connection will bypass any parasitic resistances, Rp, formed
, as shown in Figure 1. This
CL
by sockets and solder joints as well as internal amplifier losses.
The current limiting resistor may not be placed anywhere in the
output circuit except where shown in Figure 1.
The value of the current limit resistor can be calculated as
follows:
.76
R
=
CL
I
LIMIT
R
f
Figure 1.
Current Limit.
R
INPUT
10
i
1
11
CL
2
PA04
R
R
CL
P
7
CL
R
L
SAFE OPERATING AREA (SOA)
The MOSFET output stage of this power operational amplifier has two distinct limitations:
1. The current handling capability of the MOSFET geometry
and the wire bonds.
2. The junction temperature of the output MOSFETs.
NOTE: The output stage is protected against transient flyback.
However, for protection against sustained, high energy
flyback, external fast-recovery diodes should be used.
20
10
5.0
2.0
1.0
OUTPUT CURRENT (A)
.5
.2
2
5102050200
SUPPLY TO OUTPUT DIFFERENTIAL (V)
DC Tc = 85°C
DC Tc = 125°C
t = 1ms
t = 10ms
DC Tc = 25°C
100
SLEEP MODE OPERATION
In the sleep mode, pin 12 (sleep) is tied to pin 9 (+V
This disables the amplifier’s internal reference and the amplifier shuts down except for a trickle current of 3 mA which flows
into pin 12. Pin 12 should be left open if the sleep mode is not
required.
Several possible circuits can be built to take advantage of
this mode. In Figure 2A a small signal relay is driven by a logic
gate. This removes the requirement to deal with the common
mode voltage that exists on the shutoff circuitry since the sleep
mode is referenced to the +V
BOOST
voltage.
In Figure 2B, circuitry is used to level translate the sleep
mode input signal. The differential input activates sleep mode
with a differential logic level signal and allows common mode
voltages to ±V
LOGIC
Figure 2A. Sleep mode circuit.
+
-
Figure 2B.
Sleep mode circuit.
BOOST
LOGIC
INPUT
470
470
.
K1
Ω
560
Ω
Q1
Ω
1K
Ω
Q2
–V
BOOST
9
12
9
12
+V
BOOST
SLEEP
+V
BOOST
SLEEP
BOOST
BOOST OPERATION
With the V
amplifier are operated at higher supply voltages than the
amplifier’s high current output stage. +V
–V
(pin 5) are connected to the small signal circuitry of the
BOOST
amplifier. +V
current output stage. An additional 5V on the V
sufficient to allow the small signal stages to drive the output
transistors into saturation and improve the output voltage
swing for extra efficient operation when required. When close
swings to the supply rails is not required the +V
pins must be strapped together as well as the –V
pins. The boost voltage pins must not be at a voltage lower than
pins.
the V
S
feature the small signal stages of the
BOOST
(pin 9) and
BOOST
(pin 8) and –VS (pin 6) are connected to the high
S
BOOST
BOOST
BOOST
pins is
and +V
and –V
COMPENSATION
The external compensation components CC and RC are
connected to pins 3 and 4. Unity gain stability can be achieved
at any compensation capacitance greater than 330 pF with at
least 60 degrees of phase margin. At higher gains more phase
shift can be tolerated in most designs and the compensation
capacitance can accordingly be reduced, resulting in higher
bandwidth and slew rate. Use the typical operating curves as
a guide to select C
and RC for the application.
C
).
S
S
This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice.