APC Gator EPIC User Manual

+

C

Gator EPI

Motherboard

Installation Guide

Introduction

Table of Contents

Introduction........................................................................................ IV

Chapter 1 Pre-Configuration....................................................1

Step 1 Setting the Jumpers 2

Jumper Locations...............................................................................................................................3

CMOS Reset........................................................................................................................................4

ATA-Disk Connector Voltage Selection...........................................................................................4

RS422/RS485 Termination Resistors (optional)..............................................................................4

Audio Jack Output Selection ............................................................................................................4

Backlight Logic Voltage Selection....................................................................................................5

Inverter Voltage Selection .................................................................................................................5

Step 2 SDRAM and Cables Installation5

Gator EPIC Memory Configuration...................................................................................................5

Installing Cables.................................................................................................................................5

Power and Control Panel Cables......................................................................................................5

Installing Peripheral Cables..............................................................................................................5

Index of Connectors...........................................................................................................................9

Chapter 2 AMIBIOS8 Setup....................................................10

Main Setup ........................................................................................................................................13

Advanced BIOS Setup .....................................................................................................................13

PCI/PnP Setup...................................................................................................................................22

Boot Setup ........................................................................................................................................24

Security Setup ..................................................................................................................................26

Chipset Setup ...................................................................................................................................27

Power Management Setup...............................................................................................................30

Exit Menu...........................................................................................................................................30

Chapter 3 Upgrading..................................................................32

Upgrading the System Memory ......................................................................................................32

Appendix A Technical Specifications................................33

Chipsets ............................................................................................................................................33

BIOS...................................................................................................................................................33

Embedded I/O ...................................................................................................................................33

Industrial Devices.............................................................................................................................35

Miscellaneous...................................................................................................................................35

Memory Map......................................................................................................................................36

DMA Channels..................................................................................................................................36

I/O Map...............................................................................................................................................36

PCI Configuration Space Map.........................................................................................................37

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Gator EPIC – Installation Guide

Interrupts...........................................................................................................................................38

SMBUS...............................................................................................................................................38

PCI Interrupt Routing Map...............................................................................................................38

Connectors Pin-out..........................................................................................................................39

Appendix B Flash BIOS programming and codes.....47

Troubleshooting POST ....................................................................................................................47

Critical Error BEEP Codes...............................................................................................................51

Appendix C On-Board Industrial Devices.......................53

On-board Ethernet............................................................................................................................53

Serial Ports........................................................................................................................................53

Appendix On-Board Video Controller...............................59

II

Introduction

Notice

The company reserves the right to revise this publication or to change its contents without notice. Information
contained herein is for reference only and does not constitute a commitment on the part of the manufacturer or any
subsequent vendor. They are in no way responsible for any loss or damage resulting from the use (or misuse) of this
publication.

This publication and any accompanying software may not, in whole or in part, be copied, photocopied, translated or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this
publication, except for copies kept by the user for backup purposes.

Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks
of their respective companies. They are mentioned for identification purposes only and are not intended as an
endorsement of that product or its manufacturer.

First Edition.

©May 2006

III

Gator EPIC – Installation Guide

Introduction

Thank you for your purchase of the Gator EPIC industrial embedded motherboard. The Gator EPIC design was
based on the Intel 855GME chipset providing the ideal platform to industrial applications. The Gator EPIC design is
based on the Intel LV Pentium M and ULV Celeron M processors.

With proper installation and maintenance, your Gator EPIC will provide years of high performance and trouble free
operation.

This manual provides a detailed explanation into the installation and use of the Gator EPIC industrial embedded

motherboard. This manual is written for the novice PC user/installer. However, as with any major computer

component installation, previous experience is helpful and should you not have prior experience, it would be prudent
to have someone assist you in the installation. This manual is broken down into 3 chapters and 4 appendixes.

Chapter 1 - System Board Pre-Configuration

This chapter provides all the necessary information for installing the Gator EPIC. Topics discussed
include: DRAM installation and jumper settings. Connecting all the cables from the system board to the
chassis and peripherals is also explained.

Chapter 2 - BIOS Configuration

This chapter shows the final step in getting your system firmware setup.

Chapter 3 - Upgrading

The Gator EPIC provides expansion options for memory. All aspects of the upgrade possibilities are
covered.

Appendix A - Technical Specifications

A complete listing of all the major technical specifications of the Gator EPIC is provided.

Appendix B - Flash BIOS Programming and Codes

Provides all information necessary to program your AMIBIOS8 Flash BIOS. POST Codes and beep codes
are described in details.

Appendix C – On-Board Industrial Devices

One on-board 10/100 (10/100/1000 optional) Ethernet controller, and two or six serial ports (one optional
RS422/485).

Appendix D - On-Board Video Controller

On-board CRT and LVDS video controller.

IV

Introduction

Static Electricity Warning!

The Gator EPIC has been designed as rugged as possible but can still be damaged if jarred sharply or struck. Handle
the motherboard with care.
The Gator EPIC also contains delicate electronic circuits that can be damaged or weakened by static electricity.
Before removing the Gator EPIC from its protective packaging, it is strongly recommended that you use a grounding
wrist strap. The grounding strap will safely discharge any static electricity build up in your body and will avoid
damaging the motherboard. Do not walk across a carpet or linoleum floor with the bare board in hand.

Warranty

This product is warranted against material and manufacturing defects for two years from the date of delivery. Buyer
agrees that if this product proves defective the manufacturer is only obligated to repair, replace or refund the
purchase price of this product at manufacturer's discretion. The warranty is void if the product has been subjected to
alteration, misuse or abuse; if any repairs have been attempted by anyone other than the manufacturer; or if failure is
caused by accident, acts of God, or other causes beyond the manufacturer's control.

Gator EPIC - An Overview

The Gator EPIC represents the ultimate in industrial embedded motherboard technology. The board measures a
compact 4.5”x 6.5”, ideal for deeply embedded computing applications. Its low-profile design also allows proper
clearance for 1U rack-mount chassis and other low profile cases. No other system board available today provides
such impressive list of features:

CPU Support

• Supports low power/ultra low power series of Intel LV Pentium M and ULV Celeron M 400MHz PSB
processors, allowing high performance with low thermal envelopes.

Supported Bus Clocks

• 400MHz.

Memory

• One SODIMM socket up to 1GB (unbuffered, ECC & non-ECC) DDR SDRAM, PC1600 (DDR 200MHz),
PC2100 (DDR 266MHz) and PC2700 (DDR 333MHz). Please, refer to chapter 3 for memory details.

On-Board I/O

• PCI 32-bit EIDE controller – UDMA 66/100 supported. One mini-Header 44-pin for Solid State IDE disk
or any 44-pin IDE device support.

• Dual independent Serial ATA ports with transfer rates up to 150 MB/s per port.

• Two/Six high speed RS-232 serial ports 16 Bytes FIFO (16550). COM2 optional RS-232 IrDA and COM1

optional RS-422/485.

• One bi-directional parallel port. EPP/ECP mode compatible.

• One mouse/keyboard connector.

• Six Universal Serial Bus connectors, USB 1.1 and USB 2.0 compliant.

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Gator EPIC – Installation Guide

r

• One (1) 32-bit PC/104-Plus expansion One (1) Mini-PCI slot (PCI 2.2 33MHz 32-bit 124-pin connector

Type III).

• One 10/100 Ethernet connector (optional 10/100/1000).

• Power Button – advanced management support.

• Automatic CPU voltage & temperature monitoring device.

• Audio (AD1981B) AC97 compliant. Microphone In, Stereo Line In and Out, Stereo Headphone Out and

CD In.

• On-board buzzer.

ROM BIOS

• American Megatrends AMIBIOS8 with FLASH ROM.

On-Board CRT & LVDS video controller

• Standard CRT video controller (Intel 855GME chipset).

• Dedicated Local Flat Panel (LFP) LVDS interface.

Conventions Used in this Manual



8



Notes - Such as a brief discussion of memory types.

Important Information - such as static warnings, o
very important instructions.

When instructed to enter keyboard keystrokes, the
text will be noted by this graphic.

VI

Chapter 1: Pre-Configuration

r

p

l

d

Chapter 1 Pre-Configuration

This chapter provides all the necessary information for installing the Gator EPIC into a standard PC chassis. Topics
discussed include the SODIMM DRAM installation and jumper settings.

Handling Precautions

The Gator EPIC has been designed to be as rugged as possible but it can be damaged if dropped, jarred sharply or
struck. Damage may also occur by using excessive force in performing certain installation procedures such as
forcing the system board into the chassis or placing too much torque on a mounting screw.

Take special care when installing or removing the system memory DIMMs. Never force a DIMM into a socket.
Screwdrivers slipping off a screw and scraping the board can break a trace or component leads, rendering the board
unusable. Always handle the Gator EPIC with care.



Products returned for warranty repair will be
inspected for damage caused by imprope
installation and misuse as described in the

revious section and the static warning below.
Should the board show signs of abuse, the
warranty will become void and the customer wil
be billed for all repairs and shipping an
handling costs.

Special Warranty Note:

Static Warning

The Gator EPIC contains delicate electronic semiconductors that are highly sensitive to static electricity. These
components, if subjected to a static electricity discharge, can be weakened thereby reducing the serviceable life of
the system board. BEFORE THE BOARD IS REMOVED FROM ITS PROTECTIVE ANTISTATIC
PACKAGING, TAKE PROPER PRECAUTIONS! Work on a conductive surface that is connected to the ground.
Before touching any electronic device, ground yourself by touching an unpainted metal object or, and highly
recommended, use a grounding strap.

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Gator EPIC – Installation Guide

y

Step 1 Setting the Jumpers

Your Gator EPIC is equipped with a large number of peripherals. As such, there are a large number of configuration
jumpers on the board. Taken step by step, setting these jumpers is easy. We suggest you review each section and
follow the instructions.

Special note about operating frequency:



Jumper Types

Jumpers are small copper pins attached to the system board. Covering two pins with a shunt closes the connection
between them. The Gator EPIC examines these jumpers to determine specific configuration information. There are
two different categories of jumpers on the Gator EPIC.

A. Two pin jumpers are used for binary selections such as enable, disable. Instructions for this type of jumper are
open, for no shunt over the pins or closed, when the shunt covers the pins.

The Gator EPIC has the ability to run at a variet
of speeds without the need to change any crystal,
oscillator or jumper.

B. Three or four pin jumpers are used for multiple selections. Instructions for these jumpers will indicate which two

pins to cover. For example: for JPx 2-3 the shunt will be covering pins 2 and 3 leaving pins 1 and 4 exposed.

How to identify pin number 1 on Figure 1-1: Looking to the solder side (The board side with fewer components) of
the PCB (Printed Circuit Board), pin number 1 will have a squared pad J. Other pins will have a circular pad Q.

They are numbered sequentially.

Double row jumpers are numbered alternately, i.e. pin number 2 is in the other row, but in the same column of pin
number 1. Pin number 3 is in the same row of pin 1, but in the next column and so forth.

2

Chapter 1: Pre-Configuration

Jumper Locations

Use the diagram below and the tables on the following pages to locate and set the on-board configuration jumpers.

Figure 1-1 Jumper Locations

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Gator EPIC – Installation Guide

CMOS Reset

This option is provided as a convenience for those who need to reset the CMOS registers. It should always be set to
"Normal" for standard operation. If the CMOS needs to be reset, turn off the system, move JP3 to 2-3, turn the
system on, move jumper to 1-2 and press reset.

Table 1-1 CMOS Reset

Reset CMOS Normal Clear CMOS

JP3 1-2* 2-3

* Manufacturer's Settings.

ATA-Disk Connector Voltage Selection

The ATA-Disk Connector J8 can provide either 5Vcc or 3.3Vcc. The jumper JP4 selects the voltage.

Table 1-2 ATA-Disk Connector Voltage Select

ATA-Disk Voltage 5Vcc 3.3Vcc

JP4 1-2* 2-3

*Manufacturer's Settings.

RS422/RS485 Termination Resistors (optional)

The Jumper JP6 allows the insertion/removal of the termination resistors (120Ω) in the Receiver and Transmitter
lines of the COM1 when operating in RS-422/485 mode.

Table 1-3 COM1 RS-422/485 Tx & Rx Termination Resistor Selection

Termination resistor

selection

Transmitter Receiver

JP6 1-3 2-4

* Manufacturer's Setting is off.

Audio Jack Output Selection

The audio output on the header connector J2 can be selected to be stereo line out or stereo headphone out (amplified
signal). The jumper JP5 selects the audio output signals.

Table 1-4 Audio Output Mode Selection

Audio Output Mode Selection Headphone Line Out

JP5 3-5, 4-6* 1-3, 2-4

* Manufacturer's Settings.

4

Chapter 1: Pre-Configuration

Backlight Logic Voltage Selection

The LVDS power connector J5 can supply either 5Vcc or 3.3Vcc for the logic circuits in the backlight inverter. The
jumper JP1 selects the voltage.

Table 1-5 Backlight Logic Voltage Select

Backlight Logic

Voltage

5Vcc 3.3Vcc

JP1 1-2 2-3*

* Manufacturer's Settings.

Inverter Voltage Selection

The LVDS power connector J5 can supply either 5Vcc or 12Vcc for the backlight inverter. The jumper JP2 selects
the voltage.

Table 1-6 Inverter Voltage Select

Inverter Voltage 12Vcc 5Vcc

JP2 1-2 2-3*

* Manufacturer's Settings.

Step 2 SDRAM and Cables Installation

Depending upon how your Gator EPIC is configured you may need to install the following:

• SDRAM (SODIMM)

Gator EPIC Memory Configuration

The Gator EPIC offers 1 SODIMM memory sockets (Location J1 – Figure 1-2). It can be configured with 2.5V

unbuffered SDRAM DDR modules. It is very important that the quality of the DIMM is good. Unreliable operation
of the system may result if poor quality DIMMs are used. Always purchase your memory from a reliable source.
Please, refer to chapter 3 for memory details.

Installing Cables
Power and Control Panel Cables

The Gator EPIC gets power from the EPIC power connector J30 (Figure 1-2) .

Installing Peripheral Cables

Now it is a good time to install the internal peripherals such as CDROM and hard disk drives. Do not connect the
power cable to these peripherals, as it is easier to attach the bulky ribbon cables before the smaller power

5

Gator EPIC – Installation Guide

connectors. If you are installing more than one IDE drive double check your master/slave jumpers on the drives.
Review the information supplied with your drive for more information on this subject.

Most modern HDDs are UDMA-5 capable. To make use of the Ultra DMA-5 capabilities, 80-conductor cables must
be used. The BIOS and the HDD will check for the existence of the 80-conductor cable. The long leg of the cable
must be connected to the board; otherwise it won’t work as an 80-conductor cable. If connecting another peripheral
that is not UDMA-5 capable (most optical devices are not), the whole IDE channel will be downgraded to UDMA-2.
In that case, it is recommended to use a different IDE channel for the non-UDMA-5 capable peripherals.

Connect the SATA cables (not included) to the system. If using a Solid State Device, connect it to the mini-ATA
connector. Connect all interface cables to their headers. Then connect remaining ends of the ribbon cable to the
appropriate peripherals.

This concludes the hardware installation of your Gator EPIC system. Now it is a good time to re-check all of the
cable connections to make sure they are correct.

6

Chapter 1: Pre-Configuration

Figure 1-2 Location of Components and Connectors

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Gator EPIC – Installation Guide

8

Chapter 1: Pre-Configuration

Index of Connectors

Please refer to Appendix A for pin-out descriptions.

Table 1-7 Connectors description

Connector Description

J1
J2

DDR SODIMM – Back side of the board

Audio - Microphone In/ Line Out/Headphone Out

J3
J4
J5
J6
J7
J8

LVDS – Back side of the board

LVDS Backlight – Back side of the board

External RTC/CMOS Battery

Ethernet (Optional 10/100/1000)

IDE – 44-pin

J9
J10
J12
J13
J14
J15
J16
J17

Mini-PCI Slot – Back side of the board

Keyboard/Mouse

Buzzer – Alt. Speaker Header

PC104 PCI

Serial ATA 1
Serial ATA 2

LPT - Parallel Port

J18
J19
J20
J21
J22
J24
J25
J26

COM3(Optional)
COM4(Optional)

COM5/COM6(Optional)

USB (Ports 0 & 1)
USB (Ports 2 & 3)

USB (Ports 4 & 5)

J27
J28

Front Panel Header

J29
J30

JP7
JP8

User's Notes:

Power Connector

Audio – CD In

Audio – Line In

VGA

ITP

COM1
COM2

CPU Fan

IR

9

Chapter 2: BIOS Configuration

Chapter 2 AMIBIOS8 Setup

Your Gator EPIC features American Megatrends AMIBIOS8. The system configuration parameters are set via the
BIOS setup. Since the BIOS Setup resides in the ROM BIOS, it is available each time the computer is turned on.

American Megatrends’s AMIBIOS8 brand BIOS (Basic Input/Output System) pre-boot firmware is the industry’s
standard product used by most designers of X86 computer equipment in the world today. Its superior combination of
configurability and functionality enables it to satisfy the most demanding ROM BIOS needs for x86 designers. Its
modular architecture and high degree of configurability make it the most flexible BIOS in the world.

When your platform is powered on, AMIBIOS8 tests and initializes the hardware and programs the chipset and
other peripheral components. During this time, Power On Self Test (POST) progress codes are written by the system
BIOS to I/O port 80h, allowing the user to monitor the progress with a special monitor. Appendix B lists the POST
codes and their meanings.
During early POST, no video is available to display error messages should a critical error be encountered; therefore,
POST uses beeps on the speaker to indicate the failure of a critical system component during this time. Consult
Appendix B for a list of Beep codes used by the BIOS.

Starting BIOS Setup

AMIBIOS has been integrated into many motherboards for over a decade. In the past, people often referred to the
AMIBIOS setup menu as BIOS, BIOS setup, or CMOS setup.
American Megatrends refers to this setup as ezPORT. Specifically, it is the name of theAMIBIOS8 BIOS setup
utility. This chapter describes the basic navigation of the ezPORT setup screens.

To enter the ezPORT setup screens, follow the steps below:
1 Power on the motherboard
2 Press the <Delete> key on your keyboard when you see the following text prompt:

Press DEL to run Setup

3 After you press the <Delete> key, the ezPORT main BIOS setup menu displays. You can access the other setup
screens from the main BIOS setup menu, such as the Chipset and PCI/PnP menus.

BIOS Setup Main Menu

The ezPORT main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is
described in the Chapter 2.
The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be
configured. “Grayed-out” options cannot be configured. Options in blue can be.
The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an
option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.
The ezPORT BIOS setup/utility uses a key-based navigation system called hot keys. Most of the ezPORT BIOS
setup utility hot keys can be used at any time during the setup navigation process. These keys include <F1>, <F10>,
<Enter>, <ESC>, <Arrow> keys, and so on.

10

Chapter 2:BIOS Configuration

The <F8> key on your keyboard is the Fail-Safe key. It is not displayed on the ezPORT key legend by default. To
set the Fail-Safe settings of the BIOS, press the <F8> key on your keyboard. It is located on the upper row of a
standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set.
This can lessen the probability of conflicting settings.

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Gator EPIC – Installation Guide

12

Chapter 2:BIOS Configuration

Main Setup

When you first enter the ezPORT Setup Utility, you will enter the Main setup screen. You can always return to the

Main setup screen by selecting the Main tab. There are two Main Setup options.

System Time/System Date

Use this option to change the system time and date. Highlight System Time or System Date using the <Arrow> keys.

Enter new values through the keyboard. Press the <Tab> key or the <Arrow> keys to move between fields. The date
must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format.

Note: The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00.

Advanced BIOS Setup

Select the Advanced tab from the ezPORT setup screen to enter the Advanced BIOS Setup screen. You can select

any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item.
You can display an Advanced BIOS Setup option by highlighting it using the <Arrow> keys. All Advanced BIOS
Setup options are described in this section.

CPU CONFIGURATION SCREEN

Information about the CPU.

Intel SpeedStep Technology

You can select the behavior of the SpeedStep feature prior to the OS boot. The Optimal and Fail-Safe default setting

is Disabled.

Maximum speed.
Minimum speed.
Auto.
Disabled.

IDE CONFIGURATION SCREEN

IDE Configuration Settings

You can use this screen to select options for the IDE Configuration Settings. Use the up and down <Arrow> keys to
select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. A description of the
selected item appears on the right side of the screen.

Onboard PCI IDE Controller

This item specifies the IDE channels used by the onboard PCI IDE controller. The settings are Disabled, Primary,
Secondary, or Both. The Optimal and Fail-Safe default setting is Both.

Disabled Set this value to prevent the computer system from using the onboard IDE controller.
Primary Set this value to allow the computer system to detect only the Primary IDE channel. This includes both the

Primary Master and the Primary Slave.

Secondary Set this value to allow the computer system to detect only the Secondary IDE channel. This includes both

the Secondary Master and the Secondary Slave.

Both Set this value to allow the computer system to detect the Primary and Secondary IDE channels.

This includes both the Primary Master, Primary Slave, Secondary Master, and Secondary Slave. This is the default
setting.

Onboard PCI IDE Operate Mode

Native mode is the preferred mode for modern OSes like Windows 2000 and Windows XP. OSes without support

for Native mode must use Legacy Mode. The Optimal and Fail-Safe default setting is Legacy Mode.

Legacy Mode Set this value to allow the hard disk drive to be used on IRQs 14 and 15 and I/O and memory maps

following legacy IDE standards

Native Mode Set this mode for the PCI IDE controller to be treated as any other PCI device (Windows 2000 and XP

only).

13

Gator EPIC – Installation Guide

Primary IDE Master, Primary IDE Slave, Secondary IDE Master, Secondary IDE Slave

Select one of the hard disk drives to configure it. Press <Enter> to access the sub menu. The options on the sub
menu are described in the following sections.

Hard disk drive Write Protect

Set this option to protect the hard disk drive from being overwritten. The Optimal and Fail-Safe default setting is

Disabled.

Disabled Set this value to allow the hard disk drive to be used normally. Read, write, and erase functions can be

performed to the hard disk drive. This is the default setting.

Enabled Set this value to prevent the hard disk drive from being erased.

IDE Detect Time Out (Seconds)

Set this option to stop the AMIBIOS from searching for IDE devices within the specified number of seconds.
Basically, this allows you to fine-tune the settings to allow for faster boot times. Adjust this setting until a suitable
timing that can detect all IDE disk drives attached is found.

The Optimal and Fail-Safe default setting is 35.

0 This value is the best setting to use if the onboard IDE controllers are set to a specific IDE disk drive in the

AMIBIOS.

5 Set this value to stop the AMIBIOS from searching the IDE bus for IDE disk drives in five seconds. A large majority

of ultra ATA hard disk drives can be detected well within five seconds.

10 Set this value to stop the AMIBIOS from searching the IDE bus for IDE disk drives in 10 seconds.
15 Set this value to stop the AMIBIOS from searching the IDE bus for IDE disk drives in 15 seconds.
20 Set this value to stop the AMIBIOS from searching the IDE bus for IDE disk drives in 20 seconds.
25 Set this value to stop the AMIBIOS from searching the IDE bus for IDE disk drives in 25 seconds.
30 Set this value to stop the AMIBIOS from searching the IDE bus for IDE disk drives in 30 seconds.
35 35 is the default value. It is the recommended setting when all IDE connectors are set to AUTO in the AMIBIOS

setting.

Note: Different IDE disk drives take longer for the BIOS to locate than others do.

ATA (PI) 80 pin Cable Detection

Set this option to select the method used to detect the ATA (PI) 80 pin cable. The Optimal and Fail-Safe setting is

Host & Device.

Host & Device Set this value to use both the motherboard onboard IDE controller and IDE disk drive to detect the type

of IDE cable used. This is the default setting.

Host Set this value to use motherboard onboard IDE controller to detect the type of IDE cable used.
Device Set this value to use IDE disk drive to detect the type of IDE cable used.

The use of an 80-conductor ATA cable is mandatory for running Ultra ATA/66 and Ultra ATA/100 IDE hard disk
drives. The standard 40-conductor ATA cable cannot handle the higher speeds.
80-conductor ATA cable is plug compatible with the standard 40-conductor ATA cable. Because of this, the system
must determine the presence of the correct cable. This detection is achieved by having a break in one of the lines on
the 80-conductor ATA cable that is normally an unbroken connection in the standard 40-conductor ATA cable. It is
this break that is used to make this determination. The AMIBIOS can instruct the drive to run at the correct speed
for the cable type detected.

PRIMARY AND SECONDARY IDE MASTER AND SLAVE SUB MENU

Primary and Secondary IDE Master and Slave Settings

From the IDE Configuration screen, press <Enter> to access the sub menu for the primary and secondary IDE
master and slave drives. Use this screen to select options for the Primary and Secondary IDE drives. Use the up and
down <Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option.
The settings are described on the following pages.

Drive Parameters

The “grayed-out” items in the left frame are the IDE disk drive parameters taken from the firmware of the IDE disk
drive selected. The drive parameters listed are as follows:

Device Type of device, such as Hard disk drive.
Vendor Manufacturer of the device.
Size The size of the device.

14

Chapter 2:BIOS Configuration

LBA Mode LBA (Logical Block Addressing) is a method of addressing data on a disk drive. Your AMIBIOS is

already equipped with 48-bit LBA mode addressing.

Block Mode Block mode boosts IDE drive performance by increasing the amount of data transferred. Only 512 bytes

of data can be transferred per interrupt if block mode is not used. Block mode allows transfers of up to 64 KB per
interrupt.

PIO Mode IDE PIO mode programs timing cycles between the IDE drive and the programmable IDE controller. As

the PIO mode increases, the cycle time decreases.

Async DMA This indicates the highest Asynchronous DMA Mode that is supported.
Ultra DMA This indicates the highest Synchronous DMA Mode that is supported.
S.M.A.R.T. Self-Monitoring Analysis and Reporting Technology protocol used by IDE drives of some manufacturers

to predict drive failures.

Type

This option sets the type of device that the AMIBIOS attempts to boot from after the Power-On Self-Test (POST)

has completed. The Optimal and Fail-Safe default setting is Auto.

Not Installed Set this value to prevent the BIOS from searching for an IDE disk drive on the specified channel.
Auto Set this value to allow the BIOS auto detect the IDE disk drive type attached to the specified channel. This setting

should be used if an IDE hard disk drive is attached to the specified channel. This is the default setting.

CD\DVD This option specifies that an IDE CD-ROM drive is attached to the specified IDE channel. The BIOS will not

attempt to search for other types of IDE disk drives on the specified channel.

ARMD This option specifies an ATAPI Removable Media Device.

This includes, but is not limited to:

• ZIP

• LS-120

• MO

LBA/Large Mode

LBA (Logical Block Addressing) is a method of addressing data on a disk drive. The Optimal and Fail-Safe default

setting is Auto.
Note: Your AMIBIOS is equipped with 48-bit LBA mode addressing for drive capacities over 137 GB.

Disabled Set this value to prevent the BIOS from using Large Block Addressing mode control on the specified

channel.

Auto Set this value to allow the BIOS to auto detect the Large Block Addressing mode control on the specified

channel. This is the default setting.

Block (Multi-Sector Transfer)

This option sets the block mode multi sector transfers option. The Optimal and Fail-Safe default setting is Auto.

Disabled Set this value to prevent the BIOS from using Multi-Sector Transfer on the specified channel. The data to and

from the device will occur one sector at a time.

Auto Set this value to allow the BIOS to auto detect device support for Multi-Sector Transfers on the specified channel.

If supported, Set this value to allow the BIOS to auto detect the number of sectors per block for transfer from the hard
disk drive to the memory. The data transfer to and from the device will occur multiple sectors at a time. This is the
default setting.

PIO Mode

IDE PIO (Programmable I/O) mode programs timing cycles between the IDE drive and the programmable IDE

controller. As the PIO mode increases, the cycle time decreases. The Optimal and Fail-Safe default setting is Auto.

Auto Set this value to allow the BIOS to auto detect the PIO mode. Use this value if the IDE disk drive support cannot

be determined. This is the default setting.

0 Set this value to allow the BIOS to use PIO mode 0. It has a data transfer rate of 3.3 MBs.
1 Set this value to allow the BIOS to use PIO mode 1. It has a data transfer rate of 5.2 MBs.
2 Set this value to allow the BIOS to use PIO mode 2. It has a data transfer rate of 8.3 MBs.
3 Set this value to allow the BIOS to use PIO mode 3. It has a data transfer rate of 11.1 MBs.
4 Set this value to allow the BIOS to use PIO mode 4. It has a data transfer rate of 16.6 MBs. This setting generally

works with all hard disk drives manufactured after 1999. For other disk drive, such as IDE CD-ROM drives, check the
specifications of the drive.

DMA Mode

This setting allows you to adjust the DMA mode options. The Optimal and Fail-Safe default setting is Auto.

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Auto Set this value to allow the BIOS to auto detect the DMA mode. Use this value if the IDE disk drive support

cannot be determined. This is the default setting.

SWDMA0 Set this value to allow the BIOS to use Single Word DMA mode 0. It has a data transfer rate of 2.1 MBs.
SWDMA1 Set this value to allow the BIOS to use Single Word DMA mode 1. It has a data transfer rate of 4.2 MBs.
SWDMA2 Set this value to allow the BIOS to use Single Word DMA mode 2. It has a data transfer rate of 8.3 MBs.
MWDMA0 Set this value to allow the BIOS to use Multi Word DMA mode 0. It has a data transfer rate of 4.2 MBs.
MWDMA1 Set this value to allow the BIOS to use Multi Word DMA mode 1. It has a data transfer rate of 13.3 MBs.
MWDMA2 Set this value to allow the BIOS to use Multi Word DMA mode 2. It has a data transfer rate of 16.6 MBs.
UDMA0 Set this value to allow the BIOS to use Ultra DMA mode 0. It has a data transfer rate of 16.6 MBs. It has the

same transfer rate as PIO mode 4 and Multi Word DMA mode 2.

UDMA1 Set this value to allow the BIOS to use Ultra DMA mode 1. It has a data transfer rate of 25 MBs.
UDMA2 Set this value to allow the BIOS to use Ultra DMA mode 2. It has a data transfer rate of 33.3 MBs.
UDMA3 Set this value to allow the BIOS to use Ultra DMA mode 3. It has a data transfer rate of 44.4 MBs. To use this

mode, it is required that an 80-conductor ATA cable is used.

UDMA4 Set this value to allow the BIOS to use Ultra DMA mode 4. It has a data transfer rate of 66.6 MBs. To use this

mode, it is required that an 80-conductor ATA cable is used.

UDMA5 Set this value to allow the BIOS to use Ultra DMA mode 5. It has a data transfer rate of 99.9 MBs. To use this

mode, it is required that an 80-conductor ATA cable is used.

S.M.A.R.T. for Hard disk drives

Self-Monitoring Analysis and Reporting Technology (SMART) feature can help predict impending drive failures.

The Optimal and Fail-Safe default setting is Auto.

Auto Set this value to allow the BIOS to auto detect hard disk drive support. Use this setting if the IDE disk drive

support cannot be determined. This is the default setting.

Disabled Set this value to prevent the BIOS from using the SMART feature.
Enabled Set this value to allow the BIOS to use the SMART feature on support hard disk drives.

32Bit Data Transfer

This option sets the 32-bit data transfer option. The Optimal and Fail-Safe default setting is Enabled.

Disabled Set this value to prevent the BIOS from using 32-bit data transfers.
Enabled Set this value to allow the BIOS to use 32-bit data transfers on support hard disk drives. This is the default

setting.

ARMD Emulation Type

ATAPI Removable Media Device (ARMD) is a device that uses removable media, such as the LS120, MO
(Magneto-Optical), or Iomega Zip drives. If you want to boot up from media on an ARMD, it is required that you
emulate boot up from a floppy or hard disk drive. This is especially necessary when trying to boot to DOS. You can
select the type of emulation used if you are booting from such a device. The Optimal and Fail-Safe default setting is

Auto.

Auto Set this value to allow the BIOS to automatically set the emulation used by ARMD. This is the default setting.
Floppy Set this value for ARMD to emulate a floppy drive during boot up.
Hard disk drive Set this value for ARMD to emulate a hard disk drive during boot up.

FLOPPY CONFIGURATION SCREEN

Floppy Configuration Settings

You can use this screen to specify options for the Floppy Configuration Settings. Use the up and down <Arrow>
keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option.

Floppy Drive A: and B:

Move the cursor to these fields via up and down <arrow> keys. Select the floppy type. The Optimal setting for

floppy drive A: is 1.44 MB 3½”. The Fail-Safe setting for floppy drive A: is 1.44 MB 3½”. The Optimal setting for
floppy drive B: is Disabled. The Fail- Safe setting for floppy drive B: is Disabled.

Disabled Set this value to prevent the use of the selected floppy disk drive channel. This option should be set if no
floppy disk drive is installed on the specified channel. This is the default setting for Floppy Drive B.
360 KB 5 ¼ ” Set this value if the floppy disk drive attached to the corresponding channel is a 360 KB 5¼ “ floppy

disk drive.

1.2 MB 5 ¼ ” Set this value if the floppy disk drive attached to the corresponding channel is a 1.2 MB 5¼ “ floppy disk

drive.

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Chapter 2:BIOS Configuration

720 KB 3 ½ ” Set this value if the floppy disk drive attached to the corresponding channel is a 720 KB 3½ “ floppy

disk drive.

1.44 MB 3 ½ ” Set this value if the floppy disk drive attached to the corresponding channel is a 1.44 MB 3½ “ floppy
disk drive. This is the default setting for Floppy Drive A.

2.88 MB 3 ½

SUPER IO CONFIGURATION SCREEN

SuperIO Configuration Screen

You can use this screen to select options for the Super I/O settings. Use the up and down <Arrow> keys to select an
item. Use the <Plus> and <Minus> keys to change the value of the selected option.

OnBoard Floppy Controller

Set this option to Enabled to enable the floppy drive controller on the motherboard. The settings are Enabled and

Disabled. The default setting is Enabled.

Floppy Disk Control Signals

Internal FDC
Parallel LPT
The Optimal and the Fail-safe default setting is Internal FDC.

Serial Port1 Address

This option specifies the base I/O port address of serial port 1. The Optimal setting is 3F8. The Fail-Safe default
setting is 3F8.

Disabled Set this value to prevent the serial port from accessing any system resources. When this option is set to
Disabled, the serial port physically becomes unavailable.
3F8 Set this value to allow the serial port to use 3F8 as its I/O port address. This is the default setting. The majority of

serial port 1 or COM1 ports on computer systems use I/O Port 3F8 as the standard setting. The most common serial
device connected to this port is a mouse. If the system will not use a serial device, it is best to set this port to Disabled.

2F8 Set this value to allow the serial port to use 2F8 as its I/O port address. If the system will not use a serial device, it
is best to set this port to Disabled.
3E8 Set this value to allow the serial port to use 3E8 as its I/O port address. If the system will not use a serial device, it
is best to set this port to Disabled.
2E8 Set this value to allow the serial port to use 2E8 as its I/O port address. If the system will not use a serial device, it
is best to set this port to Disabled.

Serial Port1 IRQ

This option specifies the IRQ of serial port 1. The Optimal setting is 4. This option is not available if serial port1 is
disabled.

3, 4, 10 or 11.

RS-485 Control for SP1

Enables or disables the control of the transceiver of the optional RS-485. In a half-duplex RS-485 serial
communication line, the function of the transceiver (transmit or receive) must be controlled over time. The settings

are Enabled and Disabled. The default setting is Disabled.

Auto Direction Control Sel

Enables or disables the control of the transceiver of the optional RS-485 using an auto direction mechanism of the
SuperIO. The settings are FC on and FC off. The default setting is FC off.

Signal Select SP1

Selects the signal to control the RS-485 direction if auto direction control is not being used

The settings are nDTR and nRTS. The default setting is nDTR.

Polarity SP1

Selects the polarity of the signal to control the RS-485 direction if auto direction control is not being used

The settings are Low and High. The default setting is High.

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Serial Port2 Address

This option specifies the base I/O port address of serial port 2. The Optimal setting is 2F8. The Fail-Safe default
setting is 2F8.

Disabled, 3F8, 2F8, 3E8, 2E8

Serial Port2 IRQ

This option specifies the IRQ of serial port 2. The Optimal setting is 3. This option is not available if serial port2 is

disabled.

3, 4, 10 or 11.

Serial Port2 Mode

This option allows installation of an Infra-red device by the Serial Port. The settings are Normal (default), IRDA and

ASK IR.

Infra-Red Transmission Mode

The settings are Full Duplex (default) or Half Duplex.

COMB Receiver Polarity [High]
COMB Xmitter Polarity [Low]

Sets polarity for IR modes.

RS-485 Control For SP2

The settings are Disabled and Enabled.
The Optimal and Fail-safe default setting is Disabled.

Auto direction Control Sel [FC off]
Signal Select SP2 [nDTR]
Polarity SP2 [High]

Serial Port3 Address

This option specifies the base I/O port address of serial port 3. The default setting is Disabled.

Disabled, 3F8, 2F8, 3E8, 2E8, 338, 238

Serial Port3 IRQ

This option specifies the IRQ of serial port 3. This option is not available if serial port 3 is disabled.

3, 4, 10 or 11.

Serial Port4 Address

This option specifies the base I/O port address of serial port 4. The default setting is Disabled.

Disabled, 3F8, 2F8, 3E8, 2E8, 338, 238

Serial Port4 IRQ

This option specifies the IRQ of serial port 4. This option is not available if serial port 4 is disabled.

3, 4, 10 or 11.

Serial Port5 Address

This option specifies the base I/O port address of serial port 5. The default setting is Disabled.

Disabled, 3E8, 2E8, 338, 238, 228, 220

Serial Port5 IRQ

This option specifies the IRQ of serial port 5. This option is not available if serial port5 is disabled.

3, 4, 5, 6, 7, 10, 11.

Serial Port6 Address

This option specifies the base I/O port address of serial port 6. The default setting is Disabled.

Disabled, 3E8, 2E8, 338, 238, 228, 220

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Chapter 2:BIOS Configuration

Serial Port6 IRQ

This option specifies the IRQ of serial port 6. This option is not available if serial port6 is disabled.

3, 4, 5, 6, 7, 10, 11.

Parallel Port Address

This option specifies the I/O address used by the parallel port. The Optimal setting is 378. The Fail-Safe setting is
Disabled.

Disabled Set this value to prevent the parallel port from accessing any system resources. When the value of this option
is set to Disabled, the printer port becomes unavailable.
378 Set this value to allow the parallel port to use 378 as its I/O port address. This is the default setting. The majority of

parallel ports on computer systems use IRQ7 and I/O Port 378H as the standard setting.

278 Set this value to allow the parallel port to use 278 as its I/O port address.
3BC Set this value to allow the parallel port to use 3BC as its I/O port address.

Parallel Port Mode

This option specifies the parallel port mode. The Optimal setting is Normal. The Fail- Safe setting is Disabled.

Normal Set this value to allow the standard parallel port mode to be used. This is the default setting.
SPP(Bi-Dir) Set this value to allow data to be sent to and received from the parallel port.
EPP+SPP The parallel port can be used with devices that adhere to the Enhanced Parallel Port (EPP) specification.

EPP uses the existing parallel port signals to provide asymmetric bi-directional data transfer driven by the host device.

ECP The parallel port can be used with devices that adhere to the Extended Capabilities Port (ECP) specification. ECP

uses the DMA protocol to achieve data transfer rates up to 2.5 Megabits per second. ECP provides symmetric bi­directional communication.

ECP+EPP

Parallel Port IRQ

This option specifies the IRQ used by the parallel port. The Optimal and Fail-Safe default setting is 7.

5 Set this value to allow the serial port to use Interrupt 5.
7 Set this value to allow the serial port to use Interrupt 7. This is the default setting. The majority of parallel ports on

computer systems use IRQ7 and I/O Port 378h as the standard setting.

HARDWARE HEALTH CONFIGURATION SCREEN

Hardware Health Configuration Screen

Shows information about temperatures and voltages. The function can be enabled or disabled.

H/W Health Function [Enabled]

Disabled
Enabled

System Fan Configuration

Several options to control the system Fan operation.

System Fan Mode Setting [Fan Always On Full]

Auto Fan Mode
Fan Always On Full
Fan disabled Mode
Fan Manually Mode

System Fan Ramp Rate [4.85 Hz]

9.62 Hz

14.49 Hz

24.39 Hz

38.46 Hz

55.56 Hz
100 Hz
200 Hz

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CPU Fan PWM Mode Setting [Fan Always On Full]

Auto Fan Mode
Fan Always On Full
Fan disabled Mode
Fan Manually Mode

CPU Fan PWM Ramp Rate [4.85 Hz]

9.62 Hz

14.49 Hz

24.39 Hz

38.46 Hz

55.56 Hz
100 Hz
200 Hz

The following parameters are displayed:

CPU and System Temperatures
CPU and System Fan Speed

System voltages including CPU Voltage

ACPI CONFIGURATION SCREEN

ACPI Configuration Screen

You can use this screen to select options for the ACPI settings. Use the up and down <Arrow> keys to select an
item. Use the <Plus> and <Minus> keys to change the value of the selected option.

Advanced ACPI Configuration

You can use this screen to select options for the ACPI Advanced Configuration Settings. Use the up and down
<Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. A
description of the selected item appears on the right side of the screen.

ACPI Version Feature [ACPI v1.0]

Set this value to the desired ACPI specification:

ACPI v1.0, ACPI v.2.0, ACPI v.3.0

ACPI APIC support

Include ACPI APIC pointer to RSDT pointer list.

AMI OEM Table

Set this value to allow the ACPI BIOS to add a pointer to an OEMB table in the Root System Description Table
(RSDT) table.

Disabled This option disables adding an OEMB table.
Enabled This option enables adding an OEMB table. This is the default setting.

Note: OEMB table is used to pass POST data to the AML code during ACPI O/S operations.

RSDT

RSDT is the main ACPI table. It has no fixed place in memory. During the boot up process, the BIOS locates a
pointer to the table during the memory scan. A Root System Descriptor Pointer (RSDP) is located in low memory
space of the system. It provides the physical address of the RSDT. The RSDT itself is identified in memory because
it starts with the signature "RSDT." Following the signature is an array of pointers that tell the operating system the
location of other description tables that provide it with the information it needs about the standards defined on the
current system and individual devices.

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Chapter 2:BIOS Configuration

AML

ACPI Machine Language (AML) is a binary code format that the operating system's ACPI AML interpreter parses
to discover the machine's properties. On boot up the BIOS startup code copies it into system memory, where it can
be interpreted by the operating system’s ACPI AML interpreter.

Headless Mode

This option is used to update the ACPI FACP table to indicate headless operations.

Disabled This option disables updating the ACPI FACP table to indicate headless operation. This is the default setting.
Enabled This option enables updating the ACPI FACP table to indicate headless operation.

Chipset ACPI Configuration

You can use this screen to select options for the Chipset ACPI Configuration Settings. Use the up and down
<Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. A
description of the selected item appears on the right side of the screen.

APIC ACPI SCI IRQ

The Optimal and Fail-Safe default setting is Disabled.

USB Device Wakeup From S3 [Disable]

EVENT LOG CONFIGURATION SCREEN

EVENT LOG Configuration Screen

You can use this screen to select options for the Event Log settings. Use the up and down <Arrow> keys to select an
item. Use the <Plus> and <Minus> keys to change the value of the selected option.

View Event Log
Mark all events as read
Clear Event Log

PCI Error Logging

Enables or disables PCI Error logging. The Optimal and Fail-Safe default setting is Disabled.

Enabled.
Disabled.

Smbios Configuration
Smbios Smi Support [Enable]

USB CONFIGURATION SCREEN

USB Configuration Screen

You can use this screen to select options for the USB Configuration. Use the up and down <Arrow> keys to select
an item. Use the <Plus> and <Minus> keys to change the value of the selected option.

USB Function

Number of USB ports enabled. The Optimal and Fail-Safe default setting is 6 USB Ports

2, 4, 6

Legacy USB Support

Legacy USB Support refers to the USB mouse and USB keyboard support. Normally if this option is not enabled,
any attached USB mouse or USB keyboard will not become available until a USB compatible operating system is
fully booted with all USB drivers loaded. When this option is enabled, any attached USB mouse or USB keyboard
can control the system even when there is no USB drivers loaded on the system. Set this value to enable or disable

the Legacy USB Support. The Optimal and Fail-Safe default setting is Auto.

Disabled Set this value to prevent the use of any USB device in DOS or during system boot.

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Enabled Set this value to allow the use of USB devices during boot and while using DOS.
Auto This option auto detects USB Keyboards or Mice and if found, allows them to be utilized during boot and while

using DOS.

USB 2.0 Controller Mode[Full Speed] (default)

Set this option to HiSpeed for 480Mbps or FullSpeed for 12Mbps.

BIOS EHCI Hand-off

Work around for OSes without hand-off support. The EHCI ownership should be claimed by the EHCI driver. The

Optimal and Fail-Safe default setting is Enabled.

USB Mass Storage Device Configuration Screen

You can use this screen to select options for the USB Mass Storage Devices Configuration. Use the up and down
<Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option.

USB Mass Storage Device Delay

Set the value for the number of seconds that POST waits for the USB mass storage device after start unit command
is issued. The options are 10, 20, 30 and 40 seconds.

Emulation Type

Set the emulation type to Auto, Floppy, Forced FDD, Hard Disk or CDROM. If Auto, USB devices less than
530MB will be emulated as floppy and remaining devices as Hard Drive. Forced FDD option can be used to force a
formatted HDD device to boot as FDD (ex. ZIP Drive).

PCI/PnP Setup

Select the PCI/PnP tab from the ezPORT setup screen to enter the Plug and Play BIOS Setup screen. You can

display a Plug and Play BIOS Setup option by highlighting it using the <Arrow> keys.

Clear NVRAM
Set this value to allow the system to clear the NVRAM. The Optimal and Fail-Safe default setting is No.

Plug and Play O/S

Set this value to allow the system to modify the settings for Plug and Play operating system support. The Optimal

and Fail-Safe default setting is Yes.

No The No setting is for operating systems that do not meet the Plug and Play specifications. It allows the BIOS to

configure all the devices in the system.

Yes The Yes setting allows the operating system to change the interrupt, I/O, and DMA settings. Set this option if the

system is running Plug and Play aware operating systems.

PCI Latency Timer

Set this value to allow the PCI Latency Timer to be adjusted. This option sets the latency of all PCI devices on the

PCI bus. The Optimal and Fail-Safe default setting is 64.

32 This option sets the PCI latency to 32 PCI clock cycles.
64 This option sets the PCI latency to 64 PCI clock cycles. This is the default setting.
96 This option sets the PCI latency to 96 PCI clock cycles.
128 This option sets the PCI latency to 128 PCI clock cycles.
160 This option sets the PCI latency to 160 PCI clock cycles.
192 This option sets the PCI latency to 192 PCI clock cycles.
224 This option sets the PCI latency to 224 PCI clock cycles.
248 This option sets the PCI latency to 248 PCI clock cycles.

Allocate IRQ to VGA

Set this value to allow or restrict the system from giving the VGA adapter card an interrupt address. The Optimal

and Fail-Safe default setting is Yes.

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Chapter 2:BIOS Configuration

Yes Set this value to allow the allocation of an IRQ to a VGA adapter card that uses the PCI local bus. This is the

default setting.

No Set this value to prevent the allocation of an IRQ to a VGA adapter card that uses the PCI local bus.

Palette Snooping

Set this value to allow the system to modify the Palette Snooping settings. The Optimal and Fail-Safe default setting

is Disabled.

Disabled This is the default setting and should not be changed unless the VGA card manufacturer requires Palette

Snooping to be Enabled.

Enabled This setting informs the PCI devices that an ISA based Graphics device is installed in the system. It does this

so the ISA based Graphics card will function correctly. This does not necessarily indicate a physical ISA adapter card.
The graphics chipset can be mounted on a PCI card. Always check with your adapter card’s manuals first, before
modifying the default settings in the BIOS.

PCI IDE BusMaster

Set this value to allow or prevent the use of PCI IDE bus mastering. The Optimal and Fail-Safe default setting is

Disabled.

Disabled Set this value to prevent PCI bus mastering. This is the default setting.
Enabled This option specifies that the IDE controller on the PCI local bus has mastering capabilities.

OffBoard PCI/ISA IDE Card

Set this value to allow the OffBoard PCI/ISA IDE Card to be selected. The Optimal and Fail-Safe default setting is

Auto.

Auto This setting will auto select the location of an OffBoard PCI IDE adapter card. This is the default setting.
PCI Slot1 This setting will select PCI Slot 1 as the location of the OffBoard PCI IDE adapter card. Use this setting

only if there is an IDE adapter card installed in PCI Slot 1.

PCI Slot2 This setting will select PCI Slot 2 as the location of the OffBoard PCI IDE adapter card. Use this setting

only if there is an IDE adapter card installed in PCI Slot 2.

PCI Slot 3
PCI slot 4
PCI slot 5
PCI slot 6

IRQ

Set this value to allow the IRQ settings to be modified. The Optimal and Fail-Safe default setting is Available.

IRQ3
IRQ4
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
IRQ14
IRQ15

Available This setting allows the specified IRQ to be used by a PCI/PnP device. This is the default setting.
Reserved This setting allows the specified IRQ to be used by a legacy ISA device.

DMA

Set this value to allow the DMA setting to be modified. The optimal and Fail-Safe default setting is Available.

DMA Channel 0
DMA Channel 1
DMA Channel 3
DMA Channel 5
DMA Channel 6
DMA Channel 7

Available This setting allows the specified DMA to be used by PCI/PnP device. This is the default setting.
Reserved This setting allows the specified DMA to be used by a legacy ISA device.

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Reserved Memory Size

Set this value to allow the system to reserve memory that is used by ISA devices. The optimal and Fail-Safe default

setting is Disabled.

Disabled Set this value to prevent BIOS from reserving memory to ISA devices.
16K Set this value to allow the system to reserve 16K of the system memory to the ISA devices.
32K Set this value to allow the system to reserve 32K of the system memory to the ISA devices.
64K Set this value to allow the system to reserve 64K of the system memory to the ISA devices.

Reserved Memory Address

Set this value to the base address of memory block to reserve for legacy ISA devices. The optimal and Fail-Safe

default setting is C8000.

C0000
C4000
C8000
CC000
D0000
D4000
D8000
DC000

Boot Setup

Select the Boot tab from the ezPORT setup screen to enter the Boot BIOS Setup screen. You can select any of the

items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can
display a Boot BIOS Setup option by highlighting it using the <Arrow> keys.

BOOT SETTINGS CONFIGURATION SCREEN

Boot Settings Configuration

Use this screen to select options for the Boot Settings Configuration. Use the up and down <Arrow> keys to select
an item. Use the <Plus> and <Minus> keys to change the value of the selected option.

Quick Boot

The Optimal and Fail-Safe default setting is Enabled.

Disabled Set this value to allow the BIOS to perform all POST tests.
Enabled Set this value to allow the BIOS to skip certain POST tests to boot faster.

Quiet Boot

Set this value to allow the boot up screen options to be modified between POST messages or OEM logo. The

Optimal and Fail-Safe default setting is Disabled.

Disabled Set this value to allow the computer system to display the POST messages.
Enabled Set this value to allow the computer system to display the OEM logo. This is the default setting.

(AddOn) ROM Display Mode

Set this option to display add-on ROM (read-only memory) messages. The Optimal and Fail-Safe default setting is

Force BIOS. An example of this is a SCSI BIOS or VGA BIOS.

Force BIOS Set this value to allow the computer system to force a third party BIOS to display during system boot.

This is the default setting.

Keep Current Set this value to allow the computer system to display the ezPORT information during system boot.

(Bootup) Num-Lock

Set this value to allow the Number Lock setting to be modified during boot up. The Optimal and Fail-Safe default

setting is On.

Off This option does not enable the keyboard Number Lock automatically. To use the 10-keys on the keyboard, press

the Number Lock key located on the upper left-hand corner of the 10-key pad. The Number Lock LED on the keyboard
will light up when the Number Lock is engaged.

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Chapter 2:BIOS Configuration

On Set this value to allow the Number Lock on the keyboard to be enabled automatically when the computer system is

boot up. This allows the immediate use of 10-keys numeric keypad located on the right side of the keyboard. To
confirm this, the Number Lock LED light on the keyboard will be lit.

PS/2 Mouse Support

Set this value to allow the PS/2 mouse support to be adjusted. The Optimal and Fail-Safe default setting is Auto.

Disabled This option will prevent the PS/2 mouse port from using system resources and will prevent the port from

being active. Use this setting if installing a serial mouse.

Enabled Set this value to allow the system to use a PS/2 mouse. This is the default setting.
Auto

Wait for ‘F1’ If Error

Set this value to allow the Wait for ‘F1’ Error setting to be modified. The Optimal and Fail-Safe default setting is

Enabled.

Disabled This prevents the ezPORT to wait on an error for user intervention. This setting should be used if there is a

known reason for a BIOS error to appear. An example would be a system administrator must remote boot the system.
The computer system does not have a keyboard currently attached. If this setting is set, the system will continue to boot
up in to the operating system. If ‘F1’ is enabled, the system will wait until the BIOS setup is entered.

Enabled Set this value to allow the system BIOS to wait for any error. If an error is detected, pressing <F1> will enter

Setup and the BIOS setting can be adjusted to fix the problem. This normally happens when upgrading the hardware
and not setting the BIOS to recognize it. This is the default setting.

Hit ‘DEL’ Message Display

Set this value to allow the Hit “DEL” to enter Setup Message Display to be modified. The Optimal and Fail-Safe
default setting is Enabled.

Disabled This prevents the ezPORT to display

during memory initialization. If Quiet Boot is enabled, the Hit ‘DEL’ message will not display.

Enabled This allows the ezPORT to display

during memory initialization. This is the default setting.

Interrupt 19 Capture[Disabled] (Default)

Set this value to allow option ROMs such as network controllers to trap BIOS interrupt 19.

Disabled The BIOS prevents option ROMs from trapping interrupt 19.
Enabled The BIOS allows option ROMs to trap interrupt 19.

BOOT DEVICE PRIORITY

Boot Device Priority

Use this screen to specify the order in which the system checks for the device to boot from. To access this screen,
select Boot Device Priority on the Boot Setup screen and press <Enter>.

1

st Boot Device

2

nd Boot Device

3

rd Boot Device

Set the boot device options to determine the sequence in which the computer checks which device to boot from. The

settings are Removable Dev., Hard Drive, or ATAPI CDROM. The Optimal and Fail-Safe settings are:

• 1

• 2

• 3

To change the boot order, select a boot category type such as Hard disk drives, Removable media, or ATAPI CD
ROM devices from the boot menu. For example, if the 1
to boot to hard disk drives first.

Note: When you select a boot category from the boot menu, a list of devices in that category appears. For example,

if the system has three hard disk drives connected, then the list will show all three hard disk drives attached.

Hit Del to enter Setup

Hit Del to enter Setup

st boot device – 1

nd boot device – CD/DVD

rd boot device – HDD

st

FLOPPY DRIVE

st boot device is set to Hard disk drives, then BIOS will try

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Gator EPIC – Installation Guide

HARD DISK DRIVES

Hard disk drives

Use this screen to view the hard disk drives in the system. To access this screen, select Hard disk drives on the Boot
Setup screen and press <Enter>.

1st Drive [HD:PM..]

REMOVABLE DRIVES

Removable Devices

Use this screen to view the removable drives attached to the system. To access this screen, select Removable
Devices on the Boot Setup screen and press <Enter>.

CD/DVD DRIVES

ATAPI CD-ROM Drives

Use this screen to view the ATAPI CD-ROM drives in the system. To access this screen, select ATAPI CDROM
Drives on the Boot Setup screen and press <Enter>.

1st Drive [CD/DVD: PS..]

Security Setup
ezPORT Password Support

Two Levels of Password Protection

ezPORT provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must
be set first. The system can be configured so that all users must enter a password every time the
system boots or when ezPORT Setup is executed, using either or either the Supervisor password or User password.
The Supervisor and User passwords activate two different levels of password security. If you select password
support, you are prompted for a one to six character password. Type the password on the keyboard. The password
does not appear on the screen when typed. Make sure you write it down. If you forget it, you must drain NVRAM
and reconfigure.

Remember the Password

Keep a record of the new password when the password is changed. If you forget the password, you must erase the
system configuration information in NVRAM. See (Deleting a Password) for information about erasing system
configuration information.
Select Security Setup from the ezPORT Setup main BIOS setup menu. All Security Setup options, such as password
protection and virus protection, are described in this section. To access the sub menu for the following items, select
the item and press <Enter>:

• Change Supervisor Password

• Change User Password

• Clear User Password

Supervisor Password

Indicates whether a supervisor password has been set. If the password has been installed, Installed displays. If not,
Not Installed displays.

User Password

Indicates whether a user password has been set. If the password has been installed, Installed displays. If not, Not
Installed displays.

Change Supervisor Password

Select this option and press <Enter> to access the sub menu. You can use the sub menu to change the supervisor
password.

26

Chapter 2:BIOS Configuration

Change User Password

Select this option and press <Enter> to access the sub menu. You can use the sub menu to change the user password.

Clear User Password

Select this option and press <Enter> to access the sub menu. You can use the sub menu to clear the user password.

Boot Sector Virus Protection

This option is near the bottom of the Security Setup screen. The Optimal and Fail-Safe default setting is Disabled

Disabled Set this value to prevent the Boot Sector Virus Protection. This is the default setting.
Enabled Select Enabled to enable boot sector protection. ezPORT displays a warning when any program (or virus)

issues a Disk Format command or attempts to write to the boot sector of the hard disk
drive. If enabled, the following appears when a write is attempted to the boot sector. You may have to type N several
times to prevent the boot sector write.
Boot Sector Write!
Possible VIRUS: Continue (Y/N)? _
The following appears after any attempt to format any cylinder, head, or sector of any hard disk drive via the BIOS INT
13 Hard disk drive Service:
Format!!!
Possible VIRUS: Continue (Y/N)? _

CHANGE SUPERVISOR PASSWORD

Change Supervisor Password

Select Change Supervisor Password from the Security Setup menu and press <Enter>.

Enter New Password:

appears. Type the password and press <Enter>. The screen does not display the characters entered. Retype the
password as prompted and press <Enter>. If the password confirmation is incorrect, an error message appears. The
password is stored in NVRAM after ezPORT completes.

Change User Password

Select Change User Password from the Security Setup menu and press <Enter>.

Enter New Password:

appears. Type the password and press <Enter>. The screen does not display the characters entered. Retype the
password as prompted and press <Enter>. If the password confirmation is incorrect, an error message appears. The
password is stored in NVRAM after ezPORT completes.

Clear User Password

Select Clear User Password from the Security Setup menu and press <Enter>.

Clear New Password
[Ok] [Canc el]

appears. Type the password and press <Enter>. The screen does not display the characters entered. Retype the
password as prompted and press <Enter>. If the password confirmation is incorrect, an error message appears. The
password is stored in NVRAM after ezPORT completes.

Deleting a Password

If you forget the passwords you set up through ezPORT Setup, the only way you can reset the password is to erase
the system configuration information where the passwords are stored. System configuration data is stored in CMOS
RAM, a type of memory that consumes very little power. You can drain CMOS RAM power by removing the
battery or resetting CMOS information using the CMOS erase jumper.

Chipset Setup

Select the Chipset tab from the ezPORT setup screen to enter the Chipset BIOS Setup screen. You can select any of

the items in the left frame of the screen, such as CPU Configuration, to go to the sub menu for that item. You can
display a Chipset BIOS Setup option by highlighting it using the <Arrow> keys. All Chipset BIOS Setup options are
described in this section.

27

Gator EPIC – Installation Guide

NORTH BRIDGE CONFIGURATION

North Bridge Configuration

You can use this screen to select options for the North Bridge Configuration. Use the up and down <Arrow> keys to
select an item. Use the <Plus> and <Minus> keys to change the value of the selected option.

DRAM Frequency

Set this value to the desired DRAM Frequency. The Optimal is Auto and Fail-Safe is 200MHz default setting.

200MHz, 266MHz, 333MHz, Auto.

Configure DRAM Timing by SPD

Set this value to disabled, so the desired DRAM parameters can be set or let them be retrieved from the SPD. The

Optimal and Fail-Safe default setting is Enabled.

Memory Hole

Enables the 15MB – 16MB memory hole. The Optimal and Fail-Safe default setting is Disabled.

Initial Graphics Adapter Priority

Set this value to allow the Primary video device to be selected. The Optimal and Fail-Safe default setting is AGP/Int
VGA.

Internal VGA, (AGP/Int. VGA), AGP/PCI, PCI/AGP, (PCI/Int. VGA)

Internal Graphics Mode Select

Set this value to select the amount of system memory used by the internal graphics device for legacy VESA modes.

The Optimal and Fail-Safe default setting is Enabled, 8MB.

Disabled This setting will not assign memory for the internal graphics engine.
Enabled, 1MB This setting will enable the internal graphics engine and allocate 1MB of system memory for it.
Enabled, 4MB This setting will enable the internal graphics engine and allocate 4MB of system memory for it.
Enabled, 8MB This setting will enable the internal graphics engine and allocate 8MB of system memory for it. This is

the default setting.

Enabled, 16MB This setting will enable the internal graphics engine and allocate 16MB of system memory for it.
Enabled, 32MB This setting will enable the internal graphics engine and allocate 32MB of system memory for it.

Graphic Aparture Size [64MB] (Optimal and Fail-safe setting)

Options: 64MB, 128MB, 256MB

IGD Device 2, Function 1

Enable or Disable the internal graphics device by setting item to the desired value. The Optimal and Fail-Safe

default setting is Enabled.

Disabled.
Enabled.

Boot Type

Selects the display devices to be enabled during boot.

VBIOS default. Let the Video BIOS decide based on its settings. Default option.
CRT. CRT only.
LFP. LVDS Panel only.
CRT+LFP. CRT and LVDS panel on.

Flat Panel Type

Selects the LVDS panel resolution to be enabled. Default is 1024x768.

640x480LVDS.
800x600LVDS.
1024x768LVDS.
1280x1024LVDS.
1400x1050LVDS.
1600x1200LVDS.

28

Chapter 2:BIOS Configuration

Flat Panel Scaling

Selects the policies for LVDS panel scaling. The CRT and LVDS must have the same resolution.

Auto.
Force Scaling.
Disabled.

SOUTH BRIDGE CONFIGURATION

Intel ICH4 South Bridge Configuration

You can use this screen to select options for the South Bridge Configuration. Use the up and down <Arrow> keys to
select an item. Use the <Plus> and <Minus> keys to change the value of the selected option.

On Board AC97 Audio

Set this option to Enable or Disable the on board Audio AC97 controller. If Audio is enabled, certain OSs will
require a driver installation on every boot.

Auto This setting will keep the onboard Audio Controller enabled. This is the default setting.
Disabled This setting will turn off the on board Audio controller.

Primary LAN

Set this option to Enable or Disable the on board primary LAN controller.

Disabled This setting will turn off the on board primary Ethernet controller.
Enabled This setting will keep the onboard Primary Ethernet Controller enabled. This is the default setting.

Secondary LAN

Set this option to Enable or Disable the on board (optional) secondary LAN controller. This option does not appear
on boards without the optional secondary LAN controller.

Disabled This setting will turn off the optional on board secondary Ethernet controller.
Enabled This setting will keep the optional onboard secondary Ethernet Controller enabled. This is the default setting.

Restore on A/C Power Loss

Set this value to select how the CPU board will recover from an accidental A/C power failure – Mechanical off G3
State.

Power OFF This setting will keep the CPU board OFF when A/C power is reestablished. To turn the board ON, the

power button must be used.

Power ON This setting will force the CPU board to turn ON as soon as A/C power is reestablished. This is the default

setting.

Last State This setting will put the CPU board back to its state before the accidental power failure. It requires ACPI

enabled and an ACPI capable OS. The board must be normally turned OFF through a controlled S5 (soft OFF/Power
button) transition if it is not an accidental power failure.

SATA Control

Set this option to Enable or Disable the on board SATA controller.

Disabled This setting will turn off SATA controller.
Enabled This setting will keep SATA Controller enabled. This is the default setting.

SATA RAID Control

Set this option to Enable or Disable the RAID function of the on board SATA controller.

RAID SATA Controller in RAID mode enabled. This is the default setting.
Non RAID This setting will turn off SATA controller RAID function.

29

Gator EPIC – Installation Guide

Power Management Setup

Select the Power tab from the ezPORT setup screen to enter the Power BIOS Setup screen. You can display a Power

BIOS Setup option by highlighting it using the <Arrow> keys. All Power BIOS Setup options are described in this
section.

Power Management/APM

Set this option to Enable or Disable the SMI based power management and APM support.

Enabled This is the default setting.
Disabled

Power Savings Under AC [Disabled]

Disabled
Enabled

Power Saving Level [Disabled]

Disabled
Minimum
Medium
Maximum
Customized

USB Controller Resume [Enabled]

Disabled
Enabled

PME Resume [Disabled]

Disabled
Enabled

Power Button Mode

This option specifies how the power button mounted externally on the computer chassis is used. The settings are:
On/Off and suspend. The default setting is On/Off.

On/Off This is the default setting.
Suspend

Exit Menu

Select the Exit tab from the ezPORT setup screen to enter the Exit BIOS Setup screen. You can display an Exit

BIOS Setup option by highlighting it using the <Arrow> keys. All Exit BIOS Setup options are described in this
section.

Exit Saving Changes

When you have completed the system configuration changes, select this option to leave ezPORT Setup and reboot
the computer so the new system configuration parameters can take effect. Select Exit Saving Changes from the Exit
menu and press <Enter>.

Save Configuration Changes and Exit Now?
[Ok] [Cancel]

appears in the window. Select Ok to save changes and exit.

Exit Discarding Changes

Select this option to quit ezPORT Setup without making any permanent changes to the system configuration. Select
Exit Discarding Changes from the Exit menu and press <Enter>.

Discard Changes and Exit Setup Now?
[Ok] [Cancel]

30

Chapter 2:BIOS Configuration

appears in the window. Select Ok to discard changes and exit.

Discard Changes

Select Discard Changes from the Exit menu and press <Enter>.

Select Ok to discard changes.

Load Optimal Defaults

ezPORT automatically sets all ezPORT Setup options to a complete set of default settings when you Select this
option. The Optimal settings are designed for maximum system performance, but may not work best for all
computer applications. In particular, do not use the Optimal ezPORT Setup options if your computer is experiencing
system configuration problems.
Select Load Optimal Defaults from the Exit menu and press <Enter>.

Select Ok to load optimal defaults.

Load Fail-Safe Defaults

ezPORT automatically sets all ezPORT Setup options to a complete set of default settings when you Select this
option. The Fail-Safe settings are designed for maximum system stability, but not maximum performance. Select the
Fail-Safe ezPORT Setup options if your computer is experiencing system configuration problems. Select Load Fail­Safe Defaults from the Exit menu and press <Enter>.

Load Fail-Safe Defaults?
[Ok] [Cancel]

appears in the window. Select Ok to load Fail-Safe defaults.

31

Chapter 3: Upgrading

Chapter 3 Upgrading

Upgrading the System Memory

The Gator EPIC allows an upgrade of the system memory with up to 1GB unbuffered SDRAM DDR SODIMM
modules in one memory slot. ECC and non-ECC DDR SDRAM modules are supported, PC1600 (DDR 200MHz),
PC2100 (DDR 266MHz) and PC2700 (DDR 333MHz). It is very important that the quality of the DIMM is good.
Unreliable operation of the system may result if poor quality DIMMs are used. Always purchase your memory from
a reliable source.

System Memory Features:

• 2.5 V (only) 200-pin DDR SDRAM SODIMMs with gold-plated contacts.

• Unbuffered, unregistered single-sided or double-sided DIMMs.

• Maximum total system memory: 1 GB; minimum total system memory: 32 MB .

• DDR333 MHz (PC2700) and DDR266 MHz (PC2100) DDR SDRAM SODIMMs only.

• Serial Presence Detect (SPD).

• You can use ECC and non-ECC DIMMs.

• Do not use Registered DIMMs.

• Double sided x16 DIMMs are not supported.

The following table lists the supported DDR DIMM Configurations:

Table 3-1 Supported DDRSO DIMM Configurations

DIMM
Capacity

64 MB 4 SS 128 Mbit 4 8 M x 16
128 MB 8 SS 128 Mbit 8 16 M x 8
128 MB 4 SS 256 Mbit 4 16 M x 16
256 MB 16 DS 128 Mbit 8 16 M x 8 8 16 M x 8
256 MB 8 SS 256 Mbit 8 32 M x 8
256 MB 4 SS 512 Mbit 4 32 M x 16
512 MB 16 DS 256 Mbit 8 32 M x 8 8 32 M x 8
512 MB 8 SS 512 Mbit 8 64 M x 8
1024 MB 16 DS 512 Mbit 8 64 M x 8 8 64 M x 8

# of
Dev./
DIMM

# of
Sides

DRAM
Tech.

Front Side
Population
Count Config Count Config

Back Side
Population

User's Notes:

32

Appendix A: Technical Specifications

Appendix A Technical Specifications

Chipsets

Core Logic

North Bridge - Intel 855GME.

South Bridge – Intel ICH4.

Peripheral I/O

Standard Microsystems (SMSC) SCH311x.

BIOS

System BIOS

American Megatrends AMIBIOS8.

Flash BIOS

Standard feature for System BIOS. Flash programming built into the BIOS. BIOS to be flashed is read from a
floppy.

Embedded I/O

IDE

PCI 32-bit EIDE controller – UDMA 66/100 supported. Mini-Header 44 pin for Solid State IDE disk or
any 44 pin IDE device support.

Parallel ATA IDE Interfaces

The ICH4 Parallel ATA IDE controller has the independent bus-mastering Parallel ATA IDE interface. The
Parallel ATA IDE interface support the following modes:

• Programmed I/O (PIO): processor controls data transfer.

• 8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.

• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates of

up to 33 MB/sec.

• ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up
to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.

• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH ATA-100 logic
can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.

NOTE

ATA-66 and ATA-100 are faster timings and require a specialized cable (80-conductor) to reduce
reflections, noise, and inductive coupling.

The Parallel ATA IDE interface also support ATAPI devices (such as CD-ROM drives).

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Gator EPIC – Installation Guide

The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS. The Gator EPIC
supports Laser Servo (LS-120) diskette technology through the Parallel ATA IDE interfaces. The BIOS
supports booting from an LS-120 drive.

NOTE

The BIOS will always recognize an LS-120 drive as an ATAPI floppy drive. To ensure correct operation, do
not configure the drive as a hard disk drive.

Serial ATA Interfaces

The Gator EPIC features two (Sil 3512) independent Serial ATA ports with a theoretical maximum transfer
rate of 150 MB/s per port. One device can be installed on each port for a maximum of two Serial ATA
devices. A point-to-point interface is used for host to device connections, unlike Parallel IDE, which
supports a master/slave configuration and two devices per channel.
For compatibility, the underlying Serial ATA functionality is transparent to the operating system.

NOTE

Many Serial ATA drives use new low-voltage power connectors and require adaptors or power supplies
equipped with low-voltage power connectors.

Serial Ports

Up to six high speed RS-232 serial ports 16 Bytes FIFO (16550/16550D). COM2 optional RS-232 IrDA
and COM1 optional RS-422/485. COM1 and COM2 are standard, other ports are optional.

Parallel Port

One bi-directional parallel port. EPP/ECP mode compatible.

Keyboard/Mouse Port

One mouse/keyboard combined connector.

USB Interfaces

Six Universal Serial Bus connectors. USB 1.1 and USB 2.0 compliant.

On-board Ethernet

One Ethernet connector (optional 10/100/1000).

On-board Buzzer

Audio

Audio (AD1981B) AC97 compliant. Microphone In, Stereo Line In and Out, Headphone Out and CD In.

34

Appendix A: Technical Specifications

Industrial Devices

Temperature and Voltage Device

Automatic CPU voltage & temperature monitoring device embedded on the peripheral I/O controller.

Power Management

Power button function: advanced power management support.

Miscellaneous

CMOS/Battery

RTC with lithium battery. Connector for external connection.

Control Panel Connections

Reset, Soft Power. LEDs for power and IDE.

CPU

Two possible BGA configurations: ULV 1.0 Ghz Celeron M, 5.5W, 512KB L2 cache or LV 1.4Ghz Pentium
M, 10W, 2MB L2 cache.

Form Factor

EPIC form factor (4.5” x 6.5”).

PCB Construction

Twelve Layers, dry film mask.

Manufacturing Process

Automated surface mount.

Table A-1 Environmental

Environmental Operating Non-operating

Temperature

Humidity

Shock 2.5G @ 10ms 10G @ 10ms

Vibration 0.25 @ 5-100Hz 5 @ 5-100Hz

0° to +55° C -40° to +65° C

5 to 95% @ 40° C non-

condensing

5 to 95% @ 40° C non-

condensing

35

Gator EPIC – Installation Guide

Memory Map

Address Range Decimal

960K-1M 0F0000-0FFFFF 64 KB Upper BIOS
896K-960K 0E0000-0EFFFF 64 KB Lower BIOS

768K-896K 0C0000-0DFFFF 128 KB

640K-768K 0A0000-0BFFFF 128 KB

633K-640K 09E400-09FFFF 7KB BIOS Reserved

512K-633K 080000-09E3FF 121 KB
0K- 512K 000000-07FFFF 512 KB Conventional memory

Address Range
Hexadecimal

Size Description

Expansion Card BIOS and

Buffer

Standard PCI/ISA Video

Memory

Ext. Conventional

memory

DMA Channels

DMA # Data Width System Resource
0
1
2
3
4
5
6
7

8- or 16-bits
8- or 16-bits Parallel port (for ECP) (if selected)
8- or 16-bits
8- or 16-bits Parallel port (for ECP) (if selected)
Reserved- cascade channel
16-bits Open
16-bits Open
16-bits Open

I/O Map

Address (hex) Description

0000-000F DMA 1
0020-0021 Interrupt Controller 1
0040 Timer/Counter 0
0041 Timer/Counter 1
0042 Timer/Counter 2
0043 Timer Control Word
0060 Keyboard Controller Byte _ Reset IRQ
0061 NMI Status and Control
0070, bit 7 NMI enable
0070, bits 6:0 RTC Index
0071 RTC Data
0072 RTC Extended Index
0073 RTC Extended Data
0080-008F DMA page registers / POST code display also located at 0080h
0092 Port 92
00A0-00A1 Interrupt Controller 2
00B2-00B3 APM control

36

Appendix A: Technical Specifications

Address (hex) Description

00C0-00DE DMA 2
00F0 Coprocessor Error
0170 _ 0177 Secondary IDE channel
01F0 _ 01F7 Primary IDE channel
0278-027F LPT2 (if selected)
02E8-02EF COM4 (default)
02F8-02FF COM2 (default)
0376 Secondary IDE channel command port
0377 Floppy channel 2 command
0377, bit 7 Floppy disk change, channel 2
0377, bits 6:0 Secondary IDE channel status port
0378-037F LPT1 (default)
03B4-03B5 Video (VGA)
03BA Video (VGA)
03BC-03CD LPT3 (if selected)
03C0-03CA Video (VGA)
03CC Video (VGA)
03CE-03CF Video (VGA)
03D4-03D5 Video (VGA)
03DA Video (VGA)
03E8-03EF COM3 (default)
03F0-03F5 Floppy Channel 1
03F6 Primary IDE channel command port
03F7 Floppy Channel 1 command
03F7, bit 7 Floppy disk change channel 1
03F7, bits 6:0 Primary IDE channel status report
03F8-03FF COM1 (default)
0CF8-0CFB - 4 bytes PCI configuration address register
0CF9 Reset control register
0CFC-0CFF - 4 bytes PCI configuration data register

PCI Configuration Space Map

Bus # Device # Function # Description

00 00 00 855GME (Host Bridge)
00 00 01 855GME DDR SDRAM Reg.
00 00 03 855GME Config. Reg.
00 01 00 855GME PCI to PCI Bridge
00 02 00 855GME VGA Controller
00 1D 00 ICH4 USB UHC 1
00 1D 01 ICH4 USB UHC 2
00 1D 02 ICH4 USB UHC 3
00 1D 07 ICH4 USB EHC
00 1E 00 Hub Interface to PCI Bridge
00 1F 00 ICH4 LPC Bridge
00 1F 01 ICH4 Master IDE Controller
00 1F 03 ICH4 SMBus Controller
00 1F 05 ICH4 AC97 Audio Controller

01 00 00 AGP Card

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Gator EPIC – Installation Guide

02 02 00 Mini-PCI slot
02 00 00 LAN Controller
02 01 00 SATA
02 04 00 PC104 PCI IDSEL0
02 05 PC104 PCI IDSEL1
02 06 PC104 PCI IDSEL2
02 07 PC104 PCI IDSEL3

Interrupts

IRQ System Resource

NMI I/O channel check
0 Reserved, interval timer
1 Reserved (keyboard)
2 Reserved (cascade)
3 COM2*
4 COM1*
5 User Available for PCI
6 Floppy Drive
7 LPT1*
8 Real time clock
9 User Available for PCI
10 User Available for PCI
11 User Available for PCI
12 PS/2 mouse port
13 Reserved (math coprocessor)
14 Primary IDE
15 Secondary IDE

*Default, but can be changed to another IRQ

SMBUS

Device Slave Address

SIO 00101101b
SODIMM 01010000b
Clock Chip Write 11010010b
Clock Chip Read 11010011b

PCI Interrupt Routing Map

PCI Device ID SEL PIRQA PIRQB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH
PC104 PCI AD20 INTA INTB INTC INTD
PC104 PCI AD21 INTB INTC INTD INTA
PC104 PCI AD22 INTC INTD INTA INTB
PC104 PCI AD23 INTD INTA INTB INTC
Mini-PCI AD18 INTB INTA
Ethernet AD16 INTA
IDE INTA
Audio INTA
SATA AD17 INTA
USB 1 INTA
USB 2 INTA
USB 3 INTA
USB 2.0 INTA
SMBus INTA
VGA INTA

38

Appendix A: Technical Specifications

Connectors Pin-out

How to identify pin number 1: Looking to the solder side (The board side with fewer components) of the PCB
(Printed Circuit Board), pin number 1 will have a squared pad J. Other pins will have a circular pad Q.

How to identify other pins: Connectors type DB, PS/2, RJ45, Power ATX and USB are industry standards. DB
connectors, for instance, are numbered sequentially. The first row is numbered in sequence (be aware that male and
female connectors are mirrored – male connectors are numbered from left to right when viewed from front and
female connectors are numbered from right to left when viewed from front). The following rows resume the
counting on the same side of pin number 1. The counting is NOT circular like Integrated Circuits (legacy from
electronic tubes).

1z2z3z4z5z
6z7z8z9z

Header connectors are numbered alternately, i.e. pin number 2 is in the other row, but in the same column of pin
number 1. Pin number 3 is in the same row of pin 1, but in the next column and so forth.

DB9 Male
Front view

54321
9876

DB9 Female
Front view

1 3z 5z 7z 9z
2z 4z 6z 8z10z

Table A-9 Serial Port COM1 Header Connector J18

Header 10 pin connector
View from solder side of the PCB

Pin# Serial Port COM 1 – J18

1 DCD - RS-422/485RXB(opt.)
2 DSR
3 RX - RS-422/485TXB(opt.)
4 RTS
5 TX - RS-422/485TXA(opt.)
6 CTS
7 DTR
8 RI – RS-422/485RXA(opt.)
9 GND

10 N.C.

Table A-10 Serial Port COM2 Header Connector J19

Pin# Serial Port COM 2 – J19

1 DCD
2 DSR
3 RX
4 RTS
5 TX
6 CTS
7 DTR
8 RI
9 GND

10 N.C

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Gator EPIC – Installation Guide

Table A-11 Serial Port COM3 Header Connector J20

Pin# Serial Port COM 3 – J20

1 DCD
2 DSR
3 RX
4 RTS
5 TX
6 CTS
7 DTR
8 RI
9 GND

10 N.C

Table A-12 Serial Port COM4 Header Connector J21

Pin# Serial Port COM 4 – J21

1 DCD
2 DSR
3 RX
4 RTS
5 TX
6 CTS
7 DTR
8 RI
9 GND

10 N.C

Table A-13 Serial Port COM5-6 Header Connector J22

Pin# Serial Port COM5-6 Header – J22

1 RX5 TTL
2 TX5 TTL
3 RX5 RS232
4 SCOUT5 RS232
5 TX5 RS232
6 SCIN5 RS232
7 GND
8 GND

9 RX6 RS232
10 SCOUT6 RS232
11 TX6 RS232
12 SCIN6 RS232
13 N.C.
14 N.C.

40

Appendix A: Technical Specifications

Table A-14 J7 Ethernet

Pin# Ethernet (optional 1Gbe) Connector – J17

1 TX1+ (optional 1Gbe)
2 RX-/ RX- (optional 1Gbe)
3 TX1- (optional 1Gbe)
4 RX+/RX+ (optional 1Gbe)
5 RX1+ (optional 1Gbe)
6 TX-/ TX- (optional 1Gbe)
7 RX1- (optional 1Gbe)
8 TX+/TX+ (optional 1Gbe)

9 CHASSIS GND
10 CHASSIS GND
11 LED ACT
12 LED LINK
13 3.3V/SPEED (optional 1Gbe)
14 SPEED

Table A-15 J24 USB Ports 0 & 1 Header Connector

Pin# USB Header – J24

1 +5V – USB0
2 +5V – USB1
3 -D – USB0
4 -D – USB1
5 +D – USB0
6 +D – USB1
7 GROUND – USB0
8 GROUND – USB1
9 NC

10 Over Current

Table A-16 J25 USB Ports 2 & 3 Header Connector

Pin# USB Header – J25

1 +5V – USB2
2 +5V – USB3
3 -D – USB2
4 -D – USB3
5 +D – USB2
6 +D – USB3
7 GROUND – USB2
8 GROUND – USB3
9 NC

10 Over Current

41

Gator EPIC – Installation Guide

Table A-17 J26 USB Ports4 & 5 Header Connector

Pin# USB Header – J26

1 +5V – USB4
2 +5V – USB5
3 -D – USB4
4 -D – USB5
5 +D – USB4
6 +D – USB5
7 GROUND – USB4
8 GROUND – USB5
9 NC

10 Over Current

Table A-18 J3 VGA Header Connector

Pin# VGA Header – J3

1 RED
2 GND
3 GREEN
4 GND
5 BLUE
6 GND
7 HSYNC
8 GND

9 VSYNC
10 GND
11 DDC SCL
12 GND
13 DDC SDA
14 VCC 5V

Table A-19 J10 KBD/Mouse Header Connector

Pin# KBD/Mouse Header – J10

1 MSCLOCK

2 KBCLOCK

3 N.C.

4 KBDATA

5 VCC

6 VCC

7 GND

8 MSDATA

9 GND
10 N.C.

42

Appendix A: Technical Specifications

Table A-20 J28 Front Panel Header Connector

Pin# Front Panel Header – J28

1 HDD LED Anode

2 Power LED Green Blink

3 HDD LED Cathode

4 Power LED Yellow Blink

5 Reset - GND

6 Power Switch

7 Reset

8 Power Switch - GND

9 +5V
10 NC

Table A-21 J29 Front Panel Header Connector-IR

Pin# Front Panel IR Header – J29

1 Infra Red Rx (Opt.)

2 GND

3 GND

4 NC

5 Infra Red Tx (Opt.)

6 +5VDC

Table A-22 J30 Power Connector

Pin# Power – J30

1 PS_ON

2 GND

3 GND

4 +12V

5 +3.3V

6 +5V STDBY

7 +5V

8 +5V

9 -12V
10 GND

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Gator EPIC – Installation Guide

Table A23 J17 Parallel Header Connector

Pin# Parallel Header – J17

1 STROBE
2 AUTOFEED
3 +DATA BIT 0
4 ERROR
5 +DATA BIT 1
6 INIT
7 +DATA BIT 2
8 SLCT IN

9 +DATA BIT 3
10 GND
11 +DATA BIT 4
12 GND
13 +DATA BIT 5
14 GND
15 +DATA BIT 6
16 GND
17 +DATA BIT 7
18 GND
19 ACK
20 GND
21 BUSY
22 GND
23 PAPER EMPTY
24 GND
25 SLCT
26 NC

Table A-24 CPU Fan, External Battery, Speaker, CD IN and Line IN.

Connector Description

44

J27

J6

J12

JP7

JP8

1) GND 2)+12V 3) Sense

External Battery

1)+Vbat 2)GND

Speaker (Alternate)

1)VCC 2) GND (PWM) 3) GND (PWM)

1) Right 2)GND 3)GND 4) Left

1) Right 2)GND 3)GND 4) Left

CPU FAN

CD IN

Line IN

Appendix A: Technical Specifications

Table A-25 J2 Audio Microphone, Line out/Headphone Connector

Pin# Audio Microphone, Line Out/Headphone – J2

1 MIC
2 GND
3 MIC BIAS
4 +5V
5 LINEOUT/HEADPHONE RIGHT
6 N.C.
7 N.C.
8 N.C.
9 LINEOUT/HEADPHONE LEFT

10 SENSE

Table A-26 J5 LVDS Backlight Connector

Pin# LVDS Backlight – J5

1 Inverter Vcc
2 GND
3 GND
4 Backlight Logic Vcc
5 SMBUS Clock (optional)
6 SMBUS Data (optional)
7 Backlight Enable

Table A-27 J4 LVDS Connector

Pin# LVDS – J4

1 GND
2 LVDS VDD 3.3V
3 LVDS VDD 3.3V
4 LVDS DDC VCC 3.3V
5 NC
6 DDC CLK
7 DDC DATA
8 LVDS YAM0

9 LVDS YAP0
10 GND
11 LVDS YAM1
12 LVDS YAP1
13 GND
14 LVDS YAM2
15 LVDS YAP2
16 GND
17 LVDS CLK AM
18 LVDS CLK AP

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Gator EPIC – Installation Guide

19 GND
20 LVDS YBM0
21 LVDS YBP0
22 GND
23 LVDS YBM1
24 LVDS YBP1
25 GND
26 LVDS YBM2
27 LVDS YBP2
28 GND
29 LVDS CLK BM
30 LVDS CLK BP

User's Notes:

46

Appendix B: Flash BIOS

Appendix B Flash BIOS programming and codes

The Gator EPIC offers the standard FLASH BIOS. When installed, you will be able to update your BIOS without
having to replace the EEPROM. The AMIBIOS8 will read the new BIOS file from a USB floppy disk during boot
and replace the old BIOS.

When updating your BIOS, make sure you have a disk with the correct BIOS file (its size should be 4Mb (512kB))
named AMIBOOT.ROM.

How to reflash the BIOS:

• Insert a floppy containing AMIBOOT.ROM into (USB) floppy A:

• Press [ctrl][home] during the beginning of POST(boot).

• Wait for the procedure to finish and reboot.

Please never turn the power off while reprogramming a FLASH BIOS.

Troubleshooting POST

AMIBIOS8 writes progress codes, also known as POST codes, to I/O port 80h during POST, in order to provide
information to OEM developers about system faults. These POST codes may be monitored by the On-board POST
Display.

Table B-1 Bootblock Initialization Code Checkpoints

The Bootblock initialization code sets up the chipset, memory and other components before system memory is
available. The following table describes the type of checkpoints that may occur during the bootblock initialization
portion of the BIOS.

Checkpoint Code Description

Before D1 Early chipset initialization is done. Early super I/O initialization is done including RTC and

keyboard controller. NMI is disabled.

D1 Perform keyboard controller BAT test. Check if waking up from power management

suspend state. Save power-on CPUID value in scratch CMOS.
D0 Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum.
D2 Disable CACHE before memory detection. Execute full memory sizing module. Verify that

flat mode is enabled.
D3 If memory sizing module not executed, start memory refresh and do memory sizing in

Bootblock code. Do additional chipset initialization. Re-enable CACHE. Verify that flat

mode is enabled.
D4 Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5 Bootblock code is copied from ROM to lower system memory and control is given to it.

BIOS now executes out of RAM.
D6 Both key sequence and OEM specific method is checked to determine if BIOS recovery is

forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to

checkpoint E0. See Bootblock Recovery Code Checkpoints section of document for

more information.
D7 Restore CPUID value back into register. The Bootblock-Runtime interface module is

moved to system memory and control is given to it. Determine whether to execute serial

flash.

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Gator EPIC – Installation Guide

D8 The Runtime module is uncompressed into memory. CPUID information is stored in

memory.
D9 Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory.

Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but

closing SMRAM.
DA Restore CPUID value back into register. Give control to BIOS POST

(ExecutePOSTKernel). See POST Code Checkpoints section of document for more

information.
E1-E8 EC-EE OEM memory detection/configuration error. This range is reserved for chipset vendors &

system manufacturers.

Table B-2 Bootblock Recovery Code Checkpoints

The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because
the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of
checkpoints that may occur during the Bootblock recovery portion of the BIOS:

Checkpoint Code Description

E0 Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA

controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9 Set up floppy controller and data. Attempt to read from floppy.
EA Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EB Disable ATAPI hardware. Jump back to checkpoint E9.
EF Read error occurred on media. Jump back to checkpoint EB.
F0 Search for pre-defined recovery file name in root directory.
F1 Recovery file not found.
F2 Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
E0 Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA

controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9 Set up floppy controller and data. Attempt to read from floppy.
EA Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EB Disable ATAPI hardware. Jump back to checkpoint E9.
EF Read error occurred on media. Jump back to checkpoint EB.
F0 Search for pre-defined recovery file name in root directory.
F1 Recovery file not found.
F2 Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.

Table B-3 POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The following
table describes the type of checkpoints that may occur during the POST portion of the BIOS:

Checkpoint Code Description

03 Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST,

Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized

CMOS as mentioned in the Kernel Variable "wCMOSFlags."
04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is

OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is

bad, update CMOS with power-on default values and clear passwords. Initialize status

register A.

Initializes data variables that are based on CMOS setup questions. Initializes both the 8259

compatible PICs in the system
05 Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06 Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch

handler. Enable IRQ-0 in PIC for system timer interrupt.

48

Appendix B: Flash BIOS

Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
C0 Early CPU Init Start -- Disable Cache - Init Local APIC
C1 Set up boot strap processor Information
C2 Set up boot strap processor for POST
C5 Enumerate and set up application processors
C6 Re-enable cache for boot strap processor
C7 Early CPU Init Exit
0A Initializes the 8042 compatible Key Board Controller.
0B Detects the presence of PS/2 mouse.
0C Detects the presence of Keyboard in KBC port.
0E Testing and initialization of different Input Devices. Also, update the Kernel Variables.

Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.

Uncompress all available language, BIOS logo, and Silent logo modules.
13 Early POST initialization of chipset registers.
24 Uncompress and initialize any platform specific BIOS modules.
30 Initialize System Management Interrupt.
2A Initializes different devices through DIM.

See DIM Code Checkpoints section of document for more information.

2C Initializes different devices. Detects and initializes the video adapter installed in the system

that have optional ROMs.
2E Initializes all the output devices.
31 Allocate memory for ADM module and uncompress it. Give control to ADM module for

initialization. Initialize language and font modules for ADM. Activate ADM module.
33 Initializes the silent boot module. Set the window for displaying text information.
37 Displaying sign-on message, CPU information, setup key message, and any OEM specific

information.

38 Initializes different devices through DIM. See DIM Code Checkpoints section of document

for more information.
39 Initializes DMAC-1 & DMAC-2.
3A Initialize RTC date/time.
3B Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit

memory test. Display total memory in the system.
3C Mid POST initialization of chipset registers.
40 Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, … etc.)

successfully installed in the system and update the BDA, EBDA…etc.
50 Programming the memory hole or any kind of implementation that needs an adjustment in

system RAM size if needed.
52 Updates CMOS memory size from memory found in memory test. Allocates memory for

Extended BIOS Data Area from base memory.
60 Initializes NUM-LOCK status and programs the KBD typematic rate.
75 Initialize Int-13 and prepare for IPL detection.
78 Initializes IPL devices controlled by BIOS and option ROMs.
7A Initializes remaining option ROMs.
7C Generate and write contents of ESCD in NVRam.
84 Log errors encountered during POST.
85 Display errors to the user and gets the user response for error.
87 Execute BIOS setup if needed / requested.
8C Late POST initialization of chipset registers.
8D Build ACPI tables (if ACPI is supported)
8E Program the peripheral parameters. Enable/Disable NMI as selected
90 Late POST initialization of system management interrupt.
A0 Check boot password if installed.
A1 Clean-up work needed before booting to OS.
A2 Takes care of runtime image preparation for different BIOS modules. Fill the free area in

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Gator EPIC – Installation Guide

F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the

runtime language module. Disables the system configuration display if needed.
A4 Initialize runtime language module.
A7 Displays the system configuration screen if enabled. Initialize the CPU’s before boot, which

includes the programming of the MTRR’s.
A8 Prepare CPU for OS boot including final MTRR values.
A9 Wait for user input at config display if needed.
AA Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
AB Prepare BBS for Int 19 boot.
AC End of POST initialization of chipset registers.
B1 Save system context for ACPI.
00 Passes control to OS Loader (typically INT19h).
61-70 OEM POST Error.

Table B-4 DIM Code Checkpoints

The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different
system busses. The following table describes the main checkpoints where the DIM module is accessed:

Checkpoint Code Description

2A Initialize different buses and perform the following functions: Reset, Detect, and Disable

(function 0); Static Device Initialization (function 1); Boot Output Device Initialization

(function 2). Function 0 disables all device nodes, PCI devices, and PnP ISA cards. It also

assigns PCI bus numbers. Function 1 initializes all static devices that include manual

configured onboard peripherals, memory and I/O decode windows in PCI-PCI bridges, and

noncompliant PCI devices. Static resources are also reserved. Function 2 searches for and

initializes any PnP, PCI, or AGP video devices.
38 Initialize different buses and perform the following functions: Boot Input Device

Initialization (function 3); IPL Device Initialization (function 4); General Device

Initialization (function 5). Function 3 searches for and configures PCI input devices and

detects if system has standard keyboard controller. Function 4 searches for and configures

all PnP and PCI boot devices. Function 5 configures all onboard peripherals that are set to

an automatic configuration and configures all remaining PnP and PCI devices.

While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify
the routines under execution. The low byte value indicates the main POST Code Checkpoint. The high byte is
divided into two nibbles and contains two fields. The details of the high byte of these checkpoints are as follows:

HIGH BYTE XY

The upper nibble 'X' indicates the function number that is being executed. 'X' can be from 0 to 7.

0 = func#0, disable all devices on the BUS concerned.
1 = func#1, static devices initialization on the BUS concerned.
2 = func#2, output device initialization on the BUS concerned.
3 = func#3, input device initialization on the BUS concerned.
4 = func#4, IPL device initialization on the BUS concerned.
5 = func#5, general device initialization on the BUS concerned.
6 = func#6, error reporting for the BUS concerned.
7 = func#7, add-on ROM initialization for all BUSes.
8 = func#8, BBS ROM initialization for all BUSes.

The lower nibble 'Y' indicates the BUS on which the different routines are being executed. 'Y' can be from 0 to 5.

0 = Generic DIM (Device Initialization Manager).

50

Appendix B: Flash BIOS

1 = On-board System devices.
2 = ISA devices.
3 = EISA devices.
4 = ISA PnP devices.
5 = PCI devices.

Table B-5 ACPI Runtime Checkpoints

ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The
following table describes the type of checkpoints that may occur during ACPI sleep or wake events:

Checkpoint Code Description

AC First ASL check point. Indicates the system is running in ACPI mode.
AA System is running in APIC mode.
01, 02, 03, 04, 05 Entering sleep state S1, S2, S3, S4, or S5.
10, 20, 30, 40, 50 Waking from sleep state S1, S2, S3, S4, or S5.

Critical Error BEEP Codes

The following table describes the beep codes that are used by AMIBIOS:

Table B-6 AMIBIOS Beep Codes

Number of Beeps Description

1 Memory refresh timer error.
2 Parity error
3 Main memory read / write test error.
4 Motherboard timer not operational
5 Processor error
6 Keyboard controller BAT test error.
7 General exception error.
8 Display memory error.
9 ROM checksum error
10 CMOS shutdown register read/write error
11 Cache memory bad

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Gator EPIC – Installation Guide

User's Notes:

52

Appendix C: Industrial Devices

Appendix C On-Board Industrial Devices

The Gator EPIC offers an on-board 10/100 (10/100/1000 optional) Ethernet controller and up to six serial ports (one
optional RS422/485).

On-board Ethernet

The Gator EPIC features either a 10/100 Ethernet controller or a 10/100/1000 Ethernet controller. Ethernet
controller 10/100 is an Intel 82559ER 10/1000 (or 82551ER), that may optionally be upgraded to an Intel 82541ER,
which is a 10/100/1000Mbps device.

The 82559ER/551ER is a 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities,
which enable the 82559ER/551ER to perform high-speed data transfers over the PCI bus. The 82559ER/551ER bus
master capabilities enable the component to process high-level commands and to perform multiple operations,
thereby off-loading communication tasks from the system CPU.

It can operate in either full duplex or half duplex mode. In full duplex mode it adheres to the IEEE 802.3x Flow
Control specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism.

The Intel
circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE_TX, and 10BASE-T
applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of
1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides
a 32-bit wide direct Peripheral Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or
66 MHz.

The 82541ER Architecture is designed for high performance and low memory latency. Wide internal data paths
eliminate performance bottlenecks by efficiently handling large address and data words. The 82541ER controller
includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes efficient
bus usage. The 82541ER uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached
on chip. A large 64Kbyte on-chip packet buffer maintains superior performance as available PCI bandwidth
changes. In addition, using hardware acceleration, the controller offloads tasks from the host controller, such as
TCP/UDP/IP checksum calculations and TCP segmentation.

The pin out of the Ethernet connector J7 can be seen on Table A14.

® 82541ER (optional) integrates fourth generation gigabit MAC design with fully integrated, physical layer

Serial Ports

The Gator EPIC can be configured with up to six fixed RS-232 serial ports (COM1 RS-422/485 optional). COM1
and COM2 are standard, the others are optional.

The pin out of COM1 to COM 6 connectors can be seen on Table A9 to Table A13.

TIA/EIA-232

RS is the abbreviation for recommended standard. Usually, it is based on or is identical to other standards, e.g.,
EIA/TIA-232-F. TIA/EIA-232, previously known as RS-232 was developed in the 1960’s to interconnect layers of
the interface (ITU–T V.11), but also the pignut of the appropriate connectors (25-pin D-type or 9-pin DB9S) (ISO

2210) and the protocol (ISSUED-T V.24). The interface standard specifies also handshake and control lines in
addition to the 2 unidirectional receive data line (RD) and transmit data line (TD). The control lines data carrier
detect (DCD), data set ready (DSR), request to send (RTS), clear to send (CTS), data terminal ready (DTR), and the
ring indicator (RI) might be used, but do not necessarily have to be (for example, the PC-serial-mouse utilizes only

53

Gator EPIC – Installation Guide

RI, TD, RD and GND). Although the standard supports only low speed data rates and line length of approximately
20 m maximum, it is still widely used. This is due to its simplicity and low cost.

Electrical

TIA/EIA-232 has high signal amplitudes of ±(5 V to 15 V) at the driver output. The triggering of the receiver
depends on the sign of the input voltage: that is, it senses whether the input is above 3 V or less than –3 V. The line
length is limited by the allowable capacitive load of less than 2500 pF. This results in a line length of approximately
20 m. The maximum slope of the signal is limited to 30 V/ms. The intention here is to limit any reflections that can
occur to the rise-and fall-times of the signal. Therefore, transmission line theory does not need to be applied, so no
impedance matching and termination measures are necessary.

Do not connect termination resistor when operating in RS-232 mode.

Protocol

Different from other purely electrical-layer-standards, TIA/EIA-232 defines not only the physical layer of the
interface (ITU-T V.11), but also the pinout of the appropriate connectors (25-pin D-type or 9-pin DB9S) (ISO 2210)
and the protocol (ITU-T V.24). The interface standard specifies also handshake and control lines in addition to the 2
unidirectional receive data line (RD) and transmit data line (TD). The control lines might be used, but do not
necessarily have to be.

RS-232 is Single-Ended Point-to-point Transmission

Single-Ended, Point-to-Point

Single-ended transmission is performed on one signal line, and the logical state is interpreted with respect to ground.
For simple, low-speed interfaces, a common ground return path is sufficient; for more advanced interfaces featuring
higher speeds and heavier loads, a single return path for each signaling line (twisted pair cable) is recommended.
The figure below shows the electrical schematic diagram of a single-ended transmission system.

Advantages of Single-Ended Transmission

The advantages of single-ended transmission are simplicity and low cost of implementation. A single-ended system
requires only one line per signal. It is therefore ideal for cabling, and connector costs are more important than the
data transfer rate, e.g. PC, parallel printer port or serial communication with many handshaking lines, e.g. EIA-232.
Cabling costs can be kept to a minimum with short distance communication, depending on data throughput,
requiring no more than a low cost ribbon cable. For longer distances and/or noisy environments, shielding and
additional ground lines are essential. Twisted pair cables are recommended for line lengths of more than 1 meter.

54

Appendix C: Industrial Devices

TIA/EIA-422

TIA/EIA-422 (RS-422) allows a multi-drop interconnection of one driver, transmitting unidirectionally to up to 10
receivers. Although it is not capable of bidirectional transfer, it is still applicable and used for talker-audience
scenarios.

Electrical

TIA/EIA-422 (ITU-T V.11) is comparable to TIA/EIA-485. It is limited to unidirectional data traffic and is

terminated only at the line-end opposite to the driver. The maximum line length is 1200m, the maximum data

rate is determined by the signal rise- and fall-times at the receiver’s side (requirement: <10% of bit duration).
TIA/EIA-422 allows up to ten receivers (input impedance of 4 kΩ attached to one driver. The maximum load is
limited to 80 Ω. Although any TIA/EIA-485 transceiver can be used in a TIA/EIA-422 system, dedicated TIA/EIA­422 circuits are not feasible for TIA/EIA-485, due to short circuit current limitations. The TIA/EIA-422 standard
requires only short circuit limitation to 150 mA to ground, while TIA/EIA-485 additionally has to limit short circuit
currents to 250 mA from the bus pins to –7 V and 12 V to address malfunctions in combination with ground shifts.

RS-422 is terminated only at the line-end opposite to the driver even if there is only one receiver.

Protocol

Not applicable/none specified.

RS-422 is Differential and may be either Point-to-Point or Multi-Drop Connected

Differential, Point-to-Point

Differential, Multi-Drop

Differential Transmission

For balanced or differential transmission, a pair of signal lines is necessary for each channel. On one line, a true
signal is transmitted, while on the second one, the inverted signal is transmitted. The receiver detects voltage

55

Gator EPIC – Installation Guide

difference between the inputs and switches the output depending on which input line is more positive. As shown
below, there is additionally a ground return path.

Balanced interface circuits consist of a generator with differential outputs and a receiver with differential inputs.
Better noise performance stems from the fact that noise is coupled into both wires of the signal pair in much the
same way and is common to both signals. Due to the common mode rejection capability of a differential amplifier,
this noise will be rejected. Additionally, since the signal line emits the opposite signal like the adjacent signal return
line, the emissions cancel each other. This is true in any case for crosstalk from and to neighboring signal lines. It is
also true for noise from other sources as long as the common mode voltage does not go beyond the common mode
range of the receiver. Since ground noise is also common to both signals, the receiver rejects this noise as well. The
twisted pair cable used in these interfaces in combination with a correct line termination—to avoid line reflections—
allows very high data rates and a cable length of up to 1200 m.

Advantages of Differential Transmission

Differential data transmission schemes are less susceptible to common-mode noise than single-ended schemes.
Because this kind of transmission uses two wires with opposite current and voltage swings compared to only one
wire for single-ended, any external noise is coupled onto the two wires as a common mode voltage and is rejected by
the receivers. This two-wire approach with opposite current and voltage swings also radiates less electro-magnetic
interference (EMI) noise than single-ended signals due to the canceling of magnetic fields.

TIA/EIA-485

Historically, TIA/EIA-422 was on the market before TIA/EIA-485. Due to the lack of bi-directional capabilities, a
new standard adding this feature was created: TIA/EIA-485 . The standard (TIA/EIA-485-A or ISO/IEC 8284)
defines the electrical characteristics of the interconnection, including driver, line, and receiver. It allows data rates in
the range of 35 Mbps and above and line lengths of up to 1200 m. Of course both limits can not be reached at the
same time. Furthermore, recommendations are given regarding wiring and termination. The specification does not
give any advice on the connector or any protocol requirements.

Electrical

TIA/EIA-485 describes a half-duplex, differential transmission on cable lengths of up to 1200 m and at data rates of
typically up to 35 Mbps (requirement similar to TIA/EIA-422, but tr<30% of the bit duration, there are also faster
devices available, suited for higher rates under certain load-conditions). The standard allows a maximum of 32 unit
loads of 12 kΩ, equal to 32 standard nodes or even higher count with increased input impedance. The maximum
total load should not drop below 52 Ω. The common-mode voltage levels on the bus have to maintain between –7 V
and 12 V. The receivers have to be capable to detect a differential input signal as low as 200 mV.

56

Appendix C: Industrial Devices

RS-485 is terminated at both sides of the common bus, even if only two stations are connected to the
backbone.

Protocol

Not applicable/none specified; exceptions: SCSI systems and the DIN-Bus DIN66348.

RS-485 is Differential and Multi-Point Connected

Differential Transmission

Please, read the Differential Transmission explanation in the previous RS-422 section.

Termination Resistors

Follow instructions in the previous RS-422 and RS-485 sections. The termination resistors available are rated to
120Ω.

Ground Connections

All 422- and 485-compliant system configurations shown up to this point do not have incorporated signal-return
paths to ground. Obviously, having a solid ground connection so that both receivers and drivers can talk error free is
imperative. The figure below shows how to make this connection and recommends adding some resistance between
logic and chassis ground to avoid excess ground-loop currents. Logic ground does not have any resistance in its path
from the driver or receiver. A potential problem might exist, especially during transients, when a high-voltage
potential between the remote grounds could develop. Therefore, some resistance between them is recommended.

57

Gator EPIC – Installation Guide

User's Notes:

58

Appendix D: On-Board Video

Appendix On-Board Video Controller

The Gator EPIC has an On-board video controller. The On-board video controller is based on the Intel 82855GME
GMCH.

Graphics Features

The GMCH IGD provides a highly integrated graphics accelerator delivering high performance 2D, 3D, and video
capabilities. With its interfaces to UMA using a DVMT configuration, an analog display and a LVDS port, the
GMCH can provide a complete graphics solution.
The GMCH also provides 2D hardware acceleration for block transfers of data (BLTs). The BLT engine provides
the ability to copy a source block of data to a destination and perform raster operations (e.g., ROP1, ROP2, and
ROP3) on the data using a pattern, and/or another destination. Performing these common tasks in hardware reduces
CPU load, and thus improves performance.
High bandwidth access to data is provided through the system memory interface. The GMCH uses Tiling
architecture to increase system memory efficiency and thus maximize effective rendering bandwidth. The Intel
855GME GMCH improves 3D performance and quality with 3D Zone rendering technology. The Intel 855GME
GMCH also supports Video Mixer rendering, and Bi-Cubic filtering.

3D/2D Instruction Processing

The GMCH contains an extensive set of instructions that control various functions including 3D rendering, BLT
operations, display, MPEG decode acceleration, and overlay. The 3D instructions set 3D pipeline states and control
the processing functions. The 2D instructions provide an efficient method for invoking BLT operations.

3D Engine

The 3D engine of the GMCH has been designed with a deeply pipelined architecture, where performance is
maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the
same primitive. The GMCH supports the following:

• Perspective-corrected Texture mapping

• Multitexturing

• Embossed and Dot-Product Bump mapping

• Cubic Environment Maps

• Bilinear, Trilinear, and Anisotropic MIP map filtering

• Gouraud shading and Flat shading

• Alpha-blending

• Per-Vertex and per- pixel fog

• Z/W buffering

These features are independently controlled via a set of 3D instructions. The 3D pipeline subsystem performs the 3D
rendering acceleration. The main blocks of the pipeline are the Setup Engine, Scan Converter, Texture Pipeline, and
Raster Pipeline. A typical programming sequence would be to send instructions to set the state of the pipeline
followed by rendering instructions containing 3D primitive vertex data.

2D Engine

The GMCH provides an extensive set of 2D instructions and 2D HW acceleration for block transfers of data (BLTs).
The BLT engine provides the ability to copy a source block of data to a destination and
perform operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination. The
Stretch BLT engine is used to move source data to a destination that need not be the same size, with source
transparency. Performing these common tasks in hardware reduces CPU load, and thus improves performance.

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Display Features

The Intel 855GME GMCH has four display ports, one analog and three digital. With these interfaces, the GMCH
can provide support for a progressive scan analog monitor, a dedicated dual channel LVDS LCD panel, and two
DVO devices (not available in the Gator EPIC). Each port can transmit data according to one or more protocols. The
data that is sent out the display port is selected from one of the two possible sources, Pipe A or Pipe B.

GMCH Analog Display Port

Intel 855GME GMCH has an integrated 350-MHz, 24-bit RAMDAC that can directly drive a progressive scan
analog monitor pixel resolution up to 1600x1200 at 85-Hz refresh and up to 2048x1536 at 75-Hz refresh. The
Analog display port can be driven by Pipe A or Pipe B.

Analog Display Port Characteristics

The Analog display port provides an RGB signal output along with an HSYNC and VSYNC signal.
There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The
intended target device is for a CRT based monitor with a VGA connector.

Integrated RAMDAC

The display function contains a 350-MHz, integrated, 24-bit, RAM-based Digital-to-Analog Converter (RAMDAC)
that transforms up to 2048X1536 digital pixels at a maximum refresh rate of 75-Hz. Three, 8-bit DACs provide the
R, G, and B signals to the monitor.

DDC (Display Data Channel)

DDC is defined by VESA. It allows communication between the host system and display. Both configuration and
control information can be exchanged allowing plug-and-play systems to be realized.
Support for DDC 1 and 2 is implemented.

GMCH Integrated LVDS Port

The Intel 855GME GMCH have an integrated dual channel LFP Transmitter interface to support LVDS LCD panel
resolutions up to UXGA The display pipe provides panel up-scaling to fit a smaller source image onto a specific
native panel size, as well as provides panning and centering support. The LVDS port is only supported on Pipe B.
The LVDS port can only be driven by Pipe B, either independently or simultaneously with the Analog Display port.
Spread Spectrum Clocking is supported: center and down spread support of 0.5%, 1%, and 2.5% utilizing an
external SSC clock.

Dedicated LVDS Interface

The GMCH has a dedicated ANSI/TIA/EIA –644-1995 Specification compliant dual channel LFP LVDS interface
that can support TFT panel resolutions up to UXGA with a maximum pixel format of 18 bpp (with SSC supported
frequency range from 35-MHz to 112-MHz (single channel/dual channel).
The display pipe selected by the LVDS display port is programmed with the panel timing parameters that are
determined by installed panel specifications or read from an onboard EDID ROM. The programmed timing values
are then “locked” into the registers to prevent unwanted corruption of the values. From that point on, the display
modes are changed by selecting a different source size for that pipe, programming the VGA registers, or selecting a
source size and enabling the VGA. The timing signals will remain stable and active through mode changes. These
mode changes include VGA to VGA, VGA to HiRes, HiRes to VGA, and HiRes to HiRes.
The transmitter can operate in a variety of modes and supports several data formats. The serializer supports 6-bit or
8-bit color and single or dual channel operating modes. The display stream from the display pipe is sent to the
LVDS transmitter port at the dot clock frequency, which is determined by the panel timing requirements. The output
of LVDS is running at a fixed multiple of the dot clock frequency, which is determined by the mode of operation;
single or dual channel.

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Depending on configuration and mode, a single channel can take 18-bits of RGB pixel data plus 3 bits of timing
control (HSYNC/VSYNC/DE) and output them on three differential data pair outputs; or 24 bits of RGB plus 3 bits
of timing control output on four differential data pair outputs. A dual channel interface converts 36 bits or 48 bits of
color information plus the 3 bits of timing control and outputs it on six or eight sets of differential data outputs.
This display port is normally used in conjunction with the pipe functions of panel scaling and a 6-bit to 8-bit dither.
This display port is also used in conjunction with the panel power sequencing and additional associated functions.
When enabled, the LVDS constant current drivers consume significant power. Individual pairs or sets of pairs can be
selected to be powered down when not used. When disabled, individual or sets of pairs will enter a low power state.
When the port is disabled all pairs enters a low power mode. The panel power sequencing can be set to override the
selected power state of the drivers during power sequencing.

LVDS Interface Signals

LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical standard only
defining driver output characteristics and receiver input characteristics. There are two LVDS transmitter channels
(channel A and channel B) in the LVDS interface. Each channel consists of four data pairs and a clock pair. The
interface consists of a total of ten differential signal pairs of which eight are data and two are clocks. The phase
locked transmit clock is transmitted in parallel with the data being sent out over the data pairs and over the LVDS
clock pair.
Each channel supports transmit clock frequency ranges from 35 MHz to 112 MHz, which provides a throughput of
up to 784 Mbps on each data output and up to 112 MHz on the input. When using both channels, they each operate
at the same frequency each carrying a portion of the data. The maximum pixel rate is increased to 224 MHz but may
be limited to less than that due to restrictions elsewhere in the circuit.
The LVDS Port Enable bit enables or disables the entire LVDS interface. When the port is disabled, it will be in a
low power state. Once the port is enabled, individual driver pairs will be disabled based on the operating mode.
Disabled drivers can be powered down for reduced power consumption or optionally fixed to forced 0’s output.

LVDS Pair States

The LVDS pairs can be put into one of the following five states: powered down tri-state, powered down Zero Volts,
common mode, send zeros, or active. When in the active state, several data formats are supported. When in powered
down state, the circuit enters a low power state and drives out 0 V or tristates on both the output pins for the entire
channel. The common mode tri-state is both pins of the pair set to the common mode voltage. When in the send
zeros state, the circuit is powered up but sends only zero for the pixel color data regardless what the actual data is
with the clock lines and timing signals sending the normal clock and timing data.

Single Channel versus Dual Channel Mode

Both single channel and dual channel modes are available to allow interfacing to either single or dual channel panel
interfaces. This LVDS port can operate in single channel or dual channel mode. Dual channel mode uses twice the
number of LVDS pairs and transfers the pixel data at twice the rate of the single channel. In general, one channel
will be used for even pixels and the other for odd pixel data.
The first pixel of the line is determined by the display enable going active and that pixel will be sent out channel A.
All horizontal timings for active, sync, and blank will be limited to be on two pixel boundaries in the two channel
modes.

LVDS Channel Skew

When in dual channel mode, the two channels must meet the panel requirements with respect to the inter channel
skew.

SSC Support

The GMCH is designed to tolerate 0.5%, 1.0%, and 2.5% down/center spread at a modulation rate from 30-50 kHz
triangle. An external SSC clock synthesizer can be used to provide the 48/66-MHz reference clock into the GMCH
Pipe B PLL.

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Panel Power Sequencing

This section provides details for the power sequence timing relationship of the panel power, the backlight enable and
the LVDS data timing delivery. In order to meet the panel power timing specification requirements, two signals,
PANELVDDEN and PANELBKLTEN are provided to control the timing sequencing function of the panel and the
backlight power supplies.

Panel Power Sequence States

A defined power sequence is recommended when enabling the panel or disabling the panel. The set of timing
parameters can vary from panel to panel vendor, provided that they stay within a predefined range of values. The
panel VDD power, the backlight on/off state and the LVDS clock and data lines are all managed by an internal
power sequencer.
A requested power-up sequence is only allowed to begin after the power cycle delay time requirement is met.

Back Light Inverter Control

The GMCH offers integrated PWM for TFT panel Backlight Inverter control. Other methods of control are specified
below:

• SMBus-based Backlight Brightness Control

• GMBus-based Backlight Brightness Control

• PWM – based Backlight Brightness Control

• DBL(Display Brightness Link) –to- VDL (Video Data Link) Power Sequencing.

Concurrent and Simultaneous Display

The GMCH has two independent pipes, each with its own timing generator and dot clock, and thus is able to support
two displays concurrently. Windows 98* and Windows 2000* have enabled support for multi-monitor display.
There are two types of multi-monitor solutions: concurrent and simultaneous.
Concurrent displays different data on two screens whereas simultaneous displays the same information on both
displays. The GMCH also supports a combination of concurrent and simultaneous displays.

The pin out of the LVDS connector J4 can be seen on Table A27, the pin out of the LVDS Backlight connector J5
can be seen on Table A26 and the pin out of the VGA connector J3 can be seen on Table A18.

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Appendix D: On-Board Video

User's Notes:

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MN-GMEEP-01