Aopen AP5T FAQ

Appendix B

BIOS revision

(AP5T-1)

48.87901.011

Frequently Asked Question

Note: FAQ may be updated without notice. If
you cannot find the information that you need in
this appendix, visit our WWW home page,
(address: http://www.aopen.com.tw) and check
the FAQ area and other new information.

Q: How can I identify the mainboard BIOS version?

A: The AOpen mainboard BIOS version appears on the upper-left corner of

the POST (Power-On Self Test) screen. Normally, it starts with R and is
found in between the model name and the date. For example:

AP53/AX53 R3.80 Oct.22.1996

Q: How can I identify version of the mainboard?

A: The AOpen mainboard version appears as ppppp-x on the PCB, near the

PCI slot and is enclosed in a white bordered box. The ppppp is the project
code used by AOpen internally and -x is the version code. For example, for
AP5T with 95152 project code and -1 version code, the mainboard version
appears on the PCB as follows:

MB verison -1

95152-1
AP5T MB

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Frequently Asked Questions

Q: Why the AOpen mainboards (MB) do not have cache module

expansion slot?

A: Faster CPU speed requires more difficult and complex MB timing design.

Every trace and components delay must be taken into consideration. The
expansion cache slot design will cause 2 or 3ns delay in PBSRAM timing,
and the extended trace length to the cache module through the golden
finger will further delay the timing by 1 or 2ns. This may result in unreliable
system once the cache module and slot becomes worn. All AOpen MBs
support 512KB PBSRAM onboard. For better performance (around 3%
higher than 256KB), we strongly recommend you to use 512KB onboard.
Otherwise, reliable 256KB is better than unreliable 512KB with cache
module. AOpen is the first company to promote this concept since the
fourth quarter of 1995.

Q: What is MMX?

A: MMX is the new single-line multiple-instruction technology of the new Intel

Pentium PP/MT (P55C) CPU. A new Pentium Pro CPU (Klamath) with
MMX technology is also expected to be released soon. The MMX
instructions are specifically useful for multimedia applications (such as 3D
video, 3D sound, video conference). The performance can be improved if
applications use these instructions. All AOpen MBs have at least dual
power onboard to support PP/MT, it is not necessary to have special
chipset for MMX CPU.

Q: What is USB (Universal Serial Bus)?

A: USB is a new 4-pin serial peripheral bus that is capable of cascading

low/medium speed peripherals (less than 10Mbit/s) such as keyboard,
mouse, joystick, scanner, printer and modem/ISDN. With USB, the
traditional complex cables from back panel of your PC can be eliminated.

You need the USB driver to support USB device(s). AOpen MBs are all
USB ready, you may get latest BIOS from AOpen web site
(http://www.aopen.com.tw). Our latest BIOS includes the keyboard driver
(called Legacy mode), that simulates USB keyboard to act as AT or PS/2
keyboard and makes it possible to use USB keyboard if you don't have
driver in your OS. For other USB devices, you may get the drivers from
your device vendor or from OS (such as Win95). Be sure to turn off "USB
Legacy Support" in BIOS "Chipset Setup" if you have another driver in your
OS.

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Frequently Asked Question

Q: What is P1394?

A: P1394 (IEEE 1394) is another standard of high-speed serial peripheral

bus. Unlike low or medium speed USB, P1394 supports 50 to 1000Mbit/s
and can be used for video camera, disk and LAN. Since P1394 is still
under development, , there is no P1394 device currently available in the
PC market. Also, there is no chipset that can support P1394. Probably in
the near future, a card will be developed to support P1394 device.

Q: What is SMBus (System Management Bus, also called I2C bus)?

A: SMBus is a two-wire bus developed for component communication

(especially for semiconductor IC). It is most useful for notebook to detect
component status and replace hardware configuration pin (pull-high or pull­low). For example, disabling clock of DIMM that does not exist, or
detecting battery low condition. The data transfer rate of SMBus is only
100Kbit/s, it allows one host to communicate with CPU and many masters
and slaves to send/receive message. The SMBus may be used for
jumpless mainboard, the components which support SMbus are not ready
yet, we will keep eyes on it.

Q: What is FCC DoC (Declaration of Conformity)?

A: The DoC is new certification standard of FCC regulations. This new

standard allows DIY component (such as mainboard) to apply DoC label
separately without a shielding of housing. The rule to test mainboard for
DoC is to remove housing and test it with regulation 47 CFR 15.31. The
DoC test of mainboard is more difficult than traditional FCC test. If the
mainboard passes DoC test, that means it has very low EMI radiation and
you can use any kind of housing (even paper housing). Following is an
example of DoC label. Currently, AOpen AX65/AP57/AP5T/AX5T had
passed DoC test.

AP5T

Test To Comply
With FCC Standards

FOR HOME OR OFFICE USE

Q: What is PBSRAM (Pipelined Burst SRAM)?

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Frequently Asked Questions

A: For Pentium CPU, the Burst means reading four QWord (Quad-word, 4x16

= 64 bits) continuously with only the first address decoded by SRAM. The
PBSRAM will automatically send the remaining three QWord to CPU
according to predefined sequence. The normal address decoding time for
SRAM is 2 to 3 clocks. This makes the CPU data read timing of four
QWord to be at least 3-2-2-2 and a total of 9 clocks if traditional
asynchronous SRAM is used. However, with PBSRAM, there is no need to
decode address for rest three Qword. Therefore, data read timing can be
3-1-1-1, that is equivalent to 6 clocks and is faster than asynchronous
SRAM.

Q: What is EDO (Extended Data Output) memory?

A: The EDO DRAM technology of EDO is actually very similar to FPM (Fast

Page Mode). Unlike traditional FPM that tri-states the memory output data
to start the pre-charge activity, EDO DRAM holds the memory data valid
until the next memory access cycle, that is similar to pipeline effect and
reduces one clock state.

Q: What is SDRAM (Synchronous DRAM)?

A: The SDRAM is a new generation DRAM technology that allows DRAM to

use the same clock as the CPU host bus (EDO and FPM are asynchronous
and do not have clock signal). The idea is the same as "Burst" (refer to the
previous Q & A). It requires only one clock for the 2nd, 3rd, and 4th
QWord (for example, 5-1-1-1 compares with EDO 5-2-2-2). The SDRAM
comes in 64-bit 168-pin DIMM (Dual-in-line Memory Module) and operates
at 3.3V. Note that some old DIMMs are made by FPM/EDO and only
operate at 5V. Do not confuse them with SDRAM DIMM. AOpen is the first
company to support dual-SDRAM DIMMs onboard (AP5V), from Q1 1996.

Q: Can SDRAM DIMM work together with FPM/EDO SIMM?

A: The FPM/EDO operate at 5V while SDRAM operates at 3.3V. The current

MB design provides different power to DIMM and SIMM but connects the
data bus together. If you combine SIMM and DIMM, the system will still
work fine; however, only temporarily. After a few months, the SDRAM 3.3V
data input will be damaged by 5V FPM/EDO data output line. Therefore,
we strongly NOT recommend DIMM and SIMM combined together. There
is one exception, if your SDRAM supports 5V tolerance (such as TI or
Samsung), which accepts 5V signal at 3.3V operating power, you can
combine them.

Manufacturer Model Suggested

CAS Latency

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5V Tolerance

Frequently Asked Question

Time

Samsung KM416511220AT-G12 2 Yes
NEC D4S16162G5-A12-7JF 2 No
Hitachi HM5216805TT10 2 No
Fujitsu 81117822A-100FN 2 No
TI TMX626812DGE-12 2 Yes
TI TMS626812DGE-15 3 Yes
TI TMS626162DGE-15 3 Yes
TI TMS626162DGE-M67 3 Yes

Q: What is Bus Master IDE (DMA mode)?

A: The traditional PIO (Programmable I/O) IDE requires the CPU to involve in

all the activities of the IDE access including waiting for the mechanical
events. To reduce the workload of the CPU, the bus master IDE device
transfers data from/to memory without interrupting CPU, and releases CPU
to operate concurrently while data is transferring between memory and IDE
device. You need the bus master IDE driver and the bus master IDE HDD
to support bus master IDE mode. Note that it is different with master/slave
mode of the IDE device connection. For more details, refer to section 2.3
"Connectors".

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