DDR2 And DDR3 Power Solution Synchronous Buck Controller With 1.5A LDO
FeaturesGeneral Description
Buck Controller (VDDQ)
•High Input Voltages Range from 3V to 28V Input
Power
•Provide 1.8V (DDR2), 1.5V (DDR3) or Adjustable
Output Voltage from 0.75V to 5.5V
- ±1% Accuracy Over-Temperature
•Integrated MOSFET Drivers and Bootstrap Diode
•Excellent Line and Load Transient Responses
•PFM Mode for Increased Light Load Efficiency
•Constant-On-Time Controller Scheme
- Switching Frequency Compensation for PWM
Mode
- Adjustable Switching Frequency from 100kHz
to 550kHz in PWM Mode with DC Output Current
•Integrated MOSFET Drivers and Bootstrap Diode
•S3 and S5 Pins Control The Device in S0, S3, or
S4/S5 State
•Power Good Monitoring
•70% Under-Voltage Protection (UVP)
•125% Over-Voltage Protection (OVP)
•Adjustable Current-Limit Protection
- Using Sense Low-Side MOSFET R
±1.5A LDO Section (VTT)
DS(ON)
•Souring or Sinking Current up to 1.5A
• Fast Transient Response for Output Voltage
• Output Ceramic Capacitors Support at Least
10µF MLCC
•VTT and VTTREF Track at Half the VDDQSNS by
Internal Divider
•±20mV Accuracy for VTT and VTTREF
•Independent Over-Current-Limit (OCL)
The APW8813/A integrates a synchronous buck PWM
controller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It provides a complete
power supply for DDR2 and DDR3 memory system. It
offers the lowest total solution cost in system where space
is at a premium.
The APW8813/A provides excellent transient response
and accurate DC voltage output in either PFM or PWM
Mode. In Pulse Frequency Mode (PFM), the APW8813/A
provides very high efficiency over light to heavy loads with
loading-modulated switching frequencies. On TQFN4x424A package, the Forced PWM Mode works nearly at constant frequency for low-noise requirements.
The APW8813/A is equipped with accurate current-limit,
output under-voltage, and output over-voltage protections.
A Power-On-Reset function monitors the voltage on V
prevents wrong operation during power on.
The LDO is designed to provide a regulated voltage with
bi-directional output current for DDR-SDRAM termination.
The device integrates two power transistors to source or
sink current up to 1.5A. It also incorporates current-limit
and thermal shutdown protection.
The output voltage of LDO tracks the voltage at VTTREF
pin. An internal resistor divider is used to provide a half
voltage of VDDQ for VTTREF and VTT Voltage. The VTT
output voltage is only requiring 20µF of ceramic output
capacitance for stability and fast transient response. The
S3 and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.
The APW8813/A is available in 4mmx4mm 24-pin TQFN
package, and the APW8813A is available in 3mmx3mm
20-pin TQFN package.
•Thermal Shutdown Protection
•QFN-24 4mmx4mm Thin Package (TQFN4x4-24A)
for APW8813 and QFN-20 3mmx3mm Thin
Package (TQFN3x3-20) for APW8813A
•Lead Free and Green Devices Available
(RoHS Compliant)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Package Code
QB : TQFN4x4-24A QB : TQFN3x3-20
Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
XXXXX - Date Code
APW8813 QB :
APW8813
XXXXX
Assembly Material
Handling Code
Temperature Range
Package Code
APW
APW8813A QB :XXXXX - Date Code
8813A
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings(Note 1, 2)
Symbol
VCC VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V
V
PVCC Supply Voltage (PVCC to GND) -0.3 ~ 7 V
PVCC
V
BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 7 V
BOOT
V
BOOT-GND
BOOT Supply Voltage (BOOT to GND) -0.3 ~ 35 V
UGATE Voltage (UGATE to PHASE)
<400ns Pulse Width
>400ns Pulse Width
LGATE Voltage (LGATE to GND)
<400ns Pulse Width
>400ns Pulse Width
PHASE Voltage (PHASE to GND)
<400ns Pulse Width
>400ns Pulse Width
PGND, VTTGND and CS_GND to GND Voltage -0.3 ~ 0.3 V
All Other Pins (CS, MODE, S3, S5, VTTSNS, VDDQSNS, LDOIN, FCCM,
VDDQSET, PGOOD, VTT, VTTREF GND)
TJ Maximum Junction Temperature 150
T
Storage Temperature -65 ~ 150
STG
T
Maximum Soldering Temperature, 10 Seconds 260
SDR
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Note 2: The device is ESD sensitive. Handling precautions are recommended.
Parameter Rating Unit
-5 ~ V
-0.3 ~ V
BOOT
BOOT
+0.3
+0.3
V
-5 ~ PVCC+0.3
V
-0.3 ~ PVCC+0.3
-5 ~ 35
V
-0.3 ~ 28
-0.3 ~ 7 V
o
C
o
C
o
C
Copyright ANPEC Electronics C orp.
www.anpec.com.tw3
Rev. A.6 - Sep., 2012
APW8813/A
Thermal Resistance
- Junction to Ambient
1.8V)/
Thermal Characteristics (Note 3)
Symbol
θ
JA
Thermal Resistance - Junction to Case
θ
JC
Note 3: θJA and θJC are measured with the component mounted on a high effective the thermal conductivity test board in free air. The
Parameter Typical Value Unit
TQFN4x4-24A
TQFN3x3-20
52
68
°C/W
TQFN4x4-24A
TQFN3x3-20
7
°C/W
8
exposed pad of package is soldered directly on the PCB.
Recommended Operating Conditions(Note 4)
Symbol
VCC, V
V
V
C
VCC
C
C
VTTREF
Note 4: Refer to the typical application circuit.
VCC and PVCC Supply Voltage 4.5 ~ 5.5 V
PVCC
VIN
Converter Input Voltage 3 ~ 28 V
Converter Output Voltage
VDDQ
LDO Output Voltage 0.375 ~ 2.75 V
VTT
I
Converter Output Current 0 ~ 15 A
OUT
I
LDO Output Current -1.5 ~ +1.5 A
VTT
, C
VCC and PVCC Capacitance 1~
PVCC
VTT Output Capacitance 10~100
VTT
VTTREF Output Capacitance 0.01~0.1
TA
Ambient Temperature -40 ~ 85
TJ
Junction Temperature -40 ~ 125
Parameter Range Unit
0.75 ~5.5V/ DDR2 (
DDR3 (1.5V)
V
µF
µF
µF
o
C
o
C
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V
VCC=VPVCC=VBOOT
otherwise s pecified. Typical values are at TA=25°C.
Symbol
Parameter Test Conditions
SUPPLY CURRENT
I
PVCCSDN
I
VCC
I
VCCSTB
I
VCCSDN
I
LDOIN
I
LDOINSTB
I
LDOINSDN
PVCC Shutdown Current TA =25oC, VS3 = V
VCC Supply Current
VCC Standby Current
TA = 25oC, VS3 = VS5 = 5V, no load,
PVCC Plus VCC Current, No Switching
TA = 25oC, VS3 = 0V, VS5 = 5V, no load,
PVCC Plus VCC Current, No Switching
VCC Shutdown Current TA =25oC, VS3 = V
= 0V, no load - 0.1 1
S5
= 0V, no load - 0.1 1
S5
LDOIN Supply Current TA = 25oC, VS3 = VS5 = 5V, no load - - 40
LDOIN Standby Current TA = 25oC, VS3 = 0V, VS5 = 5V, no load - 0.1 10
LDOIN Shutdown Current TA = 25oC, VS3 = VS5 = 0V, no load - 0.1 1
UGATE Pull-Up Resistance BOOT-UGATE = 0.5V - 5 7
UGATE Sink Resistance UGATE-PHASE = 0.5V - 1 2.5
LGATE Pull-Up Resistance PVCC-LGATE = 0.5V - 5 7
LGATE Sink Resistance LGATE-PGND = 0.5V - 1 2.5
UGATE to LGATE Dead Time UGATE falling to LGATE rising, no load - 40 - ns
LGATE to UGATE Dead Time LGATE falling to UGATE rising, no load - 40 - ns
BOOTSTRAP DIODE
Forward Voltage V
Reverse Leakage
- V
PVCC
V
= 30V, V
BOOT
TA = 25oC
, IF = 10mA, TA = 25oC - 0.5 0.8 V
BOOT
PHASE
= 25V, V
PVCC
= 5V,
- - 0.5
µA
LOGIC THRESHOLD
VIH S3, S5 High Threshold Voltage S3, S5 Rising 1.6 - - V
VIL S3, S5 Low Threshold Voltage S3, S5 Falling - - 0.3 V
S5 to S3 Debounce Time S5 from L to H, VDDQ, VREF are on - 90 S3 to S0 Debounce Time S3 from L to H, VTT is on - 10 -
I
Logic Input Leakage Current VS3 = VS5 = V
ILEAK
V
FCCMTHR
V
FCCMTHF
V
THMODE
FCCM High Threshold (Only for
APW8813)
FCCM Low Threshold (Only for
APW8813)
MODE Threshold (Only for
APW8813)
VDDQSET Threshold
In Automatic PFM/PWM Mode 4.7 - - V
In Force PWM Mode - - 0.1 V
No Discharge 4.7 - Non-tracking Discharge - - 0.1
V
= 1.5V 0.08 0.15 0.4
VDDQ
V
= 1.8V 3.5 4 4.5
VDDQ
= 5V, TA = 25oC -1 - 4.7
MODE
µs
µs
µA
THERMAL SHUTDOWN
TSD Thermal Shutdown Temperature TJ Rising - 160 -
Thermal Shutdown Hysteresis - 25 -
o
oC
Ω
Ω
Ω
Ω
V
V
C
Copyright ANPEC Electronics C orp.
www.anpec.com.tw7
Rev. A.6 - Sep., 2012
APW8813/A
this pin connects to VDDQ, it is tracking discharge state. When this pin connects to GND, it is
Also it is current sense comparator positive input terminal and the ground
as
Pin Description
PIN
APW8813 APW8813A NAME
1 1 VTTGND Power ground output for the VTT LDO.
2 2 VTTSNS
3 3 GND
4 - MODE
5 4 VTTREF VTTREF buffered reference output.
6 - FCCM
7 - NC No Connection.
8 5 VDDQSNS
9 6 VDDQSET VDDQ output voltage setting pin.
10 7 S3 S3 signal input.
11 8 S5 S5 signal input.
12 9 TON
13 10 PGOOD
14 11 VCC
15 12 PVCC 5V power supply voltage input pin for low-side MOSFET gate driver on TQFN-24 package.
16 13 CS
17 - CS_GND Current sense comparator positive input terminal and the ground for power good circuit.
18 14 PGND
19 15 LGATE
20 16 PHASE
21 17 UGATE
22 18 BOOT
23 19 LDOIN Supply voltage input for the VTT LDO.
24 20 VTT Power output for the VTT LDO .
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output
capacitor.
Signal ground for the PWM controller and VTT LDO. Connect to minus terminal of the VTT
LDO output capacitor.
Discharge mode setting pin. When this pin connects to VCC, it is no discharge state. When
non-tracking discharge state.
Selection pin for PWM controller to operate in either forced PWM or automatic PWM/PFM
mode. Force PWM mode is enable when FCCM pin is pulled below the falling threshold
voltage V
threshold voltage V
VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge
current sinking terminal for VDDQ non-tracking discharge. Output voltage feedback input for
VDDQ output if VDDQSET pin is connected to VCC or GND.
This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor R
pin to PHASE VIN terminal.
Power-good output pin. PGOOD is an open drain output used to Indicate the status of the
output voltage. When VDDQ output voltage is within the target range, it is in high state.
Filtered 5V power supply input for internal control circuitry. Connect R-C network from PVCC
to VCC.
Over-current trip voltage setting input for R
through the voltage setting resistor.
Power ground of the LGATE low-side MOSFET driver. Connect the pin to the Source of the
low-side MOSFET.
of power good circuit on SSOP-20 package.
Output of the low-side MOSFET driver for PWM. Connect this pin to Gate of the low-side
MOSFET. Swings from PGND to VCC.
Junction point of the high-side MOSFET Source, output filter inductor and the low-side
MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves
the lower supply rail for the UGATE high-side gate driver.
Output of the high-side MOSFET driver for PWM. Connect this pin to Gate of the high-side
MOSFET.
Supply Input for the UGATE Gate Driver and an internal level-shift circuit. Connect to an
external capacitor and diode to create a boosted voltage suitable to drive a logic-level
N-channel MOSFET.
, and force PWM is disabled when the FCCM pin is pulled above the rising