Low Power, High Speed
JFET Operational Amplifiers
OP282/OP482
Rev. I Document Feedback
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1
2
3
4
5
6
7
8
OUT
A
–IN A
+IN A
V–
OP-482
V+
OUT B
–IN B
+IN B
OP282
00301-001
00301-002
OUT
A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
OP282
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP482
– +
+ –
– +
+ –
00301-003
1
2
3
4
5
6
7
14
13
12
1
1
10
9
8
OUT
A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP482
00301-004
TOP VIEW (BALL SIDE DOWN)
Not to Scale
00301-048
BALL A1 CORNER
OUT A
+IN D
V–
+IN C
OUT C
OUT D
–IN A
V+
–IN B
OUT B
–IN D
+IN A
+IN B
–IN C
A
B
C
D
E
F
1
2
3
G
H
J
Data Sheet
FEATURES
High slew rate: 9 V/µs
Wide bandwidth: 4 MHz
Low supply current: 250 µA/amplifier maximum
Low offset voltage: 3 mV maximum
Low bias current: 100 pA maximum
Fast settling time
Common-mode range includes V+
Unity-gain stable
14-ball wafer level chip scale for quad
Dual/Quad,
PIN CONNECTIONS
Figure 1. 8-Lead, Narrow-Body SOIC (S-Suffix) [R-8]
APPLICATIONS
Active filters
Fast amplifiers
Integrators
Supply current monitoring
GENERAL DESCRIPTION
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. The slew
rate is typically 9 V/µs with a supply current of less than 250 µA
per amplifier. These unity-gain stable amplifiers have a typical
gain bandwidth of 4 MHz.
The JFET input stage of the OP282/OP482 ensures that the bias
current is typically a few picoamps and is less than 500 pA over
the full temperature range. The offset voltage is less than 3 mV
for the dual amplifier and less than 4 mV for the quad amplifier.
With a wide output swing (within 1.5 V of each supply), low
power consumption, and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power-restricted applications. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for highside signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. The OP282 is available in the standard
8-lead, narrow SOIC and MSOP packages. The OP482 is
available in the PDIP and narrow SOIC packages, as well as
a 14-ball WLCSP.
Figure 2. 8-Lead MSOP [RM-8]
Figure 3. 14-Lead PDIP (P-Suffix) [N-14]
Figure 4. 14-Lead, Narrow-Body SOIC (S-Suffix) [R-14]
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 5. 14-Ball WLCSP [CB-14-2]
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1991–2013 Analog Devices, Inc. All rights reserved.
OP282/OP482 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Connections ............................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
REVISION HISTORY
9/13—Rev. H to Rev. I
Changes to Figure 5 .......................................................................... 1
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 16
9/10—Rev. G to Rev. H
Added WLCSP .................................................................... Univers al
Changes to Features Section............................................................ 1
Changes to General Description Section ...................................... 1
Added Figure 5; Renumbered Sequentially .................................. 1
Changes to Large-Signal Voltage Gain Parameter, Table 1 ......... 3
Changes to Table 2, Thermal Resistance Section, and Ta b le 3 ... 4
Change to Figure 30 ......................................................................... 9
Added Figure 53 .............................................................................. 16
Changes to Ordering Guide .......................................................... 16
7/08—Rev. F t o R e v. G
Changes to Phase Inversion Section ............................................ 12
Deleted Figure 45 ............................................................................ 12
Added Figure 45 and Figure 46..................................................... 12
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 16
10/04—Rev. E to Rev. F
Deleted 8-Lead PDIP ......................................................... Universal
Added 8-Lead MSOP ......................................................... Universal
Changes to Format and Layout ......................................... Universal
Changes to Features .......................................................................... 1
Changes to Pin Configurations ....................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications ................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 4
Changes to Table 3 ............................................................................ 4
ESD Caution...................................................................................4
Typical Performance Characteristics ..............................................5
Applications Information .............................................................. 12
High-Side Signal Conditioning ................................................ 12
Phase Inversion ........................................................................... 12
Active Filters ............................................................................... 12
Programmable State Variable Filter ......................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 16
Added Figure 5 through Figure 20; Renumbered
Successive Figures .............................................................................. 5
Updated Figure 21 and Figure 22 .................................................... 7
Updated Figure 23 and Figure 27 .................................................... 8
Updated Figure 29 ............................................................................. 9
Updated Figure 35 and Figure 36 ................................................. 10
Updated Figure 43 .......................................................................... 11
Changes to Applications Information ......................................... 12
Changes to Figure 44 ...................................................................... 12
Deleted OP282/OP482 Spice Macro Model Section .................... 9
Deleted Figure 4 ................................................................................. 9
Deleted OP282 Spice Marco Model ............................................. 10
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
10/02—Rev. D t o R e v. E
Edits to 8-Lead Epoxy DIP (P-Suffix) Pin ...................................... 1
Edits to Ordering Guide ................................................................... 3
Edits to Outline Dimensions ......................................................... 11
9/02—Rev. C to R e v. D
Edits to 14-Lead SOIC (S-Suffix) Pin ............................................. 1
Replaced 8-Lead SOIC (S-Suffix) ................................................. 11
4/02—Rev. B t o R e v. C
Wafer Test Limits Deleted ................................................................ 2
Edits to Absolute Maximum Ratings .............................................. 3
Dice Characteristics Deleted ............................................................ 3
Edits to Ordering Guide ................................................................... 3
Edits to Figure 1 ................................................................................. 7
Edits to Figure 3 ................................................................................. 8
20-Position Chip Carrier (RC Suffix) Deleted ........................... 11
Rev. I | Page 2 of 16
Data Sheet OP282/OP482
OP482
0.2 4 mV
Bias Current Drift
ΔIB/ΔT
8 pA/°C
Settling Time
tS
To 0.01%
1.6 µs
NOISE PERFORMANCE
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VS = ±15.0 V, TA = 25°C, unless otherwise noted; applies to both A and G grades.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS OP282 0.2 3 mV
OP282, −40°C ≤ TA ≤ +85°C 4.5 mV
OP482, −40°C ≤ TA ≤ +85°C 6 mV
Input Bias Current IB VCM = 0 V 3 100 pA
VCM = 0 V1 500 pA
Input Offset Current IOS VCM = 0 V 1 50 pA
VCM = 0 V1 250 pA
Input Voltage Range −11 +15 V
Common-Mode Rejection Ratio CMRR −11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C 70 90 dB
Large-Signal Voltage Gain AVO RL = 10 kΩ, VO = ±13.5 V 20 V/mV
RL = 10 kΩ, −40°C ≤ TA ≤ +85°C 15 V/mV
Offset Voltage Drift ΔVOS/ΔT 10 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ 13.5 13.9 V
Output Voltage Low VOL RL = 10 kΩ −13.9 −13.5 V
Short-Circuit Limit ISC Source 3 10 mA
Sink −12 −8 mA
Open-Loop Output Impedance Z
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V, −40°C ≤ TA ≤ +85°C 25 316 µV/V
Supply Current/Amplifier ISY VO = 0 V, −40°C ≤ TA ≤ 85°C 210 250 µA
Supply Voltage Range VS ±4.5 ±18 V
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 7 9 V/µs
Full-Power Bandwidth BWP 1% distortion 125 kHz
Gain Bandwidth Product GBP 4 MHz
Phase Margin ØM 55 Degrees
Voltage Noise en p-p 0.1 Hz to 10 Hz 1.3 µV p-p
Voltage Noise Density en f = 1 kHz 36 nV/√Hz
Current Noise Density in 0.01 pA/√Hz
1
The input bias and offset currents are characterized at TA = TJ = 85°C. Bias and offset currents are guaranteed but not tested at −40°C.
f = 1 MHz 200 Ω
OUT
Rev. I | Page 3 of 16
OP282/OP482 Data Sheet
Input Voltage
±18 V
Lead Temperature (Soldering 60 sec)
300°C
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Differential Input Voltage1 36 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
1
For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device in
socket for PDIP. θ
is specified for a device soldered in the circuit
JA
board for SOIC_N, MSOP, and WLCSP packages. This was
measured using a standard 4-layer board.
Table 3.
Package Type θJA θJC Unit
8-Lead MSOP [RM] 142 45 °C/W
8-Lead SOIC_N (S-Suffix) [R] 120 45 °C/W
14-Lead PDIP (P-Suffix) [N] 83 39 °C/W
14-Lead SOIC_N (S-Suffix) [R] 112 35 °C/W
14-Ball WLCSP [CB]
1
Simulated thermal numbers per JESD51-9.
2
Junction-to-board thermal resistance.
1, 2
70 16 °C/W
ESD CAUTION
Rev. I | Page 4 of 16
Data Sheet OP282/OP482
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
1k
–40
–20
60
80
10k 1M
10M
00301-005
100k
20
40
0
V
S
= ±15V
T
A
= 25
°
C
PHASE (Degrees)
–45
135
45
90
0
–90
180
TEMPERATURE (°C)
OPEN-LOOP GAIN (V/mV)
–75
0
5
35
45
–25 100 125
00301-006
25
15
25
10
VS = ±15V
R
L
= 10kΩ
20
30
40
75500–50
LOAD CAPACITANCE (pF)
OVERSHOOT (%)
0
0
10
70
80
200 400 500
00301-007
30
50
20
40
60
300100
VS = ±15V
RL = 2kΩ
VIN = 100mV p-p
A
VCL
= 1
TA = 25°C
+OS
–OS
FREQUENC
Y (Hz)
CLOSED-LOOP
GAIN (dB)
1k
–30
–20
60
70
10k
1M 10M
00301-008
100k
20
40
0
VS = ±15V
TA = 25°C
–10
50
10
30
A
VCL
= 1
00
A
VCL
= 1
0
A
VCL
= 1
TEMPER
ATURE (°C)
SLEW RATE (V/µs)
–75
0
5
30
–25 100 125
00301-009
25
15
25
10
VS = ±15V
RL = 10kΩ
CL = 50pF
20
75500–50
–SR
+SR
TEMPERATURE (°C)
INPUT BIAS CURRE NT (pA)
–75
0.1
1000
–25 100 125
00301-010
25
1
100
10
75500–50
VS = ±15V
VCM = 0V
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. OP282 Open-Loop Gain and Phase vs. Frequency
Figure 7. OP282 Open-Loop Gain vs. Temperature
Figure 9. OP282 Closed-Loop Gain vs. Frequency
Figure 10. OP282 Slew Rate vs. Temperature
Figure 8. OP282 Small-Signal Overshoot vs. Load Capacitance
Figure 11. OP282 Input Bias Current vs. Temperature
Rev. I | Page 5 of 16
OP282/OP482 Data Sheet
FREQUENC
Y (Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
10
1
1000
100
10k
00301-011
1k
100
10
V
S
= ±15V
T
A
= 25°
C
COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRE NT (pA)
–15
0.1
1000
10 15
00301-012
–5
1
100
10
50–10
VS = ±15V
T
A
= 25°C
SUPPLY VOLTAGE (V)
SUPPL
Y CURRENT (µA)
0
450
480
±20
00301-013
±10
455
465
460
±15±5
TA = 25°C
470
475
SUPPL
Y
VOLT
AGE (V)
OUTPUT VOLT
AGE SWING (V)
0
–20
20
±20
00301-014
±10
–15
–5
–10
±15±5
TA = 25°C
R
L
= 10kΩ
0
15
V
OH
V
OL
5
10
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
1k
0.1
100
1000
10k 1M100
00301-015
100k
1
10
VS = ±15V
T
A
= 25°C
A
VCL
= 100
A
VCL
= 10
A
VCL
= 1
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
–50
450
480
125
00301-016
25
455
750
460
475
465
470
–25 50 100
Figure 12. OP282 Voltage Noise Density vs. Frequency
Figure 13. OP282 Input Bias Current vs. Common-Mode Voltage
Figure 15. OP282 Output Voltage Swing vs. Supply Voltage
Figure 16. OP282 Closed-Loop Output Impedance vs. Frequency
Figure 14. OP282 Supply Current vs. Supply Voltage
Figure 17. OP282 Supply Current vs. Temperature
Rev. I | Page 6 of 16
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