Analog Devices ee-63 Application Notes

Engineer To Engineer Note EE-63

Technical Notes on using Analog Devices’ DSP components and development tools

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Considerations for FLASH PROMS
with Timing Requirements

By H.D.

_______________________________________

Question:

I need to know the minimum time between the
rising edge of /RESET and the falling edge of /BMS
when EBOOT is high and LBOOT is low. This
parameter is important since flash PROMS also
have a /RESET input and a minimum timing
requirement between the rising edge of /RESET and
falling edge of /CS and /OE. I may need to
implement an early /RESET for the flash PROM,
but until I know how soon the SHARC asserts
/BMS, I don't know how much earlier the PROM
needs to be reset.

Answer:

Attached is a waveform for the 21065L from a
digital scope that should help make this clear.

The following applies only to the 21060/60L,
21062/62L and 21061/61L:

If the first cycle that RESET is deasserted (goes
high) is cycle #1, then BMS will be asserted (go
LOW) in cycle #6.

The following applies only to the 21065L:

If the first cycle that RESET is deasserted (goes
high) is cycle #1, then BMS will be asserted (go
LOW) in cycle #4.

Note: A cycle is defined as a CLKIN cycle. ie: if
CLKIN is 30MHz, a cycle is 33.3ns in length.

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