Analog Devices ee-60 Application Notes

Engineer To Engineer Note EE-60

Technical Notes on using Analog Devices’ DSP components and development tools

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Simulating an RS-232 UART using the Synchronous Serial Ports

on the ADSP-21xx Family DSPs

Last Modified : 4/21/1999
Submitted by : Dan L & Greg G.

Introduction

It is possible to use the synchronous serial ports on the ADSP-21xx digital signal processors to perform bi­directional RS-232 communications.

An RS-232 port has two data signals (data transmit and data receive), and a host of hand-shaking signals
(DTR,DSR,CTS,RTS). There is, however, no clock signal and no framing signal which makes it difficult to
connect it to ports which require a clock and frame sync. This application note will present a method which
allows the synchronous serial ports to communicate in such a manner. To fully understand the content of this
document, it is recommended that the reader review Chapter 5, Serial Ports of the ADSP-21xx Family User’s
Manual .

An Overview of RS-232 Communications

In a typical RS-232 interface, data is transmitted at a predetermined bit rate – this is commonly referred to as
the BAUD rate (bits per second). Since there is no clock, both devices need to know this information before
data can be effectively communicated. There are also framing and parity bits included in each data word.
These bits are commonly referred to as start-bits, stop-bits and parity-bits. RS-232 data can be between 5
and 8-bits and is always sent LSB first.

The start and stop bits occur at the beginning and end of the data transmission respectively.

A parity bit can be included in the transmission and there are 5 parity options in the RS-232 standard : even,
odd, mark, space or none. If even parity is used, then the last data bit transmitted will be a logical1 if the data
transmitted had an odd amount of ‘1’ bits. If odd parity is used, then the last data bit transmitted will be a
logical 1 if the data transmitted had an even amount of ‘1’ bits. If mark parity is used, then the last transmitted
data bit will always be a logical 1. If space parity is used, then the last transmitted data bit will always be a
logical 0. If no parity is used, then there is no parity bit transmitted.

There are 3 options for the stop-bit. These are 1, 1½ and 2.

a

So, for the sake of example, let’s examine what the transmission of the bit pattern ‘01010101’ over the RS-232
port with a typical RS-232 set-up with 8 data bits, no parity, and one stop-bit. Here, we would see

LSB ( 1 0 1 0 1 0 1 0 1 0) MSB

Or

(start-bit)(8 data bits)(stop bit)

Overview of DSP Interface

The diagram below shows the basic interface between the DSP and the RS-232 port. This diagram does not
include level-shifting devices (RS-232 uses 9 Volt signals) nor does it make use of any handshaking signals
(DSR, DTR, RTS, CTS).

SCLK

DR

DT

RFS

DT

DR

TFS

ADSP-

RS-232 Device

The serial ports require a slightly different configuration for transmitting and receiving data, therefore, it will be
impossible to transmit and receive data at the same time which is common amongst full-duplex serial port
communications systems. This problem can be overcome by using a combination of the handshaking signals to
ensure that data is not being sent to the DSP while it transmits. For example, we could de-assert the DSR (data
send ready) signal on the RS-232 port thereby instructing the device not to send and data while we are
transmitting data.

Data Reception

For data reception, we will setup the serial port of the DSP to generate an internal clock, require external frame
syncs.

As shown in the diagram above, the clock signal does not connect to anything. We are using the clock internally
so that we can sample the incoming data on the RS-232 DR line at a multiple of the bit rate it is being sent at.
We are sampling each bit more than once to ensure correct data. Remember, we only know the rate that the
data is coming in but have no information regarding the phase relation of the data to our clock. If we over­sample the data with the serial clock, we’ll always be sure that at least 2 of the 3 bits we sample for each sent
bit is accurate. So, if the RS-232 device we are communicating with is transmitting data at 9600 BAUD (9600
bits/second), we want to sample the data at 3x9600 bits/second, or 28,000 bits/second. The diagram on the
next page helps to illustrate this concept.

As shown in the diagram above, the DT signal from the RS-232 port connects to both the DR and the RFS
signals on the DSP. This is because we will be using the start-bit of the RS-232 transmission as the RFS signal.

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Remember, the DSP only pays attention to the RFS signal while its waiting for a new word and when operating

bit-pattern

Word 0 –

Word 1 –

3. State = 1

received bits and store

in framed mode. While the word is being received, the RFS signal is not polled.

We end up sampling each bit 3 times, plus 2 samples for the start-bit (the 1st bit of the start bit is interpreted as
the RFS, not data) plus another 3 samples for the stop bit. So, we need to capture 29 bits of data. The serial
ports on the ADSP-21xx family can only read in 16-bit words through the serial ports so we are going to break
it up over two words. To achieve this, we will switch the serial port into unframed mode after the first word
(word 0) is received and then set it back to framed mode after the second word (word 1) has been received.
This, in effect, will allow us to receive one contiguous block of bits from the serial port.

SCLK

(internal)

DR & RFS

(from RS-232)

Received

Start-bit

1 1 0 0 0 0 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 1

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5

< framed > < unframed

RFS is sampled by the DSP
on this edge. It will then be
ignored until the current
frame has been received.

Figure 2 : Example RS-232 word reception using the ADSP-21xx serial ports.

Below is a simple state-diagram to help illustrate this process…

SPORT Receive Interrupt

1. Set serial port to unframed

State 0

DSP waiting for

next SPORTx

receive

interrupt

mode

2. Store word 0

Bit 6

State 1

DSP waiting for

next SPORTx

receive

interrupt

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SPORT in framed

SPORT Receive Interrupt

1. set serial port to framed

mode

2. store word 1

3. State = 0

4. Extract 8-bit data from 29

SPORT in framed

Figure 3 : Receive State Diagram

Technical Notes on using Analog Devices’ DSP components and development tools

Data Transmission

The data transmit side of this interface is far simpler than the receive side. Again, we are using the same
hardware configuration but on transmit side, we have DT from the DSP connected to DR of the RS-232
device.

We will set up the serial port for internal clock, but also internal frame sync. When transmitting, the clock will
be set at the actual BAUD rate instead of a higher multiple. We will also need to manually insert start, stop and
parity bits in as well. So, if we want to transmit the following bit pattern:

b#01010101

We would need to use the shifter to add the start and stop bits. What we end up with is:

B#1010101010

The start and stop bits here are underlined and we are using no parity.

Code Examples

The following code example was written for an ADSP-218x part but can be easily modified to support non-8x
parts like the ADSP-2101. This code performs RS-232 reads and writes and also calculates and generates
parity information.

A soft version of this code can be found on our ftp site at:

ftp.analog.com/pub/dsp/app_note/UART

.MODULE/RAM/ABS=0x00 UART_21xx;

{ software uart state machine definitions }

#define UartTxStateInactive 0
#define UartTxStateWord1 1
#define UartTxStateWord2 2
#define UartTxStateWord3 3
#define UartTxStateError 4

#define UartRxStateWord1 0
#define UartRxStateWord2 1
#define UartRxStateError 2

#define TxLowerLimit 0x30
#define TxUpperLimit 0x7f

{ serial port control register stuff }

#define InvertReceiveFrameSync 6
#define InternalTransmitFrameSync 9
#define TransmitFrameAlternate 10

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Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com