ANALOG DEVICES EE-349 Service Manual

Engineer-to-Engineer Note EE-349

Technical notes on using Analog Devices DSPs, processors and development tools

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ADSP-2146x Board Design Guidelines for DDR2 Memory

Contributed by Ramdas Chary Rev 2 – September 29, 2010

Introduction

Designing DSP-based systems with DDR2
(Double Data Rate 2) SDRAM memory devices
is simpler than designing GP-based systems
because the memory devices are expected to be
board-mounted and are no t assumed to be DIMM
module interfaces.

The ADSP-2146x SHARC® processors family
supports a 16-bit DDR2 interface operating at a
maximum frequency of half the core clock. Thus,
the ADSP-2146x maximum core speed of
450 MHz translates into 225 MHz (clock) and
450 MHz (data) for the DDR2 controller.

Signal Grouping and Naming Conventions

The AD SP-2146x SHARC processors have been
designed to interface with DDR2 memories
operating at a maximum speed of 533 Mbits/sec.
This document provides suggestions for PCB
designers t o c o nside r w hile la ying out high-speed
DDR2 signals.

Table 1 shows the signal names and group

descriptions for all associated DDR2 signals. It
also shows board-level layout guidelines for
signals within a particular group, as well as
signals between different signal groups.

Given the above information, the following
sections provide the guidelines for termination,
layout, placement, and routing of DDR2 signals

Spacing is listed as center-to-center distance in
units of trace width W. In other words, 3W
spacing is 2W trace separation.

for ADSP-2146x based designs. Two separate
and operational hardware platforms have been
developed:

Skew or trace length matching should be done
within each group. Match all group A signals,
match all group B signals, a nd match all group C

 The ADSP-2146x bring-up board (BUB),

signals.

which is an Analog Devices-inte rna l plat for m
designed and developed for early silicon
testing and debugging.

 The ADSP-21469 EZ-Board™ evaluation

board, which is a general reference design for
developers.

The majority of the guidelines provided in this
document apply to all DDR2 customer designs.
Some guidelines, however, refer specifically to
the platform on which those guidelines were
implemented.

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