Analog Devices ee-34 Application Notes

Engineer To Engineer Note EE-34

T

Notes on using Analog Devices’ DSP, audio, & video components from the Computer Products Division

Phone: (800) ANALOG-D or [phone], FAX: [phone], EMAIL: [e-mail]

Understanding 21xx/218x
EZ-ICE Theory of Operation To
Aid In Designing An EZ-ICE
Compatible Target

Last Modified: 4/14/98

Overview

This EE Note will give some insight into how an ADSP­21xx or ADSP-218x Emulator DSP is powered up when
connected to an ADDS-21xx/ADDS-218x EZ-ICE. This
document can be used as a debugging tool and may
provide some clues into what is physically occurring in
your system if you are experiencing EZ-ICE power up
problems.

RS-232

Microcontroller

Block Diagram of a 21xx EZ-ICE

Port

Intel

80c31

3 bytewide bi-directional

trancievers 74F652s

x-

ceiver

8

Control

Logic

x-

ceiver

x-

ceiver

2

D0-D23

Read/Write

Logic

EMS

WR

A0

ADSP-21xx

Emulator DSP

EBRRDEBG BR BG

EIN

General EZ-ICE Theory of Operation

All ADSP-2100 Family emulators contains an Intel
80C31 ( or compatible 8051/8051 micro) host
microcontroller that performs the RS232 communication
to the PC as well as interpret the emulator commands
from the host computer at the other end of the RS232
line. The handshake mechanism for the 80C31 and the
ADSP-2100 Family DSP is done through the use of the
emulator interrupt (/EINT), emulator memory select
(/EMS), and the /BR and /BR pins.

The Bus Request (/BR) and Bus Grant (/BG) pins are
used to provide a handshake between the 80C31 and the
DSP. The ADSP-2100 Family instructions and data are
fed by the host PC to the 80C31. This two way
communication allows information to be passed from the
host PC to the DSP and from the DSP to PC. The /BR
and /BG handshake is used by the 80C31 allows for
effectively single stepping the ADSP-21xx through
emulator space code.

To achieve the actual data transfer, three byte-wide bi­directional latches are used as the communications port
between the 80C31 host and the ADSP-21xx Emulator
DSP. These latches are memory mapped into the data
memory space of the 8031 and the EZ-ICE memory space
of the DSP. The host can load or read each latch, one at
a time to construct or read a 24 bit instruction or 16 bit
data word. The DSP can read or write all 24 bits of the
three latches at once.

Whenever the 8031 host needs to intervene and
communicate with the DSP, it asserts the emulator
interrupt (/EINT) of the ADSP-21xx DSP. Halting on
breakpoints, single stepping, or halting the DSP from the
PC’s keyboard will result in the emulator interrupt pin for
the ADSP-21xx DSP to be asserted. When the DSP
reacts to the interrupt it will then vector to location 0 of
the emulator memory space while at the same time, the
emulator memory select line (/EMS) is asserted. The 24
bit instruction or data is then fetched from the 3 byte wide
latches. At the same time, interface logic between the
host and the PC will detect the /EMS line’s assertion and
immediately respond by asserting Bus Request. Once the
transfer has completed, the DSP returns from emulator
space. For software breakpoints, a TRAP instruction is
placed at the PM location where the breakpoint had been
set in the emulator software. The execution of a TRAP
instruction also forces an emulator interrupt.

To summarize, the Intel 80C31 microcontroller on the
EZ-ICE board provides RS232 communications between
the host PC and the DSP. When sending instructions to
the DSP, the microcontroller uses the /BR and /BG lines
in conjunction with the emulator interrupt features of the
DSP to effectively single step through code residing in the
DSP’s Program Memory.

The Booting Sequence of the Emulator
DSP in an EZ-ICE Compatible Target

What exactly occurs when the EZ-ICE tries to establish
communications with a target system? This is important
in understanding why some emulated target systems fail
when an EZ-ICE is attached. The following steps describe
what occurs whenever the EZ-ICE is powered up or reset:

1) At EZ-ICE power-up or reset (red/black button pushed),
the Intel 80c31 microcontroller boots it’s monitor code
from its EPROM/EEPROM to on board SRAM.

2) During booting and initialization of the monitor
program, the DSP is still held in reset by the micro with
the /RESET signal held low. The DSP is held low until
the required 2000 CLKIN cycles and then released.

3) The DSP detects the EE ( Emulator Enable ) signal at a
logic high level, and comes out of reset with it’s
emulation circuitry enabled. The Emulator DSP
immediately looks at the state of the MMAP and BMODE
pins to determine how it will boot. For the ADSP-218x
variants, the DSP will look at the MODEx pins.

Memory Space can be thought of as a 3rd memory space
for the DSP, where the data is read/written to 2 memory
locations which are physically bi-directional latches. The
assertion of /EMS by the DSP indicates that the fetching
of the 1st instruction for the emulator interrupt service
routine is occuring.

7) The /EMS signal is also used to initial a bus request.
The Microcontroller recognizes /EMS line going active
and immediately asserts /EBR.

8) /EBG is given by the DSP when it recognizes /EBR.

9) The microcontroller downloads 24 bytes of test
information in the 3 bytewide bi-directional transceivers (
the 74F652s). This is actually a 24-bit instruction that is
loaded. A test NOP instruction is executed by the DSP as
it is fetched from the 3 byte wide latches.

- If the EZ-ICE initialization is successful to this point,
then this means the DSP has a clean CLKIN signal and
/RESET circuitry, the DSP is active and responding to
interrupts, and the /BR signal is functional.

4) The DSP will initiate its boot from an EPROM in
boot ( or byte ) memory space, from the IDMA port (
ADSP-218x), or from the HIP ( ADSP-2111 and ADSP-

2171). The Intel 80c31 host microcontroller during this
time holds /EINT low to assert an emulator interrupt so
that it’s next test will be performed. The microcontroller
will test the EZ-ICE handshake circuitry and verify the
DSP communications are working correctly. The
handshake process is done through the use of the emulator
interrupt( /EINT), emulator memory select (/EMS) and the
bus request (/BR) and bus grant (/BG) pins.

5) The DSP finishes booting and immediately services the
/EINT signal from the Intel Microcontroller. The /EINT
signal has the highest priority in emulation mode. The
handshake test by the microcontroller begins. The /EINT
signal is normally used for halting the DSP on
breakpoints, single stepping, or haltin on user
intervention.

6) The emulator DSP will recognize and respond to the
interrupt by vectoring to Emulator Memory Space which
causes the DSP asserts it’s /EMS signal. Emulator

10) The Emulator released /EBR.

11) The DSP Decodes and Executes the NOP instruction
and fetches the nest instruction from the interface circuitry
in Emulator Memory Space and it will halt.

12) The DSP writes a test value to the bi-directional
transceivers.

13) The Microcontroller reads the value returned back and
compares it to what it expects to see. The micro should
see the expected value, it if does then everything is
operational.

Thus, The DSP in Emulator Memory Space will:

- Fetch an instruction from latches

- Decode the instruction

- and write back to EM Space

EE-34 Page 2

Notes on using Analog Devices’ DSP, audio, & video components from the Computer Products Division

Phone: (800) ANALOG-D or [phone], FAX: [phone], EMAIL: [e-mail]