ANALOG DEVICES EE-315 Service Manual

Engineer-to-Engineer Note EE-315

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Technical notes on using Analog Devices DSPs, processors and development tools

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Changing the PHY in the Ethernet Driver for Blackfin® Processors

Contributed by Jiang Wu Rev 1 – June 21, 2007

Introduction

This EE-Note describes how to achieve
networking functionality with ADSP­BF536/ADSP-BF537 Blackfin® processors
together with MII-compatible Ethernet Physical
Layer Transceivers (PHYs) other than the SMSC
LAN83C185, which is populated on the ADSP­BF537 EZ-KIT Lite® evaluation system. The
procedure is based on the VisualDSP++® 4.5
development tool suite and its Ethernet MAC
driver for the ADSP-BF537 processor. The work
was verified on an SMSC LAN8187 and on a
National Semiconductor DP83848.

system, you can code network applications
without having to consider any hardware
details

[4]

. However, if you use other PHYs, you
must modify the MAC driver, because the MAC
driver uses unique vendor-specific features in
addition to MII standard PHY features.

Overview

ADSP-BF536/ADSP-BF537 Blackfin processors
include a built-in Ethernet MAC controller,
providing an IEEE 802.3-2002-compliant MII
interface for easy connection to any MII-

[1]

compatible PHY

. In addition, the
VisualDSP++ 4.5 development tools are shipped
with a driver for the MAC controller, a TCP/IP
stack (LwIP), and a project template for TCP/IP
applications

[2]

. This allows you to start network­capable applications right away by using the
standard BSD socket API. This network solution
is illustrated in Figure 1.

The MAC controller driver provided by the
VisualDSP++ 4.5 tools is designed primarily for
the SMSC LAN83C185 PHY device populated
on the ADSP-BF537 EZ-KIT Lite evaluation

[3]

board

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. If you choose to use this development

Figure 1. Overview of ADSP-BF537 based network
applications

The source code of the MAC driver consists of
three files.

The project file (ADI_ETHER_BF537.dpj) and the
C source file (ADI_ETHER_BF537.c) are located
in the following directory:

<install_path>\Blackfin\lib\src\drivers
\ethernet\ADI_ETHER_BF537\

The

ADI_ETHER_BF537.h file is located in:

<install_path>\Blackfin\include\drivers
\ethernet\

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These files are copied automatically when the
VisualDSP++ 4.5 tools are installed. Opening the
project file and building it with the VisualDSP++

4.5 development tools generates a library file
named ADI_ETHER_BF537.dlb, which can then
be linked to the network application

The MAC driver is the connecting bridge
between the physical MAC controller/PHY and
the software TCP/IP stack (LwIP). On one side, it
uses two dedicated DMA channels (DMA1 and

DMA2) for the network data exchange between the

MAC controller and the system memory. On the
other side, it communicates with the TCP/IP
stack through a message box mechanism.

The MAC controller talks to the PHY via the
MII interface, which includes two parts, the
network data exchange (signals RxD[3:0],

Rx_DV, Rx_CLK, and Rx_ER for receiving; and
TxD[3:0], Tx_EN, Tx_CLK, and Tx_ER for

transmitting), and the management data
exchange (signals MDC and MDIO). The driver
controls the MAC controller by writing/reading
its memory-mapped registers (MMRs). It also
manages the PHY by commanding the MAC
controller to write/read the 32 PHY registers via
the MII management data exchange channel.

The first two of the 32 PHY registers, the
Control Register (register 0) and the Status
Register (register 1), are mandatory, according to
the MII specification, while the following 13
registers (registers 2-15) are the optional
extended register set. The remaining registers
(registers 16-31) are vendor-specific.

[5]

.

In the following section, the required
modifications to the MAC driver source code to
accommodate different PHYs will be described.

Modifying the MAC Driver Code

To enable the MAC driver for the ADSP­BF536/ADSP-BF537 processor to work with
different PHYs, you must first modify the

ADI_ETHER_BF537.c source code file as

described in the following sections.

Required changes to the source code



To make it easy to find the change locations, a
modified version of
included in the .ZIP file associated with this EE­Note
marked with a comment

/*PHY_CHANGE_LOCATION*/.

static u32 adi_pdd_Open()

This function determines all the default settings
of the PHY, such as PHY address, full/half
duplex mode, speed, and auto-negotiation. They
can be set here or in the application code by
calling the device control function

adi_dev_Control() with the corresponding
COMMAND. These settings must be done only after
adi_dev_Open() and before

adi_dev_Control(…, ADI_ETHER_CMD_START,
…)

.

are explained in RED font in the code
shown in the following steps.

ADI_ETHER_BF537.c is

[6]

, in which all the change locations are

Changing the PHY in the Ethernet Driver for Blackfin® Processors (EE-315) Page 2 of 8

dev->PhyAddr = 0x01; // 0x01 1.1 EZ kit and BUB, Changed to reflect the new PHY’s

address. The PHY’s address is used by the MAC’s MII management interface
to identify each PHY, since MII is able to manage up to 32 PHYs with the
same interface. It is usually determined by the strap option pins of the
PHYs. The values of these pins are sampled during PHY reset and are used
to strap the device into specific addresses.

dev->CLKIN = 25; //Ezkit, Changed to reflect the new application system’s

oscillator/crystal clock in unit of MHz. It will later be used for
setting up the MDC frequency. According to the MII standard, the minimum
high and low times for the MDC signal shall be 160 ns each, and the
minimum period for MDC shall be 400 ns. The driver uses this CLKIN value

to set up a MDC clock of 2.5MHz.

dev->FullDuplex=false; //Changed to reflect the new PHY’s Full Duplex capability
dev->Negotiate = true; //Changed to reflect the new PHY’s AUTONEGOTIATION

capability. If the PHY doesn’t support it, the driver code must be

changed to set the PHY’s capability correctly, which includes dev-

>FullDuplex and dev->Port10. A TRUE value of dev->Port10 means 10MBase,

otherwise it is 100MBase.

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static SetPhy()

This function is called when the application
issues the ADI_ETHER_CMD_START command to

(…, ADI_ETHER_CMD_START, …)

. It initializes

the PHY using the default parameters set in the

adi_pdd_Open()function.

the MAC driver by calling adi_dev_Control

Set software reset

// issue a reset
RawWrPHYReg(dev->PhyAddr, PHYREG_MODECTL, 0x8000);
// wait half a second
period = 30000000; // assume 600 MHZ, This provides a pure delay to allow the PHY

to complete a software RESET. It needs to be changed to reflect the new

PHY’s requirements and the application system’s clock. The MII standard

requires the RESET process be completed within 0.5 seconds from the

issuing of a software reset.

ndtime = clock()+period;
while (clock()<ndtime);

Configure settling time

WrPHYReg(dev->PhyAddr, PHYREG_MODECTL, phydat);
period = 100000000; // assume 600 MHZ, Similar to step 2, it provides a pure delay

to allow the new control settings to take effect, changed to reflect the

new PHY’s requirements

ndtime = clock()+period;
while (clock()<ndtime);

Changing the PHY in the Ethernet Driver for Blackfin® Processors (EE-315) Page 3 of 8