ANALOG DEVICES EE-296 Service Manual

Engineer-to-Engineer Note EE-296

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Technical notes on using Analog Devices DSPs, processors and development tools

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Using the UART Port Controller on SHARC® Processors

Contributed by Divya Sunkara Rev 2 – July 5, 2007

Introduction

Universal asynchronous receiver transmitters
(UARTs) are asynchronous serial
communication peripherals that convert parallel
data to serial data at the transmitter end and
convert serial data into parallel data at the
receiver end. These devices are capable of full­duplex communication over EIA-232E (formally
referred to as RS-232) serial communication
links.

This EE-Note describes UART characteristics
and the programming required to configure
communication between the ADSP-21371
ADSP-21375, ADSP-21367, ADSP-21368, and
ADSP-21369 SHARC® processor’s UART port
controller and other asynchronous serial
communication devices.

The ADSP-21367, ADSP-21368,

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ADSP-21369 SHARC processors have
two UARTs, while the ADSP-21371
and ADSP-21375 SHARC processors
have one. Hereafter, we will
representatively refer to all of them as
ADSP-21368 processors.

UART Data Frame

Figure 1 shows a typical UART data frame,

which comprises a start bit followed by data bits
and a stop bit. The parity bit, which can be
selected for even or odd parity, is used for error
detection. The total length of data bits in a frame

(excluding start, stop, and parity bits) may be of
any length varying from 5 to 8. The number of
stop bits per frame can be programmed to be 1
or 2. Considering all these variations, a UART
data frame length can vary between 7 and 12
bits. The frame's start bit is an active low bit and
is detected at the falling edge; the stop bit is an
active high bit and is detected at the rising edge.
Both the transmitter end and the receiver end
must be given identical baud rates for proper
communication between them.

Figure 1. UART data frame

Synchronization Effects

When two UARTs communicate, the transmitter
and receiver depend on the baud rate at which
data is being transmitted. The transmitter
transmits data at the given baud rate, and the
receiver detects the start of the frame and then
reads data by sampling at the same baud rate.
Because the receiver does not know when the
data frame arrives with respect to the receiver
clock, the communication is termed
asynchronous. Since the receiver has to detect
the start of the frame, the logic at the receiver
side is more complex than the transmitter side.

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Based on the communication protocol, the
receiver clock generated at the receiver side is 16
times the baud rate. Figure 2 shows the protocol
used by the receivers to synchronize to the data
frame. The receiver detects the start of a frame at
the falling edge of an active low start bit when
the data signal transitions from its stop bit or its
idle condition. At this falling edge, the receiver
resets its clock counter and expects to find the
midpoint of the start bit after eight clock cycles.
The start bit is re-sampled at the midpoint in
order to verify that the initially detected falling
edge is not noise or a glitch. It then samples the
next bit after 16 clock cycles, which is shown as
the midpoint of the D0 bit in Figure 2.

rate may not be exact. This error may further
lead to timing variations on the transmitter and
receiver, which can lead to faulty data sampling.

UART External Interface

The EIA-232E interface is used to communicate
with other external serial communication devices
(such as a PC). The EIA-232E has the same data
format as that of a UART, but with different
voltage level detection (see Figure 3). The
standard output voltage level of an EIA-232E
interface usually ranges between +12V and -12V
with a dead area of +3V to -3V to absorb line
noise. Hence, the EIA-232E data is bipolar with
+3V to +12V, indicating an on-state or 0-state
(SPACE) condition. The -3V to -12V range
indicates an off-state or 1-state (MARK).

Figure 2. UART synchronization effects

Because the UART receiver re-synchronizes at
the start of each frame, sampling errors do not
accumulate beyond the stop bit of the previous
frame. Hence, sampling errors are a concern
within a data frame, but not in the entire
transmitted data signal. Sampling errors occur
usually due to a synchronization error between
the receiver clock and the received data frame.
This error builds over the entire frame and shifts
the sampling point of a data bit closer to the
transition edges. Due to the slow rise and fall
times of these transition edges, this may lead to
detection of erroneous data. The slow rise and
fall times occur due to the high capacitance of
the transmission wires. When the stop bit is
sampled low instead of high, a framing error
occurs. Since the baud rate for the UART on the
processor side is derived from the processor’s
peripheral clock, the required generated baud

Figure 3. EIA-232E data logic levels

Because the UART port controller in the 21368
processors produce signals at lower logic levels,
an EIA-232E transceiver (see Figure 4) is
required to convert the UART signal levels to
EIA-232E levels and vice versa. The ADM3202
in Figure 4 has step-up voltage converters
coupled with level-shifting transmitters and
receivers that operate at a power supply voltage
of 3.3V. This EIA-232E transceiver is required
to communicate with other external devices. For
details on the specifications and internal
circuitry, refer to the ADM3202 data sheet. DB9
connectors are used to make physical
connections between two serial communicating
devices using EIA-232E cables.

Using the UART Port Controller on SHARC® Processors (EE-296) Page 2 of 7

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Figure 4 shows interface connections and the

devices required to allow the ADSP-21368

UART port controller communicate with external
serial devices such as a PC.

Figure 4. Connections and devices required to use the UART port controller signals on ADSP-21368 Processors

Each device capable of EIA-232E
communication is termed as a DTE (data
terminal equipment) or a DCE (data
communication equipment) device. You must
know whether the communicating devices are
DCE or DTE devices in order to use proper
connection cables between them. Figure 5 shows
the pin labeling of a DB9 connector.

Based on these pin designations, a serial
communication device with a DB9 connector
(male or female) can be determined as a DTE or
DCE device using a simple DC voltage

Using the UART Port Controller on SHARC® Processors (EE-296) Page 3 of 7

measurements on pin 2 and pin 3 with respect to
pin 5 (signal ground).

When the serial communication device is
powered and is not sending data, one of these
pins (either pin 2 or pin 3) will have a negative
voltage less than -3V and the other pin will have
little or no voltage. If the voltage on pin 2 is
more negative than -3V, the device is termed as a
DCE device; if pin 3 has a more negative
voltage, the device is termed as a DTE.